Display device and method of manufacturing the same

Abstract

A display device and a method for manufacturing the display device are disclosed, the display device may include: a substrate including a display area and a non-display area; and at least one pixel disposed in the display area and including an emission area that emits light. The pixel may include: at least one sub-electrode extending in one direction on the substrate; at least one branch electrode extending in one direction on the substrate and spaced apart from the sub-electrode; a first insulating layer disposed on the sub-electrode and the branch electrode; a first electrode disposed on the first insulating layer and electrically connected to the sub-electrode; a second electrode disposed on the first insulating layer and electrically connected to the branch electrode; and at least one light-emitting element aligned between at least one of the first electrodes and at least one of the second electrodes.

Description

Technical Field

[0001] The present disclosure relates to a display device including an ultra-small light-emitting element and a method of manufacturing the display device. Background Art

[0002] Light emitting diodes have relatively satisfactory durability even under harsh environmental conditions and have excellent performance in terms of life span and brightness.

[0003] In order to apply LEDs to lighting devices, display devices, etc., it is necessary to connect the LEDs to electrodes so that a voltage of a power source can be applied to the LEDs. Various studies have been conducted on the arrangement relationship between LEDs and electrodes with respect to the application purpose of LEDs, methods of reducing the space required for electrodes, or methods of manufacturing LEDs. Summary of the invention

[0004] Technical issues

[0005] An object of the present disclosure is to provide a display device, in which a light-emitting element is aligned only in a target area in an emission area of ​​each pixel, so that the intensity (or amount) of light emitted from each pixel can be uniform, thereby forming a uniform emission distribution in the entire area of ​​the emission area.

[0006] In addition, another object of the present disclosure is to provide a method for manufacturing the above-mentioned display device.

[0007] Technical Solutions

[0008] A display device according to an embodiment of the present disclosure may include: a substrate including a display area and a non-display area; and at least one pixel, which is arranged in the display area and includes an emission area that emits light. The pixel may include: at least one sub-electrode extending in one direction on the substrate; at least one branch electrode extending in one direction on the substrate and spaced apart from the sub-electrode; a first insulating layer, which is arranged on the sub-electrode and the branch electrode; a plurality of first electrodes, which are arranged on the first insulating layer and electrically connected to the sub-electrode; a plurality of second electrodes, which are arranged on the first insulating layer and electrically connected to the branch electrode; and at least one light-emitting element, which is aligned between at least one first electrode of the plurality of first electrodes and at least one second electrode of the plurality of second electrodes.

[0009] In an embodiment of the present disclosure, the first insulating layer may include a plurality of first through holes each exposing a predetermined region of the sub-electrode and a plurality of second through holes each exposing a predetermined region of the branch electrode.

[0010] In an embodiment of the present disclosure, at least one first through hole among the plurality of first through holes may correspond to each of the plurality of first electrodes, and at least one second through hole among the plurality of second through holes may correspond to each of the plurality of second electrodes.

[0011] In an embodiment of the present disclosure, each of the plurality of first electrodes may contact the sub-electrode through at least one first through hole, and each of the plurality of second electrodes may contact the branch electrode through at least one second through hole.

[0012] In an embodiment of the present disclosure, the sub-electrode may be divided into a first region overlapping the first electrode and a second region excluding the first region. The branch electrode may be divided into a third region overlapping the second electrode and a fourth region excluding the third region. The first insulating layer on the first region and the third region may have a thickness different from that of the first insulating layer on the second region and the fourth region.

[0013] In an embodiment of the present disclosure, a thickness of the first insulating layer on the second region and the fourth region may be greater than a thickness of the first insulating layer on the first region and the third region.

[0014] In an embodiment of the present disclosure, each of the plurality of first electrodes and each of the plurality of second electrodes may be spaced apart from each other on the first insulating layer.

[0015] In an embodiment of the present disclosure, in a plan view, each of the plurality of first electrodes and each of the plurality of second electrodes may be alternately disposed in a direction intersecting the one direction in the emission region.

[0016] In an embodiment of the present disclosure, a pixel may include: a first connection line integral with the sub-electrode and extending in a direction intersecting one direction; and a second connection line integral with the branch electrode and arranged parallel to the direction in which the first connection line extends.

[0017] In an embodiment of the present disclosure, a pixel may include: a dam pattern disposed under each of a first electrode and a second electrode; a first contact electrode electrically connecting at least one of a plurality of first electrodes to a first end of a light-emitting element; and a second contact electrode electrically connecting at least one of a plurality of second electrodes to a second end of the light-emitting element.

[0018] In an embodiment of the present disclosure, the pixel may further include: at least one transistor electrically connected to the light emitting element; at least one shielding electrode line disposed on the transistor; a driving voltage line connected to the second electrode and supplying a driving power supply voltage; and a passivation layer covering the transistor, the shielding electrode line and the driving voltage line.

[0019] In an embodiment of the present disclosure, the sub-electrode and the branch electrodes may be disposed between the transistor and the passivation layer.

[0020] In an embodiment of the present disclosure, the sub-electrodes, the branch electrodes, and the shielding electrode lines may be disposed on the same layer.

[0021] In an embodiment of the present disclosure, the pixel may further include: a second insulating layer disposed between the light emitting element and the first insulating layer; and a third insulating layer disposed on an upper surface of the light emitting element. The first contact electrode and the second contact electrode may be spaced apart from each other on the third insulating layer and electrically disconnected from each other.

[0022] The display device can be manufactured by a method comprising: forming a substrate including at least one emission area; forming on the substrate at least one sub-electrode extending in one direction and at least one branch electrode spaced from the sub-electrode and extending in the same direction as the one direction in which the sub-electrode extends; forming a first insulating layer on the sub-electrode and the branch electrode, the first insulating layer comprising a plurality of first through holes exposing predetermined areas of the sub-electrode and a plurality of second through holes exposing predetermined areas of the branch electrode; forming on the first insulating layer a plurality of first electrodes electrically connected to the sub-electrodes through the plurality of first through holes and a plurality of second electrodes electrically connected to the branch electrodes through the plurality of second through holes; aligning a plurality of light-emitting elements between at least one first electrode among the plurality of first electrodes and at least one second electrode among the plurality of second electrodes by applying an alignment voltage to each of the sub-electrode and the branch electrode; forming a second insulating layer on the upper surface of each of the plurality of light-emitting elements; and forming a first contact electrode and a second contact electrode on the substrate having the second insulating layer formed thereon.

[0023] Beneficial Effects

[0024] Embodiments of the present disclosure may provide a display device and a method of manufacturing the display device, in which light emitting elements are aligned only in a desired region (or target region) so that a uniform emission distribution may be formed in the entire region.

[0025] The effects of the present disclosure are not limited to the foregoing, and other various effects are contemplated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0027] Figure 1b It is shown Figure 1a Schematic cross-sectional view of a light-emitting element.

[0028] Figure 1c is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0029] Figure 1d It is shown Figure 1c Schematic cross-sectional view of a light-emitting element.

[0030] Figure 1eis a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0031] Figure 1f It is shown Figure 1e Schematic cross-sectional view of a light-emitting element.

[0032] Figure 1g is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure.

[0033] Figure 1h It is shown Figure 1g Schematic cross-sectional view of a light-emitting element.

[0034] Figure 2 A display device according to an embodiment of the present disclosure is shown, and in particular, a display device using Figure 1a to Figure 1h A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0035] Figure 3a to Figure 3c It is shown Figure 2 Schematic circuit diagrams of various embodiments of the electrical connection relationship of components included in any one of the pixels shown in FIG.

[0036] Figure 4 It is schematically shown Figure 2 A plan view of one of the pixels shown in FIG.

[0037] Figure 5 is only shown schematically Figure 4 A plan view of some of the components in the pixel shown in FIG.

[0038] Figure 6 is along Figure 4 A schematic cross-sectional view taken along line II'.

[0039] Figure 7 shows that the covering layers are arranged Figure 6 The first electrode and the second electrode are shown in the embodiment of Figure 4 A schematic cross-sectional view corresponding to line II'.

[0040] Figure 8 It shows Figure 6 The first electrode and the second electrode are arranged on the same layer, and are similar to Figure 4 A schematic cross-sectional view corresponding to line II'.

[0041] Fig. 9 is along Figure 4 A schematic cross-sectional view taken along line II-II'.

[0042] Fig.10 Shows Fig. 9 Another shape of the bank pattern shown in and is Figure 4 A schematic cross-sectional view corresponding to line II-II'.

[0043] Fig.11 is along Figure 4 A schematic cross-sectional view taken along line III-III'.

[0044] Figures 12a to 12i It is shown in sequence that the manufacturing Figure 4 A schematic plan view of the pixel approach shown in FIG.

[0045] Figures 13a to 13n It is shown in sequence that the manufacturing Figure 6 A schematic cross-sectional view of a method of displaying a device as shown in FIG.

[0046] Figures 14 to 16 Shows Figure 5 1 is another embodiment of a pixel of the present invention, and is a plan view schematically showing a pixel including only some components of a display element layer.

[0047] Fig.17 A display device according to an embodiment of the present disclosure is shown, and schematically shows Figure 2 A plan view of one of the pixels shown in FIG.

[0048] Fig.18 is along Fig.17 A schematic cross-sectional view taken along line IV-IV'. DETAILED DESCRIPTION

[0049] Since the present disclosure allows various changes and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a specific practice, and it should be understood that all changes, equivalents and substitutions that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0050] Throughout the disclosure, in each of the drawings and embodiments of the present disclosure, the same reference numerals represent the same parts. For clarity, the size of the elements in the drawings may be exaggerated. It should be understood that, although the terms "first", "second", etc. can be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In the present disclosure, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise.

[0051] It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the stated features, wholes, steps, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof. In addition, when a first component such as a layer, film, region or plate is disposed on a second component, the first component may not only be directly disposed on the second component, but a third component may also be inserted between the first component and the second component. In addition, when it is indicated that a first component such as a layer, film, region or plate is formed on a second component, the surface of the second component on which the first component is formed is not limited to the upper surface of the second component, but may include other surfaces such as the side surface or lower surface of the second component. On the contrary, when a first component such as a layer, film, region or plate is under a second part, the first component may not only be directly under the second component, but a third component may be inserted between the first component and the second component.

[0052] The embodiments of the present disclosure and required details are described with reference to the accompanying drawings so as to describe the present disclosure in detail so that those skilled in the art can easily practice the present disclosure. In addition, a singular form may include a plural form as long as it is not specifically mentioned in a sentence.

[0053] Figure 1a is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1b It is shown Figure 1a Schematic cross-sectional view of a light-emitting element. Figure 1c is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1d It is shown Figure 1c Schematic cross-sectional view of a light-emitting element. Figure 1e is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1f It is shown Figure 1e Schematic cross-sectional view of a light-emitting element. Figure 1g is a perspective view schematically showing a light emitting element according to an embodiment of the present disclosure. Figure 1h It is shown Figure 1g Schematic cross-sectional view of a light-emitting element.

[0054] For the purpose of explanation, reference will be made to Figures 1a to 1f The cylindrical light emitting element is described and will be referred to hereinafter Figure 1g and Figure 1h A light-emitting element having a core-shell structure is described. In the embodiments of the present disclosure, the type and / or shape of the light-emitting element is not limited to Figure 1a to Figure 1h The embodiment shown in .

[0055] First, refer to Figures 1a to 1f The light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD may be implemented as an emission stack formed by sequentially stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0056] In an embodiment of the present disclosure, the light emitting element LD may extend in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end in the extending direction. Either one of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on one end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the other end of the light emitting element LD.

[0057] Although the light emitting element LD may be provided in the form of a cylinder, the shape of the light emitting element LD is not limited thereto. The light emitting element LD may have a rod-like shape or a bar-like shape extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). For example, the length L of the light emitting element LD in the longitudinal direction may be greater than the diameter D of the light emitting element LD (or the width of the cross section of the light emitting element LD). The light emitting element LD may include a light emitting diode manufactured to have an ultra-small size (e.g., having a length L and / or a diameter D corresponding to a micrometer or nanometer level).

[0058] In the embodiment of the present disclosure, the diameter D of the light emitting element LD may be approximately 0.5 μm to 6 μm, and the length L thereof may be approximately 1 μm to 10 μm. However, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements (or design conditions) of the lighting device or self-luminous display device to which the light emitting element LD is applied.

[0059] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include an n-type semiconductor layer including any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN semiconductor materials, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material of the first semiconductor layer 11 is not limited thereto, and the first semiconductor layer 11 may be formed of various other materials.

[0060] The active layer 12 may be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 may be changed in various ways according to the type of the light emitting element LD. The active layer 12 may emit light having a wavelength of 400nm to 900nm, and a double heterostructure is used. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or under the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, the active layer 12 may be formed using a material such as AlGaN or AlInGaN, and the active layer 12 may be formed using various other materials.

[0061] If an electric field of a predetermined voltage or higher is applied to opposite ends of the light emitting element LD, the light emitting element LD emits light by coupling of electron-hole pairs in the active layer 12. Since light emission of the light emitting element LD can be controlled based on the aforementioned principle, the light emitting element LD can be used as a light source for various light emitting devices and pixels of a display device.

[0062] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including any semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a second conductive dopant such as Mg. However, the material for forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials.

[0063] In the embodiment of the present disclosure, the length (or width) of the second semiconductor layer 13 in the longitudinal direction of the light emitting element LD may be different from the length (or width) of the first semiconductor layer 11. For example, the length (or width) of the second semiconductor layer 13 relative to the longitudinal direction of the light emitting element LD may be smaller than the length (or width) of the first semiconductor layer 11 relative to the longitudinal direction of the light emitting element LD. Figures 1a to 1f As shown in FIG, the active layer 12 of the light emitting element LD may be disposed closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11. In this case, the active layer 12 may be disposed adjacent to the upper end portion of the light emitting element LD having a cylindrical shape.

[0064] In the embodiments of the present disclosure, Figure 1a , Figure 1b , Figure 1c and Figure 1dAs shown in , in addition to the first semiconductor layer 11, the active layer 12 and the second semiconductor layer 13, the light emitting element LD may further include an electrode layer 15 disposed on the second semiconductor layer 13. In an embodiment, the light emitting element LD may include not only one electrode layer 15, but also a separate electrode layer disposed on a side opposite to one side of the electrode layer 15 (for example, disposed on one end of the first semiconductor layer 11), and the separate electrode layer may be provided for ohmic contact and made of a material that is the same as or different from that of the electrode layer 15. For example, as Figure 1e and Figure 1f As shown in , the light emitting element LD may further include another electrode layer 16 provided on one end portion of the first semiconductor layer 11 in addition to the electrode layer 15 .

[0065] Although each of the electrode layers 15 and 16 may be formed of an ohmic contact electrode, the present disclosure is not limited thereto. The electrode layers 15 and 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO, and oxides or alloys thereof may be used alone or in combination with each other. However, the present disclosure is not limited thereto.

[0066] The materials included in the respective electrode layers 15 and 16 may be the same as or different from each other. The electrode layers 15 and 16 may be substantially transparent or translucent. Therefore, light generated from the light emitting element LD may pass through the electrode layers 15 and 16 and then be emitted to the outside of the light emitting element LD.

[0067] In an embodiment of the present disclosure, the light emitting element LD may further include an insulating film 14. However, in some embodiments of the present disclosure, the insulating film 14 may be omitted or may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0068] The insulating film 14 can prevent the active layer 12 from being short-circuited due to contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, due to the insulating film 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, thereby improving the life and efficiency of the light-emitting element LD. In the case where the light-emitting elements LD are arranged in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between the light-emitting elements LD. Whether the insulating film 14 is provided is not limited as long as the active layer 12 can be prevented from being short-circuited with an external conductive material.

[0069] like Figure 1a and Figure 1b As shown in , the insulating film 14 may surround the entirety of the outer peripheral surface of the emission stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13 and the electrode layer 15. For the sake of explanation, Figure 1aA shape is shown in which a part of the insulating film 14 has been removed and the entirety of the outer peripheral surface of the emission stack can be surrounded by the insulating film 14. However, the present disclosure is not limited thereto. Figure 1c and Figure 1d As shown in , the insulating film 14 may be provided on a portion of the light emitting element LD except for one of the opposite ends of the light emitting element LD. For example, the insulating film 14 may expose only the electrode layer 15 provided on one end of the second semiconductor layer 13 of the light emitting element LD, and surround the entire side surface of the component except the electrode layer 15. The insulating film 14 may expose at least the opposite ends of the light emitting element LD to the outside, and, for example, allow not only the electrode layer 15 provided on one end of the second semiconductor layer 13 but also one end of the first semiconductor layer 11 to be exposed to the outside.

[0070] In an embodiment, if Figure 1e and Figure 1f As shown in FIG, in the case where the electrode layers 15 and 16 are provided on the respective opposite ends of the light emitting element LD, the insulating film 14 may allow at least one region of each of the electrode layers 15 and 16 to be exposed to the outside. As another example, in an embodiment, the insulating film 14 may not be provided.

[0071] In an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include a material selected from SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 At least one insulating material in the group consisting of, but the present disclosure is not limited thereto. In other words, various materials having insulating properties may be used.

[0072] If the insulating film 14 is provided in the light emitting element LD, the active layer 12 can be prevented from being short-circuited with the first electrode and / or the second electrode (not shown). In addition, due to the insulating film 14, the occurrence of defects on the surface of the light emitting element LD can be minimized, thereby improving the life and efficiency of the light emitting element LD. In the case where a plurality of light emitting elements LD are provided in close contact with each other, the insulating film 14 can prevent an undesirable short circuit from occurring between the light emitting elements LD.

[0073] The light emitting element LD can be used as a light source for various display devices. The light emitting element LD can be manufactured by a surface treatment process. For example, each light emitting element LD can be surface treated so that when a plurality of light emitting elements LD are mixed with a fluid solution (or solvent) and then supplied to each emission area (e.g., the emission area of ​​each pixel), the light emitting element LD can be uniformly dispersed rather than unevenly aggregated in the solution.

[0074] The light-emitting device including the above-mentioned light-emitting element LD can be used not only in a display device, but also in various devices that require a light source. For example, in the case where the light-emitting element LD is arranged in the emission area of ​​each pixel of the display panel, the light-emitting element LD can be used as the light source of the pixel. However, the application field of the light-emitting element LD is not limited to the above-mentioned example. For example, the light-emitting element LD can also be used in other types of devices (such as, lighting devices) that require a light source.

[0075] Next, we will refer to Figure 1g and Figure 1h The light emitting element LD having a core-shell structure will be described below. The light emitting element LD having a core-shell structure will be described below focusing on the differences from the above-described embodiment, and components of the light emitting element LD that are not separately explained in the following description may be consistent with those of the foregoing embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0076] refer to Figure 1g and Figure 1h , the light emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light emitting element LD may include an emission pattern 10 having a core-shell structure. The emission pattern 10 may include a first semiconductor layer 11 disposed in a central portion of the light emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an electrode layer 15 surrounding at least one side of the second semiconductor layer 13.

[0077] The light emitting element LD may be formed in a polygonal pyramid shape extending in one direction. In an embodiment of the present disclosure, the light emitting element LD may be arranged in the form of a hexagonal pyramid. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end (or a lower end) and a second end (or an upper end) in the longitudinal direction. In an embodiment, one of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged on the first end (or the lower end) of the light emitting element LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be arranged on the second end (or the upper end) of the light emitting element LD.

[0078] In an embodiment, the light emitting element LD may have a small size corresponding to a nanometer-scale size or a micrometer-scale size, for example, a diameter D and / or a length L having a nanometer-scale range or a micrometer-scale range. However, in the present disclosure, the size of the light emitting element LD is not limited thereto, and the size of the light emitting element LD may be changed to meet the requirements (or application conditions) of the lighting device or the self-luminous display device to which the light emitting element LD is applied.

[0079] In an embodiment of the present disclosure, the first semiconductor layer 11 may be disposed in the core (i.e., the central (or middle) portion) of the light emitting element LD. The light emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting element LD and the emission pattern 10 may each also have a hexagonal pyramid shape.

[0080] The active layer 12 may be disposed and / or formed to surround the outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD. Specifically, the active layer 12 may be disposed and / or formed to surround a region of the first semiconductor layer 11 except for a lower end portion of the opposite ends of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD.

[0081] The second semiconductor layer 13 may be disposed and / or formed to surround the active layer 12 in the longitudinal direction of the light emitting element LD, and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0082] In an embodiment of the present disclosure, the light emitting element LD may include an electrode layer 15 surrounding at least one side of the second semiconductor layer 13. The electrode layer 15 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto.

[0083] As described above, the light emitting element LD may have a hexagonal pyramid shape having opposite ends protruding outward, and the light emitting element LD may be implemented as an emission pattern 10 having a core-shell structure including a first semiconductor layer 11 disposed in a central portion thereof, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an electrode layer 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be disposed on a first end (or a lower end) of the light emitting element LD having the hexagonal pyramid shape, and the electrode layer 15 may be disposed on a second end (or an upper end) of the light emitting element LD.

[0084] In an implementation, the light emitting element LD may further include an insulating film 14 disposed on an outer peripheral surface of the emission pattern 10 having the core-shell structure. The insulating film 14 may include a transparent insulating material.

[0085] Figure 2 A display device according to an embodiment of the present disclosure is shown, and in particular, a display device using Figure 1a to Figure 1h A schematic plan view of a display device using any one of the light-emitting elements shown in FIG. 1 as a light source.

[0086] For the sake of explanation, Figure 2 The structure of the display device is schematically shown by focusing on the display area where the image is displayed. In some embodiments, although not shown in the drawings, at least one driving circuit (eg, a scan driver and a data driver) and / or line may also be provided in the display device.

[0087] refer to Figure 1a to Figure 1h as well as Figure 2 According to an embodiment of the present disclosure, a display device may include a substrate SUB, pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driver (not shown) disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly (not shown) disposed to connect the pixels PXL to the driver.

[0088] According to the method of driving the light emitting element LD, the display device can be divided into a passive matrix type display device and an active matrix type display device. For example, in the case where the display device according to the embodiment is implemented as an active matrix type, each of the pixels PXL may include a driving transistor configured to control the amount of current to be supplied to the light emitting element LD and a switching transistor configured to transmit a data signal to the driving transistor.

[0089] Recently, considering resolution, contrast and operating speed, active matrix display devices capable of selectively turning on each pixel PXL have become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix display device in which the pixels PXL can be turned on in groups may also employ components (e.g., first electrodes and second electrodes) for driving the light emitting element LD.

[0090] The substrate SUB may include a display area DA and a non-display area NDA.

[0091] In an embodiment, the display area DA may be disposed in the central area of ​​the display device, and the non-display area NDA may be disposed in the peripheral area of ​​the display device in such a manner as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0092] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driver for driving the pixels PXL and some of line components for connecting the pixels PXL to the driver are disposed.

[0093] The display area DA may have various shapes. For example, the display area DA may be provided in various forms, such as a closed polygon including sides formed by straight lines, a circle including sides formed by curved lines, an ellipse, etc., and a semicircle including sides formed by straight lines and curved lines, a semiellipse, etc.

[0094] The non-display area NDA may be provided in at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the periphery of the display area DA.

[0095] The substrate SUB may include a transparent insulating material to allow light to be transmitted.

[0096] The substrate SUB may be a rigid substrate. For example, the substrate as the rigid substrate may be one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystallized glass substrate.

[0097] The substrate SUB may be a flexible substrate. Here, the substrate as the flexible substrate may be a film substrate or a plastic substrate including a polymer organic material. For example, the substrate as the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0098] However, the material constituting the substrate SUB may vary, and includes, for example, fiber reinforced plastic (FRP).

[0099] One area of ​​the substrate SUB is set as a display area DA in which the pixels PXL are disposed, and another area of ​​the substrate SUB is set as a non-display area NDA. For example, the substrate SUB may include a display area DA including a pixel area in which corresponding pixels PXL are formed, and a non-display area NDA disposed around the display area DA.

[0100] The pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in the display area DA in a stripe or PenTile arrangement structure, but the present disclosure is not limited thereto.

[0101] Each pixel PXL may include a light emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size corresponding to a micrometer or nanometer level and be electrically connected in parallel to a light emitting element LD disposed adjacent thereto, but the present disclosure is not limited thereto. The light emitting element LD may form a light source of each pixel PXL.

[0102] Each of the pixels PXL may include at least one light source driven by a predetermined control signal (eg, a scan signal and a data signal) and / or a predetermined power source (eg, a first driving power source and a second driving power source). Figure 1a to Figure 1g The light emitting element LD shown in each of the embodiments has, for example, at least one ultra-small light emitting element LD having a small size corresponding to the nanometer level or the micrometer level. However, in the embodiments of the present disclosure, the type of light emitting element LD that can be used as the light source of the pixel PXL is not limited thereto.

[0103] In an embodiment of the present disclosure, the color, type, and / or number of the pixels PXL are not particularly limited. For example, the color of light emitted from each pixel PXL may be changed in various ways.

[0104] The driver may provide a signal to each pixel PXL through the line assembly and thus control the operation of the pixel PXL. Figure 2 , the wire components are omitted.

[0105] The driver may include a timing controller, a scan driver configured to transmit a scan signal to the pixel PXL through a scan line, an emission driver configured to transmit an emission control signal to the pixel PXL through an emission control line, and a data driver configured to provide a data signal to the pixel PXL through a data line. The timing controller may control the scan driver, the emission driver, and the data driver.

[0106] Figure 3a to Figure 3c It is shown Figure 2 Schematic circuit diagrams of various embodiments of the electrical connection relationships of components included in any of the pixels shown in FIG.

[0107] For example, Figure 3a to Figure 3c Various embodiments of electrical connection relationships of components included in the pixel PXL that may be employed in an active display device are shown. However, the types of components included in the pixel PXL to which the embodiments of the present disclosure may be applied are not limited thereto.

[0108] exist Figure 3a to Figure 3c The definition of the term "pixel PXL" includes not only Figure 2 The components included in each of the pixels PXL shown in FIG. 1 and also include the region in which the components are disposed. In an embodiment, Figure 3a to Figure 3c Each pixel PXL shown in FIG. 1 may be set to Figure 2 The pixels PXL may have substantially the same or similar structures.

[0109] refer to Figure 1a to Figure 1h , Figure 2 and Figure 3a to Figure 3c Each pixel (PXL, hereinafter referred to as "pixel") may include an emission unit EMU configured to generate light having brightness corresponding to a data signal. The pixel PXL may also selectively include a pixel circuit 144 configured to drive the emission unit EMU.

[0110] In an embodiment, the emission unit EMU may include a light emitting element LD electrically connected in parallel between a first power line PL1 to which a first driving power VDD is applied and a second power line PL2 to which a second driving power VSS is applied. For example, the emission unit EMU may include a first electrode EL1 (or "first alignment electrode") electrically connected to the first driving power VDD via the first power line PL1, a second electrode EL2 (or "second alignment electrode") electrically connected to the second driving power VSS via the second power line PL2, and a plurality of light emitting elements LD electrically connected in parallel to each other in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0111] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include a first end electrically connected to a first driving power source VDD through a first electrode EL1 and a second end electrically connected to a second driving power source VSS through a second electrode EL2. The first driving power source VDD and the second driving power source VSS may have different potentials. For example, the first driving power source VDD may be set as a high potential power source, and the second driving power source VSS may be set as a low potential power source. Here, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to a value equal to or greater than the threshold voltage of the light-emitting element LD during the light-emitting period of the pixel PXL.

[0112] As described above, the light emitting elements LD electrically connected in parallel with each other in the same direction (eg, forward direction) between the first electrode EL1 and the second electrode EL2 respectively supplied with voltages of different potentials may form corresponding effective light sources. The effective light sources may collectively form the emission part EMU of the pixel PXL.

[0113] The light emitting element LD of the emission unit EMU may emit light having a brightness corresponding to the driving current supplied thereto by the pixel circuit 144. For example, during each frame period, the pixel circuit 144 may supply a driving current corresponding to the grayscale level of the corresponding frame data to the emission unit EMU. The driving current supplied to the emission unit EMU may be shunted into the light emitting elements LD electrically connected to each other in the same direction. Therefore, each of the light emitting elements LD may emit light having a brightness corresponding to the current applied thereto, so that the emission unit EMU may emit light having a brightness corresponding to the driving current.

[0114] although Figure 3a to Figure 3c An embodiment in which the light-emitting elements LD are electrically connected to each other in the same direction between the first driving power supply VDD and the second driving power supply VSS is shown, but the present disclosure is not limited thereto. In an embodiment, in addition to the light-emitting element LD forming the corresponding effective light source, the transmitting unit EMU may also include at least one invalid light source. For example, at least one reverse light-emitting element (not shown) may be electrically connected between the first electrode EL1 and the second electrode EL2 of the transmitting unit EMU. The reverse light-emitting element, together with the light-emitting element LD forming the effective light source, may be electrically connected in parallel to each other between the first electrode EL1 and the second electrode EL2. Here, the reverse light-emitting element may be electrically connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to the direction of the light-emitting element LD. Even when a predetermined driving voltage (e.g., a driving voltage of normal directionality) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element remains disabled. Therefore, current does not substantially flow through the reverse light-emitting element.

[0115] The pixel circuit 144 may be electrically connected to a scan line (e.g., the i-th scan line Si) and a data line (e.g., the j-th data line Dj) of a corresponding pixel PXL. For example, if the pixel PXL is disposed in the i-th row (where i is a natural number) and the j-th column (where j is a natural number) of the display area DA, the pixel circuit 144 of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In an embodiment, as Figure 3a As shown in FIG. 1 , the pixel circuit 144 may include a first transistor T1, a second transistor T2 and a storage capacitor Cst. The structure of the pixel circuit 144 is not limited to Figure 3a The structure of the embodiment shown in .

[0116] A first terminal of a first transistor (T1; a switching transistor) may be electrically connected to a data line (j-th data line Dj), and a second terminal thereof may be electrically connected to a first node N1. Here, the first terminal and the second terminal of the first transistor T1 may be different from each other, and for example, in the case where the first terminal is a source electrode, the second terminal may be a drain electrode. A gate electrode of the first transistor T1 may be electrically connected to a scan line (e.g., the i-th scan line Si).

[0117] In the case where a scan signal having a voltage (e.g., a low level voltage) capable of turning on the first transistor T1 is supplied from a scan line (e.g., the i-th scan line Si), the first transistor T1 is turned on to electrically connect the data line (j-th data line Dj) to the first node N1. Here, a data signal of a corresponding frame is supplied to the data line (j-th data line Dj), whereby the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 may be charged to the storage capacitor Cst.

[0118] A first terminal of the second transistor (T2; driving transistor) may be electrically connected to the first driving power source VDD, and a second terminal thereof may be electrically connected to the first electrode EL1 for the light emitting element LD. A gate electrode of the second transistor T2 may be electrically connected to the first node N1. Thus, the second transistor T2 may control the amount of driving current to be supplied to the light emitting element LD in response to the voltage of the first node N1.

[0119] The first electrode of the storage capacitor Cst may be electrically connected to the first driving power source VDD, and the second electrode thereof may be electrically connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1, and maintains the charged voltage until a data signal of a subsequent frame is supplied.

[0120] Figure 3a A pixel circuit 144 is shown including a first transistor T1 configured to transmit a data signal to the pixel PXL, a storage capacitor Cst configured to store the data signal, and a second transistor T2 configured to supply a driving current corresponding to the data signal to the light emitting element LD.

[0121] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 may be changed in various ways. For example, the pixel circuit 144 may further include at least one transistor element such as a transistor element configured to compensate for the threshold voltage of the second transistor T2, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the light emission time of the light emitting element LD, or other circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0122] In addition, despite the Figure 3a 1 and 2 , the transistors (eg, the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are shown as being formed of P-type transistors, but the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0123] Next, refer to Figure 1a to Figure 1h , Figure 2 and Figure 3b , the first transistor T1 and the second transistor T2 according to the embodiment of the present disclosure may be formed by N-type transistors. Due to the change of transistor type, Figure 3b The configuration and operation of the pixel circuit 144 shown in FIG. Figure 3a The configuration and operation of the pixel circuit 144 may be different at least in terms of the connection positions of some components. Therefore, a detailed description of the same configuration will be omitted.

[0124] In the embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 3a and Figure 3b For example, it can be implemented with Figure 3c The pixel circuit 144 is configured in the same manner as the embodiment shown in FIG.

[0125] like Figure 3c As shown in , the pixel circuit 144 may be electrically connected to a scan line (e.g., the i-th scan line Si) and a data line (j-th data line Dj) of the pixel PXL. For example, if the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the pixel PXL may be electrically connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0126] In an embodiment, the pixel circuit 144 may also be electrically connected to at least one scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may also be electrically connected to the i-1th scan line Si-1 and / or the i+1th scan line Si+1. In an embodiment, the pixel circuit 144 may be electrically connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel circuit 144 may also be connected to an initialization power supply Vint.

[0127] The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

[0128] The first transistor (T1; driving transistor) may include a first electrode (e.g., source electrode) electrically connected to the first driving power source VDD via a fifth transistor T5, and a second electrode (e.g., drain electrode) of the first transistor T1 is electrically connected to one end of the light emitting element LD via a sixth transistor T6. The gate electrode of the first transistor T1 may be electrically connected to the first node N1. The first transistor T1 may control a driving current flowing through the light emitting element LD between the first driving power source VDD and the second driving power source VSS in response to a voltage of the first node N1.

[0129] The second transistor (T2; switching transistor) may be electrically connected between the source electrode of the first transistor T1 and the j-th data line Dj electrically connected to the pixel PXL. The gate electrode of the second transistor T2 may be electrically connected to the i-th scan line Si electrically connected to the pixel PXL. In the case where a scan signal having a gate-on voltage (e.g., a low-level voltage) is supplied from the i-th scan line Si, the second transistor T2 may be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj may be transmitted to the first transistor T1.

[0130] The third transistor T3 may be electrically connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 may be electrically connected to the i-th scan line Si. When a scan signal having a gate-on voltage is supplied from a scan line (e.g., the i-th scan line Si), the third transistor T3 may be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1.

[0131] The fourth transistor T4 may be electrically connected between the first node N1 and an initialization power line to which the initialization power Vint is applied. The gate electrode of the fourth transistor T4 may be electrically connected to a previous scan line, for example, the i-1th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the i-1th scan line Si-1, the fourth transistor T4 may be turned on so that the voltage of the initialization power Vint may be transmitted to the first node N1. Here, the initialization power Vint may have a voltage equal to or less than the minimum voltage of the data signal.

[0132] The fifth transistor T5 may be electrically connected between the first driving power source VDD and the first transistor T1. The gate electrode of the fifth transistor T5 may be electrically connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0133] The sixth transistor T6 may be electrically connected between the first transistor T1 and the first end of the light emitting element LD. The gate electrode of the sixth transistor T6 may be electrically connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0134] The seventh transistor T7 may be electrically connected between the first end of the light emitting element LD (which is connected to the second node N2) and the initialization power line to which the initialization power Vint is applied. The gate electrode of the seventh transistor T7 may be electrically connected to any scan line of the scan lines of the subsequent stage, for example, to the i+1th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the i+1th scan line Si+1, the seventh transistor T7 may be turned on so that the voltage of the initialization power Vint may be supplied to the first end of the light emitting element LD.

[0135] The storage capacitor Cst may be electrically connected between the first driving power source VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both a data signal applied to the first node N1 during each frame period and a threshold voltage of the first transistor T1.

[0136] Despite Figure 3c 1 and 2 show that the transistors (eg, the first to seventh transistors T1 to T7) included in the pixel circuit 144 are formed of P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

[0137] although Figure 3a to Figure 3c An embodiment in which all light emitting elements LD of each emission unit EMU are electrically connected in parallel to each other is shown, but the present disclosure is not limited thereto. In an embodiment, the emission unit EMU may include at least one series stage including a plurality of light emitting elements LD electrically connected in parallel to each other. In other words, the emission unit EMU may be formed by a serial / parallel combination structure.

[0138] The structure of the pixel PXL applicable to the present disclosure is not limited to Figure 3a to Figure 3c , and the corresponding pixel PXL may have various structures. In the embodiment of the present disclosure, each pixel PXL may be configured in a passive light emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and the opposite ends of the light emitting element LD included in the emission unit EMU may be directly connected to the scan line, the data line, the predetermined control line, the first power line PL1 to which the first driving power VDD is applied, and / or the second power line PL2 to which the second driving power VSS is applied.

[0139] Figure 4 It is schematically shown Figure 2 A plan view of one of the pixels shown in FIG. Figure 5 It is schematically shown Figure 4 A plan view of only some of the components in a pixel shown in FIG. Figure 6 is along Figure 4 A schematic cross-sectional view taken along line II'. Figure 7 shows that the covering layers are arranged Figure 6 The first electrode and the second electrode are shown in the embodiment of Figure 4 A schematic cross-sectional view corresponding to line II'. Figure 8 It shows Figure 6 The first electrode and the second electrode are arranged on the same layer, and are similar to Figure 4 A schematic cross-sectional view corresponding to line II'. Fig. 9 is along Figure 4 A schematic cross-sectional view taken along line II-II'. Fig.10 Shows Fig. 9 Another shape of the bank pattern shown in and is Figure 4 A schematic cross-sectional view corresponding to line II-II'. Fig.11 is along Figure 4 A schematic cross-sectional view taken along line III-III'.

[0140] exist Figure 4 and Figure 5 For the sake of explanation, Figure 5 Illustration of a transistor electrically connected to a light emitting element and a signal line electrically connected to the transistor is omitted.

[0141] although Figures 4 to 11 The structure of the pixel is simply illustrated, for example, it is illustrated that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0142] In the embodiments of the present disclosure, the phrase “components are disposed and / or formed on the same layer” may mean that the components are formed through the same process.

[0143] refer to Figures 1a to 11 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a line assembly, and a pixel PXL.

[0144] Each of the pixels PXL may be disposed on a substrate SUB and include an emission area EMA that emits light and a peripheral area disposed around the emission area EMA. In an embodiment of the present disclosure, the emission area EMA may refer to an area that emits light, and the peripheral area may refer to an area that does not emit light. The pixel area of ​​each of the pixels PXL may include the emission area EMA of the corresponding pixel PXL and a peripheral area formed around the emission area EMA.

[0145] The substrate SUB, the pixel circuit layer PCL, and the display element layer DPL may be disposed and / or formed in a pixel region of each of the pixels PXL.

[0146] The substrate SUB may include a transparent insulating material and thus allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

[0147] The material applied to the substrate SUB may have resistance (heat resistance) to a high processing temperature during a process of manufacturing the display device.

[0148] The pixel circuit layer PCL of each pixel PXL may include a buffer layer BFL disposed on a substrate SUB, at least one transistor T disposed on the buffer layer BFL, a driving voltage line DVL, and a shielding electrode line SDL. In addition, the pixel circuit layer PCL of each pixel PXL may further include a passivation layer PSV.

[0149] The buffer layer BFL may prevent impurities from diffusing into the transistor T. The buffer layer BFL may be provided in a single-layer structure or a multi-layer structure having at least two layers. In the case where the buffer layer BFL has a multi-layer structure, the respective layers may be formed of the same material or different materials. Depending on the material and / or processing conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0150] The transistor T may include a first transistor T1(T) and a second transistor T2(T). In an embodiment of the present disclosure, the first transistor T1(T) may be a driving transistor electrically connected to the light emitting element LD of the corresponding pixel PXL and configured to drive the light emitting element LD. The second transistor T2(T) may be a switching transistor configured to switch the first transistor T1(T).

[0151] Each of the first transistor T1(T) and the second transistor T2(T) may include a semiconductor layer SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be a source electrode or a drain electrode, and the second terminal DE may be another electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0152] The semiconductor layer SCL may be disposed on the buffer layer BFL. The semiconductor layer SCL may include a first region in contact with the first terminal SE and a second region in contact with the second terminal DE. A region between the first region and the second region may be a channel region.

[0153] The semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor, which is an undoped semiconductor pattern. The first region and the second region may each be a semiconductor pattern doped with impurities.

[0154] The gate electrode GE may be disposed on the semiconductor layer SCL with a gate insulating layer GI interposed therebetween.

[0155] The first terminal SE and the second terminal DE may respectively contact the first region and the second region of the semiconductor layer SCL through corresponding contact holes passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0156] In an embodiment of the present disclosure, at least one transistor T included in the pixel circuit layer PCL of each of the pixels PXL may be formed by an LTPS thin film transistor, but the present disclosure is not limited thereto. In some embodiments, at least one transistor T may be formed by an oxide semiconductor thin film transistor. In addition, in an embodiment of the present disclosure, the transistor T is shown as a thin film transistor having a top gate structure, but the present disclosure is not limited thereto. In an embodiment, the transistor T may be a thin film transistor having a bottom gate structure.

[0157] The driving voltage line DVL may be disposed and / or formed on the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. In some embodiments, the driving voltage line DVL may be disposed on any one of the insulating layers included in the pixel circuit layer PCL. The second driving power source ( Figure 3a VSS) can be applied to the driving voltage line DVL. In the embodiment of the present disclosure, Figure 3a to Figure 3c As shown in each of FIG. 1 , the driving voltage line DVL may be a second power line PL2 to which the second driving power VSS is applied.

[0158] A second interlayer insulating layer ILD2 may be disposed and / or formed on the driving voltage line DVL. The second interlayer insulating layer ILD2 may cover the first transistor T1(T), the second transistor T2(T) and the driving voltage line DVL. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0159] A shielding electrode line SDL may be disposed and / or formed on the second interlayer insulating layer ILD2. The shielding electrode line SDL may block the electric field caused by the first transistor T1 (T) and the second transistor T2 (T) to prevent the electric field from affecting the alignment and / or operation of the light emitting element LD disposed on the display element layer DPL.

[0160] A passivation layer PSV may be disposed and / or formed on the shielding electrode line SDL to cover the shielding electrode line SDL. The passivation layer PSV may be disposed in the form of an organic insulating layer, an inorganic insulating layer, or a structure including an organic insulating layer disposed on an inorganic insulating layer. The inorganic insulating layer may include silicon oxide (SiO x ) and silicon nitride (SiN x ). The organic insulating layer may include an organic insulating material that allows light to pass therethrough. The organic insulating layer may include, for example, at least one of a polyacrylate resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0161] In an embodiment of the present disclosure, a predetermined area of ​​the second terminal DE of the first transistor T1 (T) may be exposed through a first contact hole CH1 sequentially passing through the second interlayer insulating layer ILD2 and the passivation layer PSV. In addition, a predetermined area of ​​the driving voltage line DVL may be exposed through a second contact hole CH2 sequentially passing through the second interlayer insulating layer ILD2 and the passivation layer PSV.

[0162] The display element layer DPL of each of the pixels PXL may include first and second connection lines CNL1 and CNL2, a bank pattern PW, a first electrode EL1, a second electrode EL2, a light emitting element LD, at least one sub-electrode PRT, and at least one branch electrode BRC. In addition, the display element layer DPL of each of the pixels PXL may also selectively include at least one first contact electrode CNE1 directly connected to each of the first electrodes EL1 and at least one second contact electrode CNE2 directly connected to each of the second electrodes EL2.

[0163] A first connection line CNL1 may be disposed and / or formed on the pixel circuit layer PCL of each of the pixels PXL. Specifically, a first connection line CNL1 may be disposed and / or formed on the passivation layer PSV of the pixel circuit layer PCL of each of the pixels PXL. The first connection line CNL1 may be disposed and / or formed to independently (or individually) drive each of the adjacent pixels PXL only in the corresponding pixel PXL, and to be electrically and / or physically separated from the first connection line CNL1 disposed and / or formed in each of the adjacent pixels PXL.

[0164] In an embodiment of the present disclosure, the first connection line CNL1 may extend in a first direction DR1 (eg, “row direction”) on the passivation layer PSV of the pixel circuit layer PCL of each of the pixels PXL. The first connection line CNL1 may be electrically and / or physically connected to at least one sub-electrode PRT.

[0165] The sub-electrode PRT may be disposed and / or formed on the passivation layer PSV of the pixel circuit layer PCL of each of the pixels PXL. The sub-electrode PRT may include a first sub-electrode PRT1, a second sub-electrode PRT2, and a third sub-electrode PRT3 extending in a second direction DR2 (e.g., a “column direction”) intersecting the first direction DR1.

[0166] The first to third sub-electrodes PRT1 to PRT3 may be arranged in the same plane (for example, on the passivation layer PSV of the pixel circuit layer PCL of each of the pixels PXL) at positions separated from each other by a predetermined distance. In an embodiment of the present disclosure, the first to third sub-electrodes PRT1 to PRT3 may be branched from the first connection line CNL1 in the second direction DR2 to the emission area EMA of each pixel PXL. The first to third sub-electrodes PRT1 to PRT3 and the first connection line CNL1 may be integral with each other and electrically and / or physically connected to each other. In the case where the first to third sub-electrodes PRT1 to PRT3 and the first connection line CNL1 are integral with each other, each of the first to third sub-electrodes PRT1 to PRT3 may be a predetermined area of ​​the first connection line CNL1, or the first connection line CNL1 may be a predetermined area of ​​any one of the first to third sub-electrodes PRT1 to PRT3.

[0167] In a plan view, the first to third sub-electrodes PRT1 to PRT3 may be sequentially arranged in the first direction DR1. For example, in the emission area EMA of each of the pixels PXL, the second sub-electrode PRT2 may be arranged adjacent to the first sub-electrode PRT1 in the first direction DR1, and the third sub-electrode PRT3 may be arranged adjacent to the second sub-electrode PRT2 in the first direction DR1.

[0168] The second sub-electrode PRT2 may be electrically connected to the second terminal DE of the first transistor T1(T) of the pixel circuit layer PCL of each of the pixels PXL through the first contact hole CH1 that sequentially passes through the passivation layer PSV and the second interlayer insulating layer ILD2. Therefore, the signal (or voltage) applied to the first transistor T1(T) may be transmitted to the second sub-electrode PRT2 of the corresponding pixel PXL. The signal (or voltage) applied to the second sub-electrode PRT2 may be transmitted to the first connection line CNL1 and the first and third sub-electrodes PRT1 and PRT3.

[0169] Although it has been described in the foregoing embodiment that the second sub-electrode PRT2 corresponds to the first contact hole CH1 and is electrically connected to the first transistor T1 (T) of the pixel circuit layer PCL of each of the pixels PXL through the first contact hole CH1, the present disclosure is not limited thereto. In an embodiment, the first connection line CNL1 and any one of the first sub-electrode PRT1 and the third sub-electrode PRT3 may correspond to the first contact hole CH1 and be electrically connected to the first transistor T1 (T) of the pixel circuit layer PCL of each of the pixels PXL through the first contact hole CH1.

[0170] A second connection line CNL2 may be provided and / or formed on the passivation layer PSV of the pixel circuit layer PCL of each of the pixels PXL. The second connection line CNL2 may extend in a direction parallel to the direction in which the first connection line CNL1 extends. In other words, the second connection line CNL2 may extend in the first direction DR1. The second connection line CNL2 may be provided in common to adjacent pixels PXL. Therefore, the pixels PXL arranged in the same pixel row in the first direction DR1 may be electrically connected to the second connection line CNL2 in common. However, the present disclosure is not limited thereto. After aligning the light emitting element LD in the emission area EMA of each pixel PXL, a portion of the second connection line CNL2 between adjacent pixels PXL may be removed so that each of the pixels PXL may operate independently of the adjacent pixels PXL.

[0171] The second connection line CNL2 may be electrically connected to the driving voltage line DVL of the pixel circuit layer PCL of each of the pixels PXL through the second contact hole CH2 sequentially passing through the passivation layer PSV and the second interlayer insulating layer ILD2. Since the second connection line CNL2 is electrically connected to the driving voltage line DVL, the second driving power VSS applied to the driving voltage line DVL may be transmitted to the second connection line CNL2, wherein the second connection line CNL2 is commonly provided to the pixels PXL disposed in the same pixel row.

[0172] The second connection line CNL2 may be electrically and / or physically connected to the branch electrode BRC.

[0173] The branch electrode BRC may be disposed and / or formed on the passivation layer PSV of the pixel circuit layer PCL of each of the pixels PXL. The branch electrode BRC may include first and second branch electrodes BRC1 and BRC2 branched from the second connection line CNL2 to the corresponding emission areas EMA of the pixels PXL in the second direction DR2.

[0174] The first branch electrode BRC1 and the second branch electrode BRC2 may be arranged in the same plane and spaced apart from each other by a predetermined distance. The first branch electrode BRC1, the second branch electrode BRC2 and the second connection line CNL2 may be integral with each other and electrically and / or physically connected to each other. In the case where the first branch electrode BRC1, the second branch electrode BRC2 and the second connection line CNL2 are integral with each other, each of the first branch electrode BRC1 and the second branch electrode BRC2 may be a predetermined area of ​​the second connection line CNL2. Therefore, the second driving power VSS transmitted to the second connection line CNL2 may be transmitted to each of the first branch electrode BRC1 and the second branch electrode BRC2.

[0175] The first branch electrode BRC1 and the second branch electrode BRC2 may be disposed at a position spaced apart from the first to third sub-electrodes PRT1 to PRT3 by a predetermined distance. In a plan view, the first branch electrode BRC1 and the second branch electrode BRC2 and the first to third sub-electrodes PRT1 to PRT3 may be alternately disposed in the first direction DR1. For example, in a plan view, the first sub-electrode PRT1 and the second sub-electrode PRT2 may be spaced apart from each other, and the first branch electrode BRC1 is inserted between the first sub-electrode PRT1 and the second sub-electrode PRT2 (or the first branch electrode BRC1 is disposed at an intermediate position between the first sub-electrode PRT1 and the second sub-electrode PRT2), and the second sub-electrode PRT2 and the third sub-electrode PRT3 may be spaced apart from each other, and the second branch electrode BRC2 is inserted between the second sub-electrode PRT2 and the third sub-electrode PRT3 (or the second branch electrode BRC2 is disposed at an intermediate position between the second sub-electrode PRT2 and the third sub-electrode PRT3).

[0176] The first connection line CNL1, the first to third sub-electrodes PRT1 to PRT3, the second connection line CNL2, and the first and second branch electrodes BRC1 and BRC2 may be disposed and / or formed on the same layer. In other words, the first connection line CNL1, the first to third sub-electrodes PRT1 to PRT3, the second connection line CNL2, and the first and second branch electrodes BRC1 and BRC2 may include the same material and be formed by the same process.

[0177] The first connection line CNL1, the first to third sub-electrodes PRT1 to PRT3, the second connection line CNL2, and the first and second branch electrodes BRC1 and BRC2 may be formed of a conductive material. The conductive material may include a metal, a conductive oxide, a conductive polymer such as PEDOT, etc. The material of each of the first connection line CNL1, the first to third sub-electrodes PRT1 to PRT3, the second connection line CNL2, and the first and second branch electrodes BRC1 and BRC2 is not limited to the above examples.

[0178] A first insulating layer INS1 may be disposed on the first connection line CNL1 , the first to third sub-electrodes PRT1 to PRT3 , the second connection line CNL2 , and the first and second branch electrodes BRC1 and BRC2 .

[0179] The first insulating layer INS1 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. The first insulating layer INS1 may protect the first connection line CNL1, the first to third sub-electrodes PRT1 to PRT3, the second connection line CNL2, and the first and second branch electrodes BRC1 and BRC2.

[0180] The first insulating layer INS1 may include first through holes VIA1 exposing corresponding predetermined regions of the first to third sub-electrodes PRT1 to PRT3 to the outside and second through holes VIA2 exposing corresponding predetermined regions of the first and second branch electrodes BRC1 and BRC2 .

[0181] In an embodiment of the present disclosure, in a cross-sectional view, the first insulating layer INS1 may change thickness in a region where it overlaps with the first electrode EL1 and the second electrode EL2. However, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may have a constant thickness regardless of whether the first insulating layer INS1 overlaps with the first electrode EL1 and the second electrode EL2. An embodiment in which the thickness of the first insulating layer INS1 changes in a region where the first insulating layer INS1 overlaps with the first electrode EL1 and the second electrode EL2 will be described in detail below in conjunction with the first electrode EL1 and the second electrode EL2.

[0182] The bank pattern PW may be a supporting portion or an insulating pattern that supports each of the first and second electrodes EL1 and EL2 to change a surface profile of each of the first and second electrodes EL1 and EL2 so that light emitted from the light emitting element LD may more efficiently travel in an image display direction of the display device.

[0183] The bank pattern PW may be disposed and / or formed on the first insulating layer INS1 of the emission area EMA of each of the pixels PXL. The bank pattern PW may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment, the bank pattern PW may include an organic insulating layer having a single-layer structure and / or an inorganic insulating layer having a single-layer structure, but the present disclosure is not limited thereto. For example, the bank pattern PW may have a multilayer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer.

[0184] The bank pattern PW may have a trapezoidal cross-section in which the width of the bank pattern PW decreases upward from one surface of the first insulating layer INS1, but the present disclosure is not limited thereto. Fig.10 As shown in , the bank pattern PW may include a curved surface having a cross-section such as a semi-elliptical cross-section, a semi-circular cross-section, etc., the width of which decreases upward from one surface of the first insulating layer INS1. In the cross-sectional view, the shape of the bank pattern PW is not limited to the aforementioned example, and may be changed in various ways as long as the efficiency of light emitted from each of the light emitting elements LD can be improved. Adjacent bank patterns PW may be arranged in the same plane on the passivation layer PSV and have the same height.

[0185] In an embodiment of the present disclosure, the bank pattern PW may be disposed and / or formed on the first insulating layer INS1 so as not to correspond to (or not to overlap) the first and second vias VIA1 and VIA2 of the first insulating layer INS1.

[0186] The display element layer DPL of each of the pixels PXL may further include a bank (not shown) disposed in a peripheral region of the corresponding pixel PXL (e.g., a non-emission region in which the light emitting element LD is not disposed) surrounding the emission region EMA of each pixel PXL. The bank may be a structure configured to define (or divide) each emission region EMA, and may be, for example, a pixel defining layer. The bank may include at least one light shielding material and / or a reflective material, and thus prevents the occurrence of a defect in which light (or rays) leaks between adjacent pixels PXL.

[0187] In an embodiment, a reflective material layer may be formed on the bank to further improve the efficiency of light emitted from each of the pixels PXL. Although the bank may be formed and / or disposed on a layer different from that of the bank pattern PW, the present disclosure is not limited thereto. In an embodiment, the bank and the bank pattern PW may be formed and / or disposed on the same layer.

[0188] Each of the first electrode EL1 and the second electrode EL2 may be disposed in the emission area EMA of each of the pixels PXL and / or formed on the bank pattern PW and the first insulating layer INS1. The first electrode EL1 and the second electrode EL2 may be disposed on the same surface and spaced apart from each other by a predetermined distance. In a plan view, one of the first electrodes EL1 and one of the second electrodes EL2 may be disposed in the same row. In a plan view, the first electrode EL1 and the second electrode EL2 may be alternately disposed in the first direction DR1 based on a row in the emission area EMA of each of the pixels PXL.

[0189] The first electrodes EL1 may be disposed in the second direction DR2. Each of the first electrodes EL1 may be spaced apart from adjacent first electrodes EL1 in the second direction DR2. In other words, each of the first electrodes EL1 may be electrically and / or physically separated from adjacent first electrodes EL1 in the second direction DR2. Each of the first electrodes EL1 may have a surface profile corresponding to the shape of the bank pattern PW disposed thereunder. For example, in a cross-sectional view, the bank pattern PW has a curved shape in which the width of the bank pattern PW decreases upward from one surface of the first insulating layer INS1. Therefore, each of the first electrodes EL1 disposed above the bank pattern PW may have a surface profile corresponding to a protruding shape.

[0190] Each of the first electrodes EL1 may have a surface area large enough to completely cover the corresponding bank pattern PW and the corresponding first through hole VIA1. Although in an embodiment of the present disclosure, each of the first electrodes EL1 may have a rectangular shape in a plan view, the present disclosure is not limited thereto. In an embodiment, the shape of the first electrode EL1 may be changed in various ways.

[0191] In an embodiment of the present disclosure, the first electrode EL1 may be disposed on the sub-electrode PRT and overlap with the sub-electrode PRT. For example, some of the first electrodes EL1 may be disposed on the first sub-electrode PRT1 and overlap with the first sub-electrode PRT1, some of the first electrodes EL1 may be disposed on the second sub-electrode PRT2 and overlap with the second sub-electrode PRT2, and other first electrodes EL1 may be disposed on the third sub-electrode PRT3 and overlap with the third sub-electrode PRT3. In the following embodiments, the first electrode EL1 disposed on the first sub-electrode PRT1 will be referred to as the 1-1 electrode EL1, the first electrode EL1 disposed on the second sub-electrode PRT2 will be referred to as the 1-2 electrode EL1, and the first electrode EL1 disposed on the third sub-electrode PRT3 will be referred to as the 1-3 electrode EL1.

[0192] In a plan view, the 1-1st electrode EL1 may be disposed above the first sub-electrode PRT1 in an extension direction of the first sub-electrode PRT1 and overlap the first sub-electrode PRT1. In a cross-sectional view, the 1-1st electrode EL1 may be disposed on the first sub-electrode PRT1, and the first insulating layer INS1 and the bank pattern PW are interposed between the 1-1st electrode EL1 and the first sub-electrode PRT1. Each of the 1-1st electrodes EL1 may be electrically and / or physically connected to the first sub-electrode PRT1 disposed thereunder through a corresponding first through hole VIA1 passing through the first insulating layer INS1. Therefore, a signal (or voltage) applied to the first sub-electrode PRT1 may be transmitted to the 1-1st electrode EL1.

[0193] In a plan view, the 1-2nd electrode EL1 may be disposed above the second sub-electrode PRT2 in the extension direction of the second sub-electrode PRT2 and overlap the second sub-electrode PRT2. In a cross-sectional view, the 1-2nd electrode EL1 may be disposed on the second sub-electrode PRT2, and the first insulating layer INS1 and the bank pattern PW are interposed between the 1-2nd electrode EL1 and the second sub-electrode PRT2. Each of the 1-2nd electrodes EL1 may be electrically and / or physically connected to the second sub-electrode PRT2 disposed thereunder through a corresponding first through hole VIA1 passing through the first insulating layer INS1. Therefore, a signal (or voltage) applied to the second sub-electrode PRT2 may be transmitted to the 1-2nd electrode EL1.

[0194] In a plan view, the 1-3rd electrode EL1 may be disposed on the third sub-electrode PRT3 along the extension direction of the third sub-electrode PRT3 and overlap the third sub-electrode PRT3. In a cross-sectional view, the 1-3rd electrode EL1 may be disposed on the third sub-electrode PRT3, and the first insulating layer INS1 is interposed between the 1-3rd electrode EL1 and the third sub-electrode PRT3. Each of the 1-3rd electrodes EL1 may be electrically and / or physically connected to the third sub-electrode PRT3 disposed thereunder through a corresponding first through hole VIA1 passing through the first insulating layer INS1. Therefore, a signal (or voltage) applied to the third sub-electrode PRT3 may be transmitted to the 1-3rd electrode EL1.

[0195] As described above, each of the first electrodes EL1 may be electrically and / or physically connected to the corresponding sub-electrode PRT through a corresponding first through hole VIA1 among the first through holes VIA1 passing through the first insulating layer INS1. Although it has been described in the foregoing embodiment that each of the first electrodes EL1 is electrically and / or physically connected to the corresponding sub-electrode PRT through one first through hole VIA1, the present disclosure is not limited thereto. In an embodiment, each of the first electrodes EL1 may be electrically and / or physically connected to the corresponding sub-electrode PRT through at least one first through hole VIA1.

[0196] In an embodiment of the present disclosure, each of the first to third sub-electrodes PRT1 to PRT3 may be divided into a first region A overlapping with each of the first electrodes EL1 and a second region B excluding the first region A. Here, the second region B may refer to a portion in which each of the first to third sub-electrodes PRT1 to PRT3 does not overlap with the first electrode EL1.

[0197] A thickness d1 of the first insulating layer INS1 corresponding to the first region A of each of the first to third sub-electrodes PRT1 to PRT3 may be different from a thickness d2 of the first insulating layer INS1 corresponding to the second region B of each of the first to third sub-electrodes PRT1 to PRT3 .

[0198] In an embodiment of the present disclosure, a thickness d1 of the first insulating layer INS1 corresponding to the first region A of each of the first to third sub-electrodes PRT1 to PRT3 may be less than a thickness d2 of the first insulating layer INS1 corresponding to the second region B of each of the first to third sub-electrodes PRT1 to PRT3. In other words, the first insulating layer INS1 corresponding to the second region B of each of the first to third sub-electrodes PRT1 to PRT3 may be designed to have a thickness greater than a thickness of the first insulating layer INS1 corresponding to the first region A of each of the first to third sub-electrodes PRT1 to PRT3.

[0199] The second electrodes EL2 may be arranged in the second direction DR2. Each of the second electrodes EL2 may be spaced apart from an adjacent second electrode EL2 in the second direction DR2. In other words, each of the second electrodes EL2 may be electrically and / or physically separated from an adjacent second electrode EL2 in the second direction DR2. Each of the second electrodes EL2 may have a surface profile corresponding to the shape of the bank pattern PW arranged thereunder. For example, in a cross-sectional view, the bank pattern PW has a protruding shape in which the width of the bank pattern PW decreases upward from one surface of the first insulating layer INS1. Therefore, each of the second electrodes EL2 arranged on the bank pattern PW may have a surface profile corresponding to the protruding shape.

[0200] Each of the second electrodes EL2 may have a large surface area sufficient to completely cover the corresponding bank pattern PW and the corresponding second through hole VIA2. Although in an embodiment of the present disclosure, each of the second electrodes EL2 may have a rectangular shape in a plan view, the present disclosure is not limited thereto. In an embodiment, the shape of the second electrode EL2 may be changed in various ways. In addition, the second electrode EL2 may have the same shape as the first electrode EL1, but the present disclosure is not limited thereto. In an embodiment, the second electrode EL2 may have a shape different from that of the first electrode EL1. In addition, the second electrode EL2 may have the same size (or surface area) as the size (or surface area) of the first electrode EL1, but the present disclosure is not limited thereto. In an embodiment, the second electrode EL2 may have a size (or surface area) different from that of the first electrode EL1.

[0201] In an embodiment of the present disclosure, the second electrode EL2 may be disposed on the branch electrode BRC and overlap with the branch electrode BRC. For example, some of the second electrodes EL2 may be disposed on the first branch electrode BRC1 and overlap with the first branch electrode BRC1, and other second electrodes EL2 may be disposed on the second branch electrode BRC2 and overlap with the second branch electrode BRC2. In the following embodiments, the second electrode EL2 disposed on the first branch electrode BRC1 will be referred to as the 2-1st electrode EL2, and the second electrode EL2 disposed on the second branch electrode BRC2 will be referred to as the 2-2nd electrode EL2.

[0202] In the plan view, the 2-1st electrode EL2 may be disposed above the first branch electrode BRC1 in the extension direction of the first branch electrode BRC1 and overlap the first branch electrode BRC1. In the cross-sectional view, the 2-1st electrode EL2 may be disposed on the first branch electrode BRC1, and the first insulating layer INS1 is interposed between the 2-1st electrode EL2 and the first branch electrode BRC1. Each of the 2-1st electrodes EL2 may be electrically and / or physically connected to the first branch electrode BRC1 disposed thereunder through a second through hole VIA2 passing through the first insulating layer INS1. Therefore, the second driving power VSS applied to the first branch electrode BRC1 may be transmitted to the 2-1st electrode EL2.

[0203] In the plan view, the 2-2 electrode EL2 may be disposed on the second branch electrode BRC2 in the extension direction of the second branch electrode BRC2 and overlap the second branch electrode BRC2. In the cross-sectional view, the 2-2 electrode EL2 may be disposed on the second branch electrode BRC2, and the first insulating layer INS1 is interposed between the 2-2 electrode EL2 and the second branch electrode BRC2. Each of the 2-2 electrodes EL2 may be electrically and / or physically connected to the second branch electrode BRC2 disposed thereunder through the second through hole VIA2 passing through the first insulating layer INS1. Therefore, the second driving power VSS applied to the second branch electrode BRC2 may be transmitted to the 2-2 electrode EL2.

[0204] As described above, each of the second electrodes EL2 may be electrically and / or physically connected to the corresponding branch electrode BRC through a corresponding second through hole VIA2 in the second through holes VIA2 passing through the first insulating layer INS1. Although it has been described in the foregoing embodiments that each of the second electrodes EL2 is electrically and / or physically connected to the corresponding branch electrode BRC through the second through hole VIA2, the present disclosure is not limited thereto. In an embodiment, each of the second electrodes EL2 may be electrically and / or physically connected to the corresponding branch electrode BRC through at least one second through hole VIA2.

[0205] In an embodiment of the present disclosure, each of the first branch electrode BRC1 and the second branch electrode BRC2 may be divided into a third region C overlapping each of the second electrodes EL2 and a fourth region D excluding the third region C. Here, the fourth region D may refer to a portion in which each of the first branch electrode BRC1 and the second branch electrode BRC2 does not overlap the second electrode EL2.

[0206] A thickness d1 of the first insulating layer INS1 corresponding to the third region C of each of the first and second branch electrodes BRC1 and BRC2 may be different from a thickness d2 of the first insulating layer INS1 corresponding to the fourth region D of each of the first and second branch electrodes BRC1 and BRC2.

[0207] In an embodiment of the present disclosure, a thickness d1 of the first insulating layer INS1 corresponding to the third region C of each of the first branch electrode BRC1 and the second branch electrode BRC2 may be smaller than a thickness d2 of the first insulating layer INS1 corresponding to the fourth region D of each of the first branch electrode BRC1 and the second branch electrode BRC2. In other words, the first insulating layer INS1 corresponding to the fourth region D of each of the first branch electrode BRC1 and the second branch electrode BRC2 may be designed to have a thickness greater than a thickness of the first insulating layer INS1 corresponding to the third region C of each of the first branch electrode BRC1 and the second branch electrode BRC2. The reason for this is to prevent the light emitting element LD from being aligned in a region between the fourth region D of each of the first branch electrode BRC1 and the second branch electrode BRC2 and the second region B of each of the first sub-electrode PRT1 to the third sub-electrode PRT3 by reducing the intensity of an electric field formed between the first branch electrode BRC1 and the second branch electrode BRC2 and the first sub-electrode PRT1 to the third sub-electrode PRT3. In other words, the reason why the first insulating layer INS1 is designed to have different thicknesses by region is to prevent the light emitting element LD in the emission area EMA of each of the pixels PXL from being aligned in a region other than a target region (eg, a region between the first electrode EL1 and the second electrode EL2 ).

[0208] Although it has been described in the foregoing embodiment that the first insulating layer INS1 has different thicknesses by region, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may have a constant thickness regardless of the region.

[0209] In an embodiment of the present disclosure, the first to third sub-electrodes PRT1 to PRT3 and the first and second branch electrodes BRC1 and BRC2 may be used as alignment voltage applying electrodes for transmitting an alignment voltage to the first and second electrodes EL1 and EL2. The first and second electrodes EL1 and EL2 may be used as alignment electrodes for aligning the light emitting element LD in the emission area EMA of each of the pixels PXL.

[0210] Before aligning the light emitting element LD in the emission area EMA of each of the pixels PXL, a first alignment voltage may be applied to the first to third sub-electrodes PRT1 to PRT3 through the first connection line CNL1, and a second alignment voltage may be applied to the first and second branch electrodes BRC1 and BRC2 through the second connection line CNL2.

[0211] In the case where the first alignment voltage is applied to each of the first to third sub-electrodes PRT1 to PRT3, the first alignment voltage may be applied to each of the first electrodes EL1 through the first through hole VIA1 passing through the first insulating layer INS1. In the case where the second alignment voltage is applied to each of the first branch electrode BRC1 and the second branch electrode BRC2, the second alignment voltage may be applied to each of the second electrodes EL2 through the second through hole VIA2 of the first insulating layer INS1. The first alignment voltage and the second alignment voltage may have different voltage levels. For example, the first alignment voltage may be a ground voltage, and the second alignment voltage may be an AC voltage.

[0212] When predetermined alignment voltages having different voltage levels are respectively applied to the first and second electrodes EL1 and EL2 , the light emitting element LD may be aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 .

[0213] After aligning the light emitting element LD in the emission area EMA of each of the pixels PXL, each of the first electrode EL1 and the second electrode EL2 may function as a driving electrode for driving the light emitting element LD.

[0214] Each of the first electrode EL1 and each of the second electrode EL2 may be made of a material having a predetermined reflectivity to allow light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD to travel in an image display direction of the display device (e.g., in a forward direction). In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may have the same material and be formed by the same process. In other words, the first electrode EL1 and the second electrode EL2 may be disposed on the same layer.

[0215] The first electrode EL1 and the second electrode EL2 may be made of a conductive material having a predetermined reflectivity. The conductive material may include a metal (such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti or an alloy thereof), a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium tin zinc oxide (ITZO)) and a conductive polymer (such as PEDOT). The material of each of the first electrode EL1 and the second electrode EL2 is not limited to the aforementioned materials. In addition, in an embodiment, the first electrode EL1 and the second electrode EL2 may be formed of the same material as the first connection line CNL1 and the second connection line CNL2.

[0216] Each of the first electrode EL1 and the second electrode EL2 may be formed of a single layer, but the present disclosure is not limited thereto. In an embodiment, the first electrode EL1 and the second electrode EL2 may be formed as a multilayer structure formed by stacking two or more materials of metal, alloy, conductive oxide and conductive polymer. Each of the first electrode EL1 and the second electrode EL2 may be formed of a multilayer structure including at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to the opposite ends EP1 and EP2 of each of the light emitting elements LD. For example, each of the first electrode EL1 and the second electrode EL2 may be formed of a multilayer structure in which layers are stacked in the order of ITO / Ag / ITO.

[0217] As described above, since each of the first electrode EL1 and the second electrode EL2 has a surface profile corresponding to the shape of the bank pattern PW disposed thereunder, light emitted from the opposite ends EP1 and EP2 of each of the light emitting elements LD can be reflected by the first electrode EL1 and the second electrode EL2 and more efficiently travel in the image display direction of the display device. Therefore, the efficiency of light emitted from each of the light emitting elements LD can be further improved.

[0218] In an embodiment of the present disclosure, the bank pattern PW and the first electrode EL1 and the second electrode EL2 may be used as a reflective component configured to guide the light emitted from the light emitting element LD in a desired direction, and thus improve the light efficiency of the display device. In other words, the bank pattern PW and the first electrode EL1 and the second electrode EL2 may be used as a reflective component configured to enable the light emitted from the light emitting element LD to travel in the image display direction of the display device, thereby improving the light output efficiency of the light emitting element LD.

[0219] One of the first electrode EL1 and the second electrode EL2 may be an anode electrode, and the other electrode may be a cathode electrode. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0220] Each of the light emitting elements LD may be formed of a light emitting diode made of a material having an inorganic crystal structure and having an ultra-small size corresponding to, for example, a nano-scale size or a micro-scale size. The light emitting element LD may be aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 in each of the pixels PXL.

[0221] Although at least two to several tens of light emitting elements LD may be aligned in the emission area EMA of each of the pixels PXL, according to an embodiment, the number of light emitting elements LD aligned in the emission area EMA of each pixel PXL may vary without limitation.

[0222] Each of the light emitting elements LD may include a cylindrical light emitting element LD manufactured by an etching method, such as Figure 1a , Figure 1c and Figure 1e As shown in, or a light-emitting element LD having a core-shell structure and manufactured by a growth method, such as Figure 1g as shown in .

[0223] In the case where each of the light emitting elements LD is a cylindrical light emitting element LD, each of the light emitting elements LD may include an emission stack (or stacking pattern) formed by sequentially stacking a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an electrode layer 15 in a longitudinal direction of the light emitting element LD. In the case where each of the light emitting elements LD is a light emitting element LD having a core-shell structure, each of the light emitting elements LD may include an emission pattern 10 having a first semiconductor layer 11 disposed in a central portion of the light emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an electrode layer 15 surrounding at least one side of the second semiconductor layer 13.

[0224] Each of the light emitting elements LD may include a first end portion EP1 and a second end portion EP2. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the first end portion EP1 of each of the light emitting elements LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed on the second end portion EP2 of each of the light emitting elements LD. Each of the light emitting elements LD may emit colored light or white light.

[0225] The light emitting element LD may be aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 by an electric field formed between the first electrodes EL1 and the second electrodes EL2 in the emission area EMA of each of the pixels PXL.

[0226] Specifically, after an electric field has been formed between the first electrode EL1 and the second electrode EL2, the light-emitting element LD may be input into the emission area EMA of each of the pixels PXL by spraying and / or applying a fluid solvent mixed with the light-emitting element LD by an inkjet printing method or the like. In an embodiment of the present disclosure, the solvent may be any one or more of acetone, water, ethanol and toluene, but the present disclosure is not limited thereto. For example, the solvent may include a material that can evaporate at room temperature or by heating. In addition, the solvent may have the form of ink or paste. The method of spraying and / or applying the light-emitting element LD is not limited to the method of the aforementioned embodiment. The method of spraying and / or applying the light-emitting element LD may be changed in various ways. After the light-emitting element LD has been input into the emission area EMA of each of the pixels PXL, the solvent may be removed.

[0227] In the case where the light emitting element LD is input into the emission area EMA of each of the pixels PXL, the self-alignment of the light emitting element LD may be caused by the electric field formed between the first electrode EL1 and the second electrode EL2. Therefore, the light emitting element LD may be aligned between the first electrode EL1 and the second electrode EL2. In other words, the light emitting element LD may be aligned only in the target area (e.g., the area between at least one of the first electrodes EL1 and at least one of the second electrodes EL2) in the emission area EMA of each of the pixels PXL.

[0228] One of the opposite ends EP1 and EP2 of each of the light emitting elements LD may be electrically connected to at least one of the first electrodes EL1, and the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD may be electrically connected to at least one of the second electrodes EL2. Therefore, the signal (or voltage) of the first transistor T1 (T) of the pixel circuit layer PCL of each of the pixels PXL may be applied to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD via the first electrode EL1. The second driving power source VSS of the driving voltage line DVL may be applied to the other end via the second electrode EL2.

[0229] The light emitting element LD may form a light source of each of the pixels PXL. For example, if a driving current flows through each of the pixels PXL during each frame period, the light emitting element LD electrically connected to the first and second electrodes EL1 and EL2 of each pixel PXL may emit light having brightness corresponding to the driving current.

[0230] The above-described light emitting element LD may be aligned in the emission area EMA of each of the pixels PXL on the second insulating layer INS2 .

[0231] In the emission area EMA of each of the pixels PXL, a second insulating layer INS2 may be formed between the first electrode EL1 and the second electrode EL2 and / or disposed under each of the light emitting elements LD. The second insulating layer INS2 may fill the space between each of the light emitting elements LD and the first insulating layer INS1, thereby stably supporting the light emitting element LD and preventing the light emitting element LD from being removed from the first insulating layer INS1.

[0232] In the emission area EMA of each of the pixels PXL, the second insulating layer INS2 may expose a predetermined area of ​​each of the first electrodes EL1, and cover the remaining area of ​​each of the first electrodes EL1 except the exposed predetermined area, so as to protect the remaining area of ​​each of the first electrodes EL1. In addition, the second insulating layer INS2 may expose a predetermined area of ​​each of the second electrodes EL2, and cover the remaining area of ​​each of the second electrodes EL2 except the exposed predetermined area, so as to protect the remaining area of ​​each of the second electrodes EL2. In addition, the second insulating layer INS2 may be disposed in and / or formed on the first insulating layer INS1 in the peripheral area of ​​each of the pixels PXL, and thus protect components disposed in the peripheral area, for example, the first connection line CNL1 and the second connection line CNL2.

[0233] The second insulating layer INS2 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the second insulating layer INS2 may be formed of an inorganic insulating layer having an advantage in protecting the light emitting element LD from the pixel circuit layer PCL of each of the pixels PXL, the present disclosure is not limited thereto. In an embodiment, the second insulating layer INS2 may be formed of an organic insulating layer having an advantage in planarizing the support surface of the light emitting element LD.

[0234] A third insulating layer INS3 may be disposed and / or formed on the light emitting element LD. The third insulating layer INS3 may be disposed and / or formed on each of the light emitting elements LD to cover a portion of the upper surface of each of the light emitting elements LD and expose the opposite ends EP1 and EP2 of each of the light emitting elements LD to the outside. The third insulating layer INS3 may be formed in an independent pattern in the emission area EMA of each of the pixels PXL, but the present disclosure is not limited thereto. In an embodiment, the third insulating layer INS3 may be omitted. In this case, the first contact electrode CNE1 may be in direct contact with one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The second contact electrode CNE2 may be in direct contact with the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD. Here, the first contact electrode CNE1 and the second contact electrode CNE2 may be electrically disconnected from each other.

[0235] The third insulating layer INS3 may be formed of a single layer or a multilayer, and include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The third insulating layer INS3 may fix each of the light emitting elements LD aligned in the emission area EMA of each of the pixels PXL in place. In an embodiment of the present disclosure, the third insulating layer INS3 may include an inorganic insulating layer having advantages in protecting the active layer 12 of each of the light emitting elements LD from external oxygen, water, etc. However, the present disclosure is not limited thereto. Depending on the design conditions of the display device to which the light emitting element LD is applied, etc., the third insulating layer INS3 may be formed of an organic insulating layer including an organic material.

[0236] In an embodiment of the present disclosure, after the alignment of the light emitting element LD in the emission area EMA of each of the pixels PXL has been completed, a third insulating layer INS3 is formed on the light emitting element LD so that the light emitting element LD can be prevented from being removed from the aligned position. If there is a space (or gap) between the second insulating layer INS2 and the light emitting element LD before the third insulating layer INS3 is formed, the space (or gap) can be filled with the third insulating layer INS3 during the process of forming the third insulating layer INS3. Therefore, the light emitting element LD can be stably supported. In this case, the third insulating layer INS3 can be formed of an organic insulating layer that has an advantage in filling the space (or gap) between the second insulating layer INS2 and the light emitting element LD with the third insulating layer INS3.

[0237] In an embodiment of the present disclosure, a third insulating layer INS3 may be formed on each of the light emitting elements LD so that the active layer 12 of each light emitting element LD can be prevented from contacting an external conductive material. The third insulating layer INS3 may cover only a portion of the upper surface of each of the light emitting elements LD so that opposite ends EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0238] In an embodiment of the present disclosure, after aligning the light emitting element LD in the emission area EMA of each of the pixels PXL, during the process of forming the second insulating layer INS2 and the third insulating layer INS3, the first connection line CNL1 may be separated between adjacent pixels PXL. A portion of the first connection line CNL1 commonly provided in the pixels PXL disposed in the same row may be removed between the adjacent pixels PXL by a method such as a laser cutting method or an etching method for removing a portion of a conductive layer, so that each pixel PXL may be driven separately (or independently) from the adjacent pixels PXL.

[0239] As described above, after aligning the light emitting element LD in the emission area EMA of each pixel PXL, the first connection line CNL1 of each pixel PXL can be electrically connected to the pixel circuit 144 of the corresponding pixel PXL, so that the first driving power VDD through the pixel circuit 144 can be transmitted to the first electrode EL1, thereby driving the light emitting element LD.

[0240] The first contact electrode CNE1 may be disposed on the first electrode EL1 of each of the pixels PXL to reliably electrically and / or reliably physically connect each of the first electrodes EL1 to one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The second contact electrode CNE2 may be disposed on the second electrode EL2 of each of the pixels PXL to reliably electrically and / or reliably physically connect each of the second electrodes EL2 to the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0241] Each of the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of various transparent conductive materials. For example, each of the first contact electrode CNE1 and the second contact electrode CNE2 may be formed of a transparent conductive material for minimizing the loss of light emitted from each of the light emitting elements LD and reflected by the corresponding electrode in the image display direction of the display device. The transparent conductive material may include at least one of various conductive materials (e.g., ITO, IZO, and ITZO), and may be substantially transparent or translucent to satisfy a predetermined transmittance.

[0242] Each of the first contact electrode CNE1 and the second contact electrode CNE2 may have a rod shape extending in the second direction DR2. The first contact electrode CNE1 may partially overlap one of the opposite ends EP1 and EP2 of each of the light emitting elements LD. The second contact electrode CNE2 may partially overlap the other of the opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0243] In an embodiment of the present disclosure, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on corresponding different layers. In this case, the first contact electrode CNE1 may be disposed and / or formed on the third insulating layer INS3 and covered by the fourth insulating layer INS4. In addition, the second contact electrode CNE2 may be disposed and / or formed on the fourth insulating layer INS4 and covered by the fifth insulating layer INS5. The fourth insulating layer INS4 and the fifth insulating layer INS5 may be formed of any insulating layer of an inorganic insulating layer including an inorganic material and an organic insulating layer including an organic material. An overcoat layer OC may be disposed and / or formed on the fifth insulating layer INS5.

[0244] Although it has been described in the foregoing embodiments that the first contact electrode CNE1 and the second contact electrode CNE2 are disposed and / or formed on respective different layers, the present disclosure is not limited thereto. In embodiments, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed and / or formed on the same layer, such as Figure 8 In this case, the first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other by a predetermined distance on the third insulating layer INS3 and thus electrically and physically separated from each other, and may be covered by the fourth insulating layer INS4. An overcoat layer OC may be disposed and / or formed on the fourth insulating layer INS4.

[0245] The overcoat layer OC may be an encapsulation layer configured to relieve a step difference formed by the bank pattern PW, the first to third sub-electrodes PRT1 to PRT3, the first and second branch electrodes BRC1 and BRC2, the first and second electrodes EL1 and EL2, the first and second contact electrodes CNE1 and CNE2, etc., and prevent oxygen or water from penetrating the light emitting element LD. In an embodiment, the overcoat layer OC may be omitted in consideration of design conditions of the display device, etc.

[0246] As described above, a predetermined voltage is applied to the opposite ends EP1 and EP2 of each of the light emitting elements LD through the first electrode EL1 and the second electrode EL2, so that each of the light emitting elements LD can emit light by coupling of electron-hole pairs in the active layer 12 of each of the light emitting elements LD. Each of the light emitting elements LD can emit light having a wavelength band of, for example, 400 nm to 900 nm.

[0247] In an embodiment, in the emission area EMA of each of the pixels PXL, a cover layer CPL may be disposed and / or formed, such as Figure 7 as shown in .

[0248] In a plan view, the cover layer CPL may be disposed between each of the first electrodes EL1 and the first contact electrode CNE1 and between each of the second electrodes EL2 and the second contact electrode CNE2 , respectively.

[0249] The cover layer CPL may prevent the respective first and second electrodes EL1 and EL2 from being damaged by defects or the like caused during a process of manufacturing the display device, and enhance adhesion between the respective first and second electrodes EL1 and EL2 and the first insulating layer INS1. The cover layer CPL may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize loss of light emitted from each of the light emitting elements LD and reflected by the respective first and second electrodes EL1 and EL2 in an image display direction of the display device.

[0250] In an embodiment of the present disclosure, each of the first electrodes EL1 may have a width greater (or longer) than that of the sub-electrode PRT in one direction (e.g., in the first direction DR1) to completely cover the corresponding sub-electrode PRT disposed below each of the first electrodes EL1. Each of the second electrodes EL2 may have a width greater (or longer) than that of the branch electrode BRC in one direction (e.g., in the first direction DR1) to completely cover the corresponding branch electrode BRC disposed below the second electrode EL2. In the case where each of the first electrode EL1 and the second electrode EL2 has a large (or long) width in one direction, the width W1 between at least one first electrode EL1 and at least one second electrode EL2 disposed in the same row in the emission area EMA of each of the pixels PXL may be reduced.

[0251] Here, if corresponding alignment voltages are applied to the first to third sub-electrodes PRT1 to PRT3 and the first branch electrode BRC1 and the second branch electrode BRC2 through the first connecting line CNL1 and the second connecting line CNL2, respectively, an electric field can be formed in each of the areas between the first electrode EL1 and the second electrode EL2, the area between the first sub-electrode PRT1 and the first branch electrode BRC1, the area between the first branch electrode BRC1 and the second sub-electrode PRT2, the area between the second sub-electrode PRT2 and the second branch electrode BRC2, and the area between the second branch electrode BRC2 and the third sub-electrode PRT3.

[0252] In an embodiment of the present disclosure, an electric field having a strength greater than that of an electric field formed between at least one sub-electrode PRT and at least one branch electrode BRC may be formed between at least one of the first electrodes EL1 and at least one second electrode EL2 disposed in the same row as the at least one first electrode EL1. The reason for this is due to the fact that a width W1 between at least one first electrode EL1 and at least one second electrode EL2 disposed in the same row is smaller than (or shorter than) a width W2 between at least one sub-electrode PRT and at least one branch electrode BRC.

[0253] In addition, although the first insulating layer INS1 and the second insulating layer INS2 are sequentially stacked on at least one sub-electrode PRT and at least one branch electrode BRC, only the second insulating layer INS2 is arranged on the first electrode EL1 and the second electrode EL2, so that the intensity of the electric field formed between the first electrode EL1 and the second electrode EL2 can be relatively increased.

[0254] In the case where the light emitting element LD is input into the emission area EMA of each of the pixels PXL, the light emitting element LD may be densely aligned between at least one first electrode EL1 and at least one second electrode EL2, wherein an electric field with a relatively high intensity is formed between the first electrode EL1 and the second electrode EL2. In other words, in the emission area EMA of each of the pixels PXL, the light emitting element LD may be densely aligned only in the area where an electric field with a relatively high intensity is formed, and not in the area where an electric field with a relatively low intensity is formed. Therefore, in the emission area EMA of each of the pixels PXL, the light emitting element LD may be densely aligned only in the target area (for example, in the area between the first electrode EL1 and the second electrode EL2). Therefore, the alignment distribution of the light emitting elements LD of the pixel PXL may become uniform, so that the intensity (or amount) of the light emitted from the emission area EMA of the corresponding pixel PXL may be substantially the same or similar to each other. Therefore, the display device in the embodiment of the present disclosure may have a uniform emission distribution throughout its entire area.

[0255] Furthermore, in the emission area EMA of each of the pixels PXL, the light emitting elements LD may be densely aligned only in a target area, so that an abnormal alignment defect causing the light emitting elements LD to be aligned in an undesired area may be prevented.

[0256] Furthermore, since the light emitting elements LD are densely aligned only in a target area in the emission area EMA of each of the pixels PXL, contact defects between each of the light emitting elements LD and electrodes electrically and / or physically connected to the light emitting elements LD can be minimized.

[0257] Figures 12a to 12i It is shown in sequence that the manufacturing Figure 4 A schematic plan view of the pixel approach shown in FIG. Figures 13a to 13n It is shown in sequence that the manufacturing Figure 6 A cross-sectional view of a method of displaying a device as shown in FIG.

[0258] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.12a and Fig.13a , a pixel circuit layer PCL of each of the pixels PXL is formed on the substrate SUB. Each of the pixels PXL may include an emission area EMA and a peripheral area disposed around the emission area EMA.

[0259] The pixel circuit layer PCL may include a first transistor T1 (T), a second transistor T2 (T), a driving voltage line DVL, a shielding electrode line SDL, and a passivation layer PSV.

[0260] A predetermined area of ​​the second terminal DE of the first transistor T1 (T) can be exposed to the outside through a first contact hole CH1 passing through the passivation layer PSV and the second interlayer insulating layer ILD2. In addition, a predetermined area of ​​the driving voltage line DVL can be exposed to the outside through a second contact hole CH2 passing through the passivation layer PSV and the second interlayer insulating layer ILD2.

[0261] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Figure 12b , Fig.13a and Fig.13b , first and second connection lines CNL1 and CNL2 , first to third sub-electrodes PRT1 to PRT3 , and first and second branch electrodes BRC1 and BRC2 are formed on the passivation layer PSV in the emission area EMA of each of the pixels PXL.

[0262] Each of the first and second connection lines CNL1 and CNL2 may be provided in common to the pixels PXL disposed in the same row. In other words, the pixels PXL disposed in the same row may be electrically connected in common to the first and second connection lines CNL1 and CNL2.

[0263] The first to third sub-electrodes PRT1 to PRT3 may be integral with the first connection line CNL1, and may be branched from the first connection line CNL1 in the second direction DR2 and disposed in the emission area EMA of each of the pixels PXL. The second sub-electrode PRT2 may be electrically connected to the second terminal DE of the first transistor T1 (T) of the pixel circuit layer PCL of each of the pixels PXL through the first contact hole CH1.

[0264] The first branch electrode BRC1 and the second branch electrode BRC2 may be integral with the second connection line CNL2, and may be branched from the second connection line CNL2 in the second direction DR2 and disposed in the emission area EMA of each of the pixels PXL. The second connection line CNL2 may be electrically connected to the driving voltage line DVL of the pixel circuit layer PCL of each of the pixels PXL through the second contact hole CH2.

[0265] The first to third sub-electrodes PRT1 to PRT3 and the first and second branch electrodes BRC1 and BRC2 may be disposed at positions spaced apart from each other by a predetermined distance and may be electrically and / or physically separated from each other. In a plan view, the first to third sub-electrodes PRT1 to PRT3 and the first and second branch electrodes BRC1 and BRC2 may be alternately disposed in a first direction DR1.

[0266] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.12c , Figures 13a to 13c , an insulating material layer (not shown) is deposited on the passivation layer PSV including the first to third sub-electrodes PRT1 to PRT3, the first and second branch electrodes BRC1 and BRC2, and the first and second connection lines CNL1 and CNL2. Subsequently, after a half-tone mask (not shown) is disposed on the insulating material layer, the insulating material layer is patterned by a mask process to form a first insulating layer INS1 including the first through hole VIA1 and the second through hole VIA2.

[0267] The first through holes VIA1 of the first insulating layer INS1 may expose corresponding predetermined regions of the first to third sub-electrodes PRT1 to PRT3 , and the second through holes VIA2 of the first insulating layer INS1 may expose corresponding predetermined regions of the first and second branch electrodes BRC1 and BRC2 .

[0268] In an embodiment of the present disclosure, the first insulating layer INS1 may have different thicknesses by region. The first insulating layer INS1 on a predetermined region of at least one sub-electrode PRT overlapping with the first electrode EL1 to be formed during a process described below may have a thickness smaller than the thickness of the first insulating layer INS1 on another region of the sub-electrode PRT that does not overlap with the first electrode EL1. In addition, the first insulating layer INS1 on a predetermined region of at least one branch electrode BRC overlapping with the second electrode EL2 to be formed during the same process as that of the first electrode EL1 may have a thickness smaller than the thickness of the first insulating layer INS1 on another region of the branch electrode BRC that does not overlap with the second electrode EL2.

[0269] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.12d as well as Figures 13a to 13d , a bank pattern PW is formed on the first insulating layer INS1. The bank pattern PW may be spaced apart from adjacent bank patterns PW on the first insulating layer INS1 by a predetermined distance. The bank pattern PW may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0270] In a plan view, the bank pattern PW may overlap with each of the corresponding sub-electrode PRT and the corresponding branch electrode BRC. In addition, the bank pattern PW does not overlap with each of the first through holes VIA1 exposing a predetermined area of ​​the corresponding sub-electrode PRT, and does not overlap with each of the second through holes VIA2 exposing a predetermined area of ​​the corresponding branch electrode BRC.

[0271] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.12e as well as Figures 13a to 13e , the first electrode EL1 and the second electrode EL2 are formed on the first insulating layer INS1 having the bank pattern PW formed thereon.

[0272] Each of the first electrodes EL1 may be spaced apart from an adjacent first electrode EL1 by a predetermined distance in the second direction DR2. In addition, each of the first electrodes EL1 may be spaced apart from the second electrode EL2 by a predetermined distance. In an embodiment of the present disclosure, in a plan view, at least one of the first electrodes EL1 may be disposed in the same row as a row of at least one of the second electrodes EL2.

[0273] In a plan view, each of the first electrodes EL1 may be disposed on and overlap a corresponding bank pattern PW. In addition, each of the first electrodes EL1 may be disposed on and overlap a corresponding sub-electrode PRT. Each of the first electrodes EL1 may be electrically and / or physically connected to a corresponding sub-electrode PRT disposed therebelow through a corresponding first through hole VIA1.

[0274] Each of the second electrodes EL2 may be disposed on a corresponding bank pattern PW and overlap with the corresponding bank pattern PW in a plan view. In addition, each of the second electrodes EL2 may be disposed on a corresponding branch electrode BRC and overlap with the branch electrode BRC. Each of the second electrodes EL2 may be electrically and / or physically connected to a corresponding branch electrode BRC disposed therebelow through a corresponding second through hole VIA2.

[0275] In a plan view, each of the first electrode EL1 and the second electrode EL2 may have a rectangular shape. In an embodiment of the present disclosure, each of the first electrodes EL1 may have a width greater (or longer) than the width of the sub-electrode PRT in one direction (e.g., in the first direction DR1) to completely cover a predetermined area of ​​at least one sub-electrode PRT. Each of the second electrodes EL2 may have a width greater (or longer) than the width of the branch electrode BRC in the first direction DR1 to completely cover a predetermined area of ​​at least one branch electrode BRC.

[0276] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 as well as Figures 13a to 13f A first insulating material layer INSM1 is formed on the entire surface of the first insulating layer INS1 on which the first and second electrodes EL1 and EL2 are formed. The first insulating material layer INSM1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0277] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.12f and Figures 13a to 13g An electric field is formed between the first electrode EL1 and the second electrode EL2 by applying an alignment voltage to the first electrode EL1 and the second electrode EL2 through the first connection line CNL1 and the second connection line CNL2, respectively.

[0278] When DC power having a predetermined voltage or AC power having a predetermined cycle is repeatedly applied to each of the first and second electrodes EL1 and EL2 through the first and second connection lines CNL1 and CNL2 , an electric field may be formed between the first and second electrodes EL1 and EL2 .

[0279] After the electric field has been formed between the first electrode EL1 and the second electrode EL2, a solvent including the light emitting element LD is input by an inkjet printing method or the like. For example, by providing a nozzle (not shown) on the first insulating layer INS1 and ejecting the solvent including the light emitting element LD through the nozzle, the light emitting element LD may be input into the emission area EMA of each of the pixels PXL. In the case where the light emitting element LD is input into the emission area EMA of each of the pixels PXL, the self-alignment of the light emitting element LD may be caused by the electric field formed between the first electrode EL1 and the second electrode EL2 and having a relatively high intensity. Therefore, the light emitting element LD may be aligned between at least one of the first electrodes EL1 and at least one of the second electrodes EL2. In other words, the light emitting element LD may be aligned only in the target area (for example, only in the area between the first electrode EL1 and the second electrode EL2 of each of the pixels PXL). Each of the light emitting elements LD may be aligned in the emission area EMA of each of the pixels PXL on the first insulating material layer INSM1.

[0280] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Figure 12g as well as Figures 13a to 13h After aligning the light emitting element LD in the emission area EMA of each of the pixels PXL, the first connection line CNL1 is separated into two parts between each pixel PXL and a pixel PXL adjacent to each pixel PXL, so that each of the pixels PXL can be driven independently of the adjacent pixels PXL.

[0281] After the separation process of the first connection line CNL1, an insulating material layer (not shown) is applied onto the first insulating material layer INSM1 and the light emitting element LD, and the insulating material layer is patterned by a mask process to form an insulating pattern INSM2. The insulating pattern INSM2 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0282] The insulating pattern INSM2 may cover the first insulating material layer INSM1 disposed on the second electrode EL2. In addition, the insulating pattern INSM2 may expose each of the first insulating material layer INSM1 disposed on the first electrode EL1 and the first insulating material layer INSM1 disposed on the first connection line CNL1 to the outside. In addition, the insulating pattern INSM2 may expose any one of the opposite ends EP1 and EP2 of each of the light emitting elements LD to the outside.

[0283] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 as well as Figures 13a to 13i After disposing a mask (not shown) over the insulating pattern INSM2, the first insulating material pattern INSM1′ is formed by patterning a portion of the first insulating material layer INSM1 exposed to the outside using the mask.

[0284] The first insulating material pattern INSM1 ′ may expose a predetermined region of the first electrode EL1 and cover other regions of the first electrode EL1 except the predetermined region.

[0285] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Figure 12h as well as Figures 13a to 13j , a first contact electrode CNE1 is formed on an exposed predetermined region of the first electrode EL1 and one of opposite end portions EP1 and EP2 of the light emitting element LD by a sputtering method or the like.

[0286] The first contact electrode CNE1 may be disposed on an exposed predetermined region of the first electrode EL1 and electrically and / or physically connected to the first electrode EL1. In addition, the first contact electrode CNE1 may be electrically and / or physically connected to one of the exposed opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0287] In a plan view, the first contact electrode CNE1 may extend in the second direction DR2 and overlap with at least one sub-electrode PRT.

[0288] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 as well as Figures 13a to 13k After disposing a mask (not shown) over the first contact electrode CNE1, the third insulating layer INS3 is formed by patterning the insulating pattern INSM2 using the mask.

[0289] The third insulating layer INS3 may cover at least a portion of the upper surface of each of the light emitting elements LD so that the other of the opposite end portions EP1 and EP2 of each of the light emitting elements LD may be exposed to the outside.

[0290] Thereafter, after forming an insulating material layer (not shown) on the third insulating layer INS3, a mask (not shown) is disposed over the insulating material layer, and then the insulating material layer is patterned by a process using the mask to form a fourth insulating layer INS4. The fourth insulating layer INS4 may cover the first contact electrode CNE1, thereby protecting the first contact electrode CNE1 from the outside. A predetermined area of ​​the first insulating material pattern INSM1' on the second electrode EL2 that is not covered by the fourth insulating layer INS4 and the other end of each of the opposite ends EP1 and EP2 of the light emitting element LD that is not covered by the fourth insulating layer INS4 may be exposed to the outside.

[0291] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 as well as Figures 13a to 131 , after disposing a mask (not shown) over the substrate SUB having the fourth insulating layer INS4 formed thereon, the second insulating layer INS2 is formed by patterning the exposed region of the first insulating material pattern INSM1′.

[0292] The second insulating layer INS2 may expose a predetermined region of the second electrode EL2 and cover other regions of the second electrode EL2 except the predetermined region.

[0293] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 , Fig.12i as well as Figure 13a to Figure 13m A second contact electrode CNE2 is formed on the other of the exposed opposite end portions EP1 and EP2 of each of the light emitting elements LD and on the second electrode EL2.

[0294] The second contact electrode CNE2 may be disposed on an exposed predetermined region of the second electrode EL2 and electrically and / or physically connected to the second electrode EL2. In addition, the second contact electrode CNE2 may be electrically and / or physically connected to the other of the exposed opposite ends EP1 and EP2 of each of the light emitting elements LD.

[0295] In a plan view, the second contact electrode CNE2 may extend in the second direction DR2 and overlap with at least one branch electrode BRC.

[0296] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Figure 4 , Figure 6 as well as Figures 13a to 13n A fifth insulating layer INS5 is formed on the entire surface of the fourth insulating layer INS4 on which the second contact electrode CNE2 is formed.

[0297] The fifth insulating layer INS5 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although the fifth insulating layer INS5 may have a single-layer structure as shown in the figure, the present disclosure is not limited thereto. In an embodiment, the fifth insulating layer INS5 may have a multi-layer structure.

[0298] Subsequently, an overcoat layer OC is formed on the fifth insulating layer INS5.

[0299] Figures 14 to 16 Shows Figure 5 1 is another embodiment of a pixel of the present invention, and is a plan view schematically showing a pixel including only some components of a display element layer.

[0300] although Figures 14 to 16 A simplified structure of a pixel is shown, for example, only a partial configuration of a display element layer of the pixel PXL is shown, but the present disclosure is not limited thereto.

[0301] In addition, Figures 14 to 16 In the figure, for the sake of explanation, the illustration of the pixel circuit layer (including at least one transistor and a signal line electrically connected to the transistor) electrically connected to the light emitting element is omitted.

[0302] The following description will focus on the differences from the description of the previous embodiment. Figures 14 to 16 to avoid repeated explanation. Figures 14 to 16 Components not described separately in the description of the embodiment of the present invention may be consistent with the description of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0303] refer to Figure 1a to Figure 1h , Figure 2 as well as Figures 14 to 16 , each of the pixels PXL may include first and second connection lines CNL1 and CNL2 , at least one sub-electrode PRT, at least one branch electrode BRC, a first electrode EL1 , a second electrode EL2 , and a light emitting element LD.

[0304] Despite Figures 14 to 16 Although not directly shown in the figure, each of the pixels PXL may further include a bank pattern disposed under each of the first electrode EL1 and the second electrode EL2 (refer to Figure 4 PW), one end of the opposite ends EP1 and EP2 of each of the light emitting elements LD, and a first contact electrode (reference Figure 4 CNE1) and a second contact electrode (reference CNE1) provided on the other end of the opposite ends EP1 and EP2 of each of the light emitting elements LD and on the second electrode EL2. Figure 4 of CNE2).

[0305] The first connection line CNL1 may extend in the first direction DR1 and be integral with at least one sub-electrode PRT. In an embodiment of the present disclosure, the sub-electrode PRT may include first to third sub-electrodes PRT1 to PRT3 branched from the first connection line CNL1 in the second direction DR2 to the emission area EMA of each pixel PXL. In a plan view, each of the first to third sub-electrodes PRT1 to PRT3 may have a rod shape extending in the second direction DR2.

[0306] The second connection line CNL2 may extend in the first direction DR1 and be integral with at least one branch electrode BRC. In an embodiment of the present disclosure, the branch electrode BRC may include a first branch electrode BRC1 and a second branch electrode BRC2 branched from the second connection line CNL2 in the second direction DR2 to the emission area EMA of each pixel PXL. In a plan view, each of the first branch electrode BRC1 and the second branch electrode BRC2 may have a rod shape extending in the second direction DR2.

[0307] Each of the first electrodes EL1 may be disposed in the emission area EMA of each of the pixels PXL and disposed at a position spaced apart from the adjacent first electrodes EL1 in the second direction DR2. In a plan view, each of the first electrodes EL1 may have an octagonal shape, but the shape of each of the first electrodes EL1 is not limited to that of the aforementioned embodiment. In an embodiment, each of the first electrodes EL1 may have a rhombus shape (e.g., Fig.15 ) or a semi-elliptical shape including a curve having a predetermined curvature (as shown in Fig.16 ). In addition, although not directly shown in the drawings, each of the first electrodes EL1 may have a triangular shape, a circular shape, an elliptical shape, a trapezoidal shape, etc. The shape of each of the first electrodes EL1 is not limited to that of the aforementioned embodiment, and may be changed in various ways as long as the corresponding sub-electrode PRT disposed thereunder can be reliably covered.

[0308] Each of the first electrodes EL1 may be electrically and / or physically connected to a corresponding sub-electrode PRT disposed thereunder through a corresponding first through-hole VIA1 .

[0309] Each of the second electrodes EL2 may be disposed in the emission area EMA of each of the pixels PXL and at a position spaced apart from the adjacent second electrodes EL2 in the second direction DR2. Although each of the second electrodes EL2 has an octagonal shape in a plan view, it may have a rhombus shape (eg, Fig.15 ) or a semi-elliptical shape including a curve having a predetermined curvature (as shown in Fig.16 ). Similarly, although not directly shown in the drawings, each of the second electrodes EL2 may have a triangular shape, a circular shape, an elliptical shape, a trapezoidal shape, etc. The shape of each of the second electrodes EL2 is not limited to the shape of the aforementioned embodiment, and may be changed in various ways as long as the corresponding branch electrode BRC disposed thereunder can be reliably covered. In an embodiment of the present disclosure, each of the second electrodes EL2 has the same shape as that of the first electrode EL1, but the present disclosure is not limited thereto. In an embodiment, the second electrode EL2 may have a shape different from that of the first electrode EL1.

[0310] Each of the second electrodes EL2 may be electrically and / or physically connected to a corresponding branch electrode BRC disposed thereunder through a corresponding second via VIA2 .

[0311] In an embodiment of the present disclosure, each of the first electrodes EL1 may be designed to have a width in the first direction DR1 that is greater (or longer) than a width of a corresponding sub-electrode PRT disposed thereunder. Each of the second electrodes EL2 may be designed to have a width in the first direction DR1 that is greater (or longer) than a width of a corresponding branch electrode BRC disposed thereunder.

[0312] Therefore, the distance between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 (reference Figure 4 W1) is comparable to the distance between the corresponding sub-electrode PRT disposed under at least one first electrode EL1 and the corresponding branch electrode BRC disposed under at least one second electrode EL2 (reference Figure 4 In this case, if each of the first connection lines CNL1 and the second connection lines CNL2 is supplied with a corresponding alignment voltage, an electric field having a high intensity may be formed between at least one of the first electrodes EL1 and at least one of the second electrodes EL2 because the distance W1 between the at least one first electrode EL1 and the at least one second electrode EL2 is relatively narrow (or short).

[0313] Therefore, the light emitting element LD may be densely aligned between the first electrode EL1 and the second electrode EL2, wherein an electric field having a relatively high intensity is formed between the first electrode EL1 and the second electrode EL2. In other words, the light emitting element LD may be densely aligned only in a region where an electric field having a relatively high intensity is formed, and not in a region where an electric field having a relatively low intensity is formed. Therefore, in the emission area EMA of each of the pixels PXL, the light emitting element LD may be densely aligned only in a target region (e.g., only in a region between the first electrode EL1 and the second electrode EL2).

[0314] Fig.17 A display device according to an embodiment of the present disclosure is shown, and schematically shows Figure 2 A plan view of one of the pixels shown in FIG. Fig.18 is along Fig.17 A schematic cross-sectional view taken along line IV-IV'.

[0315] Fig.18 The pixels shown in Figure 4 The pixels shown in the drawings may differ at least in that the first and second connecting lines, the first to third sub-electrodes, the first and second branch electrodes are arranged and / or formed on the same layer as some components of the pixel circuit layer.

[0316] Therefore, the description will focus on the differences from the description of the aforementioned embodiment. Fig.17 and Fig.18Pixels to avoid redundant explanation. Components not described separately in the following description of this embodiment may be consistent with the components of the previous embodiment. The same reference numerals will be used to represent the same components, and similar reference numerals will be used to represent similar components.

[0317] although Fig.17 and Fig.18 The structure of the pixel is simply shown, for example, in which each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0318] refer to Figure 1a to Figure 1h , Figure 2 , Figure 3a , Fig.17 and Fig.18 , each pixel PXL (hereinafter referred to as “pixel”) may include a substrate SUB, a pixel circuit layer PCL disposed on the substrate SUB, and a display element layer DPL disposed on the pixel circuit layer PCL.

[0319] The pixel circuit layer PCL may include a driving voltage line DVL, a passivation layer PSV, at least one transistor T, and at least one shielding electrode line SDL. Here, the transistor T may include a first transistor T1 (T) as a driving transistor and a second transistor T2 (T) as a switching transistor.

[0320] In an embodiment of the present disclosure, the pixel circuit layer PCL may include first and second connection lines CNL1 and CNL2 disposed on the same layer as the shielding electrode line SDL, the at least one sub-electrode PRT, and the at least one branch electrode BRC.

[0321] The shielding electrode line SDL may be disposed and / or formed on the second interlayer insulating layer ILD2. The shielding electrode line SDL may block the electric field caused by the first transistor T1(T) and the second transistor T2(T) disposed thereunder, thereby preventing the electric field from affecting the alignment and / or operation of the light emitting element LD disposed in the display element layer DPL. In the plan view and the cross-sectional view, the shielding electrode line SDL may be disposed under the light emitting element LD and overlap with the light emitting element LD, but the present disclosure is not limited thereto. In an embodiment, the shielding electrode line SDL may be disposed and / or formed in a predetermined area on the second interlayer insulating layer ILD2, as long as the shielding electrode line SDL can reliably block the electric field caused by the first transistor T1(T), the second transistor T2(T), etc.

[0322] The first connection line CNL1 may be disposed and / or formed on the second interlayer insulating layer ILD2. The second connection line CNL2 may be disposed and / or formed on the second interlayer insulating layer ILD2 and may be electrically and / or physically connected to the driving voltage line DVL through a second contact hole CH2 passing through the second interlayer insulating layer ILD2. The first connection line CNL1 and the second connection line CNL2 may be disposed and / or formed on the same surface and may be electrically and / or physically separated from each other.

[0323] The sub-electrode PRT may be disposed and / or formed on the second interlayer insulating layer ILD2 and may be integrated with the first connection line CNL1. In the case where the sub-electrode PRT and the first connection line CNL1 are integrated with each other, the sub-electrode PRT may be a predetermined area of ​​the first connection line CNL1. The sub-electrode PRT may include first to third sub-electrodes PRT1 to PRT3 in the emission area EMA of the pixel PXL that is branched from the first connection line CNL1 in the second direction DR2. The second sub-electrode PRT2 may be electrically and / or physically connected to the second terminal DE of the first transistor T1 (T) through the first contact hole CH1 that passes through the second interlayer insulating layer ILD2.

[0324] The branch electrode BRC may be disposed and / or formed on the second interlayer insulating layer ILD2 and may be integral with the second connection line CNL2. In the case where the branch electrode BRC and the second connection line CNL2 are integral with each other, the branch electrode BRC may be a predetermined area of ​​the second connection line CNL2. The branch electrode BRC may include a first branch electrode BRC1 and a second branch electrode BRC2 that are branched from the second connection line CNL2 to the emission area EMA of the pixel PXL in the second direction DR2.

[0325] Each of the first branch electrode BRC1 and the second branch electrode BRC2, each of the first sub-electrode PRT1 to the third sub-electrode PRT3, and the shielding electrode line SDL may be arranged at positions spaced apart from each other by a predetermined distance. In a plan view, the shielding electrode line SDL, the first branch electrode BRC1 and the second branch electrode BRC2, and the first sub-electrode PRT1 to the third sub-electrode PRT3 may be alternately arranged in the first direction DR1. For example, at least one shielding electrode line SDL may be arranged between one of the first sub-electrode PRT1 to the third sub-electrode PRT3 and one of the first branch electrode BRC1 and the second branch electrode BRC2. In other words, one of the first sub-electrode PRT1 to the third sub-electrode PRT3 and one of the first branch electrode BRC1 and the second branch electrode BRC2 may be spaced apart from each other by a predetermined distance, and the shielding electrode line SDL is inserted between the sub-electrode PRT and the branch electrode BRC.

[0326] The passivation layer PSV may be disposed on the shielding electrode line SDL, the first and second connection lines CNL1 and CNL2, the first to third sub-electrodes PRT1 to PRT3, and the first and second branch electrodes BRC1 and BRC2. The passivation layer PSV may cover and protect the shielding electrode line SDL, the first and second connection lines CNL1 and CNL2, the first to third sub-electrodes PRT1 to PRT3, and the first and second branch electrodes BRC1 and BRC2.

[0327] Although it has been described in the foregoing embodiments that the first connection line CNL1 and the second connection line CNL2, the first to third sub-electrodes PRT1 to PRT3, and the first branch electrode BRC1 and the second branch electrode BRC2 are disposed and / or formed on the same layer as the layer of the shielding electrode line SDL, the present disclosure is not limited thereto. In an embodiment, the first connection line CNL1 and the second connection line CNL2, the first to third sub-electrodes PRT1 to PRT3, and the first branch electrode BRC1 and the second branch electrode BRC2 may be disposed on the same layer as the layer of any one of the conductive patterns included in the pixel circuit layer PCL of the pixel PXL, as long as electrical insulation from adjacent conductive patterns can be ensured.

[0328] The display element layer DPL of the pixel PXL may be disposed and / or formed on the passivation layer PSV. The display element layer DPL may include first to fifth insulating layers INS1 to INS5, a bank pattern PW, first and second electrodes EL1 and EL2, a light emitting element LD, and first and second contact electrodes CNE1 and CNE2.

[0329] The first insulating layer INS1 may be disposed and / or formed on the passivation layer PSV. The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0330] Each of the first electrodes EL1 may be disposed and / or formed on the bank pattern PW and the first insulating layer INS1. In an embodiment of the present disclosure, the first electrodes EL1 disposed in the same column may be disposed on and overlap the corresponding sub-electrode PRT. In particular, each of the first electrodes EL1 may have a width in the first direction DR1 that is greater (or longer) than a width of the corresponding sub-electrode PRT disposed thereunder.

[0331] Each of the first electrodes EL1 may be electrically and / or physically connected with the corresponding sub-electrode PRT through a first via VIA1 sequentially passing through the first insulating layer INS1 and the passivation layer PSV.

[0332] Each of the second electrodes EL2 may be disposed and / or formed on the bank pattern PW and the first insulating layer INS1. The second electrode EL2 may be disposed and / or formed on the same layer as the first electrode EL1. In an embodiment of the present disclosure, the second electrodes EL2 disposed in the same column may be disposed on and overlap the corresponding branch electrodes BRC. In particular, each of the second electrodes EL2 may have a width in the first direction DR1 that is larger (or longer) than the width of the corresponding branch electrode BRC disposed thereunder.

[0333] Each of the second electrodes EL2 may be electrically and / or physically connected to the corresponding branch electrode BRC through a second via VIA2 sequentially passing through the first insulating layer INS1 and the passivation layer PSV.

[0334] In an embodiment of the present disclosure, each of the first electrodes EL1 may have a width in the first direction DR1 that is larger (or longer) than a width of a sub-electrode PRT disposed thereunder. Each of the second electrodes EL2 may have a width in the first direction DR1 that is larger (or longer) than a width of a branch electrode BRC disposed thereunder. In the case where each of the first electrode EL1 and the second electrode EL2 has a large (or long) width in the first direction DR1, the width between at least one first electrode EL1 and at least one second electrode EL2 disposed in the same row in the emission area EMA of the pixel PXL may be reduced (refer to Figure 4 In this case, if each of the first and second connection lines CNL1 and CNL2 is supplied with a corresponding alignment voltage, an electric field having a high intensity may be formed between at least one first electrode EL1 and at least one second electrode EL2 disposed in the same row in the emission area EMA of the pixel PXL.

[0335] Therefore, the light emitting elements LD may be densely aligned between the first electrode EL1 and the second electrode EL2 disposed in the same row, and an electric field having a relatively high intensity is formed between the first electrode EL1 and the second electrode EL2. In other words, the light emitting elements LD may be densely aligned only in the region where the electric field having a relatively high intensity is formed, and not in the region where the electric field having a relatively low intensity is formed. Therefore, in the emission region EMA of the pixel PXL, the light emitting elements LD may be densely aligned only in the target region (for example, only in the region between the first electrode EL1 and the second electrode EL2).

[0336] While various embodiments have been described above, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the present disclosure.

[0337] Therefore, the embodiments disclosed in this specification are only for illustrative purposes and do not limit the technical scope of the present disclosure. The scope of the invention to be protected must be defined by the appended claims.

Claims

1. A display device, comprising: A substrate including a display area and a non-display area; as well as at least one pixel disposed in the display area and comprising an emission area for emitting light, Wherein, the pixels include: at least one sub-electrode extending in one direction on the substrate; at least one branch electrode extending in the one direction on the substrate and spaced apart from the sub-electrode; A first insulating layer is provided on the sub-electrode and the branch electrode; A plurality of first electrodes, disposed on the first insulating layer and electrically connected to the sub-electrodes; a plurality of second electrodes, disposed on the first insulating layer and electrically connected to the branch electrodes; at least one light emitting element aligned between at least one first electrode of the plurality of first electrodes and at least one second electrode of the plurality of second electrodes; a first contact electrode electrically connecting at least one of the plurality of first electrodes to one of the opposite ends of the light emitting element; and The second contact electrode electrically connects at least one of the plurality of second electrodes to the remaining ends of the opposite ends of the light emitting element.

2. The display device according to claim 1, wherein: The pixels include: A bank pattern is disposed under each of the first electrode and the second electrode.

3. The display device according to claim 2, wherein: The pixel also includes: at least one transistor electrically connected to the light emitting element; at least one shielding electrode line, disposed on the transistor; a driving voltage line electrically connected to the second electrode and supplying a driving power voltage; and A passivation layer is configured to cover the transistor, the shielding electrode line and the driving voltage line.

4. The display device according to claim 3, wherein: The sub-electrode and the branch electrodes are disposed between the transistor and the passivation layer.

5. The display device according to claim 4, wherein: The sub-electrodes, the branch electrodes, and the shielding electrode lines are disposed on the same layer.

6. The display device according to claim 3, wherein: The pixel also includes: a second insulating layer, disposed between the light emitting element and the first insulating layer; and a third insulating layer disposed on the upper surface of the light emitting element, and The first contact electrode and the second contact electrode are spaced apart from each other on the third insulating layer and are electrically isolated from each other.

7. A display device, comprising: A substrate including a display area and a non-display area; as well as at least one pixel disposed in the display area and comprising an emission area for emitting light, Wherein, the pixels include: at least one sub-electrode extending in one direction on the substrate; at least one branch electrode extending in the one direction on the substrate and spaced apart from the sub-electrode; A first insulating layer is provided on the sub-electrode and the branch electrode; A plurality of first electrodes, disposed on the first insulating layer and electrically connected to the sub-electrodes; a plurality of second electrodes, disposed on the first insulating layer and electrically connected to the branch electrodes; at least one light emitting element aligned between at least one first electrode of the plurality of first electrodes and at least one second electrode of the plurality of second electrodes, and The first insulating layer includes a plurality of first through holes each exposing a predetermined area of ​​the sub-electrode and a plurality of second through holes each exposing a predetermined area of ​​the branch electrode.

8. The display device according to claim 7, wherein: At least one first through-hole among the plurality of first through-holes corresponds to each of the plurality of first electrodes, and at least one second through-hole among the plurality of second through-holes corresponds to each of the plurality of second electrodes.

9. The display device according to claim 8, wherein: Each of the plurality of first electrodes contacts the sub-electrode through the at least one first through-hole, and each of the plurality of second electrodes contacts the branch electrode through the at least one second through-hole.

10. The display device according to claim 8, wherein: The sub-electrode is divided into a first region overlapping the first electrode and a second region excluding the first region, The branch electrode is divided into a third region overlapping the second electrode and a fourth region excluding the third region, and The first insulating layer on the first region and the third region has a thickness different from a thickness of the first insulating layer on the second region and the fourth region.

11. The display device according to claim 10, wherein: A thickness of the first insulating layer on the second region and the fourth region is greater than a thickness of the first insulating layer on the first region and the third region.

12. The display device according to claim 8, wherein: Each of the plurality of first electrodes and each of the plurality of second electrodes are spaced apart from each other on the first insulating layer.

13. The display device according to claim 12, wherein: In a plan view, each of the plurality of first electrodes and each of the plurality of second electrodes are alternately disposed in the emission region in a direction intersecting the one direction.

14. The display device according to claim 8, wherein: The pixels include: a first connection line integral with the sub-electrode and extending in a direction intersecting the one direction; and The second connection line is integrated with the branch electrode and is arranged parallel to the direction in which the first connection line extends.

15. A method for manufacturing a display device, comprising: forming a substrate including at least one emitting region; forming, on the substrate, at least one sub-electrode extending in one direction and at least one branch electrode spaced apart from the sub-electrode and extending in the same direction as the one direction in which the sub-electrode extends; forming a first insulating layer on the sub-electrode and the branch electrode, the first insulating layer comprising a plurality of first through holes exposing a predetermined area of ​​the sub-electrode and a plurality of second through holes exposing a predetermined area of ​​the branch electrode; forming a plurality of first electrodes and a plurality of second electrodes on the first insulating layer, wherein the plurality of first electrodes are electrically connected to the sub-electrodes through the plurality of first through holes, and the plurality of second electrodes are electrically connected to the branch electrodes through the plurality of second through holes; aligning a plurality of light emitting elements between at least one first electrode of the plurality of first electrodes and at least one second electrode of the plurality of second electrodes by applying an alignment voltage to each of the sub-electrodes and the branch electrodes; forming a second insulating layer on an upper surface of each of the plurality of light emitting elements; as well as A first contact electrode and a second contact electrode are formed on the substrate having the second insulating layer formed thereon.

16. The method according to claim 15, wherein: The sub-electrode is divided into a first region overlapping the first electrode and a second region excluding the first region, The branch electrode is divided into a third region overlapping the second electrode and a fourth region excluding the third region, and The first insulating layer on the first region and the third region has a thickness different from a thickness of the first insulating layer on the second region and the fourth region.

17. The method according to claim 16, wherein: A thickness of the first insulating layer on the second region and the fourth region is greater than a thickness of the first insulating layer on the first region and the third region.

18. The method according to claim 16, further comprising: Before forming the plurality of first electrodes and the plurality of second electrodes, forming a plurality of bank patterns on the first insulating layer; Part of the plurality of bank patterns is disposed between the first insulating layer and the first electrode, and another part of the plurality of bank patterns is disposed between the first insulating layer and the second electrode.

19. The method according to claim 15, further comprising: forming, on the substrate, at least one transistor electrically connected to the light emitting element and a driving voltage line electrically connected to the second electrode and supplying a driving power supply voltage; forming a shielding electrode line on the transistor; as well as A passivation layer is formed covering the transistor, the driving voltage line and the shielding electrode line.

20. The method according to claim 19, wherein: The sub-electrodes, the branch electrodes, and the shielding electrode lines are disposed on the same layer.

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