Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a clock generation circuit and a jitter measurement circuit. The clock generation circuit is input with a control value for changing a clock period of the clock generation circuit. The jitter measurement circuit has a first logic circuit that operates using an output clock of the clock generation circuit as an input, and is configured to output presence / absence of jitter of the clock generation circuit.

Description

[0001] Cross-reference of related applications

[0002] The disclosure of Japanese Patent Application No. 2020-090120, filed on May 22, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device, and is applicable to semiconductor devices, such as those including clock generation circuitry. Background Technology

[0004] Clock generation circuits, such as PLL (Phase-Locked Loop) circuits, are incorporated into various devices and systems. Typically, the clock generated by a clock generation circuit includes a jitter component. If this jitter component exceeds an allowable value, it will interfere with the normal operation of the device or system in which the clock generation circuit is incorporated.

[0005] The following lists the technologies that have been made public.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2005-269456. Summary of the Invention

[0007] When the clock signal generated by the clock generation circuit is high-speed, it may be impossible to measure the actual value of the jitter of the clock generation circuit in some cases.

[0008] According to one aspect of this disclosure, a semiconductor device includes a clock generation circuit and a jitter measurement circuit. The clock generation circuit is input with a control value for changing its clock period. The jitter measurement circuit has a first logic circuit and a first delay element, the first logic circuit operating with the output clock of the clock generation circuit as input, and the jitter measurement circuit is configured to detect the presence / absence of jitter in the output clock source.

[0009] Based on the aforementioned semiconductor device, the magnitude of jitter in the clock generation circuit can be measured. Attached Figure Description

[0010] Figure 1 This is a diagram used to describe the jitter measurement of the clock generation circuit according to the comparison example;

[0011] Figure 2 This is a diagram used to illustrate the jitter measurement of the clock generation circuit according to an embodiment;

[0012] Figure 3 This is a block diagram showing the configuration of the jitter measurement circuit according to the PLL circuit of the first example;

[0013] Figure 4 It is shown Figure 3The block diagram showing the configuration of the PLL circuit is shown.

[0014] Figure 5 This is a diagram used to illustrate an example of changing the output clock cycle by changing the reference clock frequency;

[0015] Figure 6 This is a diagram used to illustrate an example of changing the output clock period by changing the multiplier setting;

[0016] Figure 7 This is a timing diagram illustrating the operation under the following conditions: Figure 3 The output clock period in the jitter measurement circuit shown is relatively long;

[0017] Figure 8 This is a timing diagram illustrating the operation under the following conditions: Figure 3 The output clock period in the jitter measurement circuit shown is relatively short;

[0018] Figure 9 This is a graph showing the fluctuation distribution of the output clock cycle;

[0019] Figure 10 It is a graph showing the cumulative frequency distribution of the output of the jitter output circuit;

[0020] Figure 11 It shows the basis Figure 10 The graph shows the histogram of the output clock jitter calculated from the cumulative frequency distribution.

[0021] Figure 12 This is a block diagram showing the configuration of the jitter measurement circuit according to the second example;

[0022] Figure 13A It is shown in Figure 12 The timing diagram of the jitter measurement circuit shown is for operation when the output clock period is long.

[0023] Figure 13B This is a timing diagram illustrating the operation under the following conditions: Figure 12 The output clock period in the jitter measurement circuit shown is relatively short;

[0024] Figure 14 This is a block diagram showing the configuration of the jitter measurement circuit according to the third example;

[0025] Figure 15 This is a block diagram showing the configuration of the jitter measurement circuit according to the fourth example;

[0026] Figure 16 This is a block diagram showing the configuration of the jitter measurement circuit according to the fifth example;

[0027] Figure 17This is a block diagram illustrating the configuration of the semiconductor device according to the sixth example; and

[0028] Figure 18 This is a block diagram illustrating the configuration of the semiconductor device according to the seventh example. Detailed Implementation

[0029] In the following description, embodiments and examples will be described with reference to the accompanying drawings. However, the same components are designated by the same reference numerals, and repeated descriptions thereof will be omitted in the following description. Note that, for the purpose of clarity, the drawings will be shown schematically in terms of width, thickness, shape, etc., compared to actual aspects; however, the drawings are merely examples and do not limit the interpretation of this disclosure.

[0030] First, refer to Figure 1 Describes the technology researched by the inventors of this disclosure (comparative examples). Figure 1 This is a diagram used to describe the jitter measurement of the clock generation circuit according to the comparison example.

[0031] The high-speed clock signal generated by the clock generation circuit (CG) 1 is too fast to drive the output buffer 4 located in the semiconductor device 10. Therefore, as Figure 1 As shown, the output of the clock generation circuit 1, which is divided by the frequency divider circuit 2, is output to the outside of the semiconductor device 10 via the output buffer 4, and the jitter is measured by the measuring device 30. Here, the clock frequency generated by the clock generation circuit 1 is, for example, 1 GHz or higher. In addition, the clock frequency divided by the frequency divider circuit 2 is, for example, about 100 MHz. Therefore, it is impossible to measure the actual value of the jitter (period jitter) of the clock generation circuit. In addition, due to the influence of power supply noise and inter-signal interference in the frequency divider circuit 2, the clock signal wiring 3, or the output buffer 4 in the subsequent stage of the clock signal generation circuit 1, and due to the influence of power supply noise and reflection in the system of the evaluation board 20, the actual value of the jitter cannot be measured.

[0032] Next, we will refer to Figure 2 Describe the implementation examples. Figure 2 This is a diagram used to illustrate the jitter measurement of the clock generation circuit according to an embodiment.

[0033] In this embodiment, a jitter measurement circuit (JMC) 5 is provided between the clock generation circuit 1 and the output buffer 4. The jitter measurement circuit 5 consists of logic circuits, and the clock generated by the clock generation circuit 1 is provided to the jitter measurement circuit 5 without being divided. The jitter measurement circuit 5 converts the analog time axis information, which is the clock jitter, into digital values ​​0 / 1 and outputs the converted values. Here, the clock generation circuit 1, which is the object of jitter measurement, is configured, for example, as a PLL circuit, a DLL (delay-locked loop) circuit that synchronizes the phase of the delayed clock with the phase of the reference clock, or a VCXO (voltage-controlled crystal oscillator).

[0034] Therefore, even at frequencies above 1 GHz, the actual value of the jitter in clock generation circuit 1 (e.g., period jitter) can be measured. Furthermore, the actual value of the jitter can be measured without being affected by power supply noise, inter-signal interference, and reflections in output buffer 4 or evaluation board 20. As a result, abnormal samples caused by clock jitter can be screened out during product testing.

[0035] (First example)

[0036] Reference Figure 3 and Figure 4 The configuration of the jitter measurement circuit of the semiconductor device according to the first example is described. Figure 3 This is a block diagram showing the configuration of the jitter measurement circuit according to the first example. Figure 4 It is shown Figure 3 The block diagram shown illustrates the configuration of the PLL circuit.

[0037] The semiconductor device 10 according to the first example has the following configuration: the clock generation circuit 1 of the semiconductor device 10 according to the embodiment is composed of a PLL circuit 1a and is formed in a semiconductor chip. The jitter measurement circuit 5a in the first example detects the jitter included in the output clock (CKV) output from the PLL circuit 1a. Figure 4 As shown, PLL circuit 1 consists of a phase comparator (PFD) 11, a low-pass filter (LPF) 12, a voltage-controlled oscillator (VCO) 13, and a 1 / N divider circuit 14.

[0038] In the first example, since the frequency of the output clock (CKV) of PLL circuit 1a needs to be changed for observation, PLL circuit 1a is equipped with a 1 / N divider circuit 14 as a programmable divider circuit. Clock frequency control is performed by providing a multiplier setting value (N) as a setting signal from outside PLL circuit 1a. Alternatively, the frequency of the output clock (CKV) can be changed by changing the frequency of the reference clock (RefCLK) while keeping the multiplier setting value (N) fixed.

[0039] like Figure 3As shown, the jitter measurement circuit 5a includes a first flip-flop (FF1) 51, a second flip-flop (FF2) 52, an inverter 54, a delay element 55, and an XOR circuit 56. Here, the first flip-flop (FF1) 51, the second flip-flop (FF2) 52, the inverter 54, and the XOR circuit 56 are logic circuits. The path Q1 to D1, composed of the first flip-flop 51 and the inverter 54, is a flip-flop used to generate reference data. Here, Q1 is the data at the output terminal of the first flip-flop 51, and D1 is the data at the input terminal of the first flip-flop 51. Whenever the output clock (CKV) rises, the value of Q1 alternates between "0" and "1" like "0101," and this becomes the reference data signal. The path D1 to D2 has a delay element 55 with a fixed delay, which makes the setup timing of the second flip-flop 52 more stringent than that of the first flip-flop 51. Here, Q2 is the data at the output terminal of the second flip-flop 52, and D2 is the data at the input terminal of the second flip-flop 52.

[0040] Reference Figures 5 to 11 Describe the operation of the jitter measurement circuit according to the first example. Figure 5 This is a diagram used to illustrate an example of changing the output clock cycle by changing the reference clock frequency. Figure 6 This is a diagram used to illustrate an example of changing the output clock period by changing the multiplier setting. Figure 7 It is shown in Figure 3 The timing diagram shows the operation of the jitter measurement circuit when the output clock period is long. Figure 8 It is shown in Figure 3 The timing diagram shows the operation of the jitter measurement circuit when the output clock period is short. Figure 9 This is a graph showing the fluctuation distribution of the output clock cycle. Figure 10 This is a graph showing the cumulative frequency distribution of the output of the jitter output circuit. Figure 11 It shows the basis Figure 10 The graph shows the histogram of the output clock jitter calculated from the cumulative frequency distribution.

[0041] In jitter measurement, such as Figure 5 As shown, the period (TCKV) of the output clock (CKV) is sequentially changed by altering the frequency of the reference clock (RefCLK). Alternatively, as... Figure 6 As shown, the period (TCKV) of the output clock (CKV) is changed sequentially by changing the multiplier setting (N) while keeping the frequency of the reference clock (RefCLK) fixed.

[0042] When the period of the output clock (CKV) (TCKV) is long, such as Figure 7As shown, this also ensures timing margin on the second flip-flop 52 side. Even when the period (TCKV) becomes shorter than the average value due to jitter of the output clock (CKV), there is no problem in setting up D2, and the output (QEX) of the XOR circuit 56 is always "0".

[0043] On the other hand, when the period of the output clock (CKV) (TCKV) is short, such as Figure 8 As shown, the timing margin of the second flip-flop 52 appears insufficient. A setup conflict occurs in D2 when the period (TCKV) becomes shorter than the average value due to jitter in the output clock (CKV). Figure 8 As shown in the area enclosed by the dotted-dash ellipse, Q2 does not change from "1" to "0", and the output (QEX) of the "XOR" circuit 56 only changes to "1" during that period.

[0044] like Figure 9 As shown, the period (TCKV) of the actual output clock (CKV) fluctuates and is distributed randomly for each period with respect to the average period. Furthermore, the period (T0) in which the setup margin of the second flip-flop 52 is 0 [ps] is determined by the delay element 55 between D1 and D2, and is therefore fixed during measurement.

[0045] Therefore, in jitter measurement, the probability of setup conflicts is lower when the output clock (CKV) period (TCKV) is longer. Conversely, the probability of setup conflicts increases when the output clock (CKV) period (TCKV) is shorter. Here, the probability of a setup conflict is higher when the period (TCKV) is shorter than... Figure 9 The probability of case A shown by the solid line in the diagram.

[0046] For example, when the period (TCKV) is long (such as 1000 [ps]), the establishment conflict is 0% because all periods (TCKV) are above the solid line A. Conversely, when the period (TCKV) is medium (such as 990 [ps]), the establishment conflict is 50% because approximately half of the periods (TCKV) are above the solid line A. Furthermore, when the period (TCKV) is short (such as 980 [ps]), the establishment conflict is 100% because all periods (TCKV) are below the solid line A.

[0047] Since the period (TCKV) is scanned during jitter measurement, the probability of the setup conflict of the second trigger 52 occurring 1000 times in each period (TCKV) is the same as the probability of the output (QEX) of the XOR circuit 56 becoming "1". This is plotted on a graph to obtain... Figure 10 The cumulative jitter frequency distribution is shown. Furthermore, the curve obtained by differentiating it corresponds to... Figure 11 The histogram showing the jitter is shown.

[0048] According to the first example, by using the VCO frequency (period) as a scale for measuring time, calibration is not required. As a result, the circuit size is reduced and operation is simplified. Additionally, this allows for high-precision measurement of period jitter. Note that the VCO frequency is controlled by changing the multiplier setting (N) or by changing the frequency of the reference clock (RefCLK) at the input of the PLL circuit.

[0049] In the first example, a PLL circuit has been described as an example of a clock generation circuit, but DLL circuits, VCXOs, etc., whose frequency can be variably controlled can also be used.

[0050] (Second example)

[0051] Reference Figure 12 The configuration of the jitter measurement circuit of the semiconductor device according to the second example is described. Figure 12 This is a block diagram showing the configuration of the jitter measurement circuit according to the second example.

[0052] In the semiconductor device 10 according to the second example, instead of the jitter measurement circuit 5a according to the semiconductor device 10 according to the first example, a jitter measurement circuit 5b is formed in the semiconductor chip. The jitter measurement circuit 5b in the second example measures phase jitter, which is the jitter between the reference clock (RefCLK) and the output clock (CKV) of the PLL circuit 1a, which serves as the input clock. The jitter measurement circuit 5a in the first example measures the periodic jitter of the output clock (CKV) of the PLL circuit 1a. The difference between the second example and the first example lies in the type of jitter to be measured.

[0053] like Figure 12 As shown, the jitter measurement circuit 5b includes a third flip-flop (FF3) 53 and a delay element 57. Here, the third flip-flop 53 is a logic circuit. The delay element 57 has a fixed delay and a delay amount corresponding to one cycle of the output clock (CKV). The clock (D3) obtained by delaying the reference clock (RefCLK) is input to the clock terminal of the third flip-flop 53, and the output clock (CKV) is input to the data terminal of the third flip-flop 53. Note that the clock frequency of the PLL circuit 1a is controlled in the same manner as in the first example.

[0054] Reference Figure 13A and Figure 13B Describe the operation of the jitter measurement circuit according to the second example. Figure 13A It is shown in Figure 12 The timing diagram shows the operation of the jitter measurement circuit when the output clock period is long. Figure 13B It is shown in Figure 12The timing diagram shows the operation of the jitter measurement circuit when the output clock period is short.

[0055] Since the output clock (CKV) of PLL circuit 1a is in phase with the reference clock (RefCLK), it is synchronized with the reference clock (RefCLK) at N times its frequency. Therefore, the closest 0th, Nth, 2Nth, and 3Nth phase differences remain stable and constant. Thus, even if the period (TCKV) of the output clock (CKV) of PLL circuit 1a changes and the output result of the third flip-flop 53 is plotted by RefCLK-CKV according to the same theory as in the first example, the result remains constant. Therefore, the cumulative frequency distribution and histogram of jitter cannot be obtained.

[0056] Figure 13A and Figure 13B The timing diagram is shown with TCKV = TRefCLK / 5. Here, TRefCLK is the period of the reference clock (RefCLK). The fixed delay of delay element 57 is defined as TCLV. Figure 13A and Figure 13B Within each region enclosed by a dashed ellipse, the edges of the reference clock (RefCLK), output clock (CKV), and 1 / N divider circuit 14 are synchronized with each other. The dashed lines on either side of each edge indicate the range of phase jitter (P_JITTER).

[0057] The third flip-flop 53 receives the output clock (CKV) on the rising edge of the clock (D3). The clock (D3) rises from the rising edge of the reference clock (RefCLK) with a delay of TCLV. Figure 13A Within a range where no phase jitter occurs between the output clock (CKV) and the clock (D3), a low-level output clock (CKV) is received on the rising edge of the clock (D3). Figure 13B Within the range of phase jitter of the output clock (CKV) and clock (D3), a low level output clock (CKV) is received on the rising edge of clock (D3).

[0058] like Figure 13A and Figure 13B As shown, the period (TCKV) of the output clock (CKV) is changed, and the output (Q3) of the third flip-flop 53 is plotted via D3-CKV. Therefore, the timing margin changes as in the first example, and the cumulative frequency distribution of jitter between the two clocks and the jitter histogram can be obtained.

[0059] According to the second example, by using the VCO frequency (period) as a scale for time measurement, calibration is not required. As a result, the circuit size is reduced and operation is simplified. Additionally, this allows for high-precision measurement of the phase jitter between the input and output clocks of the PLL circuit. Note that the VCO frequency is controlled by changing the multiplier setting (N) or by changing the frequency of the reference clock (RefCLK) at the PLL circuit's input.

[0060] In the second example, a PLL circuit has been described as an example of a clock generation circuit, but a DLL circuit with an input clock and an output clock and whose frequency can be variably controlled can also be used.

[0061] (Third example)

[0062] Reference Figure 14 The configuration of the jitter measurement circuit of the semiconductor device according to the third example is described. Figure 14 This is a block diagram showing the configuration of the jitter measurement circuit according to the third example.

[0063] In the semiconductor device 10 according to the third example, the jitter measurement circuit 5b of the second example is added to the semiconductor device 10 of the first example. Since the jitter measurement circuit 5a of the first example and the jitter measurement circuit 5b of the second example do not interfere with each other, the jitter measurement circuit 5c can be configured by simply combining the jitter measurement circuit 5a and the jitter measurement circuit 5b, as shown below. Figure 14 As shown. As a result, the following two things can be observed in parallel: the period jitter of the output clock (CKV) of PLL circuit 1a, and the phase jitter between the output clock (CKV) and the reference clock (RefCLK) that serves as the input clock.

[0064] (Fourth example)

[0065] Reference Figure 15 The configuration of the jitter measurement circuit of the semiconductor device according to the fourth example is described. Figure 15 This is a block diagram showing the configuration of the jitter measurement circuit according to the fourth example.

[0066] In the semiconductor device 10 according to the fourth example, a counter (CNTR) 58 is added to the semiconductor device 10 according to the third example. The counter 58 counts the output clock (CKV) of the PLL circuit 1a and sequentially switches the frequency multiplication setting value (N). For example, the counter 58 performs a monotonically increasing or decreasing operation of the frequency multiplication setting value (N) every 1000 jitter measurements (i.e., every 1000 cycles of the output clock (CKV)).

[0067] The counter 58 of the fourth example can be similarly added to the jitter measurement circuit of the first and second examples.

[0068] (Fifth Example)

[0069] Reference Figure 16 The configuration of the jitter measurement circuit of the semiconductor device according to the fifth example is described. Figure 16 This is a block diagram showing the configuration of the jitter measurement circuit according to the fifth example.

[0070] In the semiconductor device 10 according to the fifth example, a jitter measurement circuit 5e is formed instead of the jitter measurement circuit 5c according to the semiconductor device 10 according to the third example. Figure 16 As shown, the jitter measurement circuit 5e in the fifth example is configured such that the output of the delay element 55 of the jitter measurement circuit 5c in the third example is also input to the clock terminal of the third flip-flop 53. Furthermore, the jitter measurement circuit 5e includes a multiplexer 59 that selects either the output of the inverter 54 or the reference clock (RefCLK) and inputs it to the delay element 55.

[0071] The fixed delay amount when measuring period jitter in the first example, and the fixed delay amount when measuring phase jitter in the second example, are both guided by the first cycle of the output clock (CKV) and can therefore be shared. The jitter to be measured is an exclusive operation. Therefore, the delay element 57 of the jitter measurement circuit 5c in the third example becomes unnecessary.

[0072] (Sixth Example)

[0073] Reference Figure 17 Describe the configuration of the semiconductor device according to the sixth example. Figure 17 This is a block diagram illustrating the configuration of the semiconductor device according to the sixth example.

[0074] The semiconductor device 10 according to the sixth example includes a PLL circuit 1a, a jitter measurement circuit 5, an on-chip oscillator 6, and a control circuit 7. The on-chip oscillator 6 generates a reference clock (RefCLK) for the PLL circuit 1a. The control circuit 7 includes a CPU (Central Processing Unit) 7a, a memory 7b, a digital block 7c, and an interface block 7d, and operates based on the output clock (CKV) of the PLL circuit 1a. The CPU 7a executes a program stored in the memory 7b to control the entire semiconductor device 10. The jitter measurement circuit 5 is, for example, composed of the jitter measurement circuit 5d of the fourth example.

[0075] CPU 7a calculates the cumulative frequency distribution and histogram using arithmetic operations on the outputs (QEX, Q3) of the jitter measurement circuit 5, and outputs the jitter calculation result (JTTR). Additionally, CPU 7a generates a reset signal (RST) in the event of an abnormality, resetting the PLL circuit 1 or the entire semiconductor device 10. In the sixth example, the jitter measurement circuit 5 is constructed from the jitter measurement circuit 5d of the fourth example, and therefore both phase jitter and period jitter are monitored.

[0076] According to the sixth example, clock jitter in the semiconductor device can be observed. Furthermore, the semiconductor device outputs the jitter calculation results of the PLL circuit in a self-contained manner and can reset the PLL circuit or the entire semiconductor device in the event of an anomaly.

[0077] The jitter measurement circuit 5 can be a jitter measurement circuit of the first, second, third, or fifth example. In this case, the multiplier setting value (N) is set from the CPU 7a.

[0078] (Seventh Example)

[0079] Reference Figure 18 Describe the configuration of the semiconductor device according to the seventh example. Figure 18 This is a block diagram illustrating the configuration of the semiconductor device according to the seventh example.

[0080] The jitter measurement circuit 5 in the seventh example is, for example, constructed from the jitter measurement circuit 5a of the first example. The frequency multiplier setting value (N) is set from the CPU 7a. The other configurations of the semiconductor device 10 in the seventh example are the same as those in the sixth example. In the seventh example, only periodic jitter is observed.

[0081] Although the disclosure of this disclosure has been specifically described above based on embodiments and examples, it is self-evident that this disclosure is not limited to the above embodiments and examples, and various modifications can be made.

Claims

1. A semiconductor device, comprising: A clock generation circuit is input with a control value to change the clock period of the clock generation circuit; as well as The jitter measurement circuit includes a first logic circuit and a first delay element. The first logic circuit operates using the output clock of the clock generation circuit as input, and the jitter measurement circuit is configured to output the presence / absence of jitter in the output clock. The first logic circuit includes a first flip-flop and a second flip-flop, an inverter, and a comparator circuit. The first and second flip-flops each have a clock terminal, and the output clock is input to the clock terminal. The inverter is configured to invert the output of the first flip-flop and input the inverted output of the first flip-flop to its data terminal. The comparator circuit is configured to compare the output of the first flip-flop with the output of the second flip-flop. The first delay element is configured to delay the output of the inverter and input the delayed output of the inverter to the data terminal of the second flip-flop.

2. The semiconductor device according to claim 1, The clock generation circuit mentioned above is a PLL, DLL, or VCXO.

3. The semiconductor device according to claim 1, The jitter measurement circuit further includes a second logic circuit and a second delay element. The second logic circuit operates using the input clock and the output clock of the clock generation circuit as inputs, and the jitter measurement circuit is configured to output the presence / absence of phase jitter of the input clock and the output clock.

4. The semiconductor device according to claim 3, The second logic circuit includes a third flip-flop that is input to the output clock, and The second delay element is configured to delay the input clock and input the delayed input clock to the clock terminal of the third flip-flop.

5. The semiconductor device according to claim 4, Wherein the first delay element and the second delay element are the same delay element, and The device includes a multiplexer that selects the output or input clock of the inverter and inputs the selected output or input clock of the inverter to the delay element.

6. The semiconductor device according to claim 5, The multiplexer inputs the output of the inverter to the delay element when measuring period jitter, and inputs the input clock to the delay element when measuring phase jitter.

7. The semiconductor device of claim 3, further comprising a counter configured to control the period of the output clock of the clock generation circuit. The counter is configured to increase or decrease the control value by using the output clock as input to perform counter operations.

8. The semiconductor device of claim 7, further comprising a control circuit, the control circuit performing arithmetic operations on the output of the jitter measurement circuit. The control circuit is configured to output the jitter calculation result through the arithmetic operation, perform jitter value anomaly detection, and supply a reset signal to the clock generation circuit.

9. A semiconductor device, comprising: A clock generation circuit is input with a control value to change the clock period of the clock generation circuit; as well as The jitter measurement circuit includes a second logic circuit and a second delay element. The second logic circuit operates using the input clock and output clock of the clock generation circuit as inputs, and the jitter measurement circuit is configured to output the presence / absence of phase jitter between the input clock and the output clock. The second logic circuit includes a third flip-flop that is input to the output clock, and The second delay element is configured to delay the input clock and input the delayed input clock to the clock terminal of the third flip-flop.

10. The semiconductor device according to claim 9, The clock generation circuit mentioned above is a PLL or a DLL.

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