A watchdog reset circuit and intelligent terminal
By introducing an N-input OR gate device and a MOSFET assembly into the watchdog reset circuit of the smart terminal, the watchdog feeding cycle is extended, which solves the system instability problem caused by frequent watchdog feeding in the prior art, improves the system's operational stability, and reduces hardware costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NUBIA TECHNOLOGY CO LTD
- Filing Date
- 2021-08-25
- Publication Date
- 2026-07-21
AI Technical Summary
The current smart terminal watchdog feeding chip has a short feeding time, which leads to frequent feeding and affects the stability of system operation.
A watchdog reset circuit employing an N-input OR gate, a watchdog device, and a MOSFET assembly is used. By adding an N-input OR gate to the watchdog input signal pin of the CPU and the watchdog device, and controlling the on/off state of the MOSFET assembly through the output signal of the watchdog output signal pin, the power supply network of the smart terminal can control the power-on and power-off operation of the CPU.
The watchdog timer cycle has been extended to N times the original cycle, reducing CPU resource consumption, lowering hardware costs, and improving system stability and user experience.
Smart Images
Figure CN113704015B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of signal processing technology, and in particular to a watchdog reset circuit and a smart terminal. Background Technology
[0002] Smart terminals generally adopt the classic computer architecture—the von Neumann architecture, which consists of five major components: the arithmetic logic unit (ALU), the controller, the memory, the input device, and the output device. The ALU and the controller constitute the core component of the computer—the central processing unit (CPU).
[0003] Watchdog circuits are a common anti-interference measure used in smart terminals. They enable the system or circuit to automatically reset, restart, and resume normal operation when subjected to interference, thus ensuring the system recovers from software and hardware errors. Watchdog circuits typically use dedicated chips independent of the smart terminal's CPU, such as the MAX706 and SP706, to provide power-on reset and system reset functions. For normal operation, the watchdog circuit needs to continuously receive clock signals (commonly known as "feeding signals") periodically output by the smart terminal's CPU. In existing technologies, the feeding time of smart terminal watchdog chips is relatively short, on the order of seconds. For smart terminals, such frequent feeding consumes a significant amount of CPU resources, thus affecting system stability. Summary of the Invention
[0004] The main objective of this invention is to propose a watchdog reset circuit and a smart terminal, aiming to solve the technical problem that the short watchdog feeding time of existing smart terminal watchdog feeding chips leads to frequent feeding, which affects the stability of system operation.
[0005] To achieve the above objectives, this invention provides a watchdog reset circuit, which includes an N-input OR gate, a watchdog device, and a MOSFET assembly. The N-input OR gate includes N signal input terminals and one signal output terminal. Each signal input terminal is connected to a watchdog signal output by the smart terminal CPU. The signal output terminal is electrically connected to the watchdog input signal pin of the watchdog device. The smart terminal power network and the watchdog output signal pin are respectively connected to the MOSFET assembly, so as to control the on / off state of the MOSFET assembly through the output signal of the watchdog output signal pin, thereby realizing the power-on / off operation of the smart terminal CPU by the smart terminal power network. N is a positive integer greater than 1.
[0006] Optionally, the MOS transistor assembly includes an NMOS transistor and a PMOS transistor. The power supply network of the smart terminal is connected to the source of the PMOS transistor, the watchdog device's feed signal pin is connected to the gate of the NMOS transistor, the source of the NMOS transistor is grounded, the drain of the NMOS transistor is connected to the gate of the PMOS transistor, and the drain of the PMOS transistor is connected to the power supply terminal of the smart terminal CPU.
[0007] Optionally, a first resistor is connected in parallel between the gate and source of the PMOS transistor, and the first resistor is connected in series between the power network of the smart terminal and the drain of the NMOS transistor.
[0008] Optionally, the N-input OR gate device further includes a power supply terminal and a ground terminal, wherein the power supply terminal is connected to the power network of the smart terminal and the ground terminal is grounded.
[0009] Optionally, a first capacitor is connected in parallel between the smart terminal power network and the power supply terminal. One end of the first capacitor is connected to the smart terminal power network, and the other end of the first capacitor is grounded.
[0010] Optionally, a second capacitor is connected in parallel between the first resistor and the drain of the NMOS transistor, with one end of the second capacitor connected to the first resistor and the other end grounded.
[0011] Optionally, a second resistor is connected in parallel between the drain of the PMOS transistor and the power supply terminal of the smart terminal CPU. One end of the second resistor is connected to the drain of the PMOS transistor, and the other end of the second resistor is grounded.
[0012] Optionally, the N-input OR gate device is a three-input OR gate device, which includes a first signal input terminal, a second signal input terminal, and a third signal input terminal. The first signal input terminal is connected to a first dog-feeding signal output by the smart terminal CPU, the second signal input terminal is connected to a second dog-feeding signal output by the smart terminal CPU, and the third signal input terminal is connected to a third dog-feeding signal output by the smart terminal CPU.
[0013] In addition, to achieve the above objectives, this embodiment of the invention also proposes a smart terminal, which has the above-mentioned reset circuit built in.
[0014] Optionally, the smart terminal also has a built-in CPU and power network. The CPU includes N watchdog signal output terminals, which are connected one-to-one with the N signal input terminals. The power network is connected to the MOS transistor assembly so as to control the on / off state of the MOS transistor assembly through the output signal of the watchdog output signal pin, thereby realizing the power-on and power-off operation of the CPU by the power network.
[0015] The watchdog reset circuit and smart terminal proposed in this invention embodiment include an N-input OR gate device, a watchdog device, and a MOSFET assembly. The N-input OR gate device includes N signal input terminals and one signal output terminal. Each signal input terminal is connected to a watchdog signal output by the smart terminal CPU. The signal output terminal is electrically connected to the watchdog input signal pin of the watchdog device. The smart terminal power network and the watchdog output signal pin of the watchdog device are respectively connected to the MOSFET assembly, so as to control the on / off state of the MOSFET assembly through the output signal of the watchdog output signal pin, thereby realizing the power-on and power-off operation of the smart terminal CPU by the smart terminal power network. In this way, the watchdog reset circuit adds an N-input OR gate to the watchdog input signal pin of the watchdog device and the feed signal pin of the CPU in the smart terminal. It then controls the switching of the MOSFET component through the output signal of the feed signal pin, enabling the power-on / off operation of the smart terminal CPU by the power network. This extends the reset circuit duration by N times, extending the watchdog feeding cycle to N times the original cycle. This reduces the consumption of CPU resources, lowers hardware costs, improves system stability, and enhances the user experience. Therefore, this watchdog reset circuit effectively solves the technical problem of the short feed time of existing smart terminal watchdog feeding chips, which leads to frequent feedings that affect system stability. Attached Figure Description
[0016] Figure 1 A schematic diagram of the hardware structure of the smart terminal to implement the various embodiments of the present invention.
[0017] Figure 2 For example Figure 1 The diagram shows the communication network system architecture upon which the smart terminal is based.
[0018] Figure 3 This is a circuit diagram of a watchdog reset circuit according to an embodiment of the present invention.
[0019] Figure 4 for Figure 3 The diagram shows the feed signal for the watchdog reset circuit.
[0020] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0021] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0022] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.
[0023] Terminals can be implemented in various forms. For example, the terminals described in this invention may include smart terminals such as mobile phones, tablets, laptops, handheld computers, personal digital assistants (PDAs), portable media players (PMPs), navigation devices, wearable devices, smart bracelets, pedometers, etc., as well as fixed terminals such as digital TVs and desktop computers.
[0024] The following description will use a smart terminal as an example. Those skilled in the art will understand that, in addition to components specifically designed for mobile purposes, the construction according to embodiments of the present invention can also be applied to fixed-type terminals.
[0025] Please see Figure 1 This is a schematic diagram of the hardware structure of a smart terminal implementing various embodiments of the present invention. The smart terminal 100 may include: an RF (Radio Frequency) unit 101, a WiFi module 102, an audio output unit 103, an A / V (Audio / Video) input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, and a power supply 111, etc. Those skilled in the art will understand that... Figure 1 The smart terminal structure shown does not constitute a limitation on the smart terminal. A smart terminal may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0026] The following is combined with Figure 1 A detailed introduction to each component of the smart terminal:
[0027] The radio frequency unit 101 can be used for receiving and transmitting signals during message sending or calls. Specifically, it receives downlink messages from the base station and processes them with the processor 110; additionally, it transmits uplink data to the base station. Typically, the radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, and a duplexer. Furthermore, the radio frequency unit 101 can also communicate wirelessly with networks and other devices. The aforementioned wireless communications may use any communication standard or protocol, including but not limited to GSM (Global System of Mobile communication), GPRS (General Packet Radio Service), CDMA2000 (Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division Duplexing-Long Term Evolution), and TDD-LTE (Time Division Duplexing-Long Term Evolution).
[0028] WiFi is a short-range wireless transmission technology. Smart terminals, through the WiFi module 102, can help users send and receive emails, browse web pages, and access streaming media, providing users with wireless broadband internet access. Although Figure 1 WiFi module 102 is shown, but it is understood that it is not a necessary component of a smart terminal and can be omitted as needed without changing the essence of the invention.
[0029] The audio output unit 103 can convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into audio signals and output them as sound when the smart terminal 100 is in call signal receiving mode, call mode, recording mode, voice recognition mode, broadcast receiving mode, etc. Furthermore, the audio output unit 103 can also provide audio output related to specific functions performed by the smart terminal 100 (e.g., call signal receiving sound, message receiving sound, etc.). The audio output unit 103 may include a speaker, a buzzer, etc.
[0030] The A / V input unit 104 is used to receive audio or video signals. The A / V input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042. The GPU 1041 processes image data of still images or videos acquired by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames can be displayed on the display unit 106. The image frames processed by the GPU 1041 can be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 can receive sound (audio data) in operating modes such as telephone call mode, recording mode, and voice recognition mode, and can process such sound into audio data. The processed audio (voice) data can be converted into a format that can be transmitted to a mobile communication base station via the radio frequency unit 101 in telephone call mode. The microphone 1042 can implement various types of noise cancellation (or suppression) algorithms to eliminate (or suppress) noise or interference generated during the reception and transmission of audio signals.
[0031] The smart terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display panel 1061 according to the ambient light level, and the proximity sensor can turn off the display panel 1061 and / or backlight when the smart terminal 100 is moved to the ear. As a type of motion sensor, the accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity and can be used for applications that recognize the phone's posture (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition-related functions (such as pedometer, tapping), etc. Other sensors that may be configured in the phone, such as fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, and infrared sensors, will not be described in detail here.
[0032] The display unit 106 is used to display messages input by the user or messages provided to the user. The display unit 106 may include a display panel 1061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.
[0033] User input unit 107 can be used to receive input numeric or character messages, and generate key signal inputs related to user settings and function control of the smart terminal. Specifically, user input unit 107 may include touch panel 1071 and other input devices 1072. Touch panel 1071, also known as a touch screen, can collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near touch panel 1071), and drive corresponding connection devices according to a pre-set program. Touch panel 1071 may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, and transmits the signal to the touch controller; the touch controller receives touch messages from the touch detection device, converts them into touch point coordinates, sends them to processor 110, and can receive and execute commands sent by processor 110. In addition, touch panel 1071 can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may also include other input devices 1072. Specifically, other input devices 1072 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons, power buttons, etc.), trackball, mouse, joystick, etc., without being limited here.
[0034] Furthermore, the touch panel 1071 may cover the display panel 1061. When the touch panel 1071 detects a touch operation on or near it, it transmits the information to the processor 110 to determine the type of touch event. Subsequently, the processor 110 provides corresponding visual output on the display panel 1061 based on the type of touch event. Although in Figure 1 In this embodiment, the touch panel 1071 and the display panel 1061 are two independent components to realize the input and output functions of the smart terminal. However, in some embodiments, the touch panel 1071 and the display panel 1061 can be integrated to realize the input and output functions of the smart terminal. The specific implementation is not limited here.
[0035] Interface unit 108 serves as an interface through which at least one external device can connect to smart terminal 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, and so on. Interface unit 108 may be used to receive input from the external device (e.g., data messages, power, etc.) and transmit the received input to one or more elements within smart terminal 100, or it may be used to transmit data between smart terminal 100 and the external device.
[0036] The memory 109 can be used to store software programs and various data. The memory 109 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area may store data created based on the use of the mobile phone (such as audio data, phonebook, etc.). Furthermore, the memory 109 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.
[0037] The processor 110 is the control center of the smart terminal. It connects various parts of the smart terminal via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 109, and by calling data stored in the memory 109, it performs various functions and processes data of the smart terminal, thereby providing overall monitoring of the smart terminal. The processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 110.
[0038] The smart terminal 100 may also include a power supply 111 (such as a battery) that supplies power to various components. Preferably, the power supply 111 can be logically connected to the processor 110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system.
[0039] although Figure 1 As not shown, the smart terminal 100 may also include a Bluetooth module, etc., which will not be described in detail here.
[0040] To facilitate understanding of the embodiments of the present invention, the communication network system on which the smart terminal of the present invention is based is described below.
[0041] Please see Figure 2 , Figure 2 This invention provides a communication network system architecture diagram. The communication network system is an LTE system based on the universal mobile communication technology. The LTE system includes a UE (User Equipment) 201, an E-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an EPC (Evolved Packet Core) 203, and the operator's IP services 204, which are connected in sequence.
[0042] Specifically, UE201 can be the aforementioned terminal 100, which will not be elaborated here.
[0043] E-UTRAN202 includes eNodeB2021 and other eNodeB2022s. Among them, eNodeB2021 can connect to other eNodeB2022s via backhaul (e.g., X2 interface), and eNodeB2021 connects to EPC203. eNodeB2021 can provide UE201 with access to EPC203.
[0044] EPC203 may include MME (Mobility Management Entity) 2031, HSS (Home Subscriber Server) 2032, other MMEs 2033, SGW (Serving Gateway) 2034, PGW (Packet Data Network Gateway) 2035, and PCRF (Policy and Charging Rules Function) 2036, etc. Among them, MME2031 is the control node that handles signaling between UE201 and EPC203, providing bearer and connection management. HSS2032 provides registers to manage functions such as the Home Location Register (not shown in the diagram) and stores user-specific messages such as service characteristics and data rates. All user data can be sent through SGW2034. PGW2035 can provide UE 201 IP address allocation and other functions. PCRF2036 is the policy and charging control decision point for service data flow and IP bearer resources. It selects and provides available policy and charging control decisions for the policy and charging enforcement function unit (not shown in the figure).
[0045] IP services 204 may include the Internet, intranet, IMS (IP Multimedia Subsystem), or other IP services.
[0046] Although the above description uses the LTE system as an example, those skilled in the art should understand that the present invention is not only applicable to the LTE system, but also to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, and future new network systems, etc., which are not limited here.
[0047] Based on the above-described intelligent terminal hardware structure and communication network system, various embodiments of the method of the present invention are proposed.
[0048] Example 1
[0049] like Figure 3 As shown, Embodiment 1 of the present invention proposes a watchdog reset circuit 300. The watchdog reset circuit 300 includes an N-input OR gate device 310, a watchdog device 320, and a MOSFET assembly 330. The N-input OR gate device 310 includes N signal input terminals and one signal output terminal. Each signal input terminal is connected to a feed signal output by the smart terminal CPU (not shown). The signal output terminal is electrically connected to the feed input signal pin of the watchdog device 320. The smart terminal power network VDD_5V and the feed output signal pin of the watchdog device 320 are respectively connected to the MOSFET assembly 330, so as to control the on / off of the MOSFET assembly 330 through the output signal of the feed output signal pin, thereby realizing the power-on and power-off operation of the smart terminal CPU by the smart terminal power network VDD_5V. N is a positive integer greater than 1.
[0050] In this embodiment, as Figure 3As shown, the N-input OR gate device 310 is specifically a three-input OR gate device D1. The three-input OR gate device D1 includes a first signal input terminal I2, a second signal input terminal I1, and a third signal input terminal I0. The first signal input terminal I2 is connected to the first watchdog signal WDI_IN2 output by the smart terminal CPU, the second signal input terminal I1 is connected to the second watchdog signal WDI_IN1 output by the smart terminal CPU, and the third signal input terminal I0 is connected to the third watchdog signal WDI_IN0 output by the smart terminal CPU. The watchdog device 320 is specifically a watchdog chip D3. The signal output terminal Y of the three-input OR gate device D1 outputs the WDI_OR signal to the watchdog input signal pin WDI of the watchdog chip D3. The MOSFET assembly 130 includes an NMOS transistor VT3 and a PMOS transistor VT4. The smart terminal power network VDD_5V is connected to the source of the PMOS transistor VT4. The watchdog chip D3's feed signal pin RESET* is connected to the gate of the NMOS transistor VT3. The source of the NMOS transistor VT3 is grounded, and the drain of the NMOS transistor VT3 is connected to the gate of the PMOS transistor VT4. The drain of the PMOS transistor VT4 is connected to the power supply terminal of the smart terminal CPU (not shown). A first resistor R37 is connected in parallel between the gate and source of the PMOS transistor VT4, and R37 is connected in series between the smart terminal power network VDD_5V and the drain of the NMOS transistor VT3, serving as a pull-up resistor for the NMOS transistor VT3. A second capacitor C2 is also connected in parallel between the first resistor R37 and the drain of the NMOS transistor VT3. One end of the second capacitor C2 is connected to the first resistor R37, and the other end of the second capacitor C2 is grounded, serving as a bypass capacitor for filtering. A second resistor R23 is connected in parallel between the drain of PMOS transistor VT4 and the power supply terminal of the smart terminal CPU. One end of the second resistor R23 is connected to the drain of PMOS transistor VT4, and the other end of the second resistor R23 is grounded to serve as a bleed resistor and to quickly discharge the voltage.
[0051] In addition, the N-input OR gate device 310 and the watchdog device 320 in this embodiment are also powered through the smart terminal power network VDD_5V, such as Figure 3As shown, the N-input OR gate device 310 (specifically, the three-input OR gate device D1 in this embodiment) also includes a power supply terminal VCC and a ground terminal GND. The power supply terminal VCC is connected to the smart terminal power network VDD_5V, and the ground terminal GND is grounded. Preferably, a first capacitor C1 is connected in parallel between the smart terminal power network VDD_5V and the power supply terminal VCC. One end of the first capacitor C1 is connected to the smart terminal power network VDD_5V, and the other end of the first capacitor C1 is grounded, serving as a bypass capacitor for filtering. Similarly, the watchdog chip device 320 (specifically, the watchdog chip D3 in this embodiment) also includes a power supply pin VCC and a ground pin GND. The power supply pin VCC is connected to the smart terminal power network VDD_5V, and the ground pin GND is grounded.
[0052] like Figure 3 As shown, when the smart terminal is powered normally, there is a 5V power output on the smart terminal power network VDD_5V. The RESET* pin of the watchdog chip D3 is high by default, that is, the gate (i.e., the control electrode) of NMOS transistor VT3 is high. When the gate of NMOS transistor VT3 is high, NMOS transistor VT3 is in the on state. The drain of NMOS transistor VT3 becomes low, that is, the gate (i.e., the control electrode) of PMOS transistor VT4 becomes low. When the gate of PMOS transistor VT4 becomes low, PMOS transistor VT4 is in the on state. The smart terminal power network VDD_5V supplies power to the smart terminal CPU through the output VDD_5V_OUT of PMOS transistor VT4. At the same time, when the gate of NMOS transistor VT3 is low, NMOS transistor VT3 is in the off state. When VDD_5V_OUT is powered on, the CPU of the smart terminal starts to work. After the CPU starts up, it outputs WDI_IN2 / WDI_IN1 / WDI_IN0 to the input signals I2 / I1 / I0 of the three-input OR gate device D1. After these three input signals are ORed by the three-input OR gate device D1, the output signal WDI_OR is used to feed the watchdog chip D3 to ensure the normal operation of the watchdog chip D3.
[0053] like Figure 4As shown in the diagram, in this circuit design, assuming the three-input OR gate D1 has a watchdog timer period of T, and the high-level time within this period is Th, then the low-level time Tl is T-Th. When the smart terminal CPU starts, the first watchdog signal WDI_IN2 outputs a low level for Tl and a high level for Th, with a period of T = watchdog timer signal. After a time interval of 2T, it outputs another low level for Tl and a high level for Th, with a period of T = watchdog timer signal, and so on. The second watchdog signal WDI_IN1 first outputs a level signal for T, then outputs a low level for Tl and a high level for Th, with a period of T = watchdog timer signal. After a time interval of 2T, it outputs another low level for Tl and a high level for Th, with a period of T = watchdog timer signal, and so on. The third watchdog signal WDI_IN0 first outputs a level signal for 2T, then outputs a low level for Tl and a high level for Th, with a period of T = watchdog timer signal. After a time interval of 2T, it outputs another low level for Tl and a high level for Th, with a period of T = watchdog timer signal, and so on. The output signal diagram is shown below. Figure 4 As shown, this embodiment uses a three-input OR gate device D1, which can triple the duration of the reset circuit, extending the watchdog timer cycle of the watchdog device 320 to three times its original cycle. This reduces the consumption of CPU resources in the smart terminal, lowers hardware costs, improves system stability, and enhances the user experience. Similarly, if an N-input OR gate device is used for watchdog timer feeding, the watchdog timer cycle will be extended to N times its original cycle.
[0054] Example 2
[0055] Embodiment 2 of the present invention proposes a smart terminal. In addition to the reset circuit of Embodiment 1, the smart terminal also includes a CPU and a power network. The CPU includes N watchdog signal output terminals, which are connected one-to-one with N signal input terminals. The power network is connected to the MOS transistor assembly 330 so as to control the on / off state of the MOS transistor assembly 330 through the output signal of the watchdog output signal pin, thereby realizing the power-on and power-off operation of the CPU by the power network.
[0056] It should be noted that the above-mentioned smart terminal and method embodiment one belong to the same concept. The specific implementation process is detailed in embodiment one, and the technical features in embodiment one are all applicable in the smart terminal embodiment, which will not be repeated here.
[0057] The watchdog reset circuit and smart terminal proposed in this invention embodiment include an N-input OR gate device, a watchdog device, and a MOSFET assembly. The N-input OR gate device includes N signal input terminals and one signal output terminal. Each signal input terminal is connected to a watchdog signal output by the smart terminal CPU. The signal output terminal is electrically connected to the watchdog input signal pin of the watchdog device. The smart terminal power network and the watchdog output signal pin of the watchdog device are respectively connected to the MOSFET assembly, so as to control the on / off state of the MOSFET assembly through the output signal of the watchdog output signal pin, thereby realizing the power-on and power-off operation of the smart terminal CPU by the smart terminal power network. In this way, the watchdog reset circuit adds an N-input OR gate to the watchdog input signal pin of the watchdog device and the feed signal pin of the CPU in the smart terminal. It then controls the switching of the MOSFET component through the output signal of the feed signal pin, enabling the power-on / off operation of the smart terminal CPU by the power network. This extends the reset circuit duration by N times, extending the watchdog feeding cycle to N times the original cycle. This reduces the consumption of CPU resources, lowers hardware costs, improves system stability, and enhances the user experience. Therefore, this watchdog reset circuit effectively solves the technical problem of the short feed time of existing smart terminal watchdog feeding chips, which leads to frequent feedings that affect system stability.
[0058] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0059] The sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0060] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0061] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.
Claims
1. A watchdog reset circuit, characterized in that, The watchdog reset circuit includes an N-input OR gate device, a watchdog device, and a MOSFET assembly. The N-input OR gate device includes N signal input terminals and one signal output terminal. Each signal input terminal is connected to a watchdog signal output by the smart terminal CPU. The signal output terminal is electrically connected to the watchdog input signal pin of the watchdog device. The smart terminal power network and the watchdog output signal pin of the watchdog device are respectively connected to the MOSFET assembly, so as to control the on / off state of the MOSFET assembly through the output signal of the watchdog output signal pin, thereby realizing the power-on and power-off operation of the smart terminal CPU by the smart terminal power network. N is a positive integer greater than 1. The MOS transistor assembly includes an NMOS transistor and a PMOS transistor. The power network of the smart terminal is connected to the source of the PMOS transistor. The watchdog device's feed signal pin is connected to the gate of the NMOS transistor. The source of the NMOS transistor is grounded. The drain of the NMOS transistor is connected to the gate of the PMOS transistor. The drain of the PMOS transistor is connected to the power supply terminal of the smart terminal CPU. A first resistor is connected in parallel between the gate and the source of the PMOS transistor, and the first resistor is connected in series between the power network of the smart terminal and the drain of the NMOS transistor. The N-input OR gate device further includes a power supply terminal and a ground terminal, wherein the power supply terminal is connected to the power network of the smart terminal and the ground terminal is grounded. A first capacitor is connected in parallel between the smart terminal power network and the power supply terminal. One end of the first capacitor is connected to the smart terminal power network, and the other end of the first capacitor is grounded. A second capacitor is connected in parallel between the first resistor and the drain of the NMOS transistor. One end of the second capacitor is connected to the first resistor, and the other end of the second capacitor is grounded. A second resistor is connected in parallel between the drain of the PMOS transistor and the power supply terminal of the smart terminal CPU. One end of the second resistor is connected to the drain of the PMOS transistor, and the other end of the second resistor is grounded. The N-input OR gate is a three-input OR gate, which includes a first signal input terminal, a second signal input terminal, and a third signal input terminal. The first signal input terminal is connected to a first watchdog signal output by the smart terminal CPU, the second signal input terminal is connected to a second watchdog signal output by the smart terminal CPU, and the third signal input terminal is connected to a third watchdog signal output by the smart terminal CPU. The three-input OR gate is used to extend the watchdog feeding cycle to three times the original cycle.
2. A smart terminal, characterized in that, The smart terminal has a built-in reset circuit as described in claim 1; The smart terminal also has a built-in CPU and power network. The CPU includes N watchdog signal output terminals, which are connected one-to-one with the N signal input terminals. The power network is connected to the MOS transistor assembly, so as to control the on and off of the MOS transistor assembly through the output signal of the watchdog output signal pin, thereby realizing the power-on and power-off operation of the CPU by the power network.