Display device

Abstract

A display device is provided. The display device includes a substrate; a conductive layer over the substrate and including first and second voltage lines extending in a first direction; first and second electrodes over the conductive layer, extending in the first direction, and spaced apart from each other; a plurality of light emitting elements over the first and second electrodes; and an electrode pattern over the conductive layer and separated from the first electrode. The electrode pattern is superposed on the first voltage line in a thickness direction and directly contacts the first voltage line.

Description

Technical Field

[0001] An aspect of the embodiments of this disclosure relates to a display device. Background Technology

[0002] With the development of multimedia technology, display devices have become increasingly important. Therefore, various display devices, such as organic light-emitting diode (OLED) displays and liquid crystal displays (LCDs), are currently used.

[0003] Display devices display images and typically include display panels such as organic light-emitting diode (OLED) display panels or liquid crystal display (LCD) panels. These display panels can be light-emitting display panels that include light-emitting elements (e.g., light-emitting diodes (LEDs)). Light-emitting diodes can include organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials. Summary of the Invention

[0004] This disclosure provides an inorganic light-emitting diode display device (e.g., an inorganic light-emitting diode display device including a novel electrode structure).

[0005] This disclosure also provides a display device that can be manufactured using a more efficient manufacturing process.

[0006] It should be noted that this disclosure is not limited to the aspects and features described above, and other aspects and features of this disclosure will be apparent to those skilled in the art from the following description.

[0007] According to embodiments of this disclosure, electrodes can be separately disposed in each sub-pixel of the display device, and alignment signals can be applied to the electrodes during the process of aligning the light-emitting elements by using a conductive layer beneath the electrodes. Because the resistance of the wire to which the alignment signal is applied is lower than the resistance of the electrode, voltage drop of the alignment signal can be avoided or mitigated. Furthermore, because the electric field of the alignment signal is not generated at the boundary of the sub-pixel, the number of light-emitting elements that might be disposed (or aligned) in undesirable locations and thus lost can be reduced.

[0008] It should be noted that the aspects and features of this disclosure are not limited to those described above, and other aspects and features of this disclosure will be apparent to those skilled in the art from the following description.

[0009] According to an embodiment of this disclosure, a display device includes: a substrate; a conductive layer on the substrate, including a first voltage line and a second voltage line extending in a first direction; a first electrode and a second electrode on the conductive layer, extending in the first direction and spaced apart from each other; a plurality of light-emitting elements on the first electrode and the second electrode; and an electrode pattern on the conductive layer, separated from the first electrode. The electrode pattern is superimposed on the first voltage line in the thickness direction and directly contacts the first voltage line.

[0010] The electrode pattern may be spaced apart from the first electrode in the first direction.

[0011] The display device may further include: an interlayer dielectric layer on a conductive layer, and an electrode pattern that can contact a first voltage line through contact openings penetrating the interlayer dielectric layer.

[0012] The display device may further include: a plurality of first barriers, between the interlayer dielectric layer and the first electrode and between the interlayer dielectric layer and the second electrode. The electrode pattern may not overlap with the first barriers and may be directly on the interlayer dielectric layer.

[0013] The display device may further include a second barrier on the interlayer dielectric layer, extending around the periphery of the emitting region where the light-emitting element is disposed and the cut-out region on a first side of the emitting region in a first direction. An electrode pattern may be superimposed on the second barrier in the thickness direction.

[0014] The first electrode and the electrode pattern can be spaced apart from each other, with a cut area between them, and the second electrode can extend from the emission area through the cut area.

[0015] The conductive layer may further include: a first conductive pattern electrically connected to a first voltage line through a first transistor between the substrate and the conductive layer; a first electrode directly contacting the first conductive pattern through a first contact opening penetrating the interlayer dielectric layer; and a second electrode directly contacting the second voltage line through a second contact opening penetrating the interlayer dielectric layer.

[0016] The first electrode can contact the first conductive pattern at the first electrode contact portion, which is arranged on the second side of the emission region in the first direction, and the second electrode can contact the second voltage line at the second electrode contact portion, which is located on the first side of the cut region in the first direction.

[0017] The display device may further include: a first insulating layer that partially covers the first electrode and the second electrode, and the light-emitting element may be directly on the first insulating layer.

[0018] The display device may further include: a first contact electrode on a first insulating layer and in contact with the first electrode and the light-emitting element; and a second contact electrode on the first insulating layer and in contact with the second electrode and the light-emitting element.

[0019] The display device may also include a second insulating layer on the light-emitting element.

[0020] According to another embodiment of this disclosure, a display device includes: a substrate having an emitting region and a cutout region on one side of the emitting region; a first electrode and a second electrode extending on the substrate in a first direction and spaced apart from each other in a second direction; a third electrode between the first electrode and the second electrode; a fourth electrode spaced apart from the third electrode in the second direction, and the second electrode being between the third electrode and the fourth electrode; a plurality of light-emitting elements on at least two of the first to fourth electrodes that are spaced apart from each other in the second direction; an electrode pattern separate from the first electrode and outside the emitting region; a first contact electrode on the first electrode and contacting the light-emitting elements; a second contact electrode on the second electrode and contacting the light-emitting elements; and a third contact electrode on the third and fourth electrodes and contacting the light-emitting elements.

[0021] The display device may further include: a conductive layer on a substrate, and including a first voltage line and a second voltage line extending in a first direction. An electrode pattern may be directly connected to the first voltage line.

[0022] The electrode pattern and the first electrode may be partially located in the cut area and spaced apart from each other.

[0023] The electrode pattern can be located on one side of the cut area in the second direction and can be superimposed on the first voltage line in the thickness direction.

[0024] The display device may further include: a first transistor located between the substrate and the conductive layer, and electrically connected to a first voltage line. A first electrode may be electrically connected to the first transistor, and a second electrode may be directly connected to a second voltage line.

[0025] The display device may further include: a plurality of first dikes, respectively between the substrate and the first to fourth electrodes; and a second dike extending around the periphery of the emission region and the cutout region. Each of the first and second electrodes may include an electrode contact portion superimposed on the second dike.

[0026] The light-emitting element may include: a first light-emitting element having a first end on a first electrode and a second end on a third electrode; and a second light-emitting element having a first end on a fourth electrode and a second end on a second electrode.

[0027] The first contact electrode can contact the first end and the first electrode of the first light-emitting element, and the second contact electrode can contact the second end and the second electrode of the second light-emitting element.

[0028] The third contact electrode can extend around the periphery of the second contact electrode and can contact the third electrode, the fourth electrode, the second end of the first light-emitting element, and the first end of the second light-emitting element. Attached Figure Description

[0029] The above and other aspects and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure.

[0031] Figure 2 This is a plan view showing the pixels of a display device according to an embodiment of the present disclosure.

[0032] Figure 3 It is shown Figure 2 The planar view of the first sub-pixel is shown.

[0033] Figure 4 It is along Figure 3 The sectional view taken from lines Q1-Q1' and Q2-Q2'.

[0034] Figure 5 It is along Figure 3 The sectional view taken by line Q3-Q3' in the middle.

[0035] Figure 6 This is a schematic diagram of a light-emitting element according to an embodiment of the present disclosure.

[0036] Figures 7 to 12 This is a schematic diagram of the process steps for manufacturing a display device according to an embodiment of the present disclosure.

[0037] Figure 13 This is a plan view showing the pixels of a display device according to another embodiment of the present disclosure.

[0038] Figure 14 It is shown Figure 13 The plan view of the first sub-pixel of the display device shown.

[0039] Figure 15 It is along Figure 14 The sectional view taken from line Q6-Q6' in the middle.

[0040] Figure 16 It is along Figure 14 The sectional view taken by line Q7-Q7' in the middle.

[0041] Figure 17 and Figure 18 It shows the manufacturing process. Figure 14 A plan view of some of the process steps of the display device shown. Detailed Implementation

[0042] This disclosure will now be described more fully below with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0043] It will be understood that when a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, it can be directly on, directly connected to, or directly bonded to the other component or layer, or there may be one or more intermediate components or layers. When a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers. For example, when a first component is described as being "bonded" or "connected" to a second component, the first component can be directly bonded to or directly connected to the second component, or the first component can be indirectly bonded to or indirectly connected to the second component via one or more intermediate components.

[0044] In the accompanying drawings, the dimensions of various elements, layers, etc., may be exaggerated for clarity. Throughout the specification and drawings, the same reference numerals indicate the same components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Furthermore, the use of "may" in describing embodiments of the invention refers to "one or more embodiments of the invention."

[0045] Expressions such as “at least one of…” when following a column of elements modify the entire column, not individual elements within the column. Furthermore, the term “embodiment” is intended to represent an example or illustration. As used herein, the term “use” and its variations may be considered synonymous with the term “utilize” and its variations, respectively. As used herein, the terms “basically,” “about,” and similar terms are used as approximations rather than terms of degree and are intended to account for inherent variations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0046] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or feature to another (other) element or feature as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, then an element described as “below” or “under” other elements or features will subsequently be positioned “above” or “above” other elements or features. Thus, the term “below” can cover both above and below orientations. The device may be otherwise positioned (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0047] The terminology used herein is for the purpose of describing particular exemplary embodiments of the invention and is not intended to limit the exemplary embodiments described herein. As used herein, the singular forms “a” and “an” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that the terms “comprising,” “including,” and / or variations thereof, when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may be referred to as the first element.

[0049] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 This is a plan view of a display device according to an embodiment of the present disclosure.

[0051] Reference Figure 1 The display device 10 displays (is configured to display) moving or still images. The display device 10 can represent any electronic device including a display screen. For example, the display device 10 may include a television, laptop computer, monitor, electronic billboard, Internet of Things (IoT) device, mobile phone, smartphone, tablet PC, electronic watch, smartwatch, watch phone, head-mounted display device, mobile communication terminal, electronic notebook, e-book reader, portable multimedia player (PMP), navigation device, game console, digital camera, camcorder, etc.

[0052] Display device 10 includes a display panel that provides (or includes) a display screen. Examples of display panels may include inorganic light-emitting diode (LED) display panels, organic light-emitting diode (OLED) display panels, quantum dot (QD) light-emitting diode (LED) display panels, plasma display panels, field emission display panels, etc. In the following description, the display panel is described as an inorganic LED display panel, but this disclosure is not limited thereto. Any other display panel may be used, as long as the technical concept of this disclosure can be equivalently applied.

[0053] The shape of the display device 10 can be modified in various ways (e.g., the display device 10 can be shaped in various ways). For example, the display device 10 can have a rectangular shape with a longer horizontal side, a rectangular shape with a longer vertical side, a square shape, a quadrilateral shape with rounded corners (vertices), other polygonal shapes, a circular shape, etc. The shape of the display area DPA of the display device 10 can be similar to the overall shape of the display device 10. Figure 1 A display device 10 with a rectangular shape having a long horizontal side and a display area DPA (e.g., a display area DPA with a similar rectangular shape) are shown.

[0054] Display device 10 may include a display area DPA and non-display areas NDA. In some embodiments, multiple separate non-display areas NDA may be provided. Images may be displayed in the display area DPA, while images may not be displayed in the non-display areas NDA. The display area DPA may be referred to as the active area, and the non-display areas NDA may be referred to as the inactive area. The display area DPA may generally occupy the center of the display device 10.

[0055] The display area DPA may include multiple pixels PX. The multiple pixels PX may be arranged in a matrix. When viewed from above, the shape of each pixel PX may be, but is not limited to, a rectangle or a square. In some embodiments, each pixel PX may have a rhombus shape with sides tilted relative to one direction. Striped pixels and Pixels (e.g., rhombus-shaped pixels) can be arranged alternately. It is a trademark owned by Samsung Display Co., Ltd. of the Republic of Korea. Each of the pixels PX may include at least one light-emitting element ED configured to emit light of a specific wavelength to represent the corresponding color (see [link to relevant documentation]). Figure 2 ).

[0056] A non-display area NDA may be disposed around the display area DPA. The non-display area NDA may partially or completely surround the display area DPA. The display area DPA may have a rectangular shape, and the non-display area NDA may be positioned adjacent to the four sides of the rectangular display area DPA. The non-display area NDA may form the border of the display device 10. Line or circuit drivers included in the display device 10 may be disposed in the non-display area NDA (e.g., in the non-display area NDA at each side of the display area DPA), or external devices may be mounted to the display device 10.

[0057] Figure 2 This is a plan view showing the pixels of a display device according to an embodiment of the present disclosure. Figure 2 The voltage lines VL1 and VL2, as well as electrodes RME1 and RME2, embankments BNL1 and BNL2, light-emitting elements ED, and contact electrodes CNE1 and CNE2 disposed on the voltage lines VL1 and VL2 are shown.

[0058] Reference Figure 2 Each of the plurality of pixels PX may include a plurality of sub-pixels PXn (where n is an integer from 1 to 3 or greater). For example, a pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light of a first color, the second sub-pixel PX2 may emit light of a second color, and the third sub-pixel PX3 may emit light of a third color. For example, the first color may be blue, the second color may be green, and the third color may be red. However, it is to be understood that this disclosure is not limited thereto. All sub-pixels PXn may emit light of the same color. Although in Figure 2 In the example shown, pixel PX includes three sub-pixels PX1 to PX3, but this disclosure is not limited thereto. Pixel PX may include more than three sub-pixels PXn.

[0059] Each of the sub-pixels PXn in the display device 10 may include an emitting region EMA and a non-emitting region. A light-emitting element ED may be disposed in the emitting region EMA to emit light of a specific wavelength. No light-emitting element ED is disposed in the non-emitting region, and light emitted from the light-emitting element ED does not reach the non-emitting region, such that no light is emitted (or emitted) from the non-emitting region. The emitting region EMA may include a region in which a light-emitting element ED is disposed, and may include a region adjacent to the light-emitting element ED where light emitted from the light-emitting element ED exits.

[0060] However, it should be understood that this disclosure is not limited thereto. The emission region EMA may also include the area from which light emitted from the light-emitting element ED is reflected or refracted by other elements and exits. Multiple light-emitting elements ED may be disposed in each of the sub-pixels PXn, and the emission region EMA may include not only the area where the light-emitting element ED is disposed, but also adjacent areas.

[0061] Each of the sub-pixels PXn may further include a cutout region CBA disposed in a non-emitting region. The cutout region CBA may be disposed on one side of the emitting region EMA in the second direction DR2. The cutout region CBA may be disposed between the emitting regions EMA of adjacent sub-pixels PXn in the second direction DR2. For example, in the display area DPA of the display device 10, multiple emitting regions EMA and cutout regions CBA may be arranged (e.g., alternately arranged). For example, multiple emitting regions EMA and cutout regions CBA may be repeatedly arranged in the first direction DR1 and alternately arranged in the second direction DR2.

[0062] The second dam BNL2 can be disposed between the notch region CBA and the emitting region EMA, and the distance between the notch region CBA and the emitting region EMA can vary depending on the width of the second dam BNL2 (e.g., the width in the second direction DR2). The light-emitting element ED is not disposed in the notch region CBA, so no light is emitted from it. A portion of the electrodes RME (including RME1 and RME2) disposed in each of the sub-pixels PXn can be disposed in the notch region CBA. The electrodes RME disposed in some sub-pixels PXn can be disposed separately from each other in the notch region CBA (e.g., they can be separated from each other). However, it is to be understood that this disclosure is not limited thereto. The electrodes RME can also be disposed in the notch region CBA without separation.

[0063] Figure 3 It is shown Figure 2 The plan view of the first sub-pixel PX1 shown. Figure 4 It is along Figure 3 The sectional view taken from lines Q1-Q1' and Q2-Q2'. Figure 3 The diagram shows voltage lines VL1 and VL2 disposed in the first sub-pixel PX1, as well as electrodes RME1 and RME2, embankments BNL1 and BNL2, light-emitting element ED, and contact electrodes CNE1 and CNE2 disposed on voltage lines VL1 and VL2. Figure 4 A cross-section is shown from one end of the light-emitting element ED disposed in a sub-pixel PXn to the other end.

[0064] Combining Figure 2 Reference Figure 3 and Figure 4The display device 10 will be described in detail below. The display device 10 may include a first substrate SUB and a semiconductor layer, a plurality of conductive layers, and a plurality of insulating layers disposed on the first substrate SUB. The semiconductor layer, conductive layers, and insulating layers may form the circuit layer and the emissive material layer of the display device 10.

[0065] The first substrate SUB can be an insulating substrate. The first substrate SUB can include insulating materials such as glass, quartz, and polymer resins (or can be made of insulating materials such as glass, quartz, and polymer resins). The first substrate SUB can be a rigid substrate or a flexible substrate, and a flexible substrate can be bent, folded, or rolled.

[0066] A light-blocking layer BML may be disposed on the first substrate SUB. The light-blocking layer BML may be stacked with the active layer ACT1 of the first transistor T1. The light-blocking layer BML may include a light-blocking material, and thus prevent or substantially prevent light from entering the active layer ACT1 of the first transistor T1. For example, the light-blocking layer BML may be formed of an opaque metallic material that blocks light transmission. However, it is to be understood that this disclosure is not limited thereto. In some embodiments, the light-blocking layer BML may be omitted (or removed).

[0067] The buffer layer BL can be disposed entirely on the first substrate SUB (e.g., on the entire surface of the first substrate SUB) and on the light blocking layer BML. The buffer layer BL can be formed on the first substrate SUB to protect the first transistor T1 of the pixel PX from moisture that may penetrate through the first substrate SUB, which may be susceptible to moisture penetration, and the buffer layer BL can also provide a flat surface.

[0068] A semiconductor layer is disposed on the buffer layer BL. The semiconductor layer may include the active layer ACT1 of the first transistor T1. The active layer ACT1 may be configured to partially stack with the gate electrode G1 of the first conductive layer, which will be described in more detail below.

[0069] Although only the first transistor T1, which is included in the transistors of the sub-pixel PXn of the display device 10, is depicted in the accompanying drawings, the present disclosure is not limited thereto. The display device 10 may include a larger number of transistors. For example, in addition to the first transistor T1, the display device 10 may include more than one transistor (e.g., two or three or more transistors in each of the sub-pixels PXn).

[0070] The semiconductor layer may include polycrystalline silicon, monocrystalline silicon, oxide semiconductors, etc. When the semiconductor layer includes an oxide semiconductor, each active layer ACT1 may include multiple conductive regions and channel regions therebetween. The oxide semiconductor may be an oxide semiconductor that includes (or contains) indium (In). For example, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), etc.

[0071] In other embodiments, the semiconductor layer may include polycrystalline silicon. Polycrystalline silicon can be formed by crystallizing amorphous silicon, and in such embodiments, the conductive regions of the active layer ACT1 may be doped regions doped with impurities.

[0072] A first gate insulating layer GI is disposed on the semiconductor layer and the buffer layer BL. The first gate insulating layer GI can be disposed on the buffer layer BL and surround the semiconductor layer. The first gate insulating layer GI can be used as the gate insulator for each transistor.

[0073] A first conductive layer is disposed on a first gate insulating layer GI. The first conductive layer may include a gate electrode G1 of a first transistor T1 and a first capacitor electrode CSE1 of a storage capacitor. The gate electrode G1 may be configured such that it is stacked in the thickness direction with the channel region of the active layer ACT1. The first capacitor electrode CSE1 may be configured such that it is stacked in the thickness direction with a second capacitor electrode CSE2, which is described in more detail below. According to embodiments of this disclosure, the first capacitor electrode CSE1 may be integral with the gate electrode G1. The first capacitor electrode CSE1 may be configured such that it is stacked in the thickness direction with the second capacitor electrode CSE2, and the storage capacitor may be formed therefrom.

[0074] A first interlayer dielectric layer IL1 is disposed on the first conductive layer. The first interlayer dielectric layer IL1 can serve as an insulating layer between the first conductive layer and other layers disposed thereon. Furthermore, the first interlayer dielectric layer IL1 can be configured to cover the first conductive layer to protect it.

[0075] The second conductive layer is disposed on the first interlayer dielectric layer IL1. The second conductive layer may include the first source electrode S1 and the first drain electrode D1 of the first transistor T1, as well as the second capacitor electrode CSE2.

[0076] The first source electrode S1 and the first drain electrode D1 of the first transistor T1 can contact the doped region of the active layer ACT1 through contact openings (e.g., contact holes) passing through the first interlayer dielectric layer IL1 and the first gate insulating layer GI, respectively. Furthermore, the first source electrode S1 of the first transistor T1 can contact the light blocking layer BML through another contact opening (e.g., contact hole).

[0077] The second capacitor electrode CSE2 can be configured to be stacked on top of the first capacitor electrode CSE1 in the thickness direction. According to an embodiment of this disclosure, the second capacitor electrode CSE2 can be integrally connected to the first source electrode S1.

[0078] The second conductive layer may also include a data line for applying data signals to another transistor. The data line may be connected to the source / drain electrode of the other transistor to transmit the signal applied from the data line.

[0079] A second interlayer dielectric layer IL2 is disposed on the second conductive layer. The second interlayer dielectric layer IL2 can serve as an insulating layer between the second conductive layer and other layers disposed thereon. Furthermore, the second interlayer dielectric layer IL2 can cover the second conductive layer to protect it.

[0080] A third conductive layer is disposed on the second interlayer dielectric layer IL2. The third conductive layer may include a first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP. A high-level voltage (e.g., a first supply voltage) may be applied to the first voltage line VL1 to be supplied to the first transistor T1, and a low-level voltage (e.g., a second supply voltage) may be applied to the second voltage line VL2 to be supplied to the second electrode RME2.

[0081] The first voltage line VL1 and the second voltage line VL2 of the third conductive layer can extend along the second direction DR2. The first voltage line VL1 may include a portion that extends along the second direction DR2 and then bends in another direction between the second direction DR2 and the first direction DR1. On the other hand, the second voltage line VL2 may not be bent, but may extend along the second direction DR2. The first voltage line VL1 and the second voltage line VL2 may be positioned such that the first voltage line VL1 and the second voltage line VL2 partially overlap with the electrodes RME1 and RME2, which are described in more detail below, in the thickness direction. The first voltage line VL1 may be configured such that it extends along the second direction DR2 at the boundary of the sub-pixel PXn and is partially bent and located within the emission region EMA. The second voltage line VL2 may be configured to pass through the emission region EMA.

[0082] The first conductive pattern CDP can be connected to the second capacitor electrode CSE2 through a contact opening (e.g., a contact hole) formed in the second interlayer dielectric layer IL2. The second capacitor electrode CSE2 can be integrated with the first source electrode S1 of the first transistor T1, thus the first conductive pattern CDP can be electrically connected to the first source electrode S1. The first conductive pattern CDP can also contact the first electrode RME1, which will be described in more detail below. The first transistor T1 can transmit a first supply voltage (VDD) applied from the first voltage line VL1 to the first electrode RME1 through the first conductive pattern CDP. Although in the example shown in the figures, the third conductive layer includes a second voltage line VL2 and a first voltage line VL1, this disclosure is not limited thereto. The third conductive layer may include more than one first voltage line VL1 and a second voltage line VL2.

[0083] The buffer layer BL, the first gate insulating layer GI, the first interlayer dielectric layer IL1, and the second interlayer dielectric layer IL2 may comprise multiple inorganic layers that are alternately stacked on top of each other (or may be composed of multiple inorganic layers that are alternately stacked on top of each other). For example, the buffer layer BL, the first gate insulating layer GI, the first interlayer dielectric layer IL1, and the second interlayer dielectric layer IL2 may comprise multiple layers (or may be composed of multiple layers), wherein silicon oxide (SiO2) is included. x ), silicon nitride (SiN) x Inorganic layers of at least one of silicon oxynitride (SiON) are stacked alternately on each other.

[0084] The first, second, and third conductive layers may comprise a single or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof (or may consist of a single or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof). However, it is to be understood that this disclosure is not limited thereto.

[0085] The third interlayer dielectric layer IL3 is disposed on the third conductive layer. The third interlayer dielectric layer IL3 may include an organic material such as polyimide (PI) (e.g., an organic insulating material) to provide a flat surface.

[0086] On the third interlayer dielectric layer IL3, multiple first barriers BNL1, multiple electrodes RME, light-emitting elements ED, multiple contact electrodes CNE1 and CNE2, and a second barrier BNL2 are disposed as a display element layer. In addition, multiple insulating layers PAS1 and PAS2 can be disposed on the third interlayer dielectric layer IL3.

[0087] Multiple first dams BNL1 can be directly disposed on the third interlayer dielectric layer IL3. A first dam BNL1 can have a shape extending in the first direction DR1 and can be disposed across other adjacent sub-pixels PXn. Furthermore, a first dam BNL1 can have a shape extending in the second direction DR2 and can be spaced apart from another first dam BNL1 disposed in the same sub-pixel PXn. For example, each of the first dams BNL1 can have a width (e.g., a predetermined width) in the first direction DR1 and the second direction DR2, and a portion of the first dam BNL1 can be disposed in the emission region EMA, while another portion of the first dam BNL1 can be disposed at the boundary of another adjacent sub-pixel PXn in the first direction DR1. The length of the first dam BNL1 in the second direction DR2 can be greater than the length of the emission region EMA in the second direction DR2, such that a portion of the first dam BNL1 can overlap with the second dam BNL2 in the non-emission region.

[0088] Multiple first dams BNL1 can be disposed in a sub-pixel PXn. For example, two first dams BNL1 can be partially disposed in the emission region EMA of a sub-pixel PXn. The two first dams BNL1 can be spaced apart from each other in the first direction DR1. The light-emitting element ED can be disposed between the first dams BNL1 at the spaced-apart locations in the first direction DR1. Although the accompanying drawings show two first dams BNL1 disposed in the emission region EMA of each sub-pixel PXn to form an island pattern, the present disclosure is not limited thereto. The number of first dams BNL1 disposed in the emission region EMA of each sub-pixel PXn can vary depending on the number of electrodes RME1 and RME2 or the arrangement of the light-emitting element ED.

[0089] The first dam BNL1 may have a structure that at least partially protrudes from the upper surface of the third interlayer dielectric layer IL3. The protrusion of the first dam BNL1 may have sloping side surfaces. Light emitted from the light-emitting element ED can be reflected by the electrode RME disposed on the first dam BNL1, allowing the light to exit towards the upper side of the third interlayer dielectric layer IL3. The first dam BNL1 may provide an area in which the light-emitting element ED is disposed, and may also serve as a reflective wall reflecting light emitted from the light-emitting element ED upwards. The side surfaces of the first dam BNL1 may be sloping in a linear shape, but this disclosure is not limited thereto. In other embodiments, the first dam BNL1 may have a semi-circular or semi-elliptical shape with a curved outer surface. The first dam BNL1 may include, but is not limited to, organic insulating materials such as polyimide (PI).

[0090] Multiple electrodes RME1 and RME2 have a shape extending in one direction and are disposed in each of the sub-pixels PXn. The multiple electrodes RME1 and RME2 may have a shape extending in a second direction DR2 and spaced apart from each other in the first direction DR1 and / or the second direction DR2, so as to be disposed in each of the sub-pixels PXn. For example, the first electrode RME1 and the second electrode RME2 disposed in each of the sub-pixels PXn may be spaced apart from each other in the first direction DR1. Multiple light-emitting elements ED may be disposed on the first electrode RME1 and the second electrode RME2. However, it is to be understood that this disclosure is not limited thereto. For example, the positions of the electrodes RME1 and RME2 disposed in each of the sub-pixels PXn may vary depending on their number or the number of light-emitting elements ED disposed in the sub-pixel PXn.

[0091] The first electrode RME1 and the second electrode RME2 can be disposed in the emission region EMA of each of the sub-pixels PXn, and a portion thereof can extend beyond the emission region EMA to overlap with the second embankment BNL2 in the thickness direction. According to embodiments of the present disclosure, the first electrode RME1 and the second electrode RME2 can extend along the second direction DR2 within each of the sub-pixels PXn, and can be spaced apart from the first electrode RME1 or the second electrode RME2 of another adjacent sub-pixel PXn in the second direction DR2.

[0092] For example, the first electrode RME1 can be located on one side of the emission region EMA in the second direction DR2 (e.g., Figure 3 The second embankment BNL2, located above the emitter EMA, extends (e.g., from below) to the opposite side in the second direction DR2 to reach the cutout region CBA. In the cutout region CBA, the first electrode RME1 may be spaced apart from the electrode pattern CP disposed in the corresponding sub-pixel PXn in the second direction DR2. The second electrode RME2 may extend from the second embankment BNL2 located above the emitter EMA to the opposite side in the second direction DR2 to extend beyond the cutout region CBA. The second electrode RME2 may be positioned adjacent to the boundary of another sub-pixel PXn adjacent to it in the second direction DR2.

[0093] The first electrode RME1 and the second electrode RME2 are similar in that they extend in the second direction DR2, but they can have different shapes. The portion of the first electrode RME1 that overlaps with the second embankment BNL2 disposed on the upper side of the emission region EMA can be (for example, formed as) a first electrode contact CTP1. The portion of the second electrode RME2 that overlaps with the second embankment BNL2 disposed on the lower side of the cutout region CBA to form a boundary with another adjacent sub-pixel PXn can be (for example, formed as) a second electrode contact CTP2. The width of the portion of the first electrode RME1 extending in the emission region EMA along the second direction DR2 can be equal to the width of the first electrode contact CTP1. The width of the portion of the second electrode RME2 where the portion extending in the emission region EMA along the second direction DR2 connects with the second electrode contact CTP2 can be relatively small. However, it should be understood that this disclosure is not limited thereto.

[0094] According to embodiments of this disclosure, the first electrode RME1 and the second electrode RME2 may be partially stacked with the first voltage line VL1 and the second voltage line VL2 in the thickness direction, respectively. Electrodes RME1 and RME2, the first voltage line VL1 and the second voltage line VL2 may extend in the second direction DR2 where they overlap each other.

[0095] Multiple electrodes RME1 and RME2 can be connected to a third conductive layer, allowing a signal to be applied to enable the light-emitting element ED to emit light (e.g., a signal to make the light-emitting element ED emit light). The first electrode RME1 can contact the first conductive pattern CDP via a first contact opening (e.g., a first contact hole) CT1 formed at the first electrode contact CTP1 and penetrating the underlying third interlayer dielectric layer IL3. The second electrode contact CTP2 of the second electrode RME2 can contact the second voltage line VL2 via a second contact opening (e.g., a second contact hole) CT2 penetrating the underlying third interlayer dielectric layer IL3. The first electrode RME1 can be electrically connected to the first transistor T1 via the first conductive pattern CDP to receive a first supply voltage. The second electrode RME2 can be electrically connected to the second voltage line VL2 to receive a second supply voltage. Multiple electrodes RME1 and RME2 can be electrically connected to the light-emitting element ED. Electrodes RME1 and RME2 can be connected to both ends of the light-emitting element ED via contact electrodes CNE1 and CNE2, which are described in more detail below (e.g., they can be connected to opposite ends of the light-emitting element ED, respectively), and can transmit electrical signals applied from the third conductive layer to the light-emitting element ED. Because electrodes RME1 and RME2 are separately disposed in each of the sub-pixels PXn, the light-emitting elements ED of different sub-pixels PXn can emit light individually.

[0096] Although the electrode contacts CTP1 and CTP2, which are respectively formed at the first contact opening CT1 and the second contact opening CT2 in the accompanying drawings, are formed in positions such that they overlap with the second dam BNL2, this disclosure is not limited thereto. For example, each of the electrode contacts CTP1 and CTP2 may be located in an emission region EMA surrounded by the second dam BNL2 (e.g., surrounded by the second dam BNL2 along its periphery).

[0097] Electrodes RME1 and RME2 disposed in each of the sub-pixels PXn can be disposed on a plurality of first dams BNL1 spaced apart from each other. Electrodes RME1 and RME2 can be disposed on one side of the first dam BNL1 in the first direction DR1 (e.g., disposed on the inclined side surface of the first dam BNL1). According to embodiments of the present disclosure, the width of the plurality of electrodes RME1 and RME2 in the first direction DR1 can be smaller than the width of the first dam BNL1 in the first direction DR1. Each of electrodes RME1 and RME2 can be configured to cover at least one side of the first dam BNL1 to reflect light emitted from the light-emitting element ED.

[0098] The spacing between electrodes RME1 and RME2, which are spaced apart on the first direction DR1, can be smaller than the spacing between the first layers BNL1. At least a portion of each of electrodes RME1 and RME2 can be directly disposed on the third interlayer dielectric layer IL3 so as to be disposed on the same plane.

[0099] According to embodiments of this disclosure, a plurality of electrodes RME1 and RME2 can transmit electrical signals for allowing light-emitting elements ED to emit light, and can also be used to generate an electric field within sub-pixels PXn during the manufacturing process of the display device 10 to align the light-emitting elements ED. The light-emitting elements ED can be sprayed onto electrodes RME1 and RME2 using an inkjet printing process. After spraying ink containing the light-emitting elements ED, an alignment signal is applied to each of electrodes RME1 and RME2 to generate an electric field. The light-emitting elements ED dispersed in the ink can receive electrophoretic forces caused by the generated electric field (e.g., can move due to electrophoretic forces caused by the generated electric field), allowing them to be aligned on electrodes RME1 and RME2.

[0100] Electrodes RME1 and RME2 can be separately formed throughout the sub-pixels PXn and can be electrically connected to the third conductive layer. Alignment signals for aligning the light-emitting elements ED during the manufacturing process of the display device 10 can be applied through the third conductive layer, and the alignment signals can be applied to electrodes RME1 and RME2 separately disposed in each of the sub-pixels PXn. The third conductive layer can be disposed below the third interlayer dielectric layer IL3 and can have a thickness greater than that of each of electrodes RME1 and RME2. When the alignment signal is applied through the third conductive layer, the resistance of the line (e.g., conductive line) during the alignment process is lower than when the alignment signal is directly applied to electrodes RME1 and RME2 disposed in the plurality of sub-pixels PXn and connected across the sub-pixels PXn. Furthermore, because the electric field formed by the alignment signal is not generated or has a relatively weak intensity at the boundary between electrodes RME1 and RME2 in the direction adjacent to each other in the neighboring sub-pixels PXn, misalignment and loss of the light-emitting elements ED at undesirable locations can be prevented or substantially prevented.

[0101] In some embodiments, alignment signals for aligning the light-emitting element ED can be applied directly through the first voltage line VL1 and the second voltage line VL2 without passing through a transistor. Alignment signals can be applied to the first voltage line VL1 and the second voltage line VL2, and can be transmitted to the first electrode RME1 and the second electrode RME2 connected to the first voltage line VL1 and the second voltage line VL2. Note that the first electrode RME1 can also be electrically connected to the first transistor T1 via a first conductive pattern CDP. During the manufacturing process of the display device 10, alignment signals can be applied by directly connecting the first electrode RME1 to the first voltage line VL1. During the manufacturing process of the display device 10, the first electrode RME1 can be directly connected to the first voltage line VL1, and in subsequent processes, the first electrode RME1 can be separated from the first voltage line VL1. For this purpose, an electrode pattern CP can be provided in each of the sub-pixels PXn of the display device 10, the electrode pattern CP being the portion of the first electrode RME1 directly connected to the first voltage line VL1 and then separated from the first electrode RME1.

[0102] The electrode pattern CP can be directly connected to the first voltage line VL1 and can be spaced apart from the first electrode RME1. For example, the electrode pattern CP can be disposed outside the emitting region EMA, can be superimposed on the second embankment BNL2, and can be spaced apart from the first electrode RME1 at the cut-out region CBA. During the manufacturing process of the display device 10, the electrode pattern CP can be formed to be connected to the first electrode RME1, and after the light-emitting element ED is aligned, the first electrode RME1 can be separated from the electrode pattern CP. Therefore, the first electrode RME1 can be electrically connected only to the first transistor T1, while the electrode pattern CP can remain electrically connected only to the first voltage line VL1. The electrode pattern CP will be described in more detail below with reference to other figures.

[0103] Each of electrodes RME1 and RME2 may include a conductive material with high reflectivity. For example, each of electrodes RME1 and RME2 may include metals such as silver (Ag), copper (Cu), and aluminum (Al) as materials with high reflectivity, and may be an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc. Each of electrodes RME1 and RME2 may reflect light emitted from the side surface of the light-emitting element ED toward the first embankment BNL1 toward the upper side of each of the sub-pixels PXn.

[0104] However, it is to be understood that this disclosure is not limited thereto. Each of electrodes RME1 and RME2 may also include a transparent conductive material. For example, each of electrodes RME1 and RME2 may include materials such as ITO, IZO, and ITZO. In some embodiments, each of electrodes RME1 and RME2 may have a structure in which one or more layers of transparent conductive material and a metal layer with high reflectivity are stacked, or may be (may include) a single layer comprising them. For example, each of electrodes RME1 and RME2 may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0105] A first insulating layer PAS1 is disposed on electrodes RME1 and RME2 and a first embankment BNL1. The first insulating layer PAS1 may be configured to cover the first embankment BNL1 and the first electrode RME1 and the second electrode RME2, while exposing a portion of the upper surface of each of the first electrode RME1 and the second electrode RME2. An opening therein, through which a portion of the upper surface of each of the electrodes RME1 and RME2 is exposed, may be formed in the first insulating layer PAS1. Contact electrodes CNE1 and CNE2 may contact electrodes RME1 and RME2 through the opening.

[0106] In an embodiment, the first insulating layer PAS1 may have a step, such that a portion of its upper surface is recessed between the first electrode RME1 and the second electrode RME2. Because the first insulating layer PAS1 is configured to cover the first electrode RME1 and the second electrode RME2, the step can be formed between them. However, it is to be understood that this disclosure is not limited thereto. The first insulating layer PAS1 protects the first electrode RME1 and the second electrode RME2 and insulates them from each other. Furthermore, the first insulating layer PAS1 prevents the light-emitting element ED disposed on the first insulating layer PAS1 from contacting other elements and being damaged.

[0107] A second dam BNL2 may be disposed on the first insulating layer PAS1. When viewed from above, the second dam BNL2 may be disposed in a grid pattern including portions extending in the first direction DR1 and the second direction DR2. The second dam BNL2 may be disposed along the boundary of each of the sub-pixels PXn to distinguish adjacent sub-pixels PXn from each other. Furthermore, the second dam BNL2 may be configured to surround (e.g., surround or around the periphery of) the emission region EMA and the cutout region CBA disposed in each of the sub-pixels PXn to distinguish the emission region EMA and the cutout region CBA. The portion of the second dam BNL2 extending in the second direction DR2 may have a larger width between the emission regions EMA than between the cutout regions CBA. The distance between the cutout regions CBA may be smaller than the distance between the emission regions EMA.

[0108] The second dike BNL2 can have a greater height than the first dike BNL1. The second dike BNL2 prevents ink containing the light-emitting elements ED from spilling into adjacent sub-pixels PXn during the inkjet printing process in the manufacturing process of the display device 10, allowing different sub-pixels PXn to be separated from each other and preventing ink from mixing between them. Because a first dike BNL1 is disposed across adjacent sub-pixels PXn in the first direction DR1, the portion of the second dike BNL2 extending in the second direction DR2 can be disposed on the first dike BNL1. Similar to the first dike BNL1, the second dike BNL2 can include, but is not limited to, polyimide (PI).

[0109] The light-emitting element ED can be disposed on the first insulating layer PAS1. The light-emitting element ED can be spaced apart from each other on the electrodes RME1 and RME2 along the second direction DR2 in which they extend, and can be aligned substantially parallel to each other. The light-emitting element ED can have a shape extending in one direction. The direction in which the electrodes RME1 and RME2 extend can be substantially perpendicular to the direction in which the light-emitting element ED extends. However, it is to be understood that this disclosure is not limited thereto. The light-emitting element ED can be oriented obliquely relative to the direction in which the electrodes RME1 and RME2 extend.

[0110] The light-emitting element (ED) may include semiconductor layers doped with different conductivity types. The ED may include multiple semiconductor layers and may be aligned such that their ends point to a specific orientation according to the direction of the electric field generated by electrodes RME1 and RME2. Furthermore, each of the ED may include an emitting layer 36 (see, for example...). Figure 6 The light-emitting elements ED disposed in each sub-pixel PXn can emit light of a specific wavelength, depending on the material of the emitting layer 36. However, it is to be understood that this disclosure is not limited thereto. The light-emitting elements ED disposed in the sub-pixel PXn can emit light of the same color.

[0111] The light-emitting element (ED) can be disposed on electrodes RME1 and RME2 between the first electrode BNL1. For example, one end of each of the light-emitting elements (ED) can be located on the first electrode RME1, while the other end can be located on the second electrode RME2. The length of the light-emitting element (ED) can be greater than the distance between the first electrode RME1 and the second electrode RME2, and the ends of the light-emitting element (ED) can be disposed on the first electrode RME1 and the second electrode RME2, respectively.

[0112] The light-emitting element ED may include multiple semiconductor layers and may be disposed on a first substrate SUB. The light-emitting elements ED of the display device 10 may be arranged such that they extend parallel to the first substrate SUB (e.g., parallel to the upper surface of the first substrate SUB). The semiconductor layers included in the light-emitting element ED may be sequentially disposed in a direction parallel to the upper surface of the first substrate SUB. However, it is to be understood that this disclosure is not limited thereto. In some embodiments, when the light-emitting elements ED have different structures, the multiple layers may be disposed in a direction perpendicular to the first substrate SUB.

[0113] Each of the light-emitting elements ED can have its end contacting contact electrodes CNE1 and CNE2, respectively. The insulating layer 38 of the light-emitting element ED (see example...) Figure 6 The semiconductor layer is not formed on the end surface of the light-emitting element ED on its extending side to expose a portion of the semiconductor layer, and the exposed portion of the semiconductor layer can contact the contact electrodes CNE1 and CNE2. However, it is to be understood that this disclosure is not limited thereto. In some embodiments, at least a portion of the insulating layer 38 is removed, or the insulating layer 38 is removed, such that the end surface of the semiconductor layer of the light-emitting element ED can be at least partially exposed. The exposed side surface of the semiconductor layer can contact the contact electrodes CNE1 and CNE2.

[0114] The second insulating layer PAS2 can be partially disposed on the light-emitting element ED. For example, the second insulating layer PAS2 can be configured to partially cover the outer surface of the light-emitting element ED, such that one end and the other end of the light-emitting element ED are not covered (e.g., are exposed). The contact electrodes CNE1 and CNE2, which will be described in more detail below, can contact the ends of the light-emitting element ED that are not covered by the second insulating layer PAS2. When viewed from above, the portion of the second insulating layer PAS2 disposed on the light-emitting element ED can extend along the second direction DR2 on the first insulating layer PAS1, thereby forming a linear pattern or island pattern in each of the sub-pixels PXn. The second insulating layer PAS2 can protect and fix the light-emitting element ED during the manufacturing process of the display device 10.

[0115] Contact electrodes CNE1 and CNE2 can be disposed on the second insulating layer PAS2. The first contact electrode CNE1 and the second contact electrode CNE2 can be disposed on portions of the first electrode RME1 and the second electrode RME2, respectively. The first contact electrode CNE1 can be formed on the first electrode RME1, and the second contact electrode CNE2 can be disposed on the second electrode RME2. Each of the first contact electrode CNE1 and the second contact electrode CNE2 can have a shape extending in the second direction DR2. The first contact electrode CNE1 and the second contact electrode CNE2 can be spaced apart from each other in the first direction DR1, and they can form a linear pattern within the emission region EMA of each of the sub-pixels PXn.

[0116] In some embodiments, the width of the first contact electrode CNE1 and the second contact electrode CNE2 in one direction may be smaller than the width of the first electrode RME1 and the second electrode RME2 in that direction (e.g., in the same direction). The first contact electrode CNE1 and the second contact electrode CNE2 may contact one end and the other end of the light-emitting element ED, and may respectively cover a portion of the upper surface of each of the first electrode RME1 and the second electrode RME2.

[0117] Contact electrodes CNE1 and CNE2 can contact the light-emitting element ED and electrodes RME1 and RME2, respectively. The semiconductor layer of the light-emitting element ED is exposed at both end surfaces in the extending direction of the light-emitting element ED, and the first contact electrode CNE1 and the second contact electrode CNE2 can contact the light-emitting element ED at the exposed end surfaces of the exposed semiconductor layer. One end of the light-emitting element ED can be electrically connected to the first electrode RME1 through the first contact electrode CNE1, and the other end of the light-emitting element ED can be electrically connected to the second electrode RME2 through the second contact electrode CNE2.

[0118] Although a first contact electrode CNE1 and a second contact electrode CNE2 are provided in a sub-pixel PXn in the accompanying drawings, this disclosure is not limited thereto. The number of first contact electrodes CNE1 and second contact electrodes CNE2 can vary depending on the number of first electrodes RME1 and second electrodes RME2 provided in each of the sub-pixels PXn.

[0119] Contact electrodes CNE1 and CNE2 may comprise conductive materials. For example, contact electrodes CNE1 and CNE2 may comprise ITO, IZO, ITZO, aluminum (Al), etc. For example, contact electrodes CNE1 and CNE2 may comprise transparent conductive materials, and light emitted from the light-emitting element ED may be transmitted through contact electrodes CNE1 and CNE2 to propagate toward electrodes RME1 and RME2. However, it is to be understood that this disclosure is not limited thereto.

[0120] In some embodiments, an insulating layer may be disposed on the contact electrodes CNE1 and CNE2 and the second embankment BNL2 to cover them. The insulating layer may be disposed entirely on the first substrate SUB to protect the components disposed on the first substrate SUB from external environmental influences.

[0121] Each of the first insulating layer PAS1 and the second insulating layer PAS2 may comprise an inorganic insulating material or an organic insulating material. According to embodiments of this disclosure, the first insulating layer PAS1 and the second insulating layer PAS2 may comprise an inorganic insulating material, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The first insulating layer PAS1 and the second insulating layer PAS2 may comprise organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate, polymethyl methacrylate-polycarbonate synthetic resin, etc. However, it will be understood that this disclosure is not limited thereto.

[0122] As described above, the display device 10 according to the embodiment may include an electrode pattern CP, which is separated at the cut-out region CBA and disposed in the non-emission region or below the second embankment BNL2.

[0123] Figure 5 It is along Figure 3 The sectional view taken by line Q3-Q3' in the middle. Figure 5A cross-section between the electrode pattern CP and the first electrode RME1 is shown, with the first electrode RME1 spaced apart from the electrode pattern CP.

[0124] Combination Figure 3 Reference Figure 5 The display device 10 according to an embodiment may include an electrode pattern CP disposed in each of the sub-pixels PXn and separated from the first electrode RME1. Each of the sub-pixels PXn may include an emission region EMA and a notch region CBA, and the electrode pattern CP may be separated from the first electrode RME1 at the notch region CBA. For example, the electrode pattern CP may be spaced apart from the first electrode RME1 in the notch region CBA along a second direction DR2 in which the first electrode RME1 extends. The electrode pattern CP may be formed to be connected to the first electrode RME1 and may be disconnected from the first electrode RME1 at the notch region CBA.

[0125] According to embodiments of this disclosure, the electrode pattern CP can be configured to overlap with the first voltage line VL1 in a third direction DR3 (e.g., the thickness direction). The electrode pattern CP can contact the first voltage line VL1 through a third contact opening (e.g., a third contact hole) CT3 penetrating the third interlayer dielectric layer IL3. An electrical signal applied to the first voltage line VL1 can be transmitted to the electrode pattern CP. During the manufacturing process of the display device 10, an alignment signal can be transmitted through the first voltage line VL1 and applied to the first electrode RME1, and when driving the display device 10, a first supply voltage can be transmitted to the first electrode RME1.

[0126] The electrode pattern CP is a trace (e.g., an electrical trace) separate from the first electrode RME1 and may have a shape that takes into account connection with the first voltage line VL1. For example, the electrode pattern CP may include a first portion in the third contact hole CT3 and a second portion connected to the first portion and separate from the first electrode RME1 with a different width. At least the first portion of the electrode pattern CP may overlap with the first voltage line VL1, and the second portion of the electrode pattern CP may have the same width as the first electrode RME1 and be separate from the first electrode RME1. However, it is to be understood that this disclosure is not limited thereto. The electrode pattern CP may substantially have a shape that includes only the first portion connected to the first voltage line VL1.

[0127] Unlike the first electrode RME1, the electrode pattern CP may not be superimposed on the first barrier BNL1. The electrode pattern CP may be disposed at a position extending from the first electrode RME1 along the second direction DR2, and may be directly disposed on the portion of the third interlayer dielectric layer IL3 that does not have the first barrier BNL1.

[0128] As will be described in more detail below, a process of separating the first electrode RME1 from the electrode pattern CP in the notch region CBA can be performed after aligning the light-emitting element ED and forming the second insulating layer PAS2. The second insulating layer PAS2 may be disposed in the emitting region EMA but not in the notch region CBA, and only the electrodes RME1 and RME2 and the first insulating layer PAS1 covering them may be disposed in the notch region CBA. When separating the first electrode RME1 from the electrode pattern CP, a portion of the first insulating layer PAS1 disposed thereon may also be removed. As a result, in the notch region CBA, the separated side surfaces of the first electrode RME1 and the electrode pattern CP can be aligned with the side surfaces of the first insulating layer PAS1, respectively. A third interlayer dielectric layer IL3 may be exposed between the separated first electrode RME1 and the electrode pattern CP. According to an embodiment of the present disclosure, the electrode pattern CP is formed via a process of separating it from the first electrode RME1 in the notch region CBA during the manufacturing process of the display device 10, and can therefore be disposed outside the notch region CBA, for example, outside the emitting region EMA.

[0129] During the manufacturing process of the display device 10, the alignment signal applied to the first voltage line VL1 can be transmitted to the first electrode RME1 via the electrode pattern CP, and the alignment signal applied to the second voltage line VL2 can be directly transmitted to the second electrode RME2. When the light-emitting element ED is disposed on electrodes RME1 and RME2, a process of separating the first electrode RME1 from the electrode pattern CP can be performed, so that the signal applied to the first voltage line VL1 is not directly transmitted to the first electrode RME1. According to an embodiment of the present disclosure, the separation process is performed in the cut-out region CBA of each of the sub-pixels PXn, and the electrode pattern CP can be retained such that it is superimposed on the second embankment BNL2. Compared with conventional display devices in which the alignment signal is directly applied to the connecting electrodes disposed in multiple sub-pixels, when the alignment signal is applied through a third conductive layer with relatively low line resistance in the display device 10, problems such as heat generation and voltage drop in the alignment signal caused by the applied signal can be mitigated or avoided. Furthermore, since the electric field formed by the alignment signal does not produce or has a relatively weak intensity at the boundary between electrodes RME1 and RME2 in the direction between adjacent sub-pixels PXn along their adjacent directions, it can prevent or substantially prevent the light-emitting element ED from being aligned at an undesirable location.

[0130] Figure 6 This is a schematic diagram illustrating a light-emitting element according to an embodiment of the present disclosure.

[0131] The light-emitting element (ED) can be a light-emitting diode (LED). For example, the ED can have a micrometer or nanometer size (e.g., micrometer or nanometer dimensions) and can be an inorganic LED comprising (or made of) inorganic materials. Due to the polarity created by forming an electric field between the two electrodes in a direction (e.g., a specific direction), an inorganic LED can be aligned between two electrodes facing each other. For example, the ED can be aligned between the two electrodes by an electric field formed between them.

[0132] The light-emitting element (ED) according to the embodiments can have a shape extending in one direction. The ED can have a cylindrical shape, a rod shape, a line shape, a tube shape, etc. However, it should be understood that the shape of the ED is not limited to these. The ED can have various suitable shapes, including polygonal prism shapes such as cubes, cuboids, hexagonal prisms, etc., or shapes extending in one direction with partially inclined outer surfaces. Multiple semiconductors included in the ED, described in more detail below, can have a structure in which they are arranged sequentially or stacked along one direction.

[0133] An ED (Emitting Light) element may comprise a semiconductor layer doped with conductive impurities (e.g., p-type or n-type). An ED can emit light of a specific wavelength by transmitting an electrical signal applied from an external power source.

[0134] like Figure 6 As shown, the light-emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, an emitting layer 36, an electrode layer 37, and an insulating layer 38.

[0135] The first semiconductor layer 31 may be an n-type semiconductor. When the light-emitting element ED emits blue light, the first semiconductor layer 31 may include a semiconductor material having the following chemical formula: Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it can be at least one of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer 31 can be doped with an n-type dopant, and the n-type dopant can be Si, Ge, Sn, etc. For example, the first semiconductor layer 31 can be n-GaN doped with n-type Si. The length of the first semiconductor layer 31 can be, but is not limited to, in the range of about 1.5 μm to about 5 μm. The first end of the light-emitting element ED can represent the side of the emitting layer 36 where the first semiconductor layer 31 is disposed.

[0136] The second semiconductor layer 32 is disposed on the emitting layer 36. The second semiconductor layer 32 may be a p-type semiconductor. When the light-emitting element ED emits blue or green light, the second semiconductor layer 32 may include a semiconductor material having the following chemical formula: Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, it can be at least one of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer 32 can be doped with a p-type dopant, and the p-type dopant can be Mg, Zn, Ca, Se, Ba, etc. For example, the second semiconductor layer 32 can be p-GaN doped with p-type Mg. The length of the second semiconductor layer 32 can be, but is not limited to, in the range of about 0.05 μm to about 0.10 μm. The second end of the light-emitting element ED can represent the other side of the emitting layer 36 where the second semiconductor layer 32 is disposed.

[0137] Although each of the first semiconductor layer 31 and the second semiconductor layer 32 is shown as a single layer in the figures, this disclosure is not limited thereto. Depending on the material of the emitter layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may also include multiple layers, such as a clad layer or a tensile strain barrier reduction (TSBR) layer.

[0138] An emitting layer 36 is disposed between a first semiconductor layer 31 and a second semiconductor layer 32. The emitting layer 36 may comprise a material having a single quantum well structure or a multi-quantum well structure. When the emitting layer 36 comprises a material having a multi-quantum well structure, the structure may comprise quantum layers and well layers stacked alternately on top of each other. The emitting layer 36 may emit light when electron-hole pairs recombine in the emitting layer 36 in response to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. When the emitting layer 36 emits light in the blue wavelength band, it may comprise materials such as AlGaN and AlGaInN. In some embodiments, when the emitting layer 36 has a multi-quantum well structure in which quantum layers and well layers are stacked alternately on top of each other, the quantum layers may comprise AlGaN or AlGaInN and the well layers may comprise materials such as GaN and AlGaN. For example, the emitting layer 36 may comprise AlGaInN as a quantum layer and AlInN as a well layer, and as described above, the emitting layer 36 may emit blue light in a central (or intermediate) wavelength band of about 450 nm to about 495 nm.

[0139] However, it is to be understood that this disclosure is not limited thereto. The emitting layer 36 may have a structure in which semiconductor materials with large bandgap energies and semiconductor materials with small bandgap energies are stacked alternately, and may include other group III to group V semiconductor materials depending on the wavelength range of the emitted light. Therefore, the light emitted from the emitting layer 36 is not limited to blue light. In some embodiments, the emitting layer 36 may emit red or green light. The length of the emitting layer 36 may be, but is not limited to, from about 0.05 μm to about 0.10 μm.

[0140] Light emitted from the emitting layer 36 can exit not only through the outer surface of the light-emitting element ED in the longitudinal direction, but also through the two side surfaces. That is to say, the direction of propagation of light emitted from the emitting layer 36 is not limited to one direction.

[0141] Electrode layer 37 may be an ohmic contact electrode. However, it is to be understood that this disclosure is not limited thereto. Electrode layer 37 may be a Schottky contact electrode. A light-emitting element ED may include at least one electrode layer 37. Although in Figure 6 The example shown includes an electrode layer 37, but this disclosure is not limited thereto. In some embodiments, the light-emitting element ED may include a larger number of electrode layers 37, or the electrode layers may be omitted. The following description of the light-emitting element ED may be applied equivalently even when the number of electrode layers 37 is different or when the light-emitting element ED includes other structures.

[0142] When the light-emitting element ED is electrically connected to an electrode or contact electrode in the display device 10 according to an embodiment of the present disclosure, the electrode layer 37 can reduce the resistance between the light-emitting element ED and the electrode or contact electrode. The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO. Furthermore, the electrode layer 37 may include a semiconductor material doped with n-type or p-type impurities. The electrode layer 37 may include the same material as the corresponding semiconductor layer, or it may include a different material. However, it is to be understood that the present disclosure is not limited thereto.

[0143] The insulating layer 38 is configured to surround the outer surfaces of the plurality of semiconductor layers and electrode layers. For example, the insulating layer 38 may be configured to at least surround the outer surface of the emitting layer 36 (e.g., to extend at least around the outer surface of the emitting layer 36), and may extend in the direction in which the light-emitting element ED extends. The insulating layer 38 can protect the aforementioned element. The insulating layer 38 may be formed to surround the side surfaces of the element while exposing both ends of the light-emitting element ED in the longitudinal direction.

[0144] Although the insulating layer 38 is shown extending in the longitudinal direction of the light-emitting element ED to cover the light-emitting element ED from the side surface of the first semiconductor layer 31 to the side surface of the electrode layer 37, this disclosure is not limited thereto. The insulating layer 38 may cover only a portion of the outer surface of the semiconductor layer (including the emitting layer 36), or it may cover only a portion of the outer surface of the electrode layer 37 to partially expose the outer surface of the electrode layer 37. Furthermore, in the cross-sectional view, the portion of the upper surface of the insulating layer 38 adjacent to at least one end of the light-emitting element ED may be circular.

[0145] The thickness of the insulating layer 38 may be, but is not limited to, in the range of 10 nm to 1.0 μm. Preferably, the thickness of the insulating layer 38 may be about 40 nm.

[0146] Insulating layer 38 may include a material with insulating properties, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y The light-emitting layer 36 contains aluminum nitride (AlN) and aluminum oxide (Al2O3). Therefore, it prevents electrical short circuits when the emitting layer 36 contacts the electrodes of the light-emitting element ED through which electrical signals are transmitted. Furthermore, because the insulating layer 38 protects the outer surface of the light-emitting element ED, including the emitting layer 36, it prevents a decrease in luminous efficiency.

[0147] Furthermore, the outer surface of the insulating layer 38 can be surface-treated. The light-emitting element ED can be dispersed in ink, and the ink can be sprayed onto the electrode. The insulating layer 38 can be surface-treated to make it hydrophobic or hydrophilic to prevent the light-emitting elements ED dispersed in the ink from agglomerating together. For example, the outer surface of the insulating layer 38 can be surface-treated with materials such as stearic acid and 2,3-naphthalenedicarboxylic acid.

[0148] The length h of the light-emitting element ED can range from about 1 μm to about 10 μm, from about 2 μm to about 6 μm, or from about 3 μm to about 5 μm. Furthermore, the diameter of the light-emitting element ED can range from about 30 nm to about 700 nm, and the aspect ratio of the light-emitting element ED can range from about 1.2 to about 100. However, it is to be understood that this disclosure is not limited thereto. Multiple light-emitting elements ED included in the display device 10 can have different diameters depending on the composition of the emitting layer 36. For example, the diameter of the light-emitting element ED can be about 500 nm.

[0149] The manufacturing process steps of the display device 10 will be described below with reference to the other accompanying drawings.

[0150] Figures 7 to 12This is a schematic diagram illustrating the process steps for manufacturing a display device according to an embodiment of the present disclosure. In the following description, for clarity, the process sequence for manufacturing the display device 10 will be described in detail, while some descriptions of repeated methods and structures for each element may be omitted.

[0151] First, refer to Figure 7 A first substrate SUB is prepared, and a circuit layer is formed on the first substrate SUB. The circuit layer includes multiple conductive layers and semiconductor layers, and includes multiple transistors for driving sub-pixels PXn. Figure 7 A first voltage line VL1, a second voltage line VL2, and a first conductive pattern CDP are shown, forming a third conductive layer. Multiple conductive and semiconductor layers can be formed via a process that includes depositing material and then patterning it.

[0152] Subsequently, referring to Figure 8 and Figure 9 A third interlayer dielectric layer IL3 is formed on the third conductive layer, and a first dam BNL1, a first electrode RME1, a second electrode RME2, a first insulating layer PAS1, and a second dam BNL2 are formed on the third interlayer dielectric layer IL3. The first dam BNL1 and the second dam BNL2 can be configured as described above. The first dam BNL1 can be configured across adjacent sub-pixels PXn in the first direction DR1 to form an island pattern on the entire surface of the display area DPA. The second dam BNL2 is configured to surround the emission area EMA and the notched area CBA.

[0153] The first electrode RME1 and the second electrode RME2 may extend in the second direction DR2. Each of the first electrode RME1 and the second electrode RME2 may traverse (or extend through) the emission region EMA and the cutout region CBA, but may not extend in the second direction DR2 beyond the boundary with other adjacent sub-pixels PXn. For example, in the display device 10 according to an embodiment of the present disclosure, electrodes RME1 and RME2 may be separated from the electrodes RME1 and RME2 of adjacent (or neighboring) sub-pixels PXn, and may be disposed only within the respective sub-pixels PXn. Electrodes RME1 and RME2 in each of the sub-pixels PXn may form an island pattern or a linear pattern on the entire surface of the display area DPA.

[0154] The portion (or portion) of the first electrode RME1 that overlaps with the second dam BNL2 located on the upper side of the emitter region EMA (relative to the drawing) is formed as a first electrode contact CTP1 to connect the first electrode RME1 to the circuit layer below it (e.g., the first conductive pattern CDP). The second electrode RME2 extends from the emitter region EMA to the cutout region CBA. The portion (or portion) of the second electrode RME2 that overlaps with the second dam BNL2 located on the lower side of the cutout region CBA (relative to the drawing) is formed as a second electrode contact CTP2. The second electrode contact CTP2 can contact the circuit layer below it (e.g., the second voltage line VL2). The electrode pattern CP can be formed to overlap with the second dam BNL2 located on the lower side of the cutout region CBA and can contact the circuit layer below it (e.g., the first voltage line VL1).

[0155] The reference shows along Figure 8 The cross section intercepted by line Q4-Q4' in the middle Figure 9 The first electrode RME1 is connected to the electrode pattern CP via the connector BP in the cut area CBA. During the manufacturing process of the display device 10, the first electrode RME1 and the electrode pattern CP are connected to each other via the connector BP, so that the alignment signal applied to the first voltage line VL1 can be transmitted to the first electrode RME1 through the electrode pattern CP and the connector BP. The first electrode RME1 and the second electrode RME2 can be electrically connected to the first voltage line VL1 and the second voltage line VL2, respectively, and can be used to generate an electric field in each of the sub-pixels PXn during the process of aligning the light-emitting element ED.

[0156] Subsequently, referring to Figure 10 and Figure 11 A plurality of light-emitting elements (EDs) are disposed on the first electrode RME1 and the second electrode RME2, and a second insulating layer PAS2' is formed on the EDs to fix them in place. According to embodiments of this disclosure, ink in which the EDs are dispersed is prepared and can be sprayed onto the emitting region EMA via an inkjet printing process. A second dam BNL2 can prevent or substantially prevent ink spillage into the emitting region EMA of adjacent sub-pixels PXn. When the ink is sprayed onto the emitting region EMA, alignment signals are applied to the first voltage line VL1 and the second voltage line VL2 to generate an electric field between electrodes RME1 and RME2. The EDs dispersed in the ink can receive (or be acted upon by) electrophoretic forces induced by the electric field, thus changing their position and orientation so that their ends can be aligned with electrodes RME1 and RME2, respectively.

[0157] According to embodiments of this disclosure, during the manufacturing process of the display device 10, alignment signals for aligning the light-emitting element ED can be applied to a first voltage line VL1 and a second voltage line VL2 of a third conductive layer. Electrodes RME1 and RME2 of each of the plurality of sub-pixels PXn are formed separately from each other (e.g., are isolated from each other) and can be electrically connected to the first voltage line VL1 and the second voltage line VL2, respectively. The first electrode RME1 can be connected to an electrode pattern CP connected to the first voltage line VL1 via a connection portion BP, and the second electrode RME2 can be directly connected to the second voltage line VL2. When the alignment signal is applied to the first voltage line VL1 and the second voltage line VL2, an electric field can be generated (e.g., synchronously or simultaneously generated) on the electrodes RME1 and RME2 disposed in each of the plurality of sub-pixels PXn, and the light-emitting element ED can be aligned in each of the sub-pixels PXn. According to embodiments of this disclosure, since the alignment signal is applied through a third conductive layer having low line resistance, unlike conventional display devices in which the alignment signal is applied directly to connected electrodes RME1 and RME2 disposed in multiple sub-pixels, problems of heat generation and voltage drop in the alignment signal caused by the applied signal can be prevented or mitigated.

[0158] Once the light-emitting element ED is in place, a second insulating layer PAS2' is formed to secure the light-emitting element ED. Reference is shown along... Figure 10 The cross section intercepted by line Q5-Q5' in the middle Figure 11 The second insulating layer PAS2' can cover the light-emitting element ED and can be disposed on the first insulating layer PAS1 in the emitting region EMA. After the light-emitting element ED is aligned, the light-emitting element ED can be covered by the second insulating layer PAS2' used to fix the position of the light-emitting element ED on electrodes RME1 and RME2. Therefore, after the light-emitting element ED is aligned, the position of the light-emitting element ED can remain unchanged or substantially unchanged during subsequent processes used to form contact electrodes CNE1 and CNE2.

[0159] Subsequently, referring to Figure 12The process involves removing the connection portion BP connecting the first electrode RME1 and the electrode pattern CP at the cut area CBA to separate the first electrode RME1 from the first voltage line VL1. This process may include removing the connection portion BP from the electrode separation portion ROP located in the cut area CBA. Because the electrode pattern CP, which directly connects the first voltage line VL1 and the first electrode RME1, is separated from the first electrode RME1 during this process, the first electrode RME1 can only be connected to the first transistor T1 via the first electrode contact portion CTP1. During the manufacturing process of the display device 10, an alignment signal applied to the first voltage line VL1 can be transmitted to the first electrode RME1 via the electrode pattern CP, and a first supply voltage applied to the first voltage line VL1 can be transmitted to the first transistor T1 of the sub-pixel PXn. For example, during driving the display device 10, the first electrode RME1 can be driven individually by the first transistor T1 of the corresponding sub-pixel PXn, while during the manufacturing process, an alignment signal is applied (e.g., synchronously or simultaneously) to the first electrode RME1 located in multiple sub-pixels PXn.

[0160] Then, a portion of the second insulating layer PAS2' is removed, exposing both ends of the light-emitting element ED to form the second insulating layer PAS2, and contact electrodes CNE1 and CNE2 are formed to contact the light-emitting element ED and electrodes RME1 and RME2, respectively. During the process of removing the second insulating layer PAS2' to form the second insulating layer PAS2, both ends of the light-emitting element ED where the semiconductor layer is disposed can be exposed. Simultaneously (or concurrently), a portion of the first insulating layer PAS1 is also removed, exposing the upper surfaces of the first electrode RME1 and the second electrode RME2, and the subsequently formed contact electrodes CNE1 and CNE2 can contact electrodes RME1 and RME2 and the ends of the light-emitting element ED, respectively. However, it is to be understood that this disclosure is not limited thereto. The first insulating layer PAS1 may have openings therein exposing the upper surfaces of the electrodes RME1 and RME2, and the process of removing a portion of the second insulating layer PAS2' may be performed before forming the contact electrodes CNE1 and CNE2.

[0161] By performing the above-described process, a display device 10 according to an embodiment of the present disclosure can be manufactured. The display device 10 can apply an alignment signal for aligning the light-emitting element ED via a first voltage line VL1 and a second voltage line VL2, and can generate an electric field between electrodes RME1 and RME2, which are separately disposed in each of the sub-pixels PXn. Because the alignment signal applied for aligning the light-emitting element ED is applied through a third conductive layer having low line resistance beneath the display element layer, problems such as heat generation due to the applied signal and voltage drop in the alignment signal can be prevented or mitigated.

[0162] Although each of the sub-pixels PXn in the embodiment shown in the accompanying drawings includes only one first electrode RME1 and one second electrode RME2, this disclosure is not limited thereto. In the display device 10 according to embodiments of this disclosure, more electrodes may be provided in each of the sub-pixels PXn. Some of the electrodes may be connected to each other such that the same alignment signal is applied to them during the process of manufacturing the light-emitting element ED, while only some of the electrodes may be signaled during the process of driving the display device 10. In the following, other embodiments of display devices according to this disclosure will be described with reference to other accompanying drawings.

[0163] Figure 13 This is a plan view illustrating the pixels of a display device according to another embodiment of the present disclosure. Figure 14 It is shown Figure 13 The plan view of the first sub-pixel of the display device shown. Figure 15 It is along Figure 14 The sectional view taken from line Q6-Q6' in the middle. Figure 14 It shows Figure 13 The first sub-pixel PX1 of the display device 10_1 shown. Figure 15 It shows the setting from Figure 14 A cross-sectional view of the first light-emitting element ED1 and the second light-emitting element ED2 in the first sub-pixel PX1 shown from one end to the other.

[0164] Reference Figures 13 to 15According to an embodiment, the display device 10_1 may include a larger number of electrodes RME1_1, RME2_1, RME3_1, and RME4_1, light-emitting elements ED1 and ED2, and contact electrodes CNE1_1, CNE2_1, and CNE3_1 in each of the sub-pixels PXn. In addition to the first electrode RME1_1 and the second electrode RME2_1 disposed in each of the sub-pixels PXn, the display device 10_1 may also include a third electrode RME3_1 and a fourth electrode RME4_1 disposed in each of the sub-pixels PXn, and may include a first light-emitting element ED1 disposed between the first electrode RME1_1 and the third electrode RME3_1 and a second light-emitting element ED2 disposed between the second electrode RME2_1 and the fourth electrode RME4_1. Each of the sub-pixels PXn may include a larger number of light-emitting elements ED1 and ED2, thereby improving the brightness per unit area. Furthermore, unlike the first electrode RME1_1 and the second electrode RME2_1, the third electrode RME3_1 and the fourth electrode RME4_1 may not be directly connected to the third conductive layer, but the first light-emitting element ED1 and the second light-emitting element ED2 can be connected in series with each other through the third contact electrode CNE3_1. In the following description, the focus will be on... Figures 2 to 5 The embodiments shown are similar to Figures 13 to 15 The differences between the embodiments shown are as follows.

[0165] Each of the first voltage line VL1 and the second voltage line VL2 in the third conductive layer can extend along the second direction DR2. The first voltage line VL1 may include a portion extending along the second direction DR2 and a portion bending therefrom. The portion of the first voltage line VL1 that extends and bends along the second direction DR2 at the boundary of the sub-pixel PXn may be located within the emission region EMA. The bent portion may be configured to overlap with the first electrode RME1_1 in the thickness direction. When viewed from top, the second voltage line VL2 may extend from the center of each of the sub-pixels PXn along the second direction DR2 and may overlap with the second electrode RME2_1 and the third electrode RME3_1 in the thickness direction.

[0166] The second voltage line VL2 may overlap with the second sub-dike BNL_B in the thickness direction and may extend in the second direction DR2. Furthermore, the second voltage line VL2 may include a line contact portion protruding in one direction of the first direction DR1 from below the extension portion of the second dike BNL2 along the first direction DR1. The second electrode RME2_1 is formed such that the second electrode contact portion CTP2 overlaps with the line contact portion in the thickness direction, and they can be connected to each other through a second contact opening (e.g., a second contact hole) CT2.

[0167] The first embankment BNL1 may include a first sub-embankment BNL_A disposed across adjacent sub-pixels PXn and a second sub-embankment BNL_B disposed between the first sub-embankments BNL_A. A plurality of second sub-embankments BNL_B extend in the second direction DR2 and are spaced apart from each other in the first direction DR1, and are disposed at the center of the emission region EMA. The first sub-embankments BNL_A may be disposed on both sides of the second sub-embankments BNL_B in the first direction DR1. In addition to the first embankment BNL1 according to this embodiment also including first sub-embankments BNL_A arranged in substantially the same pattern and second sub-embankments BNL_B disposed between the first sub-embankments BNL_A spaced apart from each other in the first direction DR1, the first embankment BNL1 according to this embodiment and... Figure 3 The first embankment BNL1 shown is essentially the same.

[0168] The first electrode RME1_1 can extend along the second direction DR2 and can traverse the emission region EMA to reach the cutout region CBA. The portion of the first electrode RME1 that overlaps with the second dike BNL2 located above the emission region EMA forms a first electrode contact portion CTP1, and the first electrode contact portion CTP1 can contact the first conductive pattern CDP through a first contact opening (e.g., a first contact hole) CT1. The first electrode RME1_1 can extend from the first electrode contact portion CTP1 along the second direction DR2 and can be partially disposed within the cutout region CBA, but may not extend beyond the cutout region CBA. Furthermore, the first electrode RME1_1 can be disposed on the first sub-dike BNL_A located on the left side of the emission region EMA within the first sub-dike BNL_A.

[0169] Similar to the first electrode RME1_1, the second electrode RME2_1 can also extend along the second direction DR2 and can traverse the emission region EMA to reach the cutout region CBA. The portion of the second electrode RME2_1 that overlaps with the second embankment BNL2 located above the emission region EMA forms a second electrode contact portion CTP2, and the second electrode contact portion CTP2 can contact the second voltage line VL2 through a second contact opening (e.g., a second contact hole) CT2. The second electrode RME2_1 can extend from the second electrode contact portion CTP2 along the second direction DR2 and can be partially disposed within the cutout region CBA, but may not extend beyond the cutout region CBA. Furthermore, the second electrode RME2_1 can be disposed on the right side of the second sub-embankment BNL_B along the first direction DR1.

[0170] The third electrode RME3_1 can be disposed between the first electrode RME1_1 and the second electrode RME2_1, and the fourth electrode RME4_1 can be disposed on the opposite side of the second electrode RME2_1 relative to the third electrode RME3_1. The third electrode RME3_1 and the fourth electrode RME4_1 can extend in the second direction DR2 and can be spaced apart from the second electrode RME2_1 disposed therebetween in the first direction DR1. Each of the third electrode RME3_1 and the fourth electrode RME4_1 can partially overlap with the second embankment BNL2 located on the upper side of the emission region EMA and can extend from the emission region EMA to the cutout region CBA. Although the length of the third electrode RME3_1 in the second direction DR2 is greater than the length of the fourth electrode RME4_1 in the second direction DR2 in the figures, this disclosure is not limited thereto. The third electrode RME3_1 and the second electrode RME2_1 are disposed on the same second sub-embankment BNL_B, but the third electrode RME3_1 is disposed on the left side of the first direction DR1 (the other side of the second sub-embankment BNL_B). The fourth electrode RME4_1 is located on another first sub-dike BNL_A that is different from the first sub-dike BNL_A on which the first electrode RME1_1 is disposed, and can be disposed on the first sub-dike BNL_A located on the right side of the center of the emission region EMA.

[0171] Unlike the first electrode RME1_1 and the second electrode RME2_1, the third electrode RME3_1 and the fourth electrode RME4_1 may not include electrode contacts and may not be connected to the underlying third conductive layer. Although the third electrode RME3_1 and the fourth electrode RME4_1 can be electrically connected to the second voltage line VL2 and the first voltage line VL1 during the manufacturing process of the display device 10_1 so that alignment signals are transmitted to them, they can be separated from the electrode separation portion ROP and may not be directly connected to the underlying circuit layer. As will be described later, the third electrode RME3_1 and the fourth electrode RME4_1 can contact and connect to the third contact electrode CNE3_1 and may not remain floating.

[0172] A first light-emitting element ED1 is disposed on a first electrode RME1_1 and a third electrode RME3_1, and a second light-emitting element ED2 is disposed on a second electrode RME2_1 and a fourth electrode RME4_1. The light-emitting elements ED1 and ED2 can be oriented such that their first ends, where the first semiconductor layer 31 is disposed, face each other. Because the sub-pixels PXn of the display device 10_1 include a larger number of electrodes, the first end of the first light-emitting element ED1 can face a direction opposite to the direction in which the first end of the second light-emitting element ED2 faces. For example, the first end of the first light-emitting element ED1 can be disposed on the third electrode RME3_1, while the opposite second end of the first light-emitting element ED1 can be disposed on the first electrode RME1_1. Therefore, the first light-emitting elements ED1 can be arranged such that their first ends face one side in the first direction DR1. On the other hand, the first end of the second light-emitting element ED2 can be disposed on the second electrode RME2_1, while the opposite second end of the second light-emitting element ED2 can be disposed on the fourth electrode RME4_1. Therefore, the second light-emitting elements ED2 can be arranged such that their first ends face the other side in the first direction DR1. The first light-emitting element ED1 and the second light-emitting element ED2, which have opposite orientations, can be connected in series with each other by a third contact electrode CNE3_1, which will be described in more detail below.

[0173] The first contact electrode CNE1_1 can be disposed on the first electrode RME1_1 and can contact the second end of the first light-emitting element ED1. The second contact electrode CNE2_1 can be disposed on the second electrode RME2_1 and can contact the first end of the second light-emitting element ED2. The first contact electrode CNE1_1 and the second contact electrode CNE2_1 can contact the first electrode RME1_1 and the second electrode RME2_1 respectively, and they can transmit the supply voltage for driving the light-emitting elements ED1 and ED2 through the first transistor T1 and the second voltage line VL2.

[0174] The third contact electrode CNE3_1 can be disposed on the third electrode RME3_1 and the fourth electrode RME4_1. The third contact electrode CNE3_1 may include an electrode extension extending in the second direction DR2 and disposed on the third electrode RME3_1 or the fourth electrode RME4_1, and a plurality of electrode connecting portions connecting therebetween. The electrode extension of the third contact electrode CNE3_1 can be disposed on the third electrode RME3_1 or the fourth electrode RME4_1 and can extend in the second direction DR2. The electrode connecting portions of the third contact electrode CNE3_1 can extend in the first direction DR1 to connect between the electrode extensions. When viewed from above, the third contact electrode CNE3_1 can be arranged in a shape surrounding the second contact electrode CNE2_1 (e.g., extending around the second contact electrode CNE2_1).

[0175] The electrode extension of the third contact electrode CNE3_1 can contact one end of the third electrode RME3_1 or the fourth electrode RME4_1, as well as one end of the light-emitting elements ED1 and ED2. For example, the electrode extension of the third contact electrode CNE3_1 disposed on the third electrode RME3_1 can contact the first end of the third electrode RME3_1 and the first light-emitting element ED1, and the electrode extension of the third contact electrode CNE3_1 disposed on the fourth electrode RME4_1 can contact the second end of the fourth electrode RME4_1 and the second light-emitting element ED2.

[0176] The supply voltage can be applied to the first light-emitting element ED1 and the second light-emitting element ED2 through the first contact electrode CNE1_1 and the second contact electrode CNE2_1, respectively. The supply voltage can flow through light-emitting elements ED1 and ED2, and can also flow through the third contact electrode CNE3_1 between the first light-emitting element ED1 and the second light-emitting element ED2. The third contact electrode CNE3_1 can form a connection path between the first light-emitting element ED1 and the second light-emitting element ED2, and the first light-emitting element ED1 and the second light-emitting element ED2 can be connected in series with each other through the third contact electrode CNE3_1. Furthermore, because the third contact electrode CNE3_1 contacts the third electrode RME3_1 and the fourth electrode RME4_1, the third electrode RME3_1 and the fourth electrode RME4_1 do not need to be floating, but can be electrically connected to the underlying circuit layer even if they are not directly connected to the circuit layer.

[0177] Incidentally, even when the display device 10_1 includes a larger number of electrodes in each of the sub-pixels PXn, the electrodes disposed in each of the sub-pixels PXn can be similar to Figure 2 and Figure 3 The electrodes of the above-described embodiment shown are separated from those of the other sub-pixels PXn. During the manufacturing process of the display device 10_1, some of the electrodes RME1_1, RME2_1, RME3_1, and RME4_1 provided in each of the sub-pixels PXn can be connected to each other, so that an alignment signal can be applied through the first voltage line VL1 and the second voltage line VL2. After the light-emitting elements ED (including ED1 and ED2) are aligned, a process can be performed to remove the connection portions BP connecting the electrodes RME1_1, RME2_1, RME3_1, and RME4_1. Therefore, the display device 10_1 according to the embodiments of the present disclosure may include an electrode pattern CP_1 formed separately from the electrodes RME1_1, RME2_1, RME3_1, and RME4_1 in the cut-out region CBA.

[0178] Figure 16 It is along Figure 14A sectional view taken from line Q7-Q7'.

[0179] Combination Figure 14 Reference Figure 16 Electrode pattern CP_1 can be disposed in a region other than the emitter region EMA, such that it overlaps with the second dam BNL2. Electrode pattern CP_1 can be disposed on one side of the notch region CBA in the first direction DR1, overlapping with the second dam BNL2 extending in the second direction DR2. Electrode pattern CP_1 can be disposed between the notch regions CBA of adjacent sub-pixels PXn along the first direction DR1, and a portion of electrode pattern CP_1 may include traces separated from the notch regions CBA of the respective sub-pixels PXn. For example, electrode pattern CP_1 can be disposed outside the emitter region EMA. Electrode pattern CP_1 can be disposed on the first voltage line VL1 below it (e.g., electrode pattern CP_1 can be disposed above the first voltage line VL1), and can contact the first voltage line VL1 by penetrating the third contact opening (e.g., the third contact hole) CT3 of the third interlayer dielectric layer IL3. Although electrode pattern CP_1 is disposed between the notch regions CBA of adjacent sub-pixels PXn in the figures, this disclosure is not limited thereto. There are no particular restrictions on the position of the electrode pattern CP_1, as long as it is connected to the first voltage line VL1 and separated from the first electrode RME1_1.

[0180] As described above, after aligning the light-emitting element ED and forming the second insulating layer PAS2, a process is performed to separate the electrodes RME1_1, RME2_1, RME3_1, and RME4_1 from the electrode pattern CP_1. When separating the electrode pattern CP_1 in the notch region CBA, the first insulating layer PAS1 can also be removed, and a portion of the upper surface of the third interlayer dielectric layer IL3 in the notch region CBA can be exposed. Furthermore, since the first insulating layer PAS1 and the electrodes RME1_1, RME2_1, RME3_1, and RME4_1 can be removed together, their separated side surfaces can be aligned with each other.

[0181] In addition to the first electrode RME1_1 and the second electrode RME2_1, each of the sub-pixels PXn of the display device 10_1 according to this embodiment may also include a third electrode RME3_1 and a fourth electrode RME4_1. The light-emitting element ED may include a first light-emitting element ED1 and a second light-emitting element ED2 whose first ends are opposite to each other, and the first light-emitting element ED1 and the second light-emitting element ED2 may be connected in series with each other via a third contact electrode CNE3_1. During the manufacturing process of the display device 10_1, some of the electrodes RME1_1, RME2_1, RME3_1, and RME4_1 are connected to each other and can receive the same alignment signal, causing the first light-emitting element ED1 and the second light-emitting element ED2 to be oriented in opposite directions.

[0182] Figure 17 and Figure 18 It shows the manufacturing process. Figure 14 A plan view of some of the process steps of the display device shown.

[0183] Reference Figure 17 and Figure 18 During the manufacturing process of the display device 10_1, the first electrode RME1_1 and the fourth electrode RME4_1 can be connected to the electrode pattern CP_1 via the first connecting portion BP1, and the second electrode RME2_1 and the third electrode RME3_1 can be connected to each other via the second connecting portion BP2. The first connecting portion BP1 and the second connecting portion BP2 can be provided in the cut area CBA to connect the electrodes RME1_1, RME2_1, RME3_1 and RME4_1 to each other. For example, the first connecting portion BP1 can also be connected to the electrode pattern CP_1 which is directly connected to the first voltage line VL1.

[0184] Alignment signals applied to the first voltage line VL1 are transmitted to the first electrode RME1_1 and the fourth electrode RME4_1 via the electrode pattern CP_1 and the first connection portion BP1. Alignment signals applied to the second voltage line VL2 are transmitted to the second electrode RME2_1 via the second electrode contact portion CTP2, and then to the third electrode RME3_1 via the second connection portion BP2. Based on the alignment signals applied to each of the first voltage line VL1 and the second voltage line VL2, electric fields can be generated between the first electrode RME1_1 and the third electrode RME3_1, and between the second electrode RME2_1 and the fourth electrode RME4_1. These electric fields can have a direction from the electrode to which the alignment signal is applied towards the electrode to which the other alignment signal is applied. The light-emitting element ED can be oriented according to the direction of the electric field. Because different alignment signals are applied to the first electrode RME1_1 and the fourth electrode RME4_1, as well as the second electrode RME2_1 and the third electrode RME3_1 during the manufacturing process of the display device 10_1, the electric field can be directed towards the second sub-bank BNL_B located at the center of the emitting region EMA, and the first end of the light-emitting element ED can also be disposed on the electrode disposed on the second sub-bank BNL_B. Therefore, the first ends of the first light-emitting element ED1 and the second light-emitting element ED2 can be disposed on the third electrode RME3_1 and the second electrode RME2_1, respectively, and they can be oriented in opposite directions.

[0185] Subsequently, the first connection portion BP1 and the second connection portion BP2 are removed at the electrode separation portion ROP in the cut area CBA to separate electrodes RME1_1, RME2_1, RME3_1, and RME4_1 from each other. The first electrode RME1_1 and the second electrode RME2_1 are connected to the first transistor T1 and the second voltage line VL2 through electrode contacts CTP1 and CTP2 formed in a position overlapping with the second dam BNL2 on the upper side of the emission area EMA. On the other hand, the third electrode RME3_1 and the fourth electrode RME4_1 are separated from the connection portions BP1 and BP2, so they can be de-electrically connected to the circuit layer below them and can remain floating in each of the sub-pixels PXn. The third electrode RME3_1 and the fourth electrode RME4_1 can contact the third contact electrode CNE3_1 formed during subsequent processes and can not remain floating when the display device 10_1 is driven. The electrode pattern CP_1 can be separated from the electrode separation section ROP and can be kept between the cut areas CBA of the adjacent sub-pixel PXn.

[0186] By removing the connecting portions BP1 and BP2 at the electrode separation section ROP to separate the electrodes RME1_1, RME2_1, RME3_1 and RME4_1 from each other, the sub-pixel PXn can be driven independently even when a signal is applied to the first voltage line VL1 and the second voltage line VL2.

[0187] Subsequently, a portion of the first insulating layer PAS1 is removed to form an opening on a portion of the upper surface of the exposed electrode, and contact electrodes CNE1_1, CNE2_1 and CNE3_1 are formed, thereby producing the display device 10_1.

[0188] According to this embodiment, a larger number of electrodes RME1_1, RME2_1, RME3_1, and RME4_1 are included, allowing a larger number of light-emitting elements ED1 and ED2 to be disposed in each of the sub-pixels PXn. Even with a larger number of electrodes RME1_1, RME2_1, RME3_1, and RME4_1, only some of them can be electrically connected to the underlying circuit layer, and the first light-emitting element ED1 and the second light-emitting element ED2 can be connected in series with each other through a current path formed by the third contact electrode CNE3_1.

[0189] The light-emitting elements (EDs) can be connected in series with each other via the third contact electrode CNE3_1, which further improves the brightness of each of the sub-pixels PXn. Furthermore, as the number of EDs connected in series increases, even if some EDs break, the other connected EDs can still emit light. As a result, it can prevent or substantially prevent the sub-pixel PXn from failing to emit light.

[0190] In summarizing the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to the embodiments described herein without substantially departing from the aspects and features of this disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense and not for limiting purposes. This disclosure will be defined by the appended claims and their equivalents.

Claims

1. A display device, the display device comprising: Base; A conductive layer is provided on the substrate and includes a first voltage line and a second voltage line extending in a first direction. The first electrode and the second electrode extend in the first direction on the conductive layer and are spaced apart from each other. Multiple light-emitting elements are located on the first electrode and the second electrode; as well as The electrode pattern is located on the conductive layer and is separate from the first electrode. The electrode pattern overlaps with the first voltage line in the thickness direction and directly contacts the first voltage line. Wherein, the first electrode is superimposed on the first voltage line in the thickness direction, and the second electrode is superimposed on the second voltage line in the thickness direction.

2. The display device according to claim 1, wherein, The electrode pattern is spaced apart from the first electrode in the first direction.

3. The display device according to claim 1, further comprising: Interlayer dielectric layer, on the conductive layer, The electrode pattern contacts the first voltage line through contact openings that penetrate the interlayer dielectric layer.

4. The display device according to claim 3, further comprising: Multiple first dikes are located between the interlayer dielectric layer and the first electrode, and between the interlayer dielectric layer and the second electrode. The electrode pattern is not superimposed on the first dam and is directly on the interlayer dielectric layer.

5. The display device according to claim 3, further comprising: The second dike extends on the interlayer dielectric layer and around the periphery of the emitting region where the light-emitting element is arranged and the cut-out region on the first side of the emitting region in the first direction. The electrode pattern is superimposed on the second embankment in the thickness direction.

6. The display device according to claim 5, wherein, The first electrode and the electrode pattern are spaced apart from each other, and the cut area is between them. The second electrode extends from the emission region through the cut region.

7. The display device according to claim 5, wherein, The conductive layer further includes a first conductive pattern electrically connected to the first voltage line via a first transistor between the substrate and the conductive layer. The first electrode directly contacts the first conductive pattern through a first contact opening penetrating the interlayer dielectric layer, and The second electrode directly contacts the second voltage line through a second contact opening that penetrates the interlayer dielectric layer.

8. The display device according to claim 7, wherein, The first electrode contacts the first conductive pattern at a first electrode contact portion, the first electrode contact portion being disposed on a second side of the emission region in the first direction, and The second electrode contacts the second voltage line at the second electrode contact portion, which is located on the first side of the cut area in the first direction.

9. The display device according to claim 1, further comprising: A first insulating layer partially covers the first electrode and the second electrode. The light-emitting element is located directly on the first insulating layer.

10. The display device according to claim 9, further comprising: The first contact electrode is on the first insulating layer and contacts the first electrode and the light-emitting element; as well as The second contact electrode is on the first insulating layer and contacts the second electrode and the light-emitting element.

11. The display device according to claim 9, further comprising: A second insulating layer is applied to the light-emitting element.

12. A display device, the display device comprising: A substrate having an emission region and a cutout region on one side of the emission region; The first electrode and the second electrode extend on the substrate in a first direction and are spaced apart from each other in a second direction; The third electrode is located between the first electrode and the second electrode; A fourth electrode is spaced apart from the third electrode in the second direction, and the second electrode is between the third electrode and the fourth electrode; A conductive layer is provided on the substrate and includes a first voltage line and a second voltage line extending in the first direction. Multiple light-emitting elements are spaced apart from each other in the second direction on at least two of the first to fourth electrodes; The electrode pattern is separate from the first electrode and is located outside the emission region; The first contact electrode is on the first electrode and in contact with the light-emitting element; The second contact electrode is on the second electrode and contacts the light-emitting element; as well as The third contact electrode is located on the third and fourth electrodes and contacts the light-emitting element. The first electrode is stacked with the first voltage line in the thickness direction, and the second electrode is stacked with the second voltage line in the thickness direction.

13. The display device according to claim 12, wherein, The electrode pattern is directly connected to the first voltage line.

14. The display device according to claim 13, wherein, The electrode pattern and the first electrode are partially located in the cut area and are spaced apart from each other.

15. The display device according to claim 13, wherein, The electrode pattern is located on one side of the cut area in the second direction and overlaps with the first voltage line in the thickness direction.

16. The display device according to claim 13, further comprising: A first transistor is located between the substrate and the conductive layer and is electrically connected to the first voltage line. The first electrode is electrically connected to the first transistor, and the second electrode is directly connected to the second voltage line.

17. The display device according to claim 13, further comprising: Multiple first dikes are respectively located between the substrate and the first to fourth electrodes; as well as The second dike extends around the periphery of the launch area and the cut area. Each of the first electrode and the second electrode includes an electrode contact portion that overlaps with the second embankment.

18. The display device according to claim 12, wherein, The light-emitting element includes: a first light-emitting element having a first end on the first electrode and a second end on the third electrode; and a second light-emitting element having a first end on the fourth electrode and a second end on the second electrode.

19. The display device according to claim 18, wherein, The first contact electrode contacts the first end of the first light-emitting element and the first electrode, and The second contact electrode contacts the second end of the second light-emitting element and the second electrode.

20. The display device according to claim 19, wherein, The third contact electrode extends around the periphery of the second contact electrode and contacts the third electrode, the fourth electrode, the second end of the first light-emitting element, and the first end of the second light-emitting element.

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