Display device and method of manufacturing the same

Abstract

A display device and a manufacturing method thereof are provided. The display device includes a substrate, first and second electrodes on the substrate, the first and second electrodes being arranged on the same layer to be spaced apart from each other, a first insulating layer on the first and second electrodes, and a light emitting element on the first insulating layer. The first insulating layer includes a recessed groove recessed toward the substrate, and the light emitting element is in the recessed groove.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0061894, filed on May 22, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure relate to display devices and methods of manufacturing the same. Background Technology

[0004] With increasing interest in information display and demand for portable information media, research and commercialization have focused on display devices. Summary of the Invention

[0005] According to aspects of embodiments of the present disclosure, a display device having reduced manufacturing costs and improved reliability, as well as a method for manufacturing the display device, are provided.

[0006] According to one or more embodiments of the present disclosure, a display device includes: a substrate; a first electrode and a second electrode on the substrate, the first electrode and the second electrode being arranged on the same layer and spaced apart from each other; a first insulating layer on the first electrode and the second electrode; and a light-emitting element on the first insulating layer, wherein the first insulating layer includes a groove recessed toward the substrate, and wherein the light-emitting element is located in the groove.

[0007] The light-emitting element may include a first end portion and a second end portion facing away from each other. The side surface of the groove in the first insulating layer may contact at least a portion of the first end portion and at least a portion of the second end portion.

[0008] The display device may further include: a third electrode electrically connecting the first electrode to a first end portion of the light-emitting element; and a fourth electrode electrically connecting the second electrode to a second end portion of the light-emitting element.

[0009] The first insulating layer may include a first opening exposing a portion of the first electrode and a second opening exposing a portion of the second electrode. A third electrode may contact the first electrode through the first opening, and a fourth electrode may contact the second electrode through the second opening.

[0010] The display device may also include a second insulating layer on the third and fourth electrodes.

[0011] The display device may also include a wavelength conversion layer on a second insulating layer. The wavelength conversion layer may include wavelength conversion particles and scattering particles. The wavelength conversion particles may be quantum dots.

[0012] The display device may also include a fixing layer surrounding at least a portion of the outer periphery of the light-emitting element. The fixing layer may be located between the third electrode and the fourth electrode.

[0013] The depth of the groove can be less than the diameter of the light-emitting element.

[0014] The width of the groove in the first direction can be equal to the length of the light-emitting element.

[0015] The display device may further include: a first dam between the substrate and the first electrode; and a second dam between the substrate and the second electrode. A light-emitting element may be located between the first dam and the second dam.

[0016] The first insulating layer may include organic materials.

[0017] The display device may also include a pixel circuit layer between the substrate and the light-emitting element. The pixel circuit layer may include at least one transistor.

[0018] According to one or more embodiments of the present disclosure, a method of manufacturing a display device includes: forming a first electrode and a second electrode on a substrate; forming an insulating material layer comprising an organic material on the first electrode and the second electrode; aligning a light-emitting element on the insulating material layer; and forming a first insulating layer by curing the insulating material layer, wherein, during the formation of the first insulating layer, the insulating material layer is reflowed, and a portion of the light-emitting element is buried in the insulating material layer and fixed to the insulating material layer.

[0019] The depth to which the light-emitting element is buried in the insulating material layer can be less than the diameter of the light-emitting element.

[0020] The light-emitting element may include a first end portion and a second end portion facing away from each other. At least a portion of the first insulating layer may be in contact with a portion of the first end portion and a portion of the second end portion.

[0021] The method may further include forming a first opening and a second opening that penetrate the first insulating layer. The first opening may expose a portion of the first electrode, and the second opening may expose a portion of the second electrode.

[0022] The method may further include: forming a conductive material layer on a first insulating layer; and forming a third electrode and a fourth electrode by patterning a portion of the conductive material layer. The third electrode can electrically connect the first electrode to a first end portion of the light-emitting element, and the fourth electrode can electrically connect the second electrode to a second end portion of the light-emitting element.

[0023] The third electrode and the fourth electrode can be spaced apart from each other. The third electrode can contact the first electrode through the first opening, and the fourth electrode can contact the second electrode through the second opening.

[0024] The method may also include forming a second insulating layer on the third and fourth electrodes, wherein the second insulating layer covers the light-emitting element, the third electrode, and the fourth electrode.

[0025] The method may further include forming a first dam and a second dam on a substrate before forming the first electrode and the second electrode. The first electrode may be formed on the first dam, and the second electrode may be formed on the second dam. When aligning the light-emitting element, the light-emitting element may be aligned between the first dam and the second dam. Attached Figure Description

[0026] Figure 1 and Figure 2 These are perspective and cross-sectional views showing a light-emitting element according to an embodiment of the present disclosure.

[0027] Figure 3 This is a perspective view showing a light-emitting element according to another embodiment of the present disclosure.

[0028] Figure 4 This is a cross-sectional view showing a light-emitting element according to another embodiment of the present disclosure.

[0029] Figure 5 This is a perspective view showing a light-emitting element according to another embodiment of the present disclosure.

[0030] Figure 6 and Figure 7 These are perspective and cross-sectional views showing a light-emitting element according to another embodiment of the present disclosure.

[0031] Figure 8 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0032] Figures 9A to 9C Each of these is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure.

[0033] Figure 10 This is a circuit diagram illustrating a pixel according to another embodiment of the present disclosure.

[0034] Figure 11 It is shown that it includes Figure 8 A plan view of an example of pixels in a display device.

[0035] Figure 12 It is along Figure 11 The image shown is a cross-sectional view of the pixels cut off by line AA′.

[0036] Figure 13 yes Figure 12 An enlarged cross-sectional view of the area “EA” shown.

[0037] Figure 14It is shown that it includes Figure 8 A cross-sectional view of another example of pixels in a display device shown.

[0038] Figure 15 It is shown that it includes Figure 8 A cross-sectional view of another example of pixels in a display device shown.

[0039] Figures 16 to 22 This is a cross-sectional view showing a method of manufacturing a display device according to an embodiment of the present disclosure. Detailed Implementation

[0040] Some exemplary embodiments will now be described more fully herein with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0041] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as "between" two elements, it can be the only element between the two elements, or there may be one or more intermediate elements. Throughout the text, the same reference numerals denote the same elements.

[0042] By referring to the following and appendix Figure 1 The effects and features of this disclosure, as well as the methods for achieving these effects and features, will become clear from the described embodiments. However, this disclosure is not limited to the embodiments disclosed herein, but can be implemented in various forms. Embodiments are provided by way of example so that those skilled in the art can fully understand the features and scope of this disclosure. Therefore, this disclosure may be defined by the scope of the appended claims.

[0043] The term "on" can be used to indicate that an element or layer is on another element or layer, including both cases where the element or layer is directly on another element or layer, and cases where the element or layer is on another element or layer via yet another element or layer. The shapes, dimensions, scales, angles, quantities, etc., shown in the drawings used to describe various embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. In the drawings, parts unrelated to this disclosure may be omitted or simply expressed to clarify the description of this disclosure.

[0044] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the “first” element discussed below may also be referred to as the “second” element. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0045] The corresponding features of the several exemplary embodiments disclosed herein may be joined or combined in part or in whole, and the technical and diverse connections are sufficient to enable those skilled in the art to fully understand that the corresponding exemplary embodiments may be implemented independently or together according to their associations.

[0046] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments of the present disclosure pertain. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0047] In this document, some exemplary embodiments of the present disclosure will be described in further detail with reference to the accompanying drawings.

[0048] Figure 1 and Figure 2 These are perspective and cross-sectional views illustrating a light-emitting element according to an embodiment of the present disclosure. Although Figure 1 and Figure 2 The diagram shows a rod-type light-emitting element (LD) with a cylindrical shape, but the type and / or shape of the light-emitting element (LD) according to this disclosure are not limited thereto.

[0049] Reference Figure 1 and Figure 2 The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In the example, the light-emitting element (LD) may be configured as a stacked structure in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked sequentially.

[0050] In some embodiments, the light-emitting element LD may be configured as a rod-shaped element extending along a direction. The light-emitting element LD may include a first end portion EP1 and a second end portion EP2 facing away from each other along a direction. The first end portion EP1 and the second end portion EP2 may be surfaces exposed to the outside.

[0051] In the example, the first semiconductor layer 11 may be disposed at the first end portion EP1 of the light-emitting element LD, and the second semiconductor layer 13 may be disposed at the second end portion EP2 of the light-emitting element LD. However, the first semiconductor layer 11 may be disposed at the second end portion EP2 of the light-emitting element LD, and the second semiconductor layer 13 may be disposed at the first end portion EP1 of the light-emitting element LD.

[0052] In some embodiments, the light-emitting element (LD) can be a rod-shaped light-emitting diode. The rod shape can include rod-like or bar-like shapes, such as cylindrical or polygonal prisms, that are longer in their length direction than in their width direction (i.e., their aspect ratio is greater than 1), and the shape of their cross-section is not particularly limited. For example, the length L of the light-emitting element LD can be greater than the diameter D (or the width of the cross-section) of the light-emitting element LD.

[0053] In some embodiments, the light-emitting element (LD) can have dimensions as small as the micrometer or nanometer scale, for example, with a diameter D and / or length L ranging from 100 nm to 10 μm. However, the size of the LD is not limited to this. For example, the size of the LD can be modified in various ways depending on the design conditions of various types of devices (e.g., display devices, etc.) in which the light-emitting device using the LD is used as a light source.

[0054] In an embodiment, the first semiconductor layer 11 may include at least one n-type semiconductor material. For example, the first semiconductor layer 11 may include at least one semiconductor material selected from AlGaInN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor material doped with a first conductive dopant such as Si, Ge, or Sn. However, the materials constituting the first semiconductor layer 11 are not limited to these. Furthermore, various materials may be used to constitute the first semiconductor layer 11.

[0055] The active layer 12 is formed on the first semiconductor layer 11 and can be formed in a single quantum well structure or a multi-quantum well structure. When the active layer 12 includes a material with a multi-quantum well structure, the active layer 12 can have a structure in which multiple quantum layers and multiple well layers are stacked alternately.

[0056] When an electric field with a voltage (e.g., a predetermined voltage) or higher is applied between the two end portions of the light-emitting element (LD), the LD emits light while electron-hole pairs recombine in the active layer 12. By controlling the light emission of the LD using this principle, the LD can be used as a light source for various light-emitting devices, including pixels of a display device.

[0057] In an embodiment, the active layer 12 can emit light with wavelengths from 400 nm to 900 nm. In an example, when the active layer 12 emits light in the blue or green wavelength band, the active layer 12 may include a nitrogen-containing inorganic material, such as AlGaN or AlGaInN. Specifically, when the active layer 12 has a structure in which quantum layers and well layers are alternately stacked in a multi-quantum-well structure, the quantum layers may include inorganic materials such as AlGaN or AlGaInN, and the well layers may include inorganic materials such as GaN or AlInN. In an exemplary embodiment, the active layer 12 may include AlGaInN as a quantum layer and AlInN as a well layer.

[0058] However, this disclosure is not limited thereto, and the active layer 12 may have a structure in which semiconductor materials with large bandgap energy and semiconductor materials with small bandgap energy are stacked alternately. Furthermore, the active layer 12 may include different semiconductor materials from group III to group V, depending on the wavelength band of the light emitted from it. The light emitted from the active layer 12 is not limited to light in the blue or green wavelength band, and may be light in the red wavelength band depending on the materials included.

[0059] Simultaneously, light emitted from the active layer 12 can be emitted along the length of the light-emitting element LD to the first end portion EP1 and the second end portion EP2 of the light-emitting element LD. Additionally, light emitted from the active layer 12 can be emitted to the side surface (or outer periphery) of the active layer 12. The directionality of light emitted from the active layer 12 is not limited to one direction.

[0060] The second semiconductor layer 13 is disposed on the active layer 12 and may include a semiconductor material of a different type than the first semiconductor layer 11. In an example, the second semiconductor layer 13 may include at least one p-type semiconductor material. For example, the second semiconductor layer 13 may include at least one semiconductor material selected from AlGaInN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor material doped with a second conductive dopant such as Mg, Zn, Ca, Se, or Ba. However, the materials constituting the second semiconductor layer 13 are not limited to these. Furthermore, various materials may constitute the second semiconductor layer 13.

[0061] Furthermore, although the accompanying drawings show a configuration in which the first semiconductor layer 11 and the second semiconductor layer 13 are each configured as a single layer, this disclosure is not limited thereto. For example, depending on the material of the active layer 12, the first semiconductor layer 11 and the second semiconductor layer 13 may comprise a greater number of layers. In the example, the first semiconductor layer 11 and the second semiconductor layer 13 may also comprise a cladding layer or a tensile strain barrier reduction (TSBR) layer.

[0062] In some embodiments, the first length L1 of the first semiconductor layer 11 may be longer than the second length L2 of the second semiconductor layer 13.

[0063] In some embodiments, the light-emitting element (LD) may further include an insulating film INF disposed on its surface. The insulating film INF may be formed on the surface of the light-emitting element LD to surround the outer periphery of the active layer 12. Furthermore, the insulating film INF may also surround the first semiconductor layer 11 and the second semiconductor layer 13.

[0064] In some embodiments, the insulating film INF may expose the first end portion EP1 and the second end portion EP2 of the light-emitting element LD. For example, the insulating film INF may not cover the ends of the first semiconductor layer 11 and the second semiconductor layer 13 located at the two ends of the light-emitting element LD in the length direction, such as the two planes of a cylinder (i.e., the upper surface and the lower surface), but may expose the ends of the first semiconductor layer 11 and the second semiconductor layer 13.

[0065] In some embodiments, the insulating film INF may comprise a transparent insulating material. For example, the insulating film INF may comprise at least one insulating material selected from SiO2, Si3N4, Al2O3, and TiO2. However, the materials constituting the insulating film INF are not particularly limited, and the insulating film INF can be made from various insulating materials currently known in the art.

[0066] The insulating film INF can prevent or substantially prevent electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. Furthermore, when the insulating film INF is formed, surface defects of the light-emitting element LD are minimized or reduced, thereby improving the lifetime and efficiency of the light-emitting element LD. Moreover, when multiple light-emitting elements LD are densely arranged, the insulating film INF can prevent or substantially prevent unwanted short circuits that may occur between the light-emitting elements LD.

[0067] In embodiments, in addition to the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and / or the insulating film INF, the light-emitting element LD may also include additional components disposed on the top and / or bottom of each layer. For example, the light-emitting element LD may also include at least one phosphor layer, at least one active layer, at least one semiconductor material layer, and / or at least one electrode layer disposed at the ends of the first semiconductor layer 11, the active layer 12, and / or the second semiconductor layer 13.

[0068] Figure 3 This is a perspective view showing a light-emitting element according to another embodiment of the present disclosure. For ease of description, as... Figure 3 As shown, a portion of the insulating film INF is omitted.

[0069] Combination Figure 1 and Figure 2 Further reference Figure 3 The light-emitting element LD may also include an electrode layer 14 disposed on the second semiconductor layer 13.

[0070] In some embodiments, electrode layer 14 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13, but this disclosure is not limited thereto. In some embodiments, electrode layer 14 may be a Schottky contact electrode. Electrode layer 14 may include a metal or a metal oxide. In examples, electrode layer 14 may include any one of Cr, Ti, Al, Au, Ni, their oxides or alloys, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), etc.

[0071] In some embodiments, the electrode layer 14 may be substantially transparent or semi-transparent. Therefore, light generated in the active layer 12 of the light-emitting element LD can be emitted to the outside of the light-emitting element LD while being transmitted through the electrode layer 14.

[0072] Figure 4 This is a cross-sectional view showing a light-emitting element according to another embodiment of the present disclosure.

[0073] Combination Figure 3 Further reference Figure 4 The insulating film INF' may have a curved shape in at least a portion of the corner region adjacent to the electrode layer 14. In some embodiments, the curved shape may be formed by an etching process when manufacturing the light-emitting element LD.

[0074] At the same time, even when the electrode layer 14 is not included in Figure 1 and Figure 2 When the light-emitting element LD shown is used, the insulating film INF' can have a curved shape in at least a portion of the corner region.

[0075] Figure 5 This is a perspective view showing a light-emitting element according to another embodiment of the present disclosure. For ease of description, as... Figure 5 As shown, a portion of the insulating film INF is omitted.

[0076] Combination Figure 1 and Figure 2 Further reference Figure 5The light-emitting element LD may further include a third semiconductor layer 15 disposed between the first semiconductor layer 11 and the active layer 12, and a fourth semiconductor layer 16 and a fifth semiconductor layer 17 disposed between the active layer 12 and the second semiconductor layer 13. In addition, the light-emitting element LD may further include a first electrode layer 14a formed on the upper surface of the second semiconductor layer 13 and a second electrode layer 14b formed on the lower surface of the first semiconductor layer 11.

[0077] Figure 5 The light-emitting element LD shown in the figure Figure 1 The difference in the illustrated embodiment is that multiple semiconductor layers 15, 16, and 17, as well as electrode layers 14a and 14b, are also provided, and the active layer 12 includes another element. Furthermore, the arrangement and structure of the insulating film INF are similar to... Figure 1 The setup and structure of the insulating film INF shown are basically the same.

[0078] As mentioned above, in Figure 1 In the light-emitting element LD shown, the active layer 12 may include nitrogen (N) to emit blue or green light. Figure 5 In the light-emitting element LD shown, each of the active layer 12 and semiconductor layers 11, 13, 15, 16, and 17 can be a semiconductor including phosphorus (P). That is, according to Figure 5 The light-emitting element (LD) of the embodiment shown can emit red light having a center wavelength band in the range of 620 nm to 750 nm. However, the center wavelength band of red light is not limited to the above range, and it should be understood that the center wavelength band of red light includes all wavelengths that can be considered red in this art.

[0079] According to Figure 5 In the light-emitting element (LD) of the embodiment shown, the first semiconductor layer 11 may include an n-type semiconductor material. For example, the first semiconductor layer 11 may include a semiconductor material selected from AlGaInP, GaP, AlGaP, InGaP, AlP, and InP, and may include an n-type semiconductor material doped with a first conductive dopant such as Si, Ge, or Sn. In an exemplary embodiment, the first semiconductor layer 11 may be n-AlGaInP doped with n-type Si.

[0080] The second semiconductor layer 13 may include a p-type semiconductor material. For example, the second semiconductor layer 13 may include a semiconductor material selected from AlGaInP, GaP, AlGaP, InGaP, AlP, and InP, and may include a p-type semiconductor material doped with a second conductive dopant such as Mg, Zn, Ca, Se, or Ba. In an exemplary embodiment, the second semiconductor layer 13 may be p-GaP doped with p-type Mg.

[0081] The active layer 12 can be disposed between the first semiconductor layer 11 and the second semiconductor layer 13. Figure 1 The active layer 12 shown is the same. Figure 5 The active layer 12 shown may include a material having a single quantum well structure or a multi-quantum well structure, thereby emitting light in a specific wavelength band. In the example, the active layer 12 may include a material such as AlGaP or AlGaInP. Specifically, when the active layer 12 has a structure in which quantum layers and well layers are alternately stacked in a multi-quantum well structure, the quantum layers may include a material such as AlGaP or AlGaInP, and the well layers may include a material such as GaP or AlInP. In an exemplary embodiment, the active layer 12 may include AlGaInP as a quantum layer and AlInP as a well layer, thereby emitting red light with a center wavelength band of 620 nm to 750 nm.

[0082] In the implementation, Figure 5 The light-emitting element LD shown may include a cladding layer disposed adjacent to the active layer 12. For example, the third semiconductor layer 15 and the fourth semiconductor layer 16 disposed between the first semiconductor layer 11 and the second semiconductor layer 13 at the top and bottom of the active layer 12 may be cladding layers.

[0083] The third semiconductor layer 15 may be disposed between the first semiconductor layer 11 and the active layer 12. Like the first semiconductor layer 11, the third semiconductor layer 15 may include an n-type semiconductor material. In an exemplary embodiment, the third semiconductor layer 15 may be n-AlInP, but this disclosure is not limited thereto.

[0084] A fourth semiconductor layer 16 may be disposed between the active layer 12 and the second semiconductor layer 13. Like the second semiconductor layer 13, the fourth semiconductor layer 16 may include a p-type semiconductor material. In an exemplary embodiment, the fourth semiconductor layer 16 may be p-AlInP.

[0085] A fifth semiconductor layer 17 may be disposed between the fourth semiconductor layer 16 and the second semiconductor layer 13. Like the second semiconductor layer 13 and the fourth semiconductor layer 16, the fifth semiconductor layer 17 may include a p-type semiconductor material. In some embodiments, the fifth semiconductor layer 17 may function to reduce the lattice constant between the fourth semiconductor layer 16 and the second semiconductor layer 13. For example, in one embodiment, the fifth semiconductor layer 17 may be a tensile strain barrier reduction (TSBR) layer. In exemplary embodiments, the fifth semiconductor layer 17 may include p-GaInP, p-AlInP, p-AlGaInP, etc., but this disclosure is not limited thereto.

[0086] The first electrode layer 14a and the second electrode layer 14b may be disposed on the second semiconductor layer 13 and the first semiconductor layer 11, respectively. The first electrode layer 14a may be disposed on the upper surface of the second semiconductor layer 13, and the second electrode layer 14b may be disposed on the lower surface of the first semiconductor layer 11. In some embodiments, at least one of the first electrode layer 14a and the second electrode layer 14b may be omitted. Each of the first electrode layer 14a and the second electrode layer 14b may include Figure 3 At least one of the aforementioned materials in the electrode layer 14 shown.

[0087] Figure 6 and Figure 7 These are perspective and cross-sectional views showing a light-emitting element according to another embodiment of the present disclosure.

[0088] Reference Figure 6 and Figure 7 According to another embodiment, the light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the first semiconductor layer 11 may be disposed in the central region of the light-emitting element LD, and the active layer 12 may be disposed on the surface of the first semiconductor layer 11 to surround at least one region of the first semiconductor layer 11. Furthermore, the second semiconductor layer 13 may be disposed on the surface of the active layer 12 to surround at least one region of the active layer 12.

[0089] Furthermore, the light-emitting element LD may also include an electrode layer 14 and / or an insulating film INF surrounding at least one region of the second semiconductor layer 13. For example, the light-emitting element LD may also include an electrode layer 14 disposed on the surface of the second semiconductor layer 13 to surround at least one region of the second semiconductor layer 13, and an insulating film INF disposed on the surface of the electrode layer 14 to surround at least one region of the electrode layer 14. That is, the light-emitting element LD according to the above embodiment can be implemented as a core-shell structure including a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, an electrode layer 14, and an insulating film INF disposed sequentially in a direction from the center to the outside. In some embodiments, the electrode layer 14 and / or the insulating film INF may be omitted.

[0090] In an implementation, the light-emitting element (LD) can be configured as a multi-faceted pyramid shape extending in one direction (e.g., the length L direction). In the example, the light-emitting element (LD) can have a hexagonal pyramid shape. However, the shape of the light-emitting element (LD) is not limited to this and can be modified in various ways.

[0091] In an embodiment, the two end portions of the first semiconductor layer 11 along the length L of the light-emitting element LD can have protruding shapes. The shapes of the two end portions of the first semiconductor layer 11 can be different from each other. In an example, one of the two end portions of the first semiconductor layer 11 located on the upper side can have a pyramidal shape, which has a width that narrows towards its top while contacting the vertex. Furthermore, the other of the two end portions of the first semiconductor layer 11 located on the lower side can have a polygonal prism shape with a constant width.

[0092] In some embodiments, the first semiconductor layer 11 may be located at the core, i.e., at the center (or central region) of the light-emitting element LD. Furthermore, the light-emitting element LD may be configured in a shape corresponding to the shape of the first semiconductor layer 11. In an example, when the first semiconductor layer 11 has a hexagonal prism shape, the light-emitting element LD may also have a hexagonal prism shape.

[0093] The application of which is described in the following embodiments. Figure 1 and Figure 2 The example shown is of a light-emitting element (LD). However, those skilled in the art can apply this concept to light-emitting elements of any shape (including...). Figures 3 to 7 The light-emitting element (LD) shown is applied in the implementation method.

[0094] Figure 8 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0095] Reference Figure 1 , Figure 2 and Figure 8 The display device 1000 may include a substrate SUB and a plurality of pixels PXL disposed on the substrate SUB. Furthermore, the substrate SUB may include a display area DA in which the plurality of pixels PXL are arranged to display an image, and a non-display area NDA other than the display area DA.

[0096] The display area DA can be the area in which the pixel PXL is set. The non-display area NDA can be the area in which the drivers SDV, DDV, and EDV for driving the pixel PXL are set, as well as various lines connecting the pixel PXL and the drivers SDV, DDV, and EDV.

[0097] The display area DA can have any of a variety of shapes. For example, the display area DA can be set to any of a variety of shapes, such as a closed polygon with linear edges, a circle with curved edges, an ellipse, etc., and a semicircle, a semi-ellipse, etc., with both linear and curved edges.

[0098] When the display area DA comprises multiple regions, each region can also be configured into the various shapes described above. Furthermore, the areas of the multiple regions can be equal to or different from each other. In embodiments of this disclosure, the case in which the display area DA is configured as a region having a quadrilateral shape including linear sides is described as an example.

[0099] The non-display area NDA can be located at least one side of the display area DA. In some embodiments, the non-display area NDA can surround the display area DA.

[0100] Pixels PXL can be disposed on the substrate SUB in the display area DA. Each of the pixels PXL may include at least one light-emitting element LD connected to the scan lines and data lines to be driven by the corresponding scan signal and the corresponding data signal.

[0101] Each of the pixels PXL can emit light of the colors red, green, and blue, but this disclosure is not limited thereto. For example, each of the pixels PXL can emit light of the colors blue-green, magenta, yellow, and white.

[0102] In an implementation, a pixel PXL may include a first pixel PXL1 (or a first sub-pixel) that emits light of a first color, a second pixel PXL2 (or a second sub-pixel) that emits light of a second color different from the first color, and a third pixel PXL3 (or a third sub-pixel) that emits light of a third color different from the first and second colors. The first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, which are arranged adjacent to each other, can constitute a pixel unit PXU capable of emitting light of various colors.

[0103] In some implementations, the first pixel PXL1 may be a red pixel that emits red light, the second pixel PXL2 may be a green pixel that emits green light, and the third pixel PXL3 may be a blue pixel that emits blue light.

[0104] In one embodiment, each pixel PXL may include a light-emitting element LD that emits light of the same color, and may include different color conversion layers disposed on the light-emitting element LD to emit light of different colors. In another embodiment, each pixel PXL may include a light-emitting element LD that emits light of different colors.

[0105] Multiple pixels PXL can be arranged along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the arrangement of pixels PXL is not particularly limited, and pixels PXL can be arranged in any of a variety of forms.

[0106] Drivers SDV, DDV, and EDV can provide signals to each of pixels PXL via line units (not shown), and therefore, the driving of each of pixels PXL can be controlled. For ease of description, in Figure 8 Line units are omitted.

[0107] In some embodiments, the drivers SDV, DDV, and EDV may include a scan driver SDV that provides scan signals to pixel PXL via scan lines, a data driver DDV that provides data signals to pixel PXL via data lines, a transmit control driver EDV that provides transmit control signals to pixel PXL via transmit control lines, and a timing controller (not shown). The timing controller can control the scan driver SDV, the data driver DDV, and the transmit control driver EDV. In some embodiments, the transmit control driver EDV may be omitted.

[0108] The scan driver SDV can be disposed on one side of the substrate SUB and disposed along a direction (e.g., a second direction DR2). The scan driver SDV can be mounted on the substrate SUB as a separate component, but this disclosure is not limited thereto. For example, the scan driver SDV can be formed directly on the substrate SUB. In embodiments, the scan driver SDV can be located outside the substrate SUB and connected to each of the pixels PXL via connecting members.

[0109] In one implementation, the data driver DDV may be disposed on one side of the substrate SUB and along a direction intersecting the direction in which the scan driver SDV is disposed (e.g., a first direction DR1). The data driver DDV may be mounted on the substrate SUB as a separate component or located outside the substrate SUB and connected to each of the pixels PXL via connecting members.

[0110] In one implementation, the transmit control driver (EDV) can be positioned on one side of the substrate (SUB) and aligned in the same direction as the scan driver (SDV) (e.g., a second direction DR2). Figure 8 As shown, the transmit control driver EDV may be located on the same side as the scan driver SDV, but this disclosure is not limited thereto. For example, the transmit control driver EDV may be located on a different side from the scan driver SDV. The transmit control driver EDV may be mounted on the substrate SUB as a separate component, but this disclosure is not limited thereto. For example, the transmit control driver EDV may be formed directly on the substrate SUB, or located outside the substrate SUB, and connected to each of the pixels PXL via connecting members.

[0111] In implementations, each of the pixels PXL can be configured as an active pixel. However, the type, structure, and / or driving method of the pixels PXL applicable to this disclosure are not particularly limited.

[0112] Figures 9A to 9C Each of these is a circuit diagram illustrating a pixel according to an embodiment of this disclosure. Specifically, Figures 9A to 9C Each example shows a pixel that constitutes an active-matrix light-emitting display panel.

[0113] Reference Figure 1 , Figure 2 and Figure 9A The pixel PXL may include at least one light-emitting element LD and a driving circuit DC connected to the light-emitting element LD to drive the light-emitting element LD.

[0114] The first electrode (e.g., anode) of the light-emitting element LD can be connected to a first driving power supply VDD via a driving circuit DC, and the second electrode (e.g., cathode) of the light-emitting element LD can be connected to a second driving power supply VSS. The light-emitting element LD can emit light with a brightness corresponding to the amount of driving current controlled by the driving circuit DC.

[0115] Despite Figure 9A Only one light-emitting element (LD) is shown in the diagram, but this is merely illustrative. In some embodiments, a pixel PXL may include multiple light-emitting elements (LDs). The multiple light-emitting elements (LDs) included in the pixel PXL may be connected in parallel and / or in series with each other.

[0116] The first driving power supply VDD and the second driving power supply VSS can have different potentials. In the example, the first driving power supply VDD can have a potential higher than the threshold voltage of the light-emitting element LD or more than the potential of the second driving power supply VSS. That is, the voltage applied through the first driving power supply VDD can be higher than the voltage applied through the second driving power supply VSS.

[0117] According to embodiments of this disclosure, the driving circuit DC may include a first transistor M1, a second transistor M2, and a storage capacitor Cst.

[0118] The first electrode of the first transistor M1 (driving transistor) can be connected to the first driving power supply VDD, and the second electrode of the first transistor M1 can be electrically connected to the first electrode (e.g., the anode) of the light-emitting element LD. The gate electrode of the first transistor M1 can be connected to the first node N1. The first transistor M1 can control the amount of driving current supplied to the light-emitting element LD corresponding to the voltage of the first node N1.

[0119] The first electrode of the second transistor M2 (switching transistor) can be connected to the data line DL, and the second electrode of the second transistor M2 can be connected to the first node N1. The first and second electrodes of the second transistor M2 are different electrodes. For example, when the first electrode is the source electrode, the second electrode can be the drain electrode. The gate electrode of the second transistor M2 can be connected to the scan line SL.

[0120] When a scan signal with a voltage (e.g., gate on-state voltage) that enables the first transistor M1 to conduct is provided from the scan line SL, the second transistor M2 can be turned on to electrically connect the data line DL to the first node N1. The data signal for the corresponding frame can then be provided to the data line DL. Therefore, the data signal can be transmitted to the first node N1. The data signal transmitted to the first node N1 can be stored in the storage capacitor Cst.

[0121] One electrode of the storage capacitor Cst can be connected to the first drive power supply VDD, and the other electrode of the storage capacitor Cst can be connected to the first node N1. The storage capacitor Cst can be charged with a voltage corresponding to the data signal provided to the first node N1, and the charging voltage is maintained until the data signal of the next frame is provided.

[0122] For ease of description, it has been... Figure 9A The diagram shows a driving circuit DC with a relatively simple structure, which includes a second transistor M2 for transmitting data signals to the interior of each pixel PXL, a storage capacitor Cst for storing the data signals, and a first transistor M1 for providing a driving current corresponding to the data signals to the light-emitting element LD.

[0123] However, this disclosure is not limited thereto, and the structure of the driving circuit DC can be modified and implemented in various ways. In the example, the driving circuit DC may also additionally include other circuit elements, such as a compensation transistor for compensating the threshold voltage of the first transistor M1, an initialization transistor for initializing the first node N1, and / or an emission control transistor for controlling the emission time of the light-emitting element LD.

[0124] Despite Figure 9A The present invention has shown a case in which both the first transistor M1 and the second transistor M2 in the drive circuit DC are p-type transistors, but this disclosure is not limited thereto. That is, at least one of the first transistor M1 and the second transistor M2 in the drive circuit DC can be an n-type transistor.

[0125] For example, such as Figure 9BAs shown, the first transistor M1 and the second transistor M2 of the drive circuit DC can be implemented using n-type transistors. Except for the fact that the connection positions of some components (e.g., the storage capacitor Cst) change due to the change in transistor type, Figure 9B The configuration or operation of the DC drive circuit shown can be related to Figure 9A The configuration or operation of the DC drive circuit shown is similar.

[0126] In another example, refer to Figure 9C The pixel PXL may also include a third transistor M3 (sensing transistor).

[0127] The gate electrode of the third transistor M3 can be connected to the sensing signal line SSL. One electrode of the third transistor M3 can be connected to the sensing line SENL, and the other electrode of the third transistor M3 can be connected to the first electrode (e.g., the anode) of the light-emitting element LD. The third transistor M3 can transmit the voltage value of the first electrode of the light-emitting element LD to the sensing line SENL according to the sensing signal provided to the sensing signal line SSL during the sensing cycle. The voltage value transmitted through the sensing line SENL can be provided to external circuitry (e.g., a timing controller), and the external circuitry can extract feature information of pixel PXL (e.g., the threshold voltage of the first transistor M1, etc.) based on the provided voltage value. In an embodiment, the extracted feature information can be used to convert image data to compensate for feature deviations of pixel PXL.

[0128] Figure 10 This is a circuit diagram illustrating a pixel according to another embodiment of the present disclosure.

[0129] Reference Figure 10 According to another embodiment of the present disclosure, the pixel PXL may include a light-emitting element LD, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7, and a storage capacitor Cst.

[0130] The first electrode (e.g., anode) of the light-emitting element LD can be connected to the first transistor T1 via a sixth transistor T6, and the second electrode (e.g., cathode) of the light-emitting element LD can be connected to a second driving power supply VSS. The light-emitting element LD can emit light with a brightness (e.g., a predetermined brightness) corresponding to the amount of driving current supplied from the first transistor T1.

[0131] One electrode of the first transistor T1 (driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and the other electrode of the first transistor T1 can be connected to the first electrode of the light-emitting element LD via the sixth transistor T6. The first transistor T1 can control the amount of current flowing from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD, and the amount of current corresponds to the voltage of the first node N1, which is the gate electrode of the first transistor T1.

[0132] A second transistor T2 (switching transistor) can be connected between the data line DL and one electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the scan line SL. When a scan signal with a gate on-state voltage is supplied to the scan line SL, the second transistor T2 can be turned on to electrically connect the data line DL to one electrode of the first transistor T1.

[0133] A third transistor T3 can be connected between the other electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the scan line SL. When a scan signal with a gate on-state voltage is provided to the scan line SL, the third transistor T3 can be turned on to electrically connect the other electrode of the first transistor T1 to the first node N1.

[0134] A fourth transistor T4 can be connected between the first node N1 and the initialization power supply Vint. The gate electrode of the fourth transistor T4 can be connected to scan line SL-1. When a scan signal with a gate on-state voltage is provided to scan line SL-1, the fourth transistor T4 can be turned on to provide the voltage of the initialization power supply Vint to the first node N1. The initialization power supply Vint can be set to a voltage lower than the voltage of the data signal. In an embodiment, the scan signal provided to scan line SL-1 can have the same waveform as the scan signal provided to the scan line of the previous pixel.

[0135] The fifth transistor T5 can be connected between the first drive power supply VDD and one electrode of the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the emitter control line EL. The fifth transistor T5 can be turned on when an emitter control signal with a gate on-state voltage is provided to the emitter control line EL, and under other conditions, the fifth transistor T5 can be turned off.

[0136] The sixth transistor T6 can be connected between the other electrode of the first transistor T1 and the first electrode of the light-emitting element LD. The gate electrode of the sixth transistor T6 can be connected to the emission control line EL. The sixth transistor T6 can be turned on when an emission control signal with a gate on-state voltage is provided to the emission control line EL, and under other conditions, the sixth transistor T6 can be turned off.

[0137] A seventh transistor T7 can be connected between the initialization power supply Vint and the first electrode (e.g., the anode) of the light-emitting element LD. The gate electrode of the seventh transistor T7 can be connected to scan line SL+1. When a scan signal with a gate on-state voltage is supplied to scan line SL+1, the seventh transistor T7 can be turned on to supply the voltage of the initialization power supply Vint to the first electrode of the light-emitting element LD. The scan signal supplied to scan line SL+1 can have the same waveform as the scan signal supplied to scan line SL, but this disclosure is not limited thereto.

[0138] exist Figure 10 The diagram illustrates a case where the gate electrode of the seventh transistor T7 is connected to scan line SL+1. However, embodiments of this disclosure are not limited to this. For example, in another embodiment of this disclosure, the gate electrode of the seventh transistor T7 may be connected to scan line SL or scan line SL-1. When a scan signal with a gate on-state voltage is provided to scan line SL or scan line SL-1, the voltage of the initialization power supply Vint may be provided to the first electrode of the light-emitting element LD via the seventh transistor T7.

[0139] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The voltage corresponding to the data signal and the threshold voltage of the first transistor T1 can be stored in the storage capacitor Cst.

[0140] At the same time, despite Figure 10 The present disclosure has shown cases where the transistors included in the DC drive circuit (e.g., first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7) are all p-type transistors, but this disclosure is not limited thereto. For example, at least one of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7 may be an n-type transistor.

[0141] Figure 11 It is shown that it includes Figure 8 A plan view of an example of pixels in a display device shown; Figure 12 It is along Figure 11 The cross-sectional view of the pixels intercepted by line AA′ shown; and Figure 13 yes Figure 12 An enlarged cross-sectional view of the area “EA” shown.

[0142] For ease of description, although each electrode is simplified and shown as a single electrode layer, this disclosure is not limited thereto, and each electrode may be configured with multiple electrode layers. In embodiments of this disclosure, the term "formed and / or disposed in the same layer" may mean formed together (e.g., simultaneously) in the same process and formed of the same material.

[0143] Furthermore, for ease of description, although in Figure 11 The diagram illustrates a case where the light-emitting elements (LDs) are aligned in the first direction DR1, but the alignment direction of the LDs is not limited to this. For example, some of the LDs can be aligned in a direction inclined to the first direction DR1.

[0144] Reference Figure 11 and Figure 12 According to embodiments of the present disclosure, the pixel PXL may include a pixel circuit layer PCL disposed on a substrate SUB and a display element layer DPL disposed on the pixel circuit layer PCL.

[0145] The pixel circuit layer (PCL) may include multiple layers. In one embodiment, for example, the pixel circuit layer (PCL) may include a buffer layer (BFL), a gate insulating layer (GI), an interlayer insulating layer (IL), and a via layer (VIAL) sequentially disposed on a substrate (SUB). These layers may be insulating layers comprising organic or inorganic insulating materials.

[0146] In addition, the pixel circuit layer PCL may include the driving circuitry that constitutes the pixel PXL. Figure 9A The diagram shows multiple circuit elements (DC). For example, the pixel circuit layer PCL may include a transistor T. In an embodiment, transistor T may be... Figure 9A The first transistor M1 shown is shown, but this disclosure is not limited thereto.

[0147] The buffer layer (BFL) prevents or substantially prevents impurities from diffusing into the circuit elements included in the pixel circuit layer (PCL). The buffer layer (BFL) can be a single layer or multiple layers. When the buffer layer (BFL) is multi-layered, the layers constituting the multi-layers can be formed from the same material or from different materials. Depending on the material and processing conditions of the substrate (SUB), the buffer layer (BFL) may be omitted.

[0148] Transistor T can be disposed on buffer layer BFL. Transistor T may include active layer ACT, gate electrode GE, first transistor electrode TET1, and second transistor electrode TET2.

[0149] The active layer ACT can be disposed between the buffer layer BFL and the gate insulating layer GI. When the pixel circuit layer PCL does not include the buffer layer BFL, the active layer ACT can be disposed between the substrate SUB and the gate insulating layer GI. The active layer ACT may include a first region in contact with the first transistor electrode TET1, a second region connected to the second transistor electrode TET2, and a channel region located between the first region and the second region. One of the first region and the second region may be a source region, and the other of the first region and the second region may be a drain region.

[0150] The active layer ACT can be a semiconductor pattern made of polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. In an embodiment, the channel region of the active layer ACT is an undoped semiconductor pattern and can be an intrinsic semiconductor. In an embodiment, each of the first and second regions of the active layer ACT can be a semiconductor pattern doped with a predetermined impurity.

[0151] The gate electrode GE can be disposed between the gate insulating layer GI and the interlayer insulating layer IL. The gate electrode GE can overlap with at least a portion of the active layer ACT. The gate electrode GE can be insulated from the active layer ACT through the gate insulating layer GI.

[0152] The first transistor electrode TET1 and the second transistor electrode TET2 can be disposed on the interlayer insulating layer IL. The first transistor electrode TET1 and the second transistor electrode TET2 can be electrically connected to the active layer ACT. For example, the first transistor electrode TET1 and the second transistor electrode TET2 can contact the first region and the second region of the active layer ACT, respectively, through contact holes penetrating the gate insulating layer GI and the interlayer insulating layer IL. In some embodiments, at least one of the first region and the second region of the active layer ACT can be used as one of the first transistor electrode TET1 and the second transistor electrode TET2. In the example, the first region of the active layer ACT can be used as the first transistor electrode TET1, and the second region of the active layer ACT can be used as the second transistor electrode TET2.

[0153] Although not shown in the accompanying drawings, one of the first transistor electrode TET1 and the second transistor electrode TET2 can be electrically connected to the first electrode RFE1, which will be described later, via a contact hole or a separate connecting member to provide drive current.

[0154] Furthermore, although the above embodiments show a case where, when viewed in cross-section, the pixel circuit layer PCL included in pixel PXL is disposed on the bottom of the display element layer DPL to overlap with the display element layer DPL, this disclosure is not limited thereto. In some embodiments, the pixel circuit layer PCL may be disposed on the bottom of the display element layer DPL and in an area that does not overlap with the display element layer DPL. In another embodiment, the pixel circuit layer PCL may be disposed on the same layer as the display element layer DPL.

[0155] In an embodiment, the display element layer DPL of pixel PXL may include a first dam BNK1, a second dam BNK2, a first electrode RFE1, a second electrode RFE2, a first insulating layer INS1, a light-emitting element LD, a third electrode CTE1, a fourth electrode CTE2, and a second insulating layer INS2.

[0156] The display element layer (DPL) can be disposed on the pixel circuit layer (PCL). In the example, the display element layer (DPL) can be disposed on the via layer (VIAL) corresponding to the topmost layer of the pixel circuit layer (PCL). In some embodiments, an organic or inorganic insulating layer can also be disposed between the display element layer (DPL) and the via layer (VIAL).

[0157] The first dam portion BNK1 and the second dam portion BNK2 can be disposed on the via layer VIAL (or substrate SUB). A space can be provided between the first dam portion BNK1 and the second dam portion BNK2 for disposing of the light-emitting element LD. In an embodiment, the first dam portion BNK1 and the second dam portion BNK2 can be spaced apart from each other along a first direction DR1 by a distance equal to or greater than the length of the light-emitting element LD. In an embodiment, the first dam portion BNK1 and the second dam portion BNK2 can be disposed on the same layer and have the same height (or thickness). However, this disclosure is not limited thereto. Furthermore, the first dam portion BNK1 and the second dam portion BNK2 can extend along a second direction DR2 intersecting the first direction DR1.

[0158] The first dam portion BNK1 and the second dam portion BNK2 can be insulating materials comprising organic or inorganic materials, but the materials of the first dam portion BNK1 and the second dam portion BNK2 are not limited thereto. In an embodiment, each of the first dam portion BNK1 and the second dam portion BNK2 can be formed as a single layer. However, this disclosure is not limited thereto, and each of the first dam portion BNK1 and the second dam portion BNK2 can be formed as a multilayer. In an embodiment, each of the first dam portion BNK1 and the second dam portion BNK2 can have a structure in which at least one organic insulating layer and at least one inorganic insulating layer are stacked.

[0159] In some embodiments, the cross-section of each of the first embankment BNK1 and the second embankment BNK2 may have a trapezoidal shape, the side surfaces of which are inclined at an angle (e.g., a predetermined angle). However, the shape of each of the cross-sections of the first embankment BNK1 and the second embankment BNK2 is not limited to this, and each of the cross-sections of the first embankment BNK1 and the second embankment BNK2 may have any of a variety of shapes such as a semi-elliptical shape, a circular shape, and a quadrilateral shape.

[0160] In some implementations, the first dike section BNK1 and the second dike section BNK2 may be omitted.

[0161] The first electrode RFE1 and the second electrode RFE2 can be respectively disposed on the corresponding first embankment BNK1 and second embankment BNK2. For example, the first electrode RFE1 can be disposed on the first embankment BNK1, and the second electrode RFE2 can be disposed on the second embankment BNK2. In some embodiments, when the pixel PXL does not include the first embankment BNK1 and the second embankment BNK2, the first electrode RFE1 and the second electrode RFE2 can be directly disposed on the via layer VIAL.

[0162] The first electrode RFE1 and the second electrode RFE2 can be spaced apart from each other. The first electrode RFE1 and the second electrode RFE2 can be spaced apart from each other by a distance (e.g., a predetermined distance) along a first direction DR1. In an embodiment, the distance between the first electrode RFE1 and the second electrode RFE2 can be less than the length of the light-emitting element LD. When the light-emitting element LD is disposed at the center portion between the first electrode RFE1 and the second electrode RFE2, at least a portion of the first electrode RFE1 and at least a portion of the second electrode RFE2 can overlap with the light-emitting element LD in a third direction DR3. The first electrode RFE1 and the second electrode RFE2 can extend in a plane along a second direction DR2.

[0163] In the implementation, the distance between the first electrode RFE1 and the second electrode RFE2 can be greater than the length of the light-emitting element LD, and the light-emitting element LD can be non-overlapping with the first electrode RFE1 and the second electrode RFE2 on the third direction DR3.

[0164] In some embodiments, the first electrode RFE1 or the second electrode RFE2 may be electrically connected to circuit elements included in the pixel circuitry layer PCL disposed on its bottom. For example, although not shown in the figures, the first electrode RFE1 may be electrically connected to the transistor T of the pixel circuitry layer PCL via a separate contact hole or connecting member, and receive drive current supplied from the transistor T.

[0165] In an embodiment, the first electrode RFE1 and the second electrode RFE2 may have uniform or substantially uniform thicknesses along the surfaces of the first embankment BNK1 and the second embankment BNK2. The first electrode RFE1 and the second electrode RFE2 may correspond to the shapes of the first embankment BNK1 and the second embankment BNK2, respectively. For example, the first electrode RFE1 may have a shape corresponding to the gradient of the first embankment BNK1, and the second electrode RFE2 may have a shape corresponding to the gradient of the second embankment BNK2. In an embodiment, the first electrode RFE1 and the second electrode RFE2 may be formed together (e.g., simultaneously).

[0166] The first electrode RFE1 and the second electrode RFE2 can be made of conductive materials. In one example, each of the first electrode RFE1 and the second electrode RFE2 may include a metal or an alloy thereof, such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti. In another example, each of the first electrode RFE1 and the second electrode RFE2 may include a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0167] However, the materials of the first electrode RFE1 and the second electrode RFE2 are not limited to those described above. For example, the first electrode RFE1 and the second electrode RFE2 may include conductive materials with constant reflectivity. When the first electrode RFE1 and the second electrode RFE2 are made of conductive materials with constant reflectivity, light emitted from the first end portion EP1 and the second end portion EP2 of each light-emitting element LD can be reflected by the first electrode RFE1 and the second electrode RFE2 to further propagate on the third direction DR3. Therefore, the light emission efficiency of the display device can be improved.

[0168] One of the first electrode RFE1 and the second electrode RFE2 can be an anode, and the other of the first electrode RFE1 and the second electrode RFE2 can be a cathode. For example, the first electrode RFE1 can be an anode, and the second electrode RFE2 can be a cathode. However, this disclosure is not limited thereto, and in embodiments, the first electrode RFE1 can be a cathode, and the second electrode RFE2 can be an anode.

[0169] The first electrode RFE1 and the second electrode RFE2 can provide the light-emitting element LD with a drive signal (or drive current) corresponding to the scan signal and the data signal, and the light-emitting element LD can emit light with a brightness corresponding to the provided drive signal.

[0170] Combining Figure 9AFurther description of the accompanying drawings. Each of the first electrode RFE1 and the second electrode RFE2 can be electrically connected to either the drive circuit DC or the second drive power supply VSS via a separate connecting line or connecting member. For example, the first electrode RFE1 can be electrically connected to the drive circuit DC, and the second electrode RFE2 can be electrically connected to the second drive power supply VSS. Therefore, the first electrode RFE1 and the second electrode RFE2 can provide drive signals to the light-emitting element LD.

[0171] The first insulating layer INS1 can be disposed on the first electrode RFE1 and the second electrode RFE2, and the light-emitting element LD can be disposed on the first insulating layer INS1.

[0172] In one embodiment, the first insulating layer INS1 may be completely disposed on the via layer VIAL to cover the first electrode RFE1 and the second electrode RFE2 described above. In another embodiment, the first insulating layer INS1 may also cover the surface of the via layer VIAL on which the first electrode RFE1 and the second electrode RFE2 are not disposed. In yet another embodiment, the first insulating layer INS1 may be an organic insulating layer made of organic material, but this disclosure is not limited thereto.

[0173] In one embodiment, a groove GRV can be formed in the first insulating layer INS1. The groove GRV can provide space for the light-emitting element LD to be disposed therein.

[0174] Also refer to Figure 13 The groove GRV of the first insulating layer INS1 is described in further detail. A groove GRV that is recessed in the first insulating layer INS1 from the upper surface INS1a of the first insulating layer INS1 toward the via layer VIAL (or substrate SUB) in one direction (e.g., third direction DR3).

[0175] The groove GRV can be formed between the first embankment BNK1 and the second embankment BNK2, and the width GW of the groove GRV in the first direction DR1 can be equal to the length L of the light-emitting element LD (e.g., Figure 1 (as shown in the image).

[0176] In this embodiment, the light-emitting element LD can be disposed in a groove GRV formed in the first insulating layer INS1, and in complete contact with the bottom surface INS1b of the groove GRV. The depth GD of the groove GRV can be less than the diameter D of the light-emitting element LD. Therefore, only a portion of the light-emitting element LD can be disposed in the groove GRV.

[0177] In some embodiments, at least a portion of the first end portion EP1 of the light-emitting element LD and at least a portion of the second end portion EP2 of the light-emitting element LD may be in contact with the first insulating layer INS1. For example, as Figure 13 As shown, a portion of the first end portion EP1 of the light-emitting element LD can contact the side surface INS1c of the groove GRV of the first insulating layer INS1. Another portion of the first end portion EP1 that is not in contact with the first insulating layer INS1 and another portion of the second end portion EP2 that is not in contact with the first insulating layer INS1 can be exposed to the outside and contact the third electrode CTE1 and the fourth electrode CTE2, which will be described later, respectively. In some embodiments, the front surface of the first end portion EP1 and the front surface of the second end portion EP2 can contact the side surface INS1c of the groove GRV and another side surface, respectively.

[0178] Because the light-emitting element (LD) is disposed in the groove GRV of the first insulating layer INS1, failures that occur when the LD is separated from the outside or moved to an unexpected position during subsequent processes performed after the alignment (or setting) of the LD can be minimized or reduced. That is, the process reliability of the display device can be improved. Furthermore, no separate fixing member is formed for fixing the LD, and therefore, manufacturing costs can be reduced.

[0179] The first insulating layer INS1 may include a first opening OP1 and a second opening OP2. The first opening OP1 and the second opening OP2 may expose at least a portion of the first electrode RFE1 and the second electrode RFE2.

[0180] The first opening OP1 and the second opening OP2 can be formed to overlap with the first electrode RFE1 and the second electrode RFE2 corresponding to the first opening OP1 and the second opening OP2, respectively. For example, the first opening OP1 can be formed to overlap with the first electrode RFE1, and the second opening OP2 can be formed to overlap with the second electrode RFE2.

[0181] The first opening OP1 and the second opening OP2 may have a thickness and / or depth corresponding to the thickness of the first insulating layer INS1. That is, the first opening OP1 and the second opening OP2 may completely penetrate the first insulating layer INS1 in their respective regions. Therefore, portions of the first electrode RFE1 and the second electrode RFE2 may be exposed to the outside to contact the third electrode CTE1 and the fourth electrode CTE2, which will be described later.

[0182] The third electrode CTE1 (or the first contact electrode) and the fourth electrode CTE2 (or the second contact electrode) can be disposed on the first insulating layer INS1 and the light-emitting element LD.

[0183] Each of the third electrode CTE1 and the fourth electrode CTE2 may contact one of the first end portion EP1 and the second end portion EP2 of the light-emitting element LD. For example, the third electrode CTE1 may contact the first end portion EP1 of each light-emitting element LD, and the fourth electrode CTE2 may contact the second end portion EP2 of each light-emitting element LD.

[0184] In some embodiments, the third electrode CTE1 may contact the exposed portion of the first end portion EP1 that is not in contact with the first insulating layer INS1, and the fourth electrode CTE2 may contact the exposed portion of the second end portion EP2 that is not in contact with the first insulating layer INS1.

[0185] When viewed on a plane, the third electrode CTE1 can cover at least a portion of the first electrode RFE1. The third electrode CTE1 can be electrically connected to the first electrode RFE1 through the first opening OP1 of the first insulating layer INS1. That is, the third electrode CTE1 can contact the first end portion EP1 of the light-emitting element LD and the first electrode RFE1.

[0186] When viewed in a plane, the fourth electrode CTE2 can cover at least a portion of the second electrode RFE2. The fourth electrode CTE2 can be electrically connected to the second electrode RFE2 through the second opening OP2 of the first insulating layer INS1. That is, the fourth electrode CTE2 can contact the second end portion EP2 of the light-emitting element LD and the second electrode RFE2.

[0187] In this embodiment, each of the third electrode CTE1 and the fourth electrode CTE2 can be made of a transparent conductive material. For example, the transparent conductive material may include any one of ITO, IZO, ITZO, etc. When the third electrode CTE1 and the fourth electrode CTE2 are made of a transparent conductive material, the light loss as the light emitted from the light-emitting element LD travels towards DR3 can be reduced. However, the materials of the third electrode CTE1 and the fourth electrode CTE2 are not limited to the materials described above.

[0188] In some embodiments, the third electrode CTE1 and the fourth electrode CTE2 can be formed together (e.g., simultaneously) in the same process. Therefore, the manufacturing process of the display device can be simplified, and the manufacturing cost of the display device can be reduced. However, this disclosure is not limited thereto.

[0189] The second insulating layer INS2 can be disposed above the light-emitting element LD, the third electrode CTE1, and the fourth electrode CTE2. In an embodiment, the second insulating layer INS2 may include an inorganic insulating layer made of inorganic materials. In an embodiment, the second insulating layer INS2 may be formed as a single layer. However, this disclosure is not limited thereto, and in an embodiment, the second insulating layer INS2 may include a multilayer structure. In an embodiment, when the second insulating layer INS2 includes a multilayer structure, the second insulating layer INS2 may further include an organic insulating layer made of organic materials, and include a multilayer structure in which organic insulating layers and inorganic insulating layers are alternately disposed.

[0190] The second insulating layer INS2 can be used as an encapsulation layer to prevent or substantially prevent the third electrode CTE1, the fourth electrode CTE2 and the light-emitting element LD from being damaged during the manufacturing process of the display device, and to prevent or substantially prevent the penetration of oxygen and / or moisture.

[0191] Although not shown in the accompanying drawings, pixel PXL may also include a partition wall configured to surround each pixel PXL. The partition wall may be a pixel-defining layer defining the light-emitting area of ​​pixel PXL. The partition wall may include at least one light-shielding material and / or at least one reflective material to prevent or substantially prevent light leakage defects in which light leaks between adjacent pixels. Furthermore, the partition wall may prevent or substantially prevent the solution including the light-emitting element LD from leaking into adjacent pixels during the process of aligning the light-emitting element LD. Depending on the process conditions of the display device, the partition wall may be omitted.

[0192] In this document, some other embodiments of the present disclosure will be described. In the following embodiments, components identical to those in the above embodiments are indicated by the same reference numerals, and their descriptions may be omitted or simplified. Furthermore, the parts that differ from those in the above embodiments will be described primarily.

[0193] Figure 14 It is shown that it includes Figure 8 A cross-sectional view of another example of pixels in a display device shown. Figure 14 The implementation methods shown are the same as Figure 12 The difference in the embodiment shown is that the display element layer DPL also includes a wavelength conversion layer WCL and a color filter layer CFL, while the other components are... Figure 12 The components of the embodiments shown are substantially the same or similar.

[0194] Reference Figure 12 and Figure 14 Pixel PXL_1 may also include a wavelength conversion layer (WCL) and a color filter layer (CFL).

[0195] The wavelength conversion layer (WCL) can be disposed on the second insulating layer (INS2). The wavelength conversion layer (WCL) may include a substrate layer (BR) and wavelength conversion particles (QD) and scattering particles (SCT) dispersed in the substrate layer BR. The substrate layer BR is not particularly limited, as long as it is a material with high transmittance and excellent dispersion characteristics relative to the wavelength conversion particles (QD) and scattering particles (SCT). For example, the substrate layer BR may include organic materials such as epoxy resins, acrylic resins, cardo resins, or imide resins.

[0196] Wavelength-converting particles (QDs) can convert the peak wavelength of incident light into another specific peak wavelength. In other words, QDs can convert the color of incident light into another color.

[0197] For example, when the light-emitting element (LD) emits blue light, the wavelength-converting particle (QD) can convert the blue light provided by the LD into light of another color and emit that other color. For example, the wavelength-converting particle (QD) can convert the blue light provided by the LD into red or green light and emit that red or green light.

[0198] Examples of wavelength-converting particles (QDs) include quantum dots, quantum rods, phosphors, etc. Quantum dots can be particle materials that emit light with a specific wavelength when an electron transitions from the conduction band to the valence band.

[0199] Quantum dots can be semiconductor nanocrystal materials. Quantum dots have a specific band gap depending on their composition and size, and can emit light with an inherent band after absorbing light. Examples of semiconductor nanocrystals based on quantum dots can include group IV-based nanocrystals, group II-VI-based compound nanocrystals, group III-V-based compound nanocrystals, group IV-VI-based nanocrystals, or combinations thereof.

[0200] For example, group IV-based nanocrystals may include silicon (Si), germanium (Ge), or binary compounds such as silicon carbide (SiC) and silicon-germanium (SiGe). However, this disclosure is not limited thereto.

[0201] Furthermore, group II-VI based compound nanocrystals may include any of the following: binary compounds such as CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; and compounds such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, Cd Ternary compounds such as ZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; and quaternary compounds such as HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof. However, this disclosure is not limited thereto.

[0202] Furthermore, III-V group-based compound nanocrystals may include any of the following: binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof; and quaternary compounds such as GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. However, this disclosure is not limited thereto.

[0203] Group IV-VI based nanocrystals may include any of the following: binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds such as SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. However, this disclosure is not limited thereto.

[0204] The form of quantum dots is not particularly limited and can be any form commonly used in the art. Examples of quantum dot forms include spherical, pyramidal, multi-armed, or cubic nanoparticles, nanotubes, nanowires, nanofibers, nanosheet particles, etc. The binary, ternary, or quaternary compounds described above can exist in the particles at a uniform concentration or exist in the same particles by being divided into states in which the concentration distributions are partially different.

[0205] In embodiments, quantum dots can have a core-shell structure, comprising a core having the aforementioned nanocrystals and a shell surrounding the core. The interface between the core and shell has a gradient in which the concentration of elements present in the shell decreases with increasing proximity to the center of the shell. The shell of the quantum dot can serve as a protective layer to prevent or reduce chemical degradation of the core while maintaining semiconductor properties and / or as a charge layer to impart electrophoretic properties to the quantum dot. The shell can be a single-layer or multi-layer structure. As an example, metal or non-metal oxides, semiconductor compounds, combinations thereof, etc., can be used as the shell of the quantum dot.

[0206] For example, the aforementioned metal or non-metal oxides may include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, etc.; or ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, etc. However, this disclosure is not limited thereto.

[0207] Furthermore, the aforementioned semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InSb, AlAs, AlP, AlSb, etc. However, this disclosure is not limited thereto.

[0208] In this embodiment, the light emitted by the quantum dots can have a full width at half maximum (FWHM) of approximately 45 nm or less, thereby further improving the color purity and color reproducibility of the colors displayed by the display device. Furthermore, regardless of the incident angle, the light emitted by the quantum dots can be emitted in all directions. Therefore, the side visibility of the display device can be improved.

[0209] The scattering particles (SCTs) can have a refractive index different from that of the wavelength conversion layer (WCL) and form an optical interface with the WCL. The scattering particles (SCTs) are not particularly limited, as long as they are made of a material capable of scattering at least some of the transmitted light. In embodiments, for example, the scattering particles (SCTs) can be particles made of materials such as titanium oxide (TiO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), or silica.

[0210] Regardless of the incident direction of the light, the scattering particles SCT can scatter light in several directions without substantially changing the wavelength of the light transmitted through the wavelength conversion layer WCL. Therefore, the side visibility of the display device can be improved.

[0211] A first capping layer CPL1 may be disposed on the wavelength conversion layer WCL. The first capping layer CPL1 may be an inorganic insulating layer made of inorganic material. In an embodiment, the first capping layer CPL1 may serve as an encapsulation layer that completely covers the wavelength conversion layer WCL to prevent or substantially prevent oxygen and / or moisture from penetrating into the wavelength conversion layer WCL from the outside. Therefore, the wavelength conversion layer WCL may be encapsulated by a second insulating layer INS2 and a first capping layer CPL1.

[0212] A color filter layer (CFL) can be disposed on the first capping layer (CPL1). The color filter layer (CFL) can be an absorptive filter that allows light of a specific color to selectively pass through and can block the advance of light of another color by absorbing light.

[0213] A second capping layer CPL2 can be disposed on the color filter layer CFL. The second capping layer CPL2 can be an inorganic insulating layer made of inorganic material. In an embodiment, the second capping layer CPL2 can serve as an encapsulation layer that completely covers the color filter layer CFL to prevent or substantially prevent oxygen and / or moisture from permeating into the color filter layer CFL from the outside. Therefore, the color filter layer CFL can be encapsulated by a first capping layer CPL1 and a second capping layer CPL2.

[0214] In some embodiments, at least one of the wavelength conversion layer WCL, the first capping layer CPL1, the color filter layer CFL, and the second capping layer CPL2 may be omitted.

[0215] Despite Figure 14The embodiments shown illustrate a structure in which the wavelength conversion layer WCL and the color filter layer CFL (e.g., directly) are formed on the substrate SUB, but this disclosure is not limited thereto. In some embodiments, the wavelength conversion layer WCL and the color filter layer CFL may be formed on a separate substrate different from the substrate SUB on which the light-emitting element LD is disposed. The substrate on which the wavelength conversion layer WCL and the color filter layer CFL are formed may face the substrate SUB on which the light-emitting element LD is disposed.

[0216] Figure 15 It is shown that it includes Figure 8 A cross-sectional view of another example of pixels in a display device shown. Figure 15 The implementation methods shown are the same as Figure 12 The difference in the embodiment shown is that the display element layer DPL also includes a fixing layer ANCL disposed on the light-emitting element LD, while the other components are... Figure 12 The components of the embodiments shown are substantially the same or similar.

[0217] Reference Figure 12 and Figure 15 Pixel PXL_2 may also include a fixed layer ANCL.

[0218] A fixing layer ANCL is disposed on the light-emitting element LD and can stably support and fix the light-emitting element LD. The fixing layer ANCL can be an inorganic insulating layer comprising inorganic materials or an organic insulating layer comprising organic materials. The fixing layer ANCL can cover at least a portion of the outer periphery of the light-emitting element LD and is formed to expose a first end portion EP1 and a second end portion EP2 of the light-emitting element LD. Therefore, the fixing layer ANCL can prevent or substantially prevent the light-emitting element LD from separating from the first insulating layer INS1.

[0219] Figures 16 to 22 This is a cross-sectional view showing (for example, sequentially shown) a method of manufacturing a display device according to an embodiment of the present disclosure. Specifically, Figures 16 to 22 It is shown Figure 11 and Figure 12 The diagram shows the structure.

[0220] Combination Figure 11 and Figure 12 Further reference is made to the implementation methods described herein. Figures 16 to 22 A method for manufacturing a display device according to embodiments of the present disclosure will be described sequentially. Figures 16 to 22 For ease of description, the pixel circuit layer (PCL) is briefly shown in the diagram. However, the pixel circuit layer (PCL) can be combined with... Figure 12 The pixel circuit layer PCL shown is the same.

[0221] First, such as Figure 16As shown, a first embankment BNK1, a second embankment BNK2, a first electrode RFE1, and a second electrode RFE2 can be formed on a substrate SUB (or pixel circuit layer PCL), and an insulating material layer INSL can be formed on the first electrode RFE1 and the second electrode RFE2.

[0222] The first dam section BNK1 and the second dam section BNK2 can be insulating materials comprising organic or inorganic materials, and in embodiments, the cross-section of each of the first dam section BNK1 and the second dam section BNK2 can have a trapezoidal shape, the side surfaces of which are inclined at an angle (e.g., a predetermined angle). In some embodiments, the first dam section BNK1 and the second dam section BNK2 can be omitted.

[0223] A first electrode RFE1 may be formed on a first embankment BNK1, and a second electrode RFE2 may be formed on a second embankment BNK2. In an embodiment, the first electrode RFE1 and the second electrode RFE2 may be formed together (e.g., simultaneously) and made of the same material.

[0224] In one embodiment, each of the first electrode RFE1 and the second electrode RFE2 may be formed of a metal or alloy thereof, such as Al, Mg, Ag, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti. In another embodiment, each of the first electrode RFE1 and the second electrode RFE2 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO).

[0225] An insulating material layer INSL can be formed on the first electrode RFE1 and the second electrode RFE2. In an embodiment, the insulating material layer INSL can be an organic insulating layer made of organic material, but this disclosure is not limited thereto. In an embodiment, the insulating material layer INSL can be completely disposed on the substrate SUB to cover the first electrode RFE1 and the second electrode RFE2, and to prevent or substantially prevent oxygen and moisture from penetrating into the first electrode RFE1 and the second electrode RFE2.

[0226] Next, as Figure 17 As shown, the light-emitting element LD can be aligned on the insulating material layer INSL. The light-emitting element LD can be aligned between the first electrode RFE1 and the second electrode RFE2.

[0227] In this embodiment, before setting the light-emitting element (LD), alignment voltages can be applied to the first electrode RFE1 and the second electrode RFE2. For example, an AC voltage (e.g., a predetermined AC voltage) can be applied to the first electrode RFE1, and a ground voltage can be applied to the second electrode RFE2. Therefore, an electric field can be formed between the first electrode RFE1 and the second electrode RFE2.

[0228] In one embodiment, with an electric field formed between the first electrode RFE1 and the second electrode RFE2, the light-emitting element LD can be injected onto the insulating material layer INSL using an inkjet printing process. Due to the electric field formed between the first electrode RFE1 and the second electrode RFE2, the light-emitting element LD can undergo self-alignment. Therefore, the light-emitting element LD can be aligned in the direction between the first electrode RFE1 and the second electrode RFE2. For example, the light-emitting element LD can be aligned such that its length direction corresponds to a first direction DR1.

[0229] Next, as Figure 18 As shown, the first insulating layer INS1 can be formed by curing the insulating material layer INSL.

[0230] In one embodiment, the curing process can be a process for purifying and stabilizing the insulating material layer (INSL). For example, in another embodiment, the curing process can be a process of heating the INSL at a certain temperature or higher for a certain time or longer.

[0231] The shape of the insulating material layer INSL may be partially altered by the curing process. In an embodiment, for example, the insulating material layer INSL may be reflowed due to the curing process, and when the insulating material layer INSL is reflowed, the shape of at least a portion of the insulating material layer INSL may be altered.

[0232] Due to the reflow of the insulating material layer INSL, the light-emitting element (LD) disposed on the insulating material layer INSL may move towards the substrate SUB (e.g., in the opposite direction to DR3) due to the weight of the light-emitting element LD. That is, a portion of the light-emitting element LD may be buried in the insulating material layer INSL.

[0233] Therefore, a groove GRV can be formed in the first insulating layer INS1 formed by the curing process, and the light-emitting element LD can be disposed in the groove GRV. The depth GD of the groove GRV can be less than the diameter D of the light-emitting element LD, and only a portion of the light-emitting element LD can be buried in the first insulating layer INS1.

[0234] The outer periphery of the light-emitting element LD can contact the bottom surface of the groove GRV, and a portion of the first end portion and a portion of the second end portion of the light-emitting element LD can contact the side surface of the groove GRV. Therefore, the light-emitting element LD can be fixed by the first insulating layer INS1.

[0235] Next, as Figure 19 As shown, a first opening OP1 and a second opening OP2 that penetrate the first insulating layer INS1 can be formed.

[0236] The first opening OP1 can penetrate the first insulating layer INS1 and expose a portion of the first electrode RFE1. The second opening OP2 can penetrate the first insulating layer INS1 and expose a portion of the second electrode RFE2. The first opening OP1 and the second opening OP2 can have a thickness and / or depth corresponding to the thickness of the first insulating layer INS1. In some embodiments, the process of forming the first opening OP1 and the second opening OP2 can be performed before the curing process after aligning the light-emitting element LD.

[0237] Next, as Figure 20 and Figure 21 As shown, a conductive material layer CTEL can be formed on the first insulating layer INS1, and a third electrode CTE1 and a fourth electrode CTE2 can be formed by patterning a portion of the conductive material layer CTEL.

[0238] In this embodiment, the conductive material layer CTEL can be completely formed on the first insulating layer INS1 and the light-emitting element LD. The conductive material layer CTEL can be made of a transparent conductive material to minimize the loss of light emitted from the light-emitting element LD. For example, the conductive material layer CTEL can be formed of ITO, IZO, ITZO, etc., which are transparent conductive materials, but this disclosure is not limited thereto.

[0239] The area where the conductive material layer CTEL is patterned and removed can be the area overlapping with the light-emitting element LD. Although not shown in the figures, the removed area of ​​the conductive material layer CTEL can extend along a second direction intersecting the first direction DR1 and the third direction DR3. Therefore, a third electrode CTE1 and a fourth electrode CTE2 that are physically spaced apart from each other can be formed by patterning the conductive material layer CTEL.

[0240] The third electrode CTE1 can contact the first electrode RFE1 through the first opening OP1. Furthermore, the third electrode CTE1 can contact a portion of the first end portion of the light-emitting element LD. Therefore, the third electrode CTE1 can electrically connect the first end portion of the light-emitting element LD to the first electrode RFE1.

[0241] The fourth electrode CTE2 can contact the second electrode RFE2 through the second opening OP2. Furthermore, the fourth electrode CTE2 can contact a portion of the second end portion of the light-emitting element LD. Therefore, the fourth electrode CTE2 can electrically connect the second end portion of the light-emitting element LD to the second electrode RFE2.

[0242] Next, as Figure 22 As shown, a second insulating layer INS2 can be formed over the light-emitting element LD, the third electrode CTE1, and the fourth electrode CTE2. The second insulating layer INS2 can be formed as an inorganic insulating layer made of inorganic material and covers the light-emitting element LD, the third electrode CTE1, and the fourth electrode CTE2. Therefore, the second insulating layer INS2 can serve as an encapsulation layer that prevents or substantially prevents damage to the third electrode CTE1, the fourth electrode CTE2, and the light-emitting element LD during the manufacturing process of the display device, and prevents or substantially prevents the penetration of oxygen and / or moisture.

[0243] As described above, when a portion of the light-emitting element (LD) is embedded in and fixed to the first insulating layer INS1, no separate fixing member is formed for fixing the light-emitting element (LD) to the first insulating layer INS1, thereby reducing the manufacturing cost of the display device. Furthermore, the light-emitting element (LD) can be positioned at a desired location, thus improving the reliability of the display device.

[0244] According to one aspect of this disclosure, a display device and a method of manufacturing the same can be provided, wherein a light-emitting element is embedded in and fixed to an organic insulating layer disposed on the bottom of the light-emitting element without any separate fixing components, thereby reducing manufacturing costs and improving reliability.

[0245] Exemplary embodiments have been disclosed herein, and although specific terminology has been used, it is intended and construed as having a general and descriptive meaning and not as a limitation. In some instances, it will be apparent to those skilled in the art at the time of filing this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display device, including: Substrate; A first electrode and a second electrode are arranged on the same layer on the substrate and spaced apart from each other. A first insulating layer is provided on the first electrode and the second electrode; as well as The light-emitting element is located on the first insulating layer. The first insulating layer includes a groove recessed towards the substrate. The light-emitting element is located in the groove. Wherein, the depth of the groove is less than the diameter of the light-emitting element, and The upper part of the groove is lower than the upper surface of the light-emitting element and higher than the lower surface of the light-emitting element.

2. The display device according to claim 1, wherein, The light-emitting element includes a first end portion and a second end portion that are back-to-back with each other, and Wherein, the side surface of the groove of the first insulating layer is in contact with at least a portion of the first end portion and at least a portion of the second end portion.

3. The display device according to claim 2, further comprising: The third electrode electrically connects the first electrode to the first end portion of the light-emitting element; as well as The fourth electrode electrically connects the second electrode to the second end portion of the light-emitting element.

4. The display device according to claim 3, wherein, The first insulating layer includes a first opening exposing a portion of the first electrode and a second opening exposing a portion of the second electrode, and The third electrode contacts the first electrode through the first opening, and The fourth electrode is in contact with the second electrode through the second opening.

5. The display device according to claim 3, further comprising a second insulating layer on the third electrode and the fourth electrode.

6. The display device according to claim 5, further comprising a wavelength conversion layer on the second insulating layer, in, The wavelength conversion layer includes wavelength conversion particles and scattering particles, and The wavelength-converting particles are quantum dots.

7. The display device of claim 3, further comprising a fixing layer surrounding at least a portion of the outer periphery of the light-emitting element. in, The fixing layer is located between the third electrode and the fourth electrode.

8. The display device according to claim 1, wherein, The width of the groove in the first direction is equal to the length of the light-emitting element.

9. The display device according to claim 1, further comprising: A first embankment is located between the substrate and the first electrode; as well as The second embankment is located between the substrate and the second electrode. The light-emitting element is located between the first embankment and the second embankment.

10. The display device according to claim 1, wherein, The first insulating layer comprises organic materials.

11. The display device according to claim 1, further comprising a pixel circuit layer between the substrate and the light-emitting element. in, The pixel circuit layer includes at least one transistor.

12. A method for manufacturing a display device, the method comprising: A first electrode and a second electrode are formed on a substrate; An insulating material layer comprising organic material is formed on the first electrode and the second electrode; Align the light-emitting element with the insulating material layer; as well as The first insulating layer is formed by curing the insulating material layer. During the formation of the first insulating layer, the insulating material layer is reflowed and forms a groove, and a portion of the light-emitting element is embedded in the groove and fixed to the insulating material layer. The depth of the groove is less than the diameter of the light-emitting element, and The upper part of the groove is lower than the upper surface of the light-emitting element and higher than the lower surface of the light-emitting element.

13. The method according to claim 12, wherein, The light-emitting element includes a first end portion and a second end portion that are back-to-back with each other, and Wherein, at least a portion of the first insulating layer is in contact with a portion of the first end portion and a portion of the second end portion.

14. The method of claim 13, further comprising forming a first opening and a second opening penetrating the first insulating layer. in, The first opening exposes a portion of the first electrode, and The second opening exposes a portion of the second electrode.

15. The method of claim 14, further comprising: A conductive material layer is formed on the first insulating layer; as well as A third electrode and a fourth electrode are formed by patterning a portion of the conductive material layer, wherein the third electrode electrically connects the first electrode to the first end portion of the light-emitting element, and the fourth electrode electrically connects the second electrode to the second end portion of the light-emitting element.

16. The method according to claim 15, wherein, The third electrode and the fourth electrode are spaced apart from each other, and The third electrode contacts the first electrode through the first opening, and The fourth electrode is in contact with the second electrode through the second opening.

17. The method of claim 16, further comprising forming a second insulating layer on the third electrode and the fourth electrode, wherein, The second insulating layer covers the light-emitting element, the third electrode, and the fourth electrode.

18. The method of claim 12, further comprising forming a first dam and a second dam on the substrate prior to forming the first electrode and the second electrode. in, The first electrode is formed on the first embankment, and The second electrode is formed on the second embankment, and Specifically, when aligning the light-emitting element, the light-emitting element is aligned between the first embankment and the second embankment.

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