Memory devices and methods of memory programming

Abstract

A memory device and a method of memory programming are provided, the method of memory programming including receiving a first write data unit including a first plurality of data bits, programming the first plurality of data bits to a first plurality of memory cells by at least one pulse, determining whether a number of cells successfully programmed by the at least one pulse is less than a threshold, and if the number of cells successfully programmed by the at least one pulse is less than the threshold, compressing a first vector of data bits that were unsuccessfully programmed, receiving a second write data unit, joining the first vector based on the second write data unit, and programming the joined vector to a second plurality of memory cells.

Description

[0001] This application claims priority to U.S. Patent Application No. 16 / 882,031, filed May 22, 2020, with the United States Patent and Trademark Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of this disclosure relate to memory devices, and more specifically, to write operations in memory devices utilizing adaptive slow cell data compression. Background Technology

[0003] Increased data production rates have spurred a shift towards high-performance memory systems. Large analytics applications can utilize cache layers and significant parallelism to meet specific latency requirements, but not without increased hardware costs. Smaller mobile applications leverage low-area components, which limit achievable gains from caches, parallelism, multiple coordinate instructions, and / or hierarchical memory architectures, and can therefore benefit from single-die acceleration improvements. Thus, accelerating write speeds within flash dies, chips, packages, or devices can be advantageous. Summary of the Invention

[0004] An exemplary embodiment of a method for memory programming is provided, the method comprising: receiving a first write data unit comprising a plurality of data bits; programming the plurality of data bits into a plurality of memory units via at least one pulse; determining whether the number of units successfully programmed via the at least one pulse is less than a threshold; and if the number of units successfully programmed via the at least one pulse is less than the threshold, receiving another write data unit, compressing and concatenating a sparse vector of unprogrammed data bits of the first write data unit with at least one of another sparse vector of unprogrammed data bits of the other write data unit and the other write data unit, and programming the concatenated vector into a second plurality of memory units.

[0005] An exemplary embodiment of a memory device is provided, the memory device comprising: a memory cell array; a data circuit configured to receive a first write data cell including a first plurality of data bits; a row decoder connected to the memory cell array and configured to select a first word line connected to the first plurality of memory cells of the memory cell array; a page buffer connected to the data circuit and the memory cell array and configured to program the first plurality of data bits to the first plurality of memory cells by at least one pulse; a counter configured to determine whether the number of cells successfully programmed by the at least one pulse is less than a threshold; a slow cell data compressor connected to the counter and configured to: compress a first sparse vector of unprogrammed data bits if the number of cells successfully programmed by the at least one pulse is less than the threshold; and a control circuit connected to the slow cell data compressor and the page buffer and configured to: concatenate the first sparse vector based on a second write data cell if the number of cells successfully programmed by the at least one pulse is less than the threshold, and write the concatenated vector to a second plurality of memory cells of the memory cell array connected to a second word line different from the first word line.

[0006] An exemplary embodiment of a program storage device is provided, the program storage device comprising the following program steps: receiving a first write data unit comprising a plurality of data bits; selecting a first address line connected to a plurality of memory units; programming the plurality of data bits to the plurality of memory units via at least one pulse; determining whether the number of units successfully programmed via the at least one pulse is less than a threshold; and if the number of units successfully programmed via the at least one pulse is less than the threshold, compressing a sparse vector of unprogrammed data bits; receiving another write data unit; concatenating a vector based on the other write data unit; selecting a second address line connected to another plurality of memory units; and programming the concatenated vector to the other plurality of memory units, wherein the first address line and the second address line are disposed at different levels of a three-dimensional memory. Attached Figure Description

[0007] The aspects of the inventive concept become clearer and better understood when the following description of exemplary embodiments is considered in conjunction with the accompanying drawings, wherein:

[0008] Figure 1 This is a schematic block diagram of a memory device according to exemplary embodiments of the present disclosure;

[0009] Figure 2 This is an example of writing data according to an exemplary embodiment of the present disclosure. Figure 1 A schematic flowchart of a method for constructing a memory device;

[0010] Figure 3This is a schematic flowchart of a method for writing data to a memory device using a controller, according to exemplary embodiments of the present disclosure.

[0011] Figure 4 This is a schematic flowchart of a method for writing data to a memory device using memory dominance, according to exemplary embodiments of the present disclosure.

[0012] Figure 5 This is an example of combining non-adaptive programming operations with... Figure 2 A schematic diagram of the mixed portion compared using the methods;

[0013] Figure 6 This is based on exemplary embodiments of the present disclosure. Figure 2 A graphical representation of write speed acceleration in an exemplary method;

[0014] Figure 7 This is based on exemplary embodiments of the present disclosure. Figure 2 A graphical representation of the write speed acceleration in the comparison method; and

[0015] Figure 8 This is based on exemplary embodiments of the present disclosure. Figure 2 The table shows the speedup of write operations in the comparison method. Detailed Implementation

[0016] I. Introduction

[0017] This section is organized into several sub-sections, including sub-section I, sub-section II, sub-section III, sub-section IV, sub-section V, sub-section VI, and sub-section VII. Sub-section I introduces exemplary embodiments of the inventive concept; sub-section II presents the symbols used; sub-section III describes the continuous write acceleration scheme in more detail; sub-section IV analyzes the optimized parameter settings of the algorithm based on product specification analysis of given general memory cell behavior and pulse write bandwidth; sub-section V presents a gain analysis of continuous write speed using various algorithm parameters and programming statistics; sub-section VI details the implementation details and overhead; and sub-section VII provides a commentary on its potential applications.

[0018] This disclosure provides a method and apparatus for increasing write programming throughput through adaptive data compression of low-bandwidth regions in a memory device. Preferred embodiments may use adaptive slow cell data compression to accelerate memory write operations. Exemplary embodiments may be directed to NAND flash memory devices, but the inventive concept is not limited thereto.

[0019] A write operation in NAND flash memory consists of multiple word line pulses and at least one subsequent read for data verification. The amount of data stored in each pulse is neither known in advance nor equally distributed. Typically, for variable obstinate cells or slow cells, early pulses have a low programming bandwidth, which increases to a maximum and then decreases exponentially with subsequent pulses.

[0020] like Figure 1 As shown, the exemplary NAND flash memory device is generally indicated by reference numeral 100. The NAND flash memory 100 includes: a memory cell array 110, a row decoder 120 connected to the memory cell array, a page buffer circuitry 130 connected to the memory cell array, a data input / output (I / O) circuitry 140 connected to the page buffer circuitry, a voltage generator 150 connected to the memory cell array, control circuitry 160 connected to the row decoder, page buffer circuitry, and voltage generator, and a slow cell data compression unit 170 connected to the control circuitry. In one example, the NAND flash memory 100 may also include a counter (not shown) for counting, and the counter may be connected to the slow cell data compression unit 170. The type of data compression performed by the slow cell data compression unit 170 may include bit-packing and / or any other lossless data compression scheme suitable for use with binary-valued sparse vectors. Although the slow cell data compression unit 170 is shown separately for illustrative purposes, it should be understood that the slow cell data compression unit 170 and the counter may be integrated into the control circuitry 160, the page buffer circuitry 130, or the line decoder 120. The flash memory 100 includes a flash translation layer (FTL) that can be implemented using the control circuitry 160.

[0021] Memory cell array 110 is connected to row decoder 120 via multiple serial select lines (SSL), multiple word lines (WL), and multiple ground select lines (GSL). Memory cell array 110 is connected to page buffer circuitry 130 via multiple bit lines (BL). Memory cell array 110 may include multiple memory cells (e.g., multiple non-volatile NAND flash memory cells) each connected to one word line of the multiple word lines (WL) and one bit line of the multiple bit lines (BL). Memory cell array 110 may be divided into multiple memory blocks BLK1 to BLKz (e.g., z may be an integer greater than 2), each of the multiple memory blocks BLK1 to BLKz comprising memory cells. Additionally, each of the multiple memory blocks BLK1 to BLKz may be divided into multiple pages.

[0022] Multiple memory cells can be arranged in a two-dimensional (2D) array structure, or preferably in a three-dimensional (3D) vertical array structure. A 3D vertical array structure may include vertically oriented strings of cells such that at least one memory cell is located above another memory cell, which allows for parallel addressability. At least one memory cell may include a charge trapping layer. Suitable configurations for memory cell arrays may include 3D vertical array structures in which the 3D memory array is constructed as multiple levels, and bit lines and / or word lines are shared between levels.

[0023] Control circuitry 160 may receive external commands CMD and logical addresses ADDR from a host device and / or a memory controller, and control erase, program, and read operations of the non-volatile memory 100 based on the commands CMD and ADDR. Erasing operations may include executing a series of erase cycles, and programming operations may include executing a series of programming cycles. Each programming cycle may include a write programming operation, a write programming verification operation, a slow cell compression operation, and a data concatenation (or combination, such as serialization) operation. Each erase cycle may include an erase operation and an erase verification operation. Read operations may include normal read operations, consolidated read operations, and data recovery read operations.

[0024] For example, control circuit 160 can generate control signals CON for controlling voltage generator 150 based on command CMD, and can also generate control signals PBC for controlling page buffer circuit 130 based on command CMD. Furthermore, it can generate row address R_ADDR and column address C_ADDR based on logical address ADDR. Control circuit 160 can provide row address R_ADDR to row decoder 120, and can provide column address C_ADDR to data I / O circuit 140. Row decoder 120 can be connected to memory cell array 110 via multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL.

[0025] Voltage generator 150 can generate a voltage VS for the operation of non-volatile memory device 100 based on power signal PWR and control signal CON. Voltage VS can be applied by row decoder 120 to multiple serial select lines SSL, multiple word lines WL, and multiple ground select lines GSL. Additionally, voltage generator 150 can generate an erase voltage VERS for data erase operations based on power signal PWR and control signal CON. Eraser voltage VERS can be applied directly or via bit line BL to memory cell array 110.

[0026] Page buffer circuitry 130 may be connected to memory cell array 110 via multiple bit lines BL. Page buffer circuitry 130 may include multiple page buffers. In one exemplary embodiment, each page buffer may be connected to one bit line. In an alternative embodiment, each page buffer may be connected to two or more bit lines.

[0027] Page buffer circuit 130 can store data DAT to be programmed into memory cell array 110 via bit line BL, or can read data DAT sensed from memory cell array 110. In other words, page buffer circuit 130 can operate as a write driver or sense amplifier depending on the operating mode of non-volatile memory device 100.

[0028] Data I / O circuitry 140 can be connected to page buffer circuitry 130 via data line DL. Data I / O circuitry 140 can provide data DAT, which typically originates from outside the non-volatile memory device 100 but includes compressed and linked data, to memory cell array 110 via data line DL to page buffer circuitry 130, based on column address C_ADDR, or it can provide data DAT from memory cell array 110 to page buffer circuitry and / or outside of non-volatile memory device 100.

[0029] Go to Figure 2 An exemplary method for writing to memory is generally indicated by reference numeral 200. The method is initialized using a start block 210, which passes control to an input block 212 to receive data bits of the current page (e.g., the first write data unit), and the input block 212 then passes control to a function block 214.

[0030] Function block 214 selects a new word line (e.g., the first word line) and passes control to function block 216. Block 216 writes data bits by applying pulses to the memory cells of the selected word line (e.g., the first memory cell) to program data bits into the cells of the selected word line and passes control to function block 218. Block 218 counts the number C of remaining unprogrammed cells and passes control to decision block 220. Block 220 determines whether the number C of remaining unprogrammed cells is less than a threshold, and if not, passes control back to block 216. In one example, the threshold may be based on the number of cells successfully programmed with a previous pulse. In one example, the threshold may be based on the number of cells successfully programmed after the same number of pulses in a previous programming cycle. In one example, the threshold may be based on the number of cells successfully programmed at the current clock speed of each manufacturer specification after a given number of pulses. In one example, the threshold may be based on the maximum write latency of the currently running application.

[0031] When block 220 determines that the number C of remaining unprogrammed cells is less than a threshold, block 220 passes control to function block 222. Block 222 compresses the vector of unprogrammed data bits initially intended for the unprogrammed cells and passes control to input block 224. Block 224 receives another page of data bits and passes control to function block 226. Block 226 sequentially concatenates the compressed vector with the received data bits of the next page and passes control back to block 214. The concatenation can be performed by inserting the compressed vector into a data buffer before receiving the data bits, but is not limited to this. In an alternative embodiment, the concatenation can be performed by inserting the compressed vector into a data buffer after receiving the data bits.

[0032] Therefore, an exemplary algorithm for accelerating continuous writes interrupts the regular write programming operation before its completion, compresses the remaining unwritten data, and programs the compressed remaining data, along with the data of the next page, into a memory cell (e.g., a second memory cell) connected to another word line (e.g., a second word line). In one example, the first and second memory cells may be on different separate addressable layers of the same three-dimensional memory die. In one example, the first and second word lines may be positioned at different levels of the three-dimensional memory.

[0033] This scheme utilizes programming pulses with high bandwidth and achieves continuously improving programming speed. Since sector reads can utilize two word lines, compressed residual data is preferably stored in NAND memory on different planes or channels to facilitate parallel sensing. The logic-to-physical address distribution has been designed accordingly. Modeling and analysis results show a significant improvement in continuous programming bandwidth based on incremental step programming pulses (ISPP) and device parameters. To implement this algorithm, firmware modifications can be used on the memory controller. The benefits of this algorithm increase proportionally to changes in slow cell devices.

[0034] NAND flash memory can be programmed using a series of incremental programming pulses, where word line reads are performed after each or more pulses for data verification and subsequent pulse suppression for cells that have reached their target level. The amount of data stored in each pulse varies. Therefore, the bandwidth of the temporary programming pulses varies during the programming operation, typically using the first few pulses to program a small number of cells, then increasing the bandwidth as a larger number of cells reach their target level, and then decreasing the write rate as fewer slow cells require additional programming resources to complete processing with low bandwidth.

[0035] To take advantage of the differences between write phases, write programming can be activated only through high-bandwidth regions. An exemplary approach is to activate regular programming and stop it when the amount of data stored in each pulse drops below a predefined threshold. The remaining unprogrammed data is then compressed, concatenated with the next sector data, and written elsewhere using the same method. In one example, to restore read performance, during idle time, for example via a page buffer, the successfully programmed data bits can be read from a first memory cell, the concatenated data bits can be read from a second memory cell, the concatenated data bits can be decompressed, and the first write data cell can be reconstructed from the successfully programmed and decompressed data bits. In one example, the page buffer can write the reconstructed first write data cell to the first memory cell via a full-pulse program.

[0036] Now go to Figure 3 An exemplary method for using a controller to control writes to memory is generally indicated by reference numeral 300. The method is initialized using a start block 310, which passes control to function block 312, through which the controller sends a page of data to memory (such as NAND memory), but also stores a copy of the page of data in the controller. Block 312 passes control to function block 314, through which the NAND memory programs the data in pulses, and passes control to decision block 316. Block 316 determines whether a low bandwidth exists with each pulse, and if not, passes control back to block 314.

[0037] If block 316 determines that low bandwidth exists for each pulse, then block 316 passes control to function block 318. Block 318 uses NAND to compute verification data and passes control to function block 320. Block 320 uses NAND to send the verification data as a vector back to the controller and passes control to function block 322. Block 322 causes the controller to compress the received vector, concatenate the compressed vector with another page of data, update the flash translation layer (FTL), and program the concatenated data elsewhere.

[0038] like Figure 4As shown, an exemplary method for utilizing memory to control writes to memory is generally indicated by reference numeral 400. The method is initialized using a start block 410, which passes control to function block 412, through which the controller sends a page of data to memory (such as NAND memory) but does not save a copy. Block 412 passes control to function block 414, through which the NAND memory programs the data in pulses and passes control to decision block 416. Block 416 determines whether a low bandwidth exists with each pulse, and if not, passes control back to block 414.

[0039] If block 416 determines that low bandwidth exists for each pulse, then block 416 passes control to function block 418. Block 418 then uses the NAND to compute verification data and passes control to function block 420. Block 420 uses the NAND to compress the vector of differences between the verification data and the original data and passes control to function block 422. Block 422 causes the NAND to concatenate the compressed vector with another page of data from the controller, which is programmed on another word line or another plane.

[0040] Now go to Figure 5 The comparison between the exemplary slow-unit adaptive algorithm operation and the non-adaptive programming operation is generally indicated by reference numeral 500. Here, the operation of non-adaptive programming 510 is shown on the left side of the comparison diagram, and the operation of the exemplary slow-unit adaptive algorithm 520 is shown on the right side of the comparison diagram.

[0041] In non-adaptive programming 510, the current state is shown on the left. An example of the data vector (0, 1, 0, 0, 0, 1) is being written. In the first stage or programming pulse stage 512, cells with 0 receive a programming pulse (e.g., a programming pulse can be applied to word line WL). N Then, in the second stage, or read stage 514, the cell is read and checked to determine whether the cell has reached the target data level. In the diagram, the fourth cell from the left is the only cell that failed the verification.

[0042] In the third stage, or continued programming stage 516, adaptive programming continues to apply programming pulses to cells that have not reached their target level, thus continuing to apply programming pulses to a fourth cell. Typically, the number of cells addressed in each pulse decreases, and therefore the amount of data written per pulse also decreases.

[0043] In the exemplary slow cell adaptive algorithm 520, the process is depicted in the right column of the diagram. Here, the first step 522 is similar to the first step 512 of the non-adaptive programming process, so repeated descriptions are omitted. Next, in the read phase 524, a read is performed and a sparse vector (0, 0, 0, 1, 0, 0) is output, where each 0 represents a cell that has reached its target level and each 1 represents a cell that has not yet reached its target level. As used herein, the term "sparse vector" refers to a vector in which most elements are zero. For example, a sparse vector may be represented as a vector in which the ratio of the number of zero elements to the number of elements is greater than a predetermined threshold. For example, the predetermined threshold may be a value greater than or equal to 50%. In one example, the sparse vector may include data bits that were not successfully programmed. The marked positions are actually the slow cells that are dynamically detected. In the third phase 526, the vector is then compressed and concatenated with other sparse vectors and / or another data sector that will be programmed on another word line. In this way, each programming pulse is used for a large number of cells, and the situation where additional pulses are applied to a small number of cells is eliminated. Therefore, the write bandwidth is increased.

[0044] In other words, in this comparison between non-adaptive programming and the exemplary slow cell adaptive algorithm used for continuous write acceleration, the following comparison can be made: In left-hand or non-adaptive programming, a programming pulse is applied to the target cell, the word line is read for verification purposes, the cell requiring further programming pulses is determined, and the next pulse is executed when returning to the beginning of the programming loop.

[0045] In the right-hand or adaptive scheme, programming pulses are applied to the word line until the number of unprogrammed cells (either the total number of pulses or the number of unprogrammed cells per pulse) falls below a predefined threshold. The resulting vector of data allocated to the slow cells is then compressed, concatenated with data from other sectors, and preferably written to another word line in a different plane. Because the programming pulses use fewer pulses to program a larger number of cells, the write bandwidth is increased.

[0046] In this exemplary embodiment, a sparse vector of compressed, unprogrammed data bits may be concatenated with another write data unit or sector (such as, but not limited to, the next write data unit or sector). In one example, the write data unit may be at least one of a byte, word, page, and sector. In an alternative embodiment, adaptive write processing may collect and concatenate multiple sparse vectors of compressed, unprogrammed data bits, and write them together (e.g., once they span the size of, for example, a buffer, write data unit, or sector). In yet another alternative embodiment, multiple sparse vectors may be concatenated and subsequently compressed (e.g., to improve compression efficiency), and in particular, it is statistically possible to re-merge bifurcated data before a large number of data read operations occur.

[0047] In other words, the sparse vector of compressed, unprogrammed data bits does not need to be concatenated with the next write data unit or sector to be programmed. For example, adaptive write processing can continue to collect multiple sparse vectors and write them together into a single write data unit. Furthermore, various write schemes can be modified to meet desired performance criteria based on the specific aggregation and distribution characteristics of the compressed sparse vectors, such as in different applications and / or environments.

[0048] Supporting resources for implementing the exemplary scheme described are storage capacity, read time, and appropriate Flash Translation Layer (FTL) management. The percentage of skipped redundant cells can be adjusted via an exemplary algorithm to improve write performance while compromising storage capacity. Since the programming of compressed data is performed in another plane or channel and can therefore be sensed in parallel, read time is unaffected in small instruction queues. In large instruction queues, the channel bus sends an increased amount of data. To restore read time to its original setting, merging (such as sector reads and reprogramming using the full programming time) can be scheduled when the device is idle. The allocation of two or more addresses per sector uses appropriate logic-to-physical (L2P) tables and software within the FTL components.

[0049] II. Symbols

[0050] Symbol #1; Word line unit and data vector: A data vector with elements representing the level of each unit indexed accordingly. D To express. When to D During programming, the physical unit vector that marks the level of each unit after k programming pulses is used. C k The number of units in a word line is represented using W. Z To express.

[0051] Symbol #2; ISPP parameters: Incremental Step Programming Pulse (ISPP) parameters are represented as three tuples (V INIT ,ΔV,V REF V INIT This is the initial programming pulse size. ΔV is the incremental voltage applied to the previous pulse size. REF This is the target voltage threshold for each level. As a result, the voltage pulse value V(p) after p+1 pulses is:

[0052] V(p)=V INIT +p·ΔV (Equation 1)

[0053] There exist ISPP programming schemes that include multiple stages, where each stage utilizes a different V INIT The parameters and ΔV parameters are programmed using pulse counts to reset.

[0054] Symbol #3; Programming operation: Write processing executes some voltage pulses. In each cell's L levels, the pulse operation is a function:

[0055]

[0056] The function takes two inputs: a vector of cell levels representing the physical cell levels and a data vector representing the target level for each cell. The function represents the input to a data vector with c i <d i The cell is charged by a pulse operation, and the charge is added based on c. i and d i Both, along with some probabilities of ISPP and device characteristics, reach d. i For example, c i and d i This can represent the voltage level of a unit. Specifically:

[0057] λ( C k , D )= C k+1 (Equation 3)

[0058] Symbol #4; Write pulse bandwidth: The number of vectors of cells in the word line using W Z To represent. In a single-layer element (SLC), W Z Equal to the sum of the following items

[0059] P( C k , D )= u (Equation 4)

[0060] Among them, elements u i (vectoru The index i in () is a... C k ) i With D i The Kronecker delta operation for subtraction between two points:

[0061]

[0062] Where P is the Kronecker function operation δ[C ki -D i The vector form of ]. Therefore, u It is an element u i vector (vector) u Index i in C. Similarly, C ki It is a vector C k The i-th element, D i It is a vector D The i-th element.

[0063] The write bandwidth of pulse number k is the number of units that reach their target level in that pulse:

[0064] BW(k)=||P( C k , D )||1-||P( C k-1 , D )||1 (Equation 6)

[0065] Where, a vector of dimension N V The norm-1 distance, or Manhattan distance, is defined as:

[0066]

[0067] Symbol #5; Programming bandwidth region: The function BW(k) has at least one local maximum. A digital threshold (Th) is represented, which can be used to distinguish between high-bandwidth and low-bandwidth regions, where BW(k) ≥ Th in the high-bandwidth region and BW(k) ≥ Th in the low-bandwidth region. <Th。

[0068] III. High-bandwidth programming

[0069] The continuous programming algorithm includes real-time analysis of the write bandwidth for each pulse. Below is an example of the flow clearly described in Algorithm 1. In step (1), data is loaded, and programming begins. In step (2), the number of remaining cells to be addressed in future pulses is counted. This measurement indicates the bandwidth region. Step (3) compares whether the number of successfully programmed cells (or, optionally, the total number of unprogrammed cells) for each pulse is below a predefined threshold (low bandwidth). In this case, the remaining data vector is compressed (step 4), and then (for varying compressed vector lengths) concatenated with metadata and / or additional page data for programming (step 5). The concatenated vector is then programmed in another word line (step 6), and processing returns to the beginning of the loop until the data stream ends.

[0070] Algorithm 1: High-bandwidth pulse programming

[0071] (0) Receive as input: D1, D2 and a threshold, where D1 and D2 represent vectors of data bits for the current page and the next page, respectively, and the threshold may be based on a percentage of slow cells (e.g., 10%).

[0072] (1) While programming D1, for each programming pulse

[0073] (2) C ← Counts the number of remaining units to be programmed.

[0074] (3) If C < threshold

[0075] (4)C comp ← Compress the vector of the remaining data

[0076] (5) NextD←{C comp ,D2}#link

[0077] (6) Program NextD on another word line and return to (1).

[0078] (7) End

[0079] (8) End

[0080] The exemplary algorithm does not rely on prior knowledge of slow cells. These are detected in parallel with write operations and can be skipped based on a predefined or computed threshold, which can be adjusted, for example, based on the percentage of slow cells and / or, for example, based on the number of pulses.

[0081] The type and characteristics of the flash memory device can affect the expected gain in write acceleration. For example, in floating-gate based devices, programming may include multiple stages, each of which may have different ISPP parameters, such as to compensate for coupling. The write flow can be adjusted to allow simultaneous programming of word line cells by first programming to an intermediate level.

[0082] In charge trapping devices, a single pulse sequence can be used, where charge is incrementally added to all target cells. Therefore, while slow cells can be at any level (randomly distributed) in floating-gate techniques, in charge trapping, the probability of a cell being slowly written is proportional to its target level. This observation can be further enhanced based on slow cell analysis for specific programming algorithms and NVM devices.

[0083] IV. Analysis

[0084] In an adaptive setting where there is no benefit from the exemplary slow-cell adaptive algorithm, the page size data Pz will be programmed in a series of pulses, each pulse having a bandwidth BW(k). Therefore, the adaptive bandwidth is:

[0085]

[0086] In the exemplary slow-unit adaptive scheme, programming in k s The process is stopped after one pulse. Since the new page size consists of uncoded and compressed portions (the sum of which is greater than Pz), the resulting data being written must be normalized.

[0087]

[0088] Where H(p) is the binary entropy function:

[0089] H(p)=∑ i p i log p i (Equation 11)

[0090] Now go to Figure 6 For k s The overall bandwidth of each pulse is indicated by reference numeral 600. This indicates that k is determined in the high bandwidth region. s The write speed acceleration is caused by the number of pulses. The ratio of programmed data to the number of pulses (shown as the dashed area divided by k) s The ratio of programmed data to the number of impulses is higher than that of non-adaptive programming (which can be visualized as all graph regions divided by k).

[0091] Further normalization is used due to the increased effective page size or compression overhead. Compression is performed on index 0 of the original page. For example, if the normal write rate is 10 MB / s,

[0092]

[0093] For ease of explanation, assume the new scheme is in k s=The case where 99% of the cells are written after 0.8k pulses. However, the amount of data to be effectively programmed increases from Pz to Pz×H(0.99). Therefore, the new accelerated write speed is:

[0094]

[0095] k in the number of write pulses s The choice that maximizes bandwidth is:

[0096]

[0097] As the variation between cell programming speeds becomes greater, the scheme gain increases. Therefore, as the number of pulses per slow cell increases, the write bandwidth bottleneck is alleviated through an exemplary slow cell adaptive compression scheme.

[0098] V. Results

[0099] General parameters are used to estimate the gain of the scheme. The gain is affected by two parameters (i.e., the number of programmed stop pulses (k)). s The number of data bits written up to that point has an impact.

[0100] k s The multiplication of a portion of the total pulse used for non-adaptive full-word-line programming is modeled as follows:

[0101] k s = xXk, 0 < x < 1 (Equation 15)

[0102] The x-values ​​considered are 0.5 to 0.9 (therefore, 50% to 90% of the total number of adaptive pulses). The k-values ​​reached... s The number of bits written before each pulse is:

[0103]

[0104] The values ​​considered are 95% to 99.9% of the total data.

[0105] like Figure 7 As shown, the overall results are indicated by reference numeral 700. This provides sustained write acceleration with a given k s An overview of the number of bits written per pulse. Due to the value k s The portion modeled as a fraction of the total number of pulses used in non-adaptive programming (referred to as k) is therefore k s = x × k.

[0106] Here, based on the given k s The percentage increase in the number of write cells per pulse results in a significant linear increase in continuous programming speedup. The gain range is in the k... s= 0.8 × k and 1.05 times the 95% programming bits with k s = 0.5 × k and twice the 99.9% programming bit. This results in k being the write bandwidth equation. s Varying from 0.5 to 0.9 (50% to 90% of fully non-adaptive programming pulses) and corresponding to k s 95% to 99.9% of the write cells per pulse s The acceleration varies between x1.05 and x2 according to the scheme parameters shown.

[0107] Go to Figure 8 The table results are generally indicated by reference number 800. That is to say, Figure 8 Will Figure 7 Specific data values ​​are graphically represented in a table.

[0108] VI. Implementation Method

[0109] Depending on the target performance and design complexity, the proposed solution can be integrated with or without NAND modifications. To restore read performance, programmatic merging can be performed during idle time, where separate word lines are read and merged for a full write operation and corresponding normal subsequent read operations.

[0110] Without NAND modification

[0111] Algorithm 2 shows a summary of the method. The controller sends the data to be programmed to the NAND flash memory, but keeps a copy (step 1). The ISPP process programs the data up to k. s The system reads the data that can be stored and sends it back to the controller (step 2). Finally, the controller compresses the received residual data, associates the compressed data with another page, updates the FTL using the segmented address of each page, and continues programming on the next word line (step 3).

[0112] Algorithm 2: Continuous writing without NAND changes

[0113] (1) The controller sends the page to the NAND and keeps a copy.

[0114] (2) NAND is currently using k s Each pulse programs the data and sends the verification data back to the controller.

[0115] (3) The controller compresses the received vector, links it to another page, updates the FTL, and programs it elsewhere.

[0116] In the case of NAND modification

[0117] The steps of this scheme are listed in Algorithm 3. If on-chip modification is permitted, a comparison between the verification data and the original data, and compression of the difference vector, are performed on the flash die without sending the verification data to the controller (steps 1 to 4). Next, the compressed vector is appended to the next or subsequent input data, and the compressed vector is programmed to the next or subsequent word line or plane using the next or subsequent input data (steps 5 and 6).

[0118] Algorithm 3: Continuous Writes with NAND Changes

[0119] (1) The controller sends the page to the NAND flash memory.

[0120] (2) NAND is currently using k s Each pulse programs the data.

[0121] (3) Execution page read verification

[0122] (4)C comp ← Compress the vector of differences between the validation data and the original data (on-chip compression)

[0123] (5) NextD←C comp Connect to the next controller data D2

[0124] (6) Program NextD on the next word line or another plane.

[0125] VII. Comments

[0126] Non-volatile memory with high sustained write throughput is desired for data-intensive applications (such as high-definition (HD) video recording). A non-preferred approach to increasing I / O operations is to utilize multiple components in parallel. However, system costs increase accordingly, and such a solution is not feasible for small applications or mobile applications (such as wearable computing devices or sensor modules). Using error-correcting codes (ECC) is also a non-preferred method to attempt to accelerate writes, but the number of slow cells that cause programming bottlenecks (which can correspond to high bit error rates and impractical ECC overhead and complexity) is typically higher than 1%.

[0127] This disclosure provides an exemplary preferred algorithm for increasing the sustained write throughput of a single NVM flash memory component. The method according to at least one embodiment executes a programming pulse only when a large number of cells are successfully programmed in each pulse. When write bandwidth slows down, the algorithm compresses the remaining data vector, concatenates the compressed data with the next page data, and continues the programming operation using the next word line. As a result, programming pulses are applied only in high-bandwidth regions, and acceleration is achieved.

[0128] While the approach accelerates sustained write speeds, read speeds of data programmed on separate word lines can be slowed due to multiple sensing operations from different word lines used for decoding compressed and / or concatenated data. Therefore, merging sector data reads and reconstructions (e.g., utilizing full programming during idle time) can be used to restore read performance. Analysis shows that, depending on ISPP parameters and device variations, the speed can be doubled throughout single-die programming.

[0129] As memory devices incorporate an increasing number of cells into each silicon die, the manufacturing and process control become correspondingly more difficult; consequently, variations between cells are unlikely to be significantly reduced. The approach disclosed herein is scalable because it dynamically utilizes the programming characteristics of NVM word lines without requiring prior knowledge of which cells might be slow due to transient environmental factors. The currently disclosed scheme eliminates bottlenecks caused by slow cells and enhances sustained system write performance.

[0130] The method of the present invention can be implemented as computer-readable instructions written on a computer-readable recording medium. The computer-readable recording medium can be any type of recording device that stores data in a computer-readable manner.

[0131] Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage devices, and carrier waves (e.g., data transmission over the Internet). Computer-readable recording media can be distributed across multiple networked computer systems, such that computer-readable instructions are written to and executed from the computer-readable recording media in a distributed manner. The functional programs, code, and code segments required to implement the methods of the present invention can be readily derived by those skilled in the art to which this invention pertains.

[0132] Although exemplary embodiments of the inventive concept have been shown and described, it should be understood that changes may be made therein by those skilled in the art without departing from the scope, principles and spirit of the inventive concept as defined by the appended claims and their equivalents.

Claims

1. A method for memory programming, comprising: Receive a first write data unit comprising a first plurality of data bits; The first plurality of data bits are programmed into the first plurality of memory cells by at least one pulse; Determine whether the number of memory cells that were unsuccessfully programmed by the at least one pulse is less than a threshold; and If the number of memory cells that failed to be programmed by the at least one pulse is less than a threshold, then the first vector of the unprogrammed data bits is compressed, a second write data cell is received, the compressed first vector is concatenated with the second write data cell, and the concatenated vector is programmed into a second plurality of memory cells. The first vector is a sparse vector. The step of linking the compressed first vector with the second write data unit includes linking the first vector with the second vector of the unprogrammed data bits of the second write data unit.

2. The method according to claim 1, wherein, The first and second vectors are each compressed before being joined.

3. The method according to claim 1 or 2, wherein, The threshold is based on the number of memory cells that have been successfully programmed by a previous pulse.

4. The method according to claim 1 or 2, wherein, The threshold is based on the number of memory cells that were successfully programmed after the same number of pulses in the previous programming cycle.

5. The method according to claim 1 or 2, wherein, The threshold is based on the number of memory cells that are successfully programmed at the current clock speed of each manufacturer's specification after a given number of pulses.

6. The method according to claim 1 or 2, wherein, The threshold is based on the maximum write latency of the currently running application.

7. The method according to claim 1 or 2, further comprising: After concatenating the vectors, the flash translation layer is updated.

8. The method according to claim 1 or 2, wherein, Each unit of data written is at least one of a byte, word, page, and sector.

9. The method according to claim 1 or 2, wherein, The first plurality of memory cells and the second plurality of memory cells are on different separate addressable layers of the same three-dimensional memory die.

10. The method according to claim 1 or 2, further comprising: Read the successfully programmed data bits from the first memory cell; Read the linked vector from the second or more memory units; Decompress the connected vectors; and The first written data unit is reconstructed from the read data bits and the decompressed vector.

11. The method according to claim 1 or 2, further comprising: Select the address lines connected to the first plurality of memory cells and / or the second plurality of memory cells; Address lines are word lines.

12. A memory device, comprising: Memory cell array; The data circuit is configured to receive a first write data unit comprising a first plurality of data bits; A line decoder, connected to a memory cell array, and configured to select the first word line of a first plurality of memory cells connected to the memory cell array; Page buffers are connected to data circuitry and memory cell arrays and are configured to program a first plurality of data bits into a first plurality of memory cells by at least one pulse. A counter is configured to determine whether the number of memory cells that have not been successfully programmed by the at least one pulse is less than a threshold. A slow cell data compressor, connected to a counter, is configured to compress a first vector of unprogrammed data bits if the number of memory cells that have failed to be programmed by the at least one pulse is less than a threshold. and A control circuit, connected to a slow cell data compressor and a page buffer, is configured to: if the number of memory cells that have not been successfully programmed by the at least one pulse is less than a threshold, concatenate a compressed first vector with a second write data cell, and write the concatenated first vector to a second plurality of memory cells in the memory cell array that are connected to a second word line different from the first word line. The page buffer is configured to read the first vector of the join from a second plurality of memory units and decompress the first vector of the join. The first vector is a sparse vector. The step of linking the compressed first vector with the second write data unit includes linking the first vector with the second vector of the unprogrammed data bits of the second write data unit.

13. The memory device according to claim 12, wherein, The slow unit data compressor and counter are controlled by the circuit.

14. The memory device according to claim 12, wherein, At least one of the slow unit data compressor and the counter is included in the page buffer.

15. The memory device according to any one of claims 12 to 14, wherein: The page buffer is configured to read successfully programmed data bits from a first plurality of memory cells and reconstruct the first write data cell from the read data bits and the decompressed first vector.

16. The memory device according to claim 15, wherein, The page buffer is also configured to write a first write data unit, including a first plurality of data bits, to a first plurality of memory units via full-pulse programming.

17. A computer-readable recording medium storing instructions, which, when executed by a processor, cause the processor to perform the method of any one of claims 1 to 11.

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