Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor packaging device and a manufacturing method thereof. By canceling the solder pad on one pad in the prior art, i.e. only forming the pad without forming the solder pad, and by directly butting the front or side surface of the lower layer pad with the solder pad of the upper layer structure, and directly butting the front or side surface of the upper layer pad with the solder pad of the lower layer structure, i.e. the positions of the upper and lower solder pads are designed in a staggered manner, more space is left to expand the space between the two adjacent electrical connections, thereby avoiding bridging.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Currently, when non-electroplated metal-to-metal bonding methods are applied to fine-pitch semiconductor packaging devices, the following problems may arise:

[0003] First, according to the fan-out design rules, in order to form adjacent electrical connections, such as Figure 1A The first electrical connector 11 and the second electrical connector 12 are shown. Forming the first electrical connector 11 requires forming a pad 111, then forming a dielectric layer 113 on the pad 111, then creating an opening in the dielectric layer 113 to expose the pad 111, and finally forming a solder pad 112 in the exposed area of ​​the pad 111. Similarly, forming the second electrical connector 12 requires forming a pad 121, then forming a dielectric layer 123 on the pad 121, then creating an opening in the dielectric layer 123 to expose the pad 121, and finally forming a solder pad 122 in the exposed area of ​​the pad 121. In this process, the openings on the pads 111 and 121 need to be relatively wide to accommodate the alignment errors of the solder pads 112 to the pads 111 and 121, respectively. For example, currently, when the diameter of the aforementioned opening is generally 10 micrometers, the diameters of pads 111 and 121 need to be at least 23.5 micrometers. Furthermore, currently, in adjacent electrical connections (such as...) Figure 1A As shown, when the pitch of the first electrical connector 11 and the second electrical connector 12) is 30 micrometers, if the diameter of the pads 111 and 121 is at least 23.5 micrometers, and the thickness of the dielectric layer 113 of the first electrical connector 11 and the dielectric layer 123 of the second electrical connector 12 is 0.7 micrometers, then the adjacent electrical connectors (such as...) Figure 1AAs shown, the space between the first electrical connector 11 and the second electrical connector 12 is only 5.8 micrometers (30-23.5-0.7=5.8). During the formation of pads 112 and 122 using a non-electroplated metal-to-metal bonding method, some metal ions (e.g., copper ions) adhere to the outer surfaces of the dielectric layers of pads 111 and 122. Since the distance between the outer dielectric layers of pads 111 and 122 is only a maximum of 5.8 micrometers, metal ions adhering to the outer surface of the outer dielectric layer of pad 111 may electrically connect to metal ions adhering to the outer surface of the outer dielectric layer of pad 122, leading to a short circuit between pads 112 and 122, resulting in bridging. Figure 1B Is with Figure 1A The image shown is a schematic diagram of the longitudinal cross-sectional structure of a practical product corresponding to the semiconductor packaging device 1a. From... Figure 1B The two dashed boxes in the middle both show the presence of bridging.

[0004] Based on the aforementioned problems, the minimum pitch of non-electroplating technology when applied to fine-pitch areas is currently 40 micrometers. Summary of the Invention

[0005] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0006] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0007] The first upper package structure includes a first upper circuit layer and a second upper circuit layer, which are arranged horizontally side by side. The first upper circuit layer includes a first upper dielectric layer, a first upper pad and a first upper solder pad arranged from top to bottom. The second upper circuit layer includes a second upper dielectric layer and a second upper pad arranged from top to bottom.

[0008] The first lower package structure includes a first lower circuit layer and a second lower circuit layer, which are arranged horizontally side by side. The first lower circuit layer includes a first lower dielectric layer, a first lower pad and a first lower solder pad arranged from bottom to top. The second lower circuit layer includes a second lower dielectric layer and a second lower pad arranged from bottom to top.

[0009] The first upper pad is electrically connected to the second lower pad, and the first lower pad is electrically connected to the second upper pad.

[0010] In some alternative embodiments, the first upper pad is disposed on the upper surface of the second lower pad, and the second upper pad is disposed on the upper surface of the first lower pad.

[0011] In some optional embodiments, the semiconductor packaging device further includes:

[0012] A first non-electroplated metal layer is disposed on the sidewall of the first upper pad, the sidewall of the second lower pad, and between the first upper pad and the second lower pad.

[0013] A second non-electroplated metal layer is disposed on the sidewall of the first lower pad, the sidewall of the second upper pad, and between the first lower pad and the second upper pad.

[0014] In some alternative embodiments, the portion of the sidewall of the first non-electroplated metal layer between the first upper pad and the second lower pad is recessed inward, and the portion of the sidewall of the second non-electroplated metal layer between the first lower pad and the second upper pad is recessed inward.

[0015] In some alternative implementations, the maximum outer diameter of the second lower pad is smaller than the maximum outer diameter of the first upper pad, and the maximum outer diameter of the second upper pad is smaller than the maximum outer diameter of the first lower pad.

[0016] In some alternative embodiments, the first unplated metal layer extends to the upper surface and / or side surface of the second lower dielectric layer, and the second unplated metal layer extends to the lower surface and / or side surface of the second upper dielectric layer.

[0017] In some alternative implementations, the first upper pad is located on the side of the second lower pad, and the first lower pad is located on the side of the second upper pad.

[0018] In some optional embodiments, the semiconductor packaging device further includes:

[0019] A third non-electroplated metal layer is disposed on the sidewall and lower surface of the first upper solder pad;

[0020] A fourth non-electroplated metal layer is disposed on the sidewall and upper surface of the first lower solder pad.

[0021] In some alternative implementations, the third non-electroplated metal layer contacts a portion of the upper surface of the second lower pad.

[0022] In some alternative embodiments, the second lower dielectric layer extends to the upper surface of the second lower pad and to the sidewall of the second lower pad that does not contact the third unplated metal layer.

[0023] In some alternative embodiments, the third non-electroplated metal layer extends to the sidewall of the second lower dielectric layer located on the upper surface portion of the second lower pad.

[0024] In some alternative embodiments, the third unplated metal layer extends to the upper surface of the second lower dielectric layer disposed on the upper surface portion of the second lower pad.

[0025] Secondly, this disclosure provides a semiconductor packaging apparatus, comprising:

[0026] The second upper package structure includes a third upper circuit layer and a fourth upper circuit layer, which are arranged horizontally side by side. The third upper circuit layer includes a third upper dielectric layer, a third upper pad and a third upper solder pad arranged from top to bottom. The fourth upper circuit layer includes a fourth upper dielectric layer, a fourth upper pad and a fourth upper solder pad arranged from top to bottom.

[0027] The second lower package structure includes a third lower circuit layer and a fourth lower circuit layer, which are arranged horizontally side by side. The third lower circuit layer includes a third lower dielectric layer and a third lower pad arranged from bottom to top, and the fourth lower circuit layer includes a fourth lower dielectric layer and a fourth lower pad arranged from bottom to top.

[0028] The sidewall of the third upper pad is electrically connected to the sidewall of the third lower pad, and the sidewall of the fourth upper pad is electrically connected to the sidewall of the fourth lower pad.

[0029] Thirdly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0030] A first upper package structure and a first lower package structure are provided. The first upper package structure includes a first upper circuit layer and a second upper circuit layer, which are arranged horizontally side by side. The first upper circuit layer includes a first upper dielectric layer, a first upper pad, and a first upper solder pad arranged from top to bottom. The second upper circuit layer includes a second upper dielectric layer and a second upper pad arranged from top to bottom. The first lower package structure includes a first lower circuit layer and a second lower circuit layer, which are arranged horizontally side by side. The first lower circuit layer includes a first lower dielectric layer, a first lower pad, and a first lower solder pad arranged from bottom to top. The second lower circuit layer includes a second lower dielectric layer and a second lower pad arranged from bottom to top.

[0031] The first upper packaging structure is placed above the first lower packaging structure;

[0032] The first upper pad is electrically connected to the second lower pad, and the first lower pad is electrically connected to the second upper pad, using a non-electroplated method.

[0033] To address the bridging issues that may arise when applying non-electroplated metal-to-metal bonding methods to fine-pitch semiconductor packaging devices, the semiconductor packaging device and method disclosed herein eliminate the pads on one pad in the prior art, i.e., only forming the pad and not the pads, and directly connect the upper layer pads to the front or side of the lower layer pads, and the lower layer pads directly connect to the front or side of the upper layer pads, i.e., the positions of the upper and lower pads are staggered, thereby leaving more space to expand the space between adjacent electrical connectors and avoiding bridging. Attached Figure Description

[0034] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0035] Figure 1A A schematic diagram of the longitudinal cross-sectional structure of an embodiment 1a of a semiconductor packaging device in the prior art;

[0036] Figure 1B Is with Figure 1A A schematic diagram of the longitudinal cross-sectional structure of the semiconductor packaging device 1a shown in the practical application.

[0037] Figure 2A , 2B 2A, 2B, 2C, 2D, and 2E are longitudinal cross-sectional structural schematic diagrams of one embodiment of the semiconductor packaging apparatus 2A, 2B, 2C, 2D, and 2E according to the present disclosure;

[0038] Figure 2F It is based on Figure 2E An enlarged schematic diagram of the dashed rectangular portion in the semiconductor packaging device 2e shown;

[0039] Figure 2G It is based on Figure 2F An enlarged schematic diagram of the dashed rectangular portion in the semiconductor packaging device shown;

[0040] Figure 2H This is a longitudinal cross-sectional structural schematic diagram of one embodiment of the semiconductor packaging apparatus 2h according to the present disclosure;

[0041] Figure 3A-3M This is a longitudinal cross-sectional structural diagram of semiconductor packaging apparatus 3a-3m manufactured at various stages according to an embodiment of the present disclosure, using semiconductor packaging apparatus 2a.

[0042] Figure 4A-4M This is a longitudinal cross-sectional structural diagram of semiconductor packaging apparatus 4a-4m manufactured at various stages according to an embodiment of the present disclosure, using semiconductor packaging apparatus 2e.

[0043] Symbol explanation:

[0044] 11-First electrical connector; 111-Pad; 112-Pad; 12-Second electrical connector; 121-Pad; 122-Pad; 21-First upper package structure; 211-First upper circuit layer; 2111-First upper dielectric layer; 2112-First upper pad; 2113-First upper pad; 212-Second upper circuit layer; 2121-Second upper dielectric layer; 2122-Second upper pad; 22-First lower package structure; 221-First lower circuit layer; 2211-First lower dielectric layer; 2212 - First lower pad; 2213 - First lower solder pad; 222 - Second lower circuit layer; 2221 - Second lower dielectric layer; 2222 - Second lower pad; 23 - First non-plated metal layer; 24 - Second non-plated metal layer; d1 - Maximum outer diameter of the second lower pad; d2 - Maximum outer diameter of the first upper solder pad; d3 - Maximum outer diameter of the first lower pad; d4 - Maximum outer diameter of the second upper solder pad; 25 - Third non-plated metal layer; 26 - Fourth non-plated metal layer; 22111 - First carrier board; 222 11-Second substrate; 22112-First dielectric layer of the first lower dielectric layer; 22212-First dielectric layer of the second lower dielectric layer; 22113-First seed layer of the first lower dielectric layer; 22213-First seed layer of the second lower dielectric layer; 22114-Second dielectric layer of the first lower dielectric layer; 22214-Second dielectric layer of the second lower dielectric layer; 22115-Second seed layer of the first lower dielectric layer; 22215-Second seed layer of the second lower dielectric layer; 27-Photoresist; 28-Second upper part Package structure; 281-Third upper circuit layer; 2811-Third upper dielectric layer; 2812-Third upper pad; 2813-Third upper pad; 282-Fourth upper circuit layer; 2821-Fourth upper dielectric layer; 2822-Fourth upper pad; 2823-Fourth upper pad; 29-Second lower package structure; 291-Third lower circuit layer; 2911-Third lower dielectric layer; 2912-Third lower pad; 292-Fourth lower circuit layer; 2921-Fourth lower dielectric layer; 2922-Fourth lower pad. Detailed Implementation

[0045] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0046] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0047] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0048] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] refer to Figure 2A ,in, Figure 2A A longitudinal cross-sectional structural schematic diagram of an embodiment 2a of a semiconductor packaging device according to the present disclosure is shown.

[0050] like Figure 2A As shown, the semiconductor packaging device 2a includes a first upper packaging structure 21 and a first lower packaging structure 22.

[0051] The first upper package structure 21 includes a first upper circuit layer 211 and a second upper circuit layer 212. The first upper circuit layer 211 and the second upper circuit layer 212 are arranged horizontally side by side. The first upper circuit layer 211 includes a first upper dielectric layer 2111, a first upper pad 2112 and a first upper pad 2113 arranged from top to bottom. The second upper circuit layer 212 includes a second upper dielectric layer 2121 and a second upper pad 2122 arranged from top to bottom.

[0052] The first lower package structure 22 includes a first lower circuit layer 221 and a second lower circuit layer 222. The first lower circuit layer 221 and the second lower circuit layer 222 are arranged horizontally side by side. The first lower circuit layer 221 includes a first lower dielectric layer 2211, a first lower pad 2212 and a first lower solder pad 2213 arranged sequentially from bottom to top. The second lower circuit layer 222 includes a second lower dielectric layer 2221 and a second lower pad 2222 arranged sequentially from bottom to top.

[0053] Here, the first upper pad 2113 of the first upper circuit layer 211 is electrically connected to the second lower pad 2222 of the second lower circuit layer 222. The first lower pad 2213 of the first lower circuit layer 221 is electrically connected to the second upper pad 2122 of the second upper circuit layer 212.

[0054] In some alternative implementations, such as Figure 1A As shown, the first upper pad 2113 is disposed on the upper surface of the second lower pad 2222, and the second upper pad 2122 is disposed on the upper surface of the first lower pad 2213. That is, the first upper circuit layer 211 and the first lower circuit layer 221 can be considered as first circuit layers with the same shape, and each first circuit layer includes a dielectric layer, a pad, and a solder pad disposed in sequence; while the second upper circuit layer 212 and the second lower circuit layer 222 are second circuit layers with the same shape, and each second circuit layer includes a dielectric layer and a pad disposed in sequence.

[0055] Furthermore, since the first upper pad 2113 of the first upper circuit layer 211 is electrically connected to the second lower pad 2222 of the second lower circuit layer 222, the first upper circuit layer 211 and the second lower circuit layer 222 can be considered to form a first electrical connector; since the first lower pad 2213 of the first lower circuit layer 221 is electrically connected to the second upper pad 2122 of the second upper circuit layer 212, the first lower circuit layer 221 and the second upper circuit layer 212 can be considered to form a second electrical connector. The first electrical connector and the second electrical connector are two adjacent electrical connectors.

[0056] In the prior art, this is equivalent to bonding two first circuit layers with the same shape, having a dielectric layer, pads, and solder pads, using a non-electroplated metal-to-metal bonding method. Therefore, in the prior art, the space between the two electrical connectors depends on the pitch of the two electrical connectors and the size of the pads on the first circuit layer. However, in the semiconductor packaging device 2a, a first circuit layer with a dielectric layer, pads, and solder pads sequentially disposed, and a second circuit layer with a dielectric layer and pads sequentially disposed, are bonded together; that is, the solder pads of the first circuit layer are bonded to the pads of the second circuit layer. Therefore, in the semiconductor packaging device 2a, the space between the two electrical connectors depends on the pitch of the two electrical connectors, the pads of the first circuit layer, and the size of the pads of the second circuit layer. Since the size of the pads on the first circuit layer is often smaller than the size of the pads on the second circuit layer, the distance between the two electrical connectors in the semiconductor packaging device 2a is increased compared to the prior art for the same pitch, which can reduce the possibility of bridging and improve product yield.

[0057] Here, the first upper dielectric layer 2111, the second upper dielectric layer 2121, the first lower dielectric layer 2211, and the second lower dielectric layer 2221 may include organic and / or inorganic materials. The organic materials may be, for example, polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylenebenzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0058] The first upper pad 2112, the second upper pad 2122, the first lower pad 2212, and the second lower pad 2222 can be various conductive materials. For example, they can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0059] The first upper pad 2113 and the first lower pad 2213 can be various conductive materials. For example, they can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0060] In some optional embodiments, the semiconductor packaging device 2a may further include: a first non-electroplated metal layer 23 and a second non-electroplated metal layer 24. Wherein:

[0061] A first non-electroplated metal layer 23 is disposed on the sidewall of the first upper solder pad 2113, the sidewall of the second lower solder pad 2222, and between the first upper solder pad 2113 and the second lower solder pad 2222. The first non-electroplated metal layer 23 is used for electrical connection between the first upper solder pad 2113 and the second lower solder pad 2222. That is, the first upper solder pad 2113 and the second lower solder pad 2222 are electrically connected through the first non-electroplated metal layer 23. The first non-electroplated metal layer 23 is a metal layer formed using a non-electroplated, i.e., chemical plating method. Using the non-electroplated first non-electroplated metal layer 23 to achieve bonding between the first upper solder pad 2113 and the second lower solder pad 2222 avoids the heating operation in the reflow process using traditional solder bonding, making it more suitable for temperature-sensitive products and preventing problems such as product warpage and cracking.

[0062] A second electroless metal layer 24 is disposed on the sidewall of the first lower solder pad 2213, the sidewall of the second upper solder pad 2122, and between the first lower solder pad 2213 and the second upper solder pad 2122. Similarly, the second electroless metal layer 24 is used for electrical connection between the first lower solder pad 2213 and the second upper solder pad 2122. That is, the first lower solder pad 2213 and the second upper solder pad 2122 are electrically connected through the second electroless metal layer 24. The second electroless metal layer 24 is a metal layer formed using electroless plating, i.e., chemical plating. Using the electroless second electroless metal layer 24 to achieve bonding between the first lower solder pad 2213 and the second upper solder pad 2122 avoids the heating operation in the reflow process using traditional solder bonding, making it more suitable for temperature-sensitive products and preventing problems such as product warpage and cracking.

[0063] Here, the first non-electroplated metal layer 23 and the second non-electroplated metal layer 24 are metal layers formed by an electroplating method. The first non-electroplated metal layer 23 and the second non-electroplated metal layer 24 can be various conductive materials. For example, they can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0064] The following is for reference. Figure 2B , Figure 2B This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2b of the semiconductor packaging apparatus according to the present disclosure. Figure 2B The semiconductor packaging device 2b shown is similar to Figure 2A The semiconductor packaging device 2a shown differs in that: the sidewall of the first non-electroplated metal layer 23 located between the first upper pad 2113 and the second lower pad 2222 is recessed inward, and the sidewall of the second non-electroplated metal layer 24 located between the first lower pad 2213 and the second upper pad 2122 is also recessed inward. This is because, during the manufacturing process, the first non-electroplated metal layer 23 is formed by chemical plating simultaneously on the first upper pad 2113 and the second lower pad 2222. During the chemical plating process, metal ions grow outward along the outer surface of the first upper pad 2113 and the second lower pad 2222. After the chemical plating is completed, a recess is formed in the portion between the first lower pad 2213 and the second upper pad 2122.

[0065] The following is for reference. Figure 2C , Figure 2C This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2c of the semiconductor packaging apparatus according to the present disclosure. Figure 2C The semiconductor packaging device 2c shown is similar to Figure 2AThe semiconductor packaging device 2a shown differs in that: the maximum outer diameter d1 of the second lower pad 2222 is smaller than the maximum outer diameter d2 of the first upper pad 2113, and the maximum outer diameter d3 of the second upper pad 2122 is smaller than the maximum outer diameter d4 of the first lower pad 2213. Thus, relative to... Figure 2A In the semiconductor packaging device 2a shown, the spacing and distance between adjacent electrical connectors are larger, further reducing the possibility of bridging.

[0066] The following is for reference. Figure 2D , Figure 2D This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2d of the semiconductor packaging apparatus according to the present disclosure. Figure 2D The semiconductor packaging device 2d shown is similar to Figure 2C The semiconductor packaging device 2c shown differs in that: the first electroless metal layer 23 extends to the upper surface and / or side surface of the second lower dielectric layer 2221, and the second electroless metal layer 24 extends to the lower surface and / or side surface of the second upper dielectric layer 2121. This is because during the formation of the first electroless metal layer 23 by electroless plating, metal ions also adhere to the upper surface and / or side surface of the second lower dielectric layer 2221, and similarly, during the formation of the first electroless metal layer 23 by electroless plating, metal ions also adhere to the lower surface and / or side surface of the second upper dielectric layer 2121.

[0067] The following is for reference. Figure 2E , Figure 2E This is a longitudinal cross-sectional structural schematic diagram of an embodiment 2d of the semiconductor packaging apparatus according to the present disclosure. Figure 2E The semiconductor packaging device 2e shown is similar to Figure 2A The semiconductor packaging device 2a shown differs in that: the first upper pad 2113 is located on the side of the second lower pad 2222, and the first lower pad 2213 is located on the side of the second upper pad 2122. Relative to Figure 2A In the semiconductor packaging device 2a shown, the first upper pad 2113 and the second lower pad 2222 are arranged vertically and electrically connected through their upper and lower surfaces, and the first lower pad 2213 and the second upper pad 2122 are arranged vertically and electrically connected through their upper and lower surfaces. In the semiconductor packaging device 2e, the first upper pad 2113 and the second lower pad 2222 are arranged horizontally and electrically connected through their sides, and the first lower pad 2213 and the second upper pad 2122 are arranged vertically and horizontally and electrically connected through their sides. This reduces the electrical connection paths between the first upper pad 2112 and the second lower pad 2222, as well as between the second upper pad 2122 and the first lower pad 2212, resulting in better electrical transmission performance.

[0068] In some alternative implementations, such as Figure 2EAs shown, the semiconductor packaging device 2e may further include: a third electroless metal layer 25 and a fourth electroless metal layer 26. Wherein:

[0069] A third non-electroplated metal layer 25 is disposed on the sidewall and lower surface of the first upper solder pad 2113. The third non-electroplated metal layer 25 is used for electrical connection between the first upper solder pad 2113 and the second lower solder pad 2222. That is, the first upper solder pad 2113 and the second lower solder pad 2222 are electrically connected through the third non-electroplated metal layer 25. The third non-electroplated metal layer 25 is a metal layer formed using a non-electroplated, i.e., chemical plating method. Using the non-electroplated third non-electroplated metal layer 25 to achieve bonding between the first upper solder pad 2113 and the second lower solder pad 2222 avoids the heating operation in the reflow process using traditional solder bonding, making it more suitable for temperature-sensitive products and preventing problems such as product warpage and cracking.

[0070] A fourth non-electroplated metal layer 26 is disposed on the sidewall and upper surface of the first lower solder pad 2213. Similarly, the fourth non-electroplated metal layer 26 is used for electrical connection between the first lower solder pad 2213 and the second upper solder pad 2122. That is, the first lower solder pad 2213 and the second upper solder pad 2122 are electrically connected through the fourth non-electroplated metal layer 26. The fourth non-electroplated metal layer 26 is a metal layer formed by non-electroplation, i.e., chemical plating. Using the non-electroplated fourth non-electroplated metal layer 26 to achieve bonding between the first lower solder pad 2213 and the second upper solder pad 2122 avoids the heating operation in the reflow process of traditional solder bonding, making it more suitable for temperature-sensitive products and avoiding problems such as product warpage and cracking.

[0071] Here, the first non-electroplated metal layer 23 and the second non-electroplated metal layer 24 are metal layers formed by an electroplating method. The first non-electroplated metal layer 23 and the second non-electroplated metal layer 24 can be various conductive materials. For example, they can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0072] The following is for reference. Figure 2F and Figure 2G , Figure 2F It is based on Figure 2E An enlarged schematic diagram of the dashed rectangular portion in the semiconductor packaging device 2e shown. Figure 2G It is based on Figure 2F The enlarged schematic diagram of the semiconductor packaging device shown is an enlarged view of the dashed rectangular portion.

[0073] In some alternative implementations, the third unplated metal layer 25 may contact a portion of the upper surface of the second lower pad 2222. For example... Figure 2GAs shown in the middle rectangle R1.

[0074] In some alternative embodiments, the second lower dielectric layer 2221 extends to the upper surface of the second lower pad 2222 and to the sidewall of the second lower pad 2222 that does not contact the third unplated metal layer 25. For example... Figure 2G Rectangles R1 and R2 are shown in the diagram.

[0075] In some alternative embodiments, the third unplated metal layer 25 may also extend to the sidewall of the second lower dielectric layer 2221 disposed on the upper surface portion of the second lower pad 2222. For example... Figure 2G As shown in rectangle R3.

[0076] In some alternative embodiments, the third unplated metal layer 25 may extend to the upper surface of the second lower dielectric layer 2221 disposed on the upper surface portion of the second lower pad 2222. For example... Figure 2G The rectangle R4 is shown in the figure.

[0077] The following is for reference. Figure 2H ,in, Figure 2H A longitudinal cross-sectional structural schematic diagram of an embodiment 2h of a semiconductor packaging device according to the present disclosure is shown.

[0078] like Figure 2H As shown, the semiconductor packaging device 2h includes: a second upper packaging structure 28 and a second lower packaging structure 29. Wherein:

[0079] The second upper package structure 28 includes a third upper circuit layer 281 and a fourth upper circuit layer 282. The third upper circuit layer 281 and the fourth upper circuit layer 282 are arranged horizontally side by side. The third upper circuit layer 281 includes a third upper dielectric layer 2811, a third upper pad 2812, and a third upper solder pad 2813 arranged from top to bottom. The fourth upper circuit layer 282 includes a fourth upper dielectric layer 2821, a fourth upper pad 2822, and a fourth upper solder pad 2823 arranged from top to bottom.

[0080] The second lower package structure 29 includes a third lower circuit layer 291 and a fourth lower circuit layer 292. The third lower circuit layer 291 and the fourth lower circuit layer 292 are arranged horizontally side by side. The third lower circuit layer 291 includes a third lower dielectric layer 2911 and a third lower pad 2912 arranged sequentially from bottom to top. The fourth lower circuit layer 292 includes a fourth lower dielectric layer 2921 and a fourth lower pad 2922 arranged sequentially from bottom to top.

[0081] The sidewall of the third upper pad 2813 is electrically connected to the sidewall of the third lower pad 2912. The sidewall of the fourth upper pad 2823 is electrically connected to the sidewall of the fourth lower pad 2922.

[0082] Optionally, the semiconductor packaging device 2h may further include a fifth electroless metal layer 30 and a sixth electroless metal layer 31. Wherein:

[0083] A fifth non-electroplated metal layer 30 is disposed on the sidewall of the third upper solder pad 2813 and between the third upper solder pad 2813 and the third lower solder pad 2912. The fifth non-electroplated metal layer 30 is used for electrical connection between the third upper solder pad 2813 and the third lower solder pad 2912. That is, the third upper solder pad 2813 and the third lower solder pad 2912 are electrically connected through the fifth non-electroplated metal layer 30, avoiding the heating operation in the traditional solder reflow process, which is more suitable for temperature-sensitive products and can also avoid problems such as product warpage and cracking.

[0084] A sixth non-electroplated metal layer 31 is disposed on the sidewall of the fourth upper solder pad 2823 and between the fourth upper solder pad 2823 and the fourth lower solder pad 2922. The sixth non-electroplated metal layer 31 is used for electrical connection between the third upper solder pad 2813 and the third lower solder pad 2912. That is, the fourth upper solder pad 2823 and the fourth lower solder pad 2922 are electrically connected through the sixth non-electroplated metal layer 31, avoiding the heating operation in the traditional solder reflow process, which is more suitable for temperature-sensitive products and can also avoid problems such as product warpage and cracking.

[0085] The following is for reference. Figures 3A-3M , Figure 3A-3M This is a longitudinal cross-sectional structural diagram of semiconductor packaging apparatus 3a-3m manufactured at various stages according to an embodiment of the present disclosure. The figures have been simplified for better understanding of the aspects of the present disclosure.

[0086] refer to Figure 3A The system provides a first carrier board 22111 and a second carrier board 22211. The first carrier board 22111 and the second carrier board 22211 can be silicon wafers or substrates.

[0087] refer to Figure 3B A first dielectric layer 22112 and a first seed layer 22113 are sequentially disposed on a first carrier board 22111, and a first dielectric layer 22212 and a first seed layer 22213 are sequentially disposed on a second carrier board 22211.

[0088] The first dielectric layer 22112 and the first dielectric layer 22212 can be set by methods such as printing, lamination, potting, coating, etc.

[0089] The first seed layer 22113 and the first seed layer 22213 can be set by methods such as sputtering, plating, electroless plating, printing, lamination, potting, coating, etc.

[0090] refer to Figure 3C Photoresist 27 was applied to the first seed layer 22113 and the first seed layer 22213 respectively, followed by photolithography.

[0091] refer to Figure 3D The areas after photoresist 27 is etched off on the first seed layer 22113 and the first seed layer 22213, respectively, to form the first lower pad 2212 and the second lower pad 2222.

[0092] refer to Figure 3E The photoresist on the first seed layer 22113 and the first seed layer 22213 is removed, and the corresponding positions of the first seed layer 22113 and the first seed layer 22213 are etched away.

[0093] refer to Figure 3F A second dielectric layer 22114 is provided on the upper surface of the first dielectric layer 22112 and the first lower pad 2212, and a second dielectric layer 22214 is provided on the upper surface of the first dielectric layer 22212 and the second lower pad 2222.

[0094] refer to Figure 3G After applying photoresist 27 to the second dielectric layer 22114, photolithography is performed to etch away a portion of the second dielectric layer 22114 and expose the upper surface of the corresponding first lower pad 2212. After applying photoresist 27 to the second dielectric layer 22214, photolithography is performed to etch away a portion of the second dielectric layer 22214 and expose the upper surface and sidewalls of the second lower pad 2222.

[0095] refer to Figure 3H Remove the photoresist 27 disposed on the second dielectric layer 22114 and the second dielectric layer 22214.

[0096] refer to Figure 3I A second seed layer 22115 is formed on the upper surface of the second dielectric layer 22114 and the exposed upper surface of the first lower pad 2212. The second seed layer 22215 is formed on the upper surface of the second dielectric layer 22214 and the exposed upper and side surfaces of the second lower pad 2222.

[0097] Here, the first substrate 22111, the first dielectric layer 22112, and the second dielectric layer 22114 constitute the first lower dielectric layer 2211.

[0098] The second substrate 22211, the first dielectric layer 22212, and the second dielectric layer 22214 constitute the second lower dielectric layer 2221.

[0099] refer to Figure 3J A first structure consisting of a first lower dielectric layer 2211, a first seed layer 22113, and a first lower pad 2212, and a second structure consisting of a second lower dielectric layer 2221, a first seed layer 22213, and a second lower pad 2222 are placed side by side. Photoresist 27 is applied above the first structure and the second structure, followed by photolithography to expose part of the second seed layer 22115.

[0100] refer to Figure 3K After forming the first lower bonding pad 2213 on the exposed second seed layer 22115, the photoresist 27 is removed and the second seed layer 22115 and the second seed layer 22215 on the surface are etched away, thereby forming the first lower circuit layer 221 and the second lower circuit layer 222.

[0101] For example, sputtering, electroplating, electroless plating, printing, lamination, potting, coating, and other methods can be used.

[0102] It should be noted that the following can be adopted: Figures 3A to 3K The same or similar methods shown form the first upper circuit layer 211 and the second upper circuit layer 212.

[0103] refer to Figure 3L The first upper circuit layer 211 and the second upper circuit layer 212 are flipped and placed above the first lower circuit layer 221 and the second lower circuit layer 222, with a certain amount of space reserved.

[0104] refer to Figure 3M A first non-electroplated metal layer 23 and a second non-electroplated metal layer 24 are formed using a non-electroplated method. The first non-electroplated metal layer 23 is used to electrically connect the first upper solder pad 2113 and the second lower solder pad 2222, and the second non-electroplated metal layer 24 is used to electrically connect the first lower solder pad 2213 and the second upper solder pad 2122.

[0105] This completes the formation of the semiconductor packaging device 2a. The manufacturing method of the semiconductor packaging device provided in this embodiment can achieve the corresponding technical effects of the semiconductor packaging device 2a described above, and will not be repeated here.

[0106] The following is for reference. Figures 4A-4M , Figure 4A-4MThis is a longitudinal cross-sectional structural diagram of semiconductor packaging apparatus 4a-4m manufactured at various stages according to an embodiment of the present disclosure. The figures have been simplified for better understanding of the aspects of the present disclosure.

[0107] refer to Figure 4A The system provides a first carrier board 22111 and a second carrier board 22211. The first carrier board 22111 and the second carrier board 22211 can be silicon wafers or substrates.

[0108] refer to Figure 4B A first dielectric layer 22112 and a first seed layer 22113 are sequentially disposed on a first carrier board 22111, and a first dielectric layer 22212 and a first seed layer 22213 are sequentially disposed on a second carrier board 22211.

[0109] refer to Figure 4C Photoresist 27 is applied to the first seed layer 22113 and the first seed layer 22213 respectively, and then photolithography is performed to expose portions of the first seed layer 22113 and the first seed layer 22213.

[0110] refer to Figure 4D The areas after photoresist 27 is etched off on the first seed layer 22113 and the first seed layer 22213, respectively, to form the first lower pad 2212 and the second lower pad 2222.

[0111] refer to Figure 4E The photoresist on the first seed layer 22113 and the first seed layer 22213 is removed, and the corresponding positions of the first seed layer 22113 and the first seed layer 22213 are etched away.

[0112] refer to Figure 4F A second dielectric layer 22114 is provided on the upper and side surfaces of the first dielectric layer 22112 and the first lower pad 2212. The second dielectric layer 22214 is provided on the upper and side surfaces of the first dielectric layer 22212 and the second lower pad 2222.

[0113] refer to Figure 4G After applying photoresist 27 to the second dielectric layer 22114, photolithography is performed to etch away a portion of the second dielectric layer 22114 and expose the upper surface of the corresponding first lower pad 2212. After applying photoresist 27 to the second dielectric layer 22214, photolithography is performed to etch away a portion of the second dielectric layer 22214 and expose a side surface of the second lower pad 2222 and the portion of the second dielectric layer 22214 corresponding to that side surface.

[0114] refer to Figure 4H Remove the photoresist 27 disposed on the second dielectric layer 22114 and the second dielectric layer 22214.

[0115] refer to Figure 4I A second seed layer 22115 is formed on the upper surface of the second dielectric layer 22114 and the exposed upper surface of the first lower pad 2212. The second seed layer 22215 is formed on the upper surface of the second dielectric layer 22214, the exposed side surface of the second lower pad 2222, and the exposed upper surface of the first dielectric layer 22212.

[0116] Here, the first substrate 22111, the first dielectric layer 22112, and the second dielectric layer 22114 constitute the first lower dielectric layer 2211.

[0117] The second substrate 22211, the first dielectric layer 22212, and the second dielectric layer 22214 constitute the second lower dielectric layer 2221.

[0118] refer to Figure 4J A first structure consisting of a first lower dielectric layer 2211, a first seed layer 22113, and a first lower pad 2212, and a second structure consisting of a second lower dielectric layer 2221, a first seed layer 22213, and a second lower pad 2222 are placed side by side. Photoresist 27 is applied above the first structure and the second structure, followed by photolithography to expose part of the second seed layer 22115.

[0119] refer to Figure 4K After forming the first lower bonding pad 2213 on the exposed second seed layer 22115, the photoresist 27 is removed and the second seed layer 22115 and the second seed layer 22215 on the surface are etched away, thereby forming the first lower circuit layer 221 and the second lower circuit layer 222.

[0120] For example, sputtering, electroplating, electroless plating, printing, lamination, potting, coating, and other methods can be used.

[0121] It should be noted that the following can be adopted: Figures 4A to 4K The same or similar methods shown form the first upper circuit layer 211 and the second upper circuit layer 212.

[0122] refer to Figure 4L The first upper circuit layer 211 and the second upper circuit layer 212 are flipped and placed above the first lower circuit layer 221 and the second lower circuit layer 222. The sidewall of the first upper pad 2113 is close to the sidewall of the second upper pad 2122 with a certain space reserved, and the sidewall of the first upper pad 2113 is close to the sidewall of the second lower pad 2222 with a certain space reserved.

[0123] refer to Figure 4MA third electroless metal layer 25 and a fourth electroless metal layer 26 are formed using an electroless plating method. The third electroless metal layer 25 is used to electrically connect the side surface of the first upper pad 2113 and the side surface of the second lower pad 2222. The fourth electroless metal layer 26 is used to electrically connect the side surface of the first lower pad 2213 and the side surface of the second upper pad 2122.

[0124] This completes the formation of the semiconductor packaging device 2e. The manufacturing method of the semiconductor packaging device provided in this embodiment can achieve the corresponding technical effects of the semiconductor packaging device 2e described above, and will not be repeated here.

[0125] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: The first upper package structure includes a first upper circuit layer and a second upper circuit layer, which are arranged horizontally side by side. The first upper circuit layer includes a first upper dielectric layer, a first upper pad and a first upper solder pad arranged from top to bottom. The second upper circuit layer includes a second upper dielectric layer and a second upper pad arranged from top to bottom. The first lower package structure includes a first lower circuit layer and a second lower circuit layer, which are arranged horizontally side by side. The first lower circuit layer includes a first lower dielectric layer, a first lower pad and a first lower solder pad arranged from bottom to top. The second lower circuit layer includes a second lower dielectric layer and a second lower pad arranged from bottom to top. The first upper solder pad is electrically connected to the second lower solder pad. The first upper solder pad is located on the side of the second lower solder pad. The first upper solder pad and the second lower solder pad are horizontally arranged and electrically connected through the side. The first lower solder pad is electrically connected to the second upper solder pad. The first lower solder pad is located on the side of the second upper solder pad. The first lower solder pad and the second upper solder pad are horizontally arranged and electrically connected through the side.

2. The semiconductor package device of claim 1, wherein, The semiconductor packaging apparatus further includes: A third non-electroplated metal layer is disposed on the sidewall and lower surface of the first upper solder pad; A fourth non-electroplated metal layer is disposed on the sidewall and upper surface of the first lower solder pad.

3. The semiconductor packaging apparatus according to claim 2, wherein, The third non-electroplated metal layer contacts a portion of the upper surface of the second lower pad.

4. The semiconductor packaging apparatus according to claim 3, wherein, The second lower dielectric layer extends to the upper surface of the second lower pad and to the sidewall of the second lower pad that does not contact the third unplated metal layer.

5. The semiconductor packaging apparatus according to claim 4, wherein, The third non-electroplated metal layer extends to the sidewall of the second lower dielectric layer located on the upper surface portion of the second lower pad.

6. The semiconductor packaging apparatus according to claim 5, wherein, The third non-electroplated metal layer extends to the upper surface of the second lower dielectric layer located on the upper surface portion of the second lower pad.

7. A semiconductor packaging apparatus, comprising: The second upper package structure includes a third upper circuit layer and a fourth upper circuit layer, which are arranged horizontally side by side. The third upper circuit layer includes a third upper dielectric layer, a third upper pad and a third upper solder pad arranged from top to bottom. The fourth upper circuit layer includes a fourth upper dielectric layer, a fourth upper pad and a fourth upper solder pad arranged from top to bottom. The second lower package structure includes a third lower circuit layer and a fourth lower circuit layer, which are arranged horizontally side by side. The third lower circuit layer includes a third lower dielectric layer and a third lower pad arranged from bottom to top, and the fourth lower circuit layer includes a fourth lower dielectric layer and a fourth lower pad arranged from bottom to top. The sidewall of the third upper pad is electrically connected to the sidewall of the third lower pad, and the sidewall of the fourth upper pad is electrically connected to the sidewall of the fourth lower pad.

8. A method for manufacturing a semiconductor packaging device, comprising: A first upper package structure and a first lower package structure are provided. The first upper package structure includes a first upper circuit layer and a second upper circuit layer, which are arranged horizontally side by side. The first upper circuit layer includes a first upper dielectric layer, a first upper pad, and a first upper solder pad arranged from top to bottom. The second upper circuit layer includes a second upper dielectric layer and a second upper pad arranged from top to bottom. The first lower package structure includes a first lower circuit layer and a second lower circuit layer, which are arranged horizontally side by side. The first lower circuit layer includes a first lower dielectric layer, a first lower pad, and a first lower solder pad arranged from bottom to top. The second lower circuit layer includes a second lower dielectric layer and a second lower pad arranged from bottom to top. The first upper package structure is placed above the first lower package structure, the first upper pad is located on the side of the second lower pad, and the first lower pad is located on the side of the second upper pad. The first upper solder pad is electrically connected to the second lower solder pad by a non-electroplated method, wherein the first upper solder pad and the second lower solder pad are horizontally arranged and electrically connected by side; and the first lower solder pad is electrically connected to the second upper solder pad, wherein the first lower solder pad and the second upper solder pad are horizontally arranged and electrically connected by side.

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