IGBT with low conduction voltage and high anti-latch-up capability and preparation method thereof

Abstract

The application provides an IGBT with low conduction voltage and high anti-latch-up capability and a preparation method thereof. A separate groove is arranged between the active region trench gates. The groove can allow the carrier storage layer to have higher doping without obvious changes in the breakdown characteristics, reliability and turn-off loss, further reduces the conduction voltage, and realizes the compromise and improvement of the conduction voltage and turn-off loss. The groove helps to push the depletion region and potential into a deeper substrate, away from the bottom end of the groove, reduces the electric field intensity at the bottom end of the groove, improves the breakdown characteristics, and reduces the influence of reliability associated with the high electric field at the bottom of the groove, such as thermal electron carrier degradation or time-dependent dielectric breakdown. A shallow groove P+ emission region is arranged in the middle of the separate groove, the anti-latch-up capability is improved, and the safe working area of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and relates to an IGBT with low on-state voltage and high latch-up resistance and its fabrication method. Background Technology

[0002] Due to their low on-state voltage and simple drive circuitry, Insulated Gate Bipolar Transistors (IGBTs) are increasingly used in various high-voltage switching devices, such as motor control, inverters, and switch-mode power supplies. Trench gate IGBTs, with their higher channel density, absence of parasitic JFET regions, and stronger carrier injection enhancement (IE) effect, represent the trend in active region development. The carrier injection enhancement (IE) effect can reduce the on-state voltage with minimal impact on turn-off losses, making it a key factor in improving the trade-off characteristics between IGBT turn-off losses and on-state voltage.

[0003] Figure 1 This is an existing trench gate IGBT structure, including a collector P+ region 1, an N-field cutoff region 2, and an N-drift region 3. In this structure, there are two solutions to improve the carrier injection enhancement effect (IE). One is to reduce the width L of the MESA (mesa between the two trench gates) to hinder the collection of holes by the emitter region 10, locally increasing the electron flow density and thus improving the carrier injection enhancement (IE) effect. However, limited by the lithography linewidth, the MESA region must have sufficient width to ensure good ohmic contact between the emitter region N+6 and the P+ region 7. Poor ohmic contact leads to device performance degradation, such as increased contact resistance, reduced latch-up current, and instability in threshold voltage and saturation current. Therefore, this approach, due to process limitations, restricts the increase of N-well 4 doping concentration, which is not conducive to further improvement in the trade-off between turn-off loss and turn-on voltage. Another solution to improve the carrier injection enhancement (IE) effect is to place a carrier storage layer N-well 4 below the P-well region 5. The doping concentration of N-well 4 should be as high as possible. However, as the doping concentration of N-well 4 increases, the electric field strength at the trench gate corner increases, which can easily lead to dynamic avalanche and thus reduce the device breakdown voltage. To prevent the reduction in breakdown voltage caused by the increase in the doping concentration of N-well 4, the MESA width L must be reduced accordingly.

[0004] Figure 2 This is another existing trench gate IGBT structure, placing the emitter region N+6 and the P+ region 7 on the surface of the P-well 5. This helps to form a good ohmic contact with a narrow MESA width L, but further reduction of the MESA width is still needed. Furthermore, with... Figure 1 In comparison, Figure 2In the diagram, the emitter P+ contact 7 is located on the surface but not below the emitter region N+6. This allows more hole current to flow below the emitter region N+6, increasing the risk of latch-up and reducing the device's latch-up resistance. In the diagram, Pbody represents the P-well, and CSL represents the carrier storage layer.

[0005] One approach to addressing these issues is to employ specific process control at the bottom of the trench gate to symmetrically expand the trench, forming a locally narrow MESA structure. This helps to increase the N-well concentration at that location, resulting in a stronger carrier injection enhancement (IE) effect. However, this method requires specialized processing techniques, making process control difficult. Another approach is to incorporate a P-ring at the bottom of the trench in the trench-gate IGBT. This P-ring compensates for the increased electric field caused by the increased N-well concentration by locally reducing the electric field effect. Therefore, at the same breakdown voltage, a higher N-well injection concentration can be achieved, enhancing the carrier injection enhancement (IE) effect. However, ensuring a localized reduction in the electric field at a specific location requires process optimization, making process control challenging.

[0006] Another solution to the above problem is as follows: Figure 3 As shown, the IGBT has one or more segmented trenches 30 in the MESA region, each segmented trench 30 comprising a gate oxide layer 31 and polysilicon 32, arranged between island-shaped P-wells 5. Compared to previous designs, this design may reduce Miller capacitance and improve carrier injection enhancement (IE) effects; however, since there are no P-wells 5 at the segmented trenches, the distance between the trenches must be very close to achieve high breakdown voltage at high N-well concentrations, which is still limited by the lithography linewidth.

[0007] The third solution to the above problem is as follows: Figure 4 As shown, the IGBT has a recessed emitter trench 60 between the two active trenches 20. The structure of the recessed emitter trench 60 is similar to... Figure 3 The segmented trench structure is shown. The emitter trench 60 has 3D features, including an "S" shape and segmentation in the extension direction of the active trench 20. In practical manufacturing, the recessed emitter trench 60 can achieve small trench spacing without being limited by the lithography linewidth. This IGBT scheme can achieve high breakdown voltage at high N-well concentrations, but this design requires a special process platform, making its implementation difficult. Summary of the Invention

[0008] In order to overcome the above-mentioned defects of the prior art, the purpose of this invention is to propose an IGBT with low on-voltage and high latch-up resistance.

[0009] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0010] An IGBT with low on-voltage and high latch-up resistance includes a collector electrode, an emitter electrode, and a gate electrode; its improvement lies in that...

[0011] The IGBT further includes: a transparent collector region 1, a drift region 3, a carrier storage layer 4, and a channel body region P-well 5; wherein the transparent collector region 1 is connected to the collector electrode; the drift region 3 is located above the transparent collector region 1; the carrier storage layer 4 is formed above the drift region 3 and has a higher doping concentration than the drift region 3; and the channel body region P-well 5 is located above the carrier storage layer 4.

[0012] The IGBT further includes a trench gate 20 and separate trenches 30; wherein the trench gate 20 extends from the surface in one dimension, passes through the channel body region P-well 5 and enters the drift region 3, and the trench gate 20 is composed of a gate oxide layer 21 and a polysilicon layer 22, the polysilicon layer 22 being connected to the gate electrode; the trench 30 extends from the surface in one dimension, passes through the channel body region P-well 5 and enters the drift region 3, is located between the two trench gates 20 in two dimensions and is segmented in three dimensions, and the trench 30 is composed of a gate oxide layer 31 and a polysilicon layer 32;

[0013] The IGBT also includes a P+ emitter region 7 and an N+ emitter region 6; wherein the P+ emitter region 7 and the N+ emitter region 6 are both located above the channel body region P-well 5, the P+ emitter region 7 is located between separate trenches in the three-dimensional direction, and the N+ emitter region 6 is located between the trench 30 and the two trench gates 20, and the doping concentration of the P+ emitter region and the N+ emitter region is higher than the concentration of the channel body region P-well.

[0014] In the conducting state, the channel body region P-well 5 forms an N-type conductive channel along the trench direction, and the drift region 3 is modulated by the conductance of the P-type carriers injected from the transparent collector 1 and the N-type carriers injected from the carrier storage layer 4.

[0015] Preferably, a dummy region structure is provided between the trench gates 20.

[0016] Preferably, the polysilicon layer of the dummy gate can be connected to the emitter electrode, the gate electrode, or it can be floating. Specifically, any of the following structures can be selected:

[0017] 1) At least one dummy gate 100 is provided between the two trench gates in a two-dimensional direction, and the polysilicon layer of the dummy gate is connected to the emitter electrode;

[0018] 2) At least one dummy gate 100 is provided between the two trench gates in a two-dimensional direction, and the polysilicon layer of the dummy gate is connected to the gate electrode;

[0019] 3) At least one dummy gate 100 is provided in the two-dimensional direction between the two trench gates, and the polysilicon layer of the dummy gate is floating and not connected to any electrode.

[0020] Preferably, the emitter electrode 10 may be disposed only between the trenches 30 separated in the three-dimensional direction.

[0021] Preferably, the one-dimensional direction can be a longitudinal direction perpendicular to the upper surface of the IGBT, and the two-dimensional and three-dimensional directions are perpendicular to the one-dimensional direction, and the two-dimensional and three-dimensional directions are perpendicular to each other.

[0022] Preferably, the bipolar transistor further includes an N-type field cutoff layer 2; the N-type field cutoff layer 2 is located between the transparent collector region 1 and the drift region 3, and the concentration of the N-type field cutoff layer 2 is higher than that of the drift region 3.

[0023] Preferably, the groove 30 may optionally include at least two grooves 30 between two groove grids in a two-dimensional direction.

[0024] Preferably, at least two trenches 30 are used to increase the doping concentration of the carrier storage layer 4.

[0025] Preferably, the polysilicon layer 32 of the trench 30 can adopt any one of the following three connection structures:

[0026] 1) The polysilicon layer 32 of the trench 30 can be connected to the emitter electrode;

[0027] 2) The polysilicon layer 32 of the trench 30 can be connected to the gate electrode;

[0028] 3) The polysilicon layer 32 of the trench 30 can be floated and not connected to any electrode;

[0029] Preferably, the P+ emitter region 7 and N+ emitter region 6 are connected to the emitter electrode only in the region between the plurality of trench regions 30.

[0030] Preferably, the distance between the trench 30 and the trench gate 20 is less than 2 micrometers, and the doping concentration of the carrier storage layer 4 is higher than 1E16cm. -3 .

[0031] Preferably, the distance between the trenches 30 is less than 2 micrometers, and the doping concentration of the carrier storage layer 4 is higher than 1E16cm. -3 .

[0032] Preferably, the transparent current collector region 1 includes at least one N-type region (N+ region) connected to the current collector electrode, forming a reverse-conducting IGBT.

[0033] On the other hand, the present invention also proposes a method for fabricating an IGBT with low on-state voltage and high latch-up resistance, applicable to any of the above-mentioned IGBTs without a dummy gate. The improvement lies in that the method includes the following steps:

[0034] A carrier storage layer 4, a channel body region P-well 5, and an N+ emitter region 6 are sequentially formed on the front side of a silicon substrate.

[0035] Trench gate 20 and trench 30 are formed by trench etching on the front side of the silicon substrate;

[0036] The gate oxide layer 21 of the trench gate and the gate oxide layer 31 of the trench are formed simultaneously on the front side of the silicon substrate;

[0037] Heavy doped polysilicon filling trenches are deposited on the front side of a silicon substrate and then etched back to form a polysilicon layer 22 for trench gates and a polysilicon layer 32 for trenches.

[0038] A P+ emitter region 7 is formed by etching back the front side of the silicon substrate and implanting P-type elements;

[0039] Emitter and gate electrodes are formed on the front side of a silicon substrate by metal deposition and etching.

[0040] P-type ions were implanted on the back side of a silicon substrate and then annealed to form a transparent current collector region 1;

[0041] Metal is deposited on the back side of a silicon substrate to form a collector electrode.

[0042] Furthermore, this invention also proposes a method for fabricating an IGBT with low on-state voltage and high latch-up resistance, applicable to any of the above-mentioned IGBT structures with a dummy region 100 between the trench gates. The improvement lies in that the method includes the following steps:

[0043] A carrier storage layer 4, a channel body region P-well 5, and an N+ emitter region 6 are sequentially formed on the front side of a silicon substrate.

[0044] Trench gate 20, trench 30 and dummy gate 50 are formed by trench etching on the front side of the silicon substrate.

[0045] A gate oxide layer 21 for trench gate 20, a gate oxide layer 31 for trench 30, and a gate oxide layer for dummy gate 50 are formed on the front side of a silicon substrate.

[0046] Heavy doped polysilicon filling trenches are deposited on the front side of a silicon substrate and then etched back to form a polysilicon layer 22 of trench gate 20, a polysilicon layer 32 of trench 30, and a polysilicon layer of dummy gate 50.

[0047] A P+ emitter region 7 is formed by etching back the front side of the silicon substrate and implanting P-type elements;

[0048] Emitter and gate electrodes are formed on the front side of a silicon substrate by metal deposition and etching.

[0049] P-type ions were implanted on the back side of a silicon substrate and then annealed to form a transparent current collector region 1;

[0050] Metal is deposited on the back side of a silicon substrate to form a collector electrode.

[0051] Preferably, before the carrier storage layer 4, the channel body region P-well 5, and the N+ emitter region 6 are sequentially formed on the front side of the silicon substrate, the method further includes:

[0052] N-type ion implantation and push-junction are performed on the back side of the silicon substrate to form an N-type field cutoff layer 2.

[0053] Preferably, the concentration of the N-type field cutoff layer 2 is higher than the concentration of the drift region 3.

[0054] Preferably, the step of sequentially forming a carrier storage layer 4, a channel body region P-well 5, and an N+ emitter region 6 on the front side of the silicon substrate includes:

[0055] N-type ion implantation and push-junction are performed on the front side of the silicon substrate to form a carrier storage layer 4, wherein the concentration of the carrier storage layer 4 is higher than that of the drift region 3.

[0056] P-type ion implantation and push-junction are performed on the front side of the silicon substrate to form a channel body region P-well 5;

[0057] N-type ion implantation is performed on the front side of the silicon substrate to form an N+ emitter region 6.

[0058] Preferably, after etching back and implanting P-type elements to form the P+ emitter region 7 on the front side of the silicon substrate, and before forming the emitter electrode and gate electrode on the front side of the silicon substrate by metal deposition and etching, the method further includes:

[0059] A phosphosilicate glass layer is deposited on the front side of a silicon substrate. The phosphosilicate glass layer is densified under high temperature conditions. Contact holes for the emitter electrode and the gate electrode are formed by etching the phosphosilicate glass layer.

[0060] Preferably, the annealing method used in the process of implanting P-type ions on the back side of the silicon substrate and annealing to form the transparent current collector region 1 is furnace tube annealing or laser annealing.

[0061] Preferably, in the method for fabricating an IGBT without a dummy gate, the simultaneous formation of the gate oxide layer 21 of the trench gate and the gate oxide layer 31 of the trench on the front side of the silicon substrate includes:

[0062] The gate oxide layer 21 of the trench gate and the gate oxide layer 31 of the trench are simultaneously formed on the front side of the silicon substrate using dry oxidation.

[0063] Preferably, in the method for fabricating an IGBT with a dummy gate, the step of forming the gate oxide layer 21 of the trench gate 20, the gate oxide layer 31 of the trench 30, and the gate oxide layer of the dummy gate 50 on the front side of the silicon substrate includes:

[0064] The gate oxide layer 21 of the trench gate 20, the gate oxide layer 31 of the trench 30, and the gate oxide layer of the dummy gate 50 are simultaneously formed on the front side of the silicon substrate using dry oxidation.

[0065] Compared with the closest existing technology, the technical solution provided by the present invention has the following beneficial effects:

[0066] This invention discloses an IGBT with low on-voltage and high latch-up resistance, comprising a collector electrode, an emitter electrode, and a gate electrode. The bipolar transistor further includes: a transparent collector region 1, a drift region 3, a carrier storage layer 4, and a channel body region P-well 5. The transparent collector region 1 is connected to the collector electrode. The drift region 3 is located above the transparent collector region 1. The carrier storage layer 4 is formed above the drift region 3, with a higher doping concentration than the drift region 3. The channel body region P-well 5 is located above the carrier storage layer 4. The bipolar transistor also includes a trench gate 20 and a separate trench 30. The trench gate 20 extends from the surface in one dimension, passes through the channel body region P-well 5, and enters the drift region 3. The trench gate 20 is composed of a gate oxide layer 21 and a polysilicon layer 22, with the polysilicon layer connected to the gate electrode. The trench 30 extends from the surface in one dimension. The bipolar transistor passes through the channel body region P-well 5 and enters the drift region 3. It is located between the two trench gates 20 in the two-dimensional direction and is segmented in the three-dimensional direction. The trench 30 is composed of a gate oxide layer 31 and a polysilicon layer 32, and the polysilicon layer 32 is connected to the gate electrode. The bipolar transistor also includes a P+ emitter region 7 and an N+ emitter region 6. The P+ emitter region and the N+ emitter region are both located above the channel body region P-well 5. The P+ emitter region 7 is located between the separated trenches 30 in the three-dimensional direction, and the N+ emitter region 6 is located between the trench 30 and the two trench gates 20. The doping concentration of the P+ emitter region and the N+ emitter region is higher than that of the channel body region P-well. In the conducting state, the channel body region P-well forms an N-type conductive channel along the trench direction. The drift region is modulated by the conductivity of the P-type carriers injected from the transparent collector and the N-type carriers injected from the carrier storage layer. This invention features separated trenches between the active region trench gate and the active region trench. These trenches allow for higher doping of the carrier storage layer without significant changes in breakdown characteristics, reliability, and turn-off loss, further reducing the turn-on voltage and achieving a trade-off improvement in turn-on voltage and turn-off loss. The trenches also help push the depletion region and potential deeper into the substrate, away from the trench bottom, reducing the electric field strength at the trench bottom and improving breakdown characteristics. This mitigates the reliability impact associated with the high electric field at the trench bottom, such as thermoelectric carrier degradation or time-dependent dielectric breakdown. A shallow recessed P+ emitter region is provided in the middle of the separated trenches, improving latch-up resistance and increasing the device's safe operating area. Therefore, by employing the above-described technical solution of this invention, high latch-up resistance can be achieved while maintaining a low turn-on voltage.

[0067] Since the short-circuit current is too large when a short circuit occurs, it can easily damage the IGBT device. Therefore, this invention can increase the cell width, reduce the chip current density, and reduce the short-circuit current by setting a dummy region structure between the trench gates 20. Attached Figure Description

[0068] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0069] Figure 1 It is a semiconductor device based on existing technology, wherein the P+ emitter region is a shallow groove region, parallel to the trench gate;

[0070] Figure 2 It is a semiconductor device based on existing technology, in which P+ emitter regions and N+ emitter regions are alternately arranged in a two-dimensional direction. This structure can reduce the MESA spacing.

[0071] Figure 3 It is a semiconductor device based on the prior art, in which a segmented trench is located between the trench gates and a channel is formed between the segmented trenches. This structure will allow for higher doping of the carrier storage layer concentration.

[0072] Figure 4 This is a semiconductor device based on existing technology, wherein there is a recessed trench between the trench gates connected to the emitter. This structure allows for higher doping of the carrier storage layer;

[0073] Figure 5 This is a semiconductor device according to the present invention, wherein a separation trench is provided between two trench gates, and a recessed P+ emitter region is provided between the separation trenches. In this structure, the separation trench is connected to the emitter.

[0074] Figure 6 yes Figure 1 The breakdown voltage comparison curves of the prior art and the present invention show that the present invention can increase the doping concentration of the carrier storage layer without reducing the breakdown voltage.

[0075] Figure 7 for Figure 1 The on-state IV curves of existing technologies and the present invention are compared. The present invention has a lower on-state voltage.

[0076] Figure 8 for Figure 1 A trade-off diagram of turn-off loss and turn-on voltage between existing technology and the present invention. The trade-off curve of the present invention is closer to the origin, achieving a better trade-off.

[0077] Figure 9 The semiconductor device according to the present invention includes two trenches disposed between the trench gates, which allows for higher concentration doping of the carrier storage layer;

[0078] Figure 10 It is a semiconductor device according to the present invention, wherein the trench is connected to the gate;

[0079] Figure 11 The semiconductor device according to the present invention has a floating trench;

[0080] Figure 12 According to the present invention, a semiconductor device is provided in which the emitter is disposed between trenches in a three-dimensional direction;

[0081] Figure 13 The semiconductor device according to the present invention includes a dummy gate added between two trench gates to increase the cell size, a portion of the dummy gates being separated, a P+ recessed emitter region being provided between the separated dummy gates, and a P-well connecting the dummy gates to the emitter electrode.

[0082] Figure 14 It is a semiconductor device according to the present invention, wherein it is applied to a reverse-conducting IGBT (RC-IGBT);

[0083] Figure 15 This is a schematic diagram of the fabrication process of an IGBT without adding a dummy gate in an embodiment of the present invention;

[0084] Figure 16 This is a schematic diagram of the fabrication process of an IGBT with an added dummy gate structure in an embodiment of the present invention. Detailed Implementation

[0085] The following detailed description, with reference to the accompanying drawings, describes the IGBT with low on-state voltage and high latch-up resistance, and its fabrication method, as provided in the embodiments of the present invention.

[0086] Example 1

[0087] Embodiment 1 of the present invention provides an IGBT with low on-state voltage and high latch-up resistance, having a high-voltage terminal (collector electrode), a low-voltage terminal (emitter electrode), and a control terminal (gate electrode), the structure of which is as follows. Figure 5 As shown, the IGBT includes: a transparent collector region 1 (Collector P+), an N-type field stop layer 2 (N-type field stop), and a drift region 3 (N-type field stop). The transparent collector region 1 is connected to the collector electrode. The drift region 3 is located above the transparent collector region 1, and the N-type field stop layer 2 is located between the transparent collector region 1 and the drift region 3. The concentration of the N-type field stop layer 2 is higher than that of the drift region 3. The IGBT also includes a carrier storage layer 4 (N-well), a channel body region P-well 5 (P-well), a P+ emitter region 7 (P+), and an N+ emitter region 6 (N+). The carrier storage layer 4 is formed above the drift region 3. The channel body region P-well 5 is located above the carrier storage layer 4. The P+ emitter region 7 and the N+ emitter region 6 are located above the channel body region P-well 5 and are directly connected to the emitter electrode. The doping concentration of the P+ emitter region 7 and the N+ emitter region 6 is higher than that of the channel body region P-well 5.

[0088] The IGBT also includes at least two trench gates 20 and at least two separate trenches 30. At least two trench gates 20 are adjacent to the P+ emitter region 7. The trench gates 20 extend from the surface in a one-dimensional direction, passing through the channel body region P-well 5 and entering the drift region 3. The separate trenches 30 are located between the two trench gates 20 in a two-dimensional direction and extend from the surface in a one-dimensional direction, passing through the channel body region P-well 5 and entering the drift region 3. The trenches 30 are located between the two trench gates 20 in a two-dimensional direction and are segmented in a three-dimensional direction. The presence of the trenches 30 allows for higher doping of the carrier storage layer 4 without significant deterioration of breakdown characteristics, reliability, and turn-off losses, further reducing the turn-on voltage and achieving a trade-off improvement in turn-on voltage and turn-off losses. The trenches 30 help push the depletion region and potential deeper into the substrate, away from the trench bottom, reducing the electric field strength at the trench bottom, improving breakdown characteristics, and reducing the reliability impact associated with the high electric field at the trench bottom, such as thermoelectric carrier degradation or time-dependent dielectric breakdown. The carrier storage layer 4 concentration is at 1E16cm -3 The distance from trench 30 to trench gate is less than 2µm, ideally less than 1µm. N+ emitter region 6 is located between trench 30 and trench gate, and P+ emitter region 7 is located between separate trenches 30. The distance between trenches 30 can be as small as possible while still having enough space to form a good ohmic contact.

[0089] The trench gate 20 consists of a gate oxide layer 21 and a polysilicon layer 22, with the polysilicon layer 22 connected to the gate electrode. All trenches 30 include a gate oxide layer 31 and a polysilicon layer 32, with the gate oxide layer 31 located outside the polysilicon layer 32. The polysilicon layer 32 in the trench 30 can be connected to the gate electrode, the emitter electrode, or it can be floating without being connected to any electrode. In this embodiment, the N+ emitter region 6, the P+ emitter region 7, and the trench 30 are all connected to the emitter electrode 10.

[0090] Furthermore, at least one P+ emission region 7 is placed between the trenches 30 in the three-dimensional direction, and the N+ emission region 6 extends toward the trench gate 20 in the two-dimensional direction.

[0091] In the on-state, the P-well 5 in the channel body region forms an N-type conductive channel along the trench direction. The drift region 3 is modulated by the conductance of the P-type carriers injected from the transparent collector 1 and the N-type carriers injected from the carrier storage layer 4. The spacing between the trench 30 and the trench gate 20 in the two-dimensional direction can be reduced. Together, they extend the depletion region in the one-dimensional direction, away from the bottom of the trench, reducing the electric field strength at the bottom of the trench and increasing the breakdown voltage. At the same time, the depletion region also expands outwards. If the spacing between them is sufficient, the carrier storage layer is completely depleted in the two-dimensional direction, and the breakdown voltage is also increased. That is, at the same breakdown voltage, the carrier storage layer concentration is greater, and the on-state voltage is reduced without significant deterioration in breakdown characteristics, reliability, and turn-off loss. The trench 30 and the trench gate 20 are formed simultaneously without increasing the process cost or difficulty.

[0092] Figure 6 and Figure 7 The following are comparisons of the breakdown voltage and on-state performance of embodiments of the present invention with those of the prior art.

[0093] Figure 8 This invention and Figure 1 The turn-off loss E of the prior art shown OFF With the on-state voltage V ON Comparison of trade-offs. Trench 30 connects to the emitter electrode, reducing the gate-to-drain capacitance by connecting more gate capacitance to the emitter electrode 10. This reduction in Miller capacitance helps reduce switching losses. Experiments of this invention show that embodiments with high carrier storage layer concentration offer a better trade-off. Because the P+ emitter region 7 area can be set larger in this design, it can be configured as a shallow trench, deeper than the N+ emitter contact hole, which improves the device's latch-up resistance, thereby increasing the device's safe operating area (SOA).

[0094] Example 2

[0095] Embodiment 2 of the present invention provides an IGBT with low on-voltage and high latch-up resistance, such as... Figure 9 As shown, the IGBT has two separation trenches 30 between the two trench gates 20. Those skilled in the art will understand that using two separation trenches is merely an example, and any number of separation trenches 30 can be added between the trench gates 20. The advantage of this structure is that it further reduces the spacing between the trenches, allowing for higher carrier storage layer doping while maintaining the same breakdown voltage. The carrier storage layer doping concentration is greater than 1E16cm⁻¹. -3 To ensure breakdown voltage, the distance from trench 30 to the trench gate is less than 2µm, ideally less than 1µm. In the two-dimensional direction, the spacing between the separation trenches is less than 2µm, ideally less than 1µm.

[0096] exist Figure 5 and Figure 9 In this configuration, the polysilicon layer 32 of the trench 30 is connected to the emitter electrode 10. However, the polysilicon layer 32 of the trench 30 may optionally be connected to the gate electrode or left floating. In some applications, this is necessary for controlling switching parameters such as di / dt, dv / dt, and voltage spikes.

[0097] Example 3

[0098] Embodiment 3 of the present invention provides an IGBT with low on-voltage and high latch-up resistance, such as... Figure 10 As shown. The IGBT has a trench structure 30, and the trench 30 is connected to the gate electrode.

[0099] Example 4

[0100] Embodiment 4 of the present invention provides an IGBT with low on-state voltage and high latch-up resistance, such as... Figure 11 As shown. This IGBT has a trench structure 30, and the polysilicon layer 32 of the trench 30 is neither connected to the emitter electrode nor the gate electrode, and is set up in a floating manner.

[0101] Example 5

[0102] Embodiment 5 of the present invention provides an IGBT with low on-state voltage and high latch-up resistance, such as... Figure 12 As shown, the P+ emission region 7 is placed between the trenches 30. This method can further reduce the distance between the trench gates 20, but only if there is enough space between the trenches 30 to form the P+ emission region.

[0103] Example 6

[0104] Embodiment 6 of the present invention provides an IGBT with low on-state voltage and high latch-up resistance, such as... Figure 13 As shown. Although in Figure 5 and Figure 10-12 Mesocellular cells contain grooved regions, and these structures can also be like... Figure 13 The cell width is extended to reduce saturation current and improve short-circuit safe operating area (SCSOA). Figure 13 A dummy gate 100 is added between the trench gates. The dummy gate 100 is formed simultaneously with the trench gate 20 without adding any process steps. The polysilicon layer of the dummy gate 100 is connected to the emitter electrode. Optionally, the polysilicon of the dummy gate 100 can be connected to the gate electrode or floated, without being connected to any electrode. The dummy gates are separated in the third dimension, and a P+ recessed emitter region is formed in the middle of the separated dummy gates. The P+ recessed emitter region is connected to the emitter electrode. Optionally, the P+ recessed emitter region can be floated. Figure 13 In the middle, N-drift represents the drift region, Field stop represents the field stop layer, and Dummyregion100 represents the dummy gate 100.

[0105] Example 7

[0106] Embodiment 7 of the present invention provides an IGBT with low on-state voltage and high latch-up resistance, such as... Figure 14 As shown. A reverse-conducting IGBT adds an additional N+ layer 200 to the IGBT structure. The N+ layer 200 is placed in the transparent collector region 1 and connected to the collector electrode. The N+ layer 200 acts as an anti-parallel cathode diode, conducting current in reverse conduction mode. Figure 14 In the middle, N+ layers 200 are displayed in the third dimension, which is optional; it may be placed in the second dimension. Figure 14 In the middle, CollectorN+ represents the collector N+ layer.

[0107] Example 8

[0108] This invention provides a method for fabricating an IGBT without adding a dummy gate, such as... Figure 15 As shown, the method may include the following steps:

[0109] S81. A carrier storage layer 4, a channel body region P-well 5, and an N+ emitter region 6 are sequentially formed on the front side of a silicon substrate.

[0110] S82. Trench etching is performed on the front side of the silicon substrate to form trench gate 20 and trench 30;

[0111] S83, A gate oxide layer 21 for trench gate 20 and a gate oxide layer 31 for trench 30 are formed on the front side of a silicon substrate;

[0112] S84. Deposit heavily doped polysilicon filling trenches on the front side of the silicon substrate and etch back to form polysilicon layer 22 of trench gate 20 and polysilicon layer 32 of trench 30.

[0113] S85. The front side of the silicon substrate is etched back and P-type elements are implanted to form a P+ emitter region 7.

[0114] S86. Emitter electrode and gate electrode are formed on the front side of silicon substrate by metal deposition and etching;

[0115] S87. P-type ions are implanted on the back side of a silicon substrate and annealed to form a transparent collector region 1;

[0116] S88. Deposit metal on the back side of a silicon substrate to form a collector electrode.

[0117] In an optional embodiment of the present invention, before S81 described above, the following steps may also be included:

[0118] S80. N-type ion implantation and push-junction are performed on the back side of the silicon substrate to form an N-type field cutoff layer 2;

[0119] Furthermore, the concentration of the N-type field cutoff layer 2 can be higher than that of the drift region 3;

[0120] In an optional embodiment of the present invention, the above S81 may include the following steps:

[0121] S811. N-type ion implantation and push junction are performed on the front side of the silicon substrate to form a carrier storage layer 4, wherein the concentration of the carrier storage layer is higher than the concentration of the drift region 3.

[0122] S812. P-type ion implantation and push-junction are performed on the front side of the silicon substrate to form a channel body region P-well 5.

[0123] S813, N-type ion implantation is performed on the front side of the silicon substrate to form an N+ emitter region 6;

[0124] In an optional embodiment of the present invention, the above S83 may include the following steps:

[0125] The gate oxide layer 21 of the trench gate 20 and the gate oxide layer 31 of the trench 30 are formed on the front side of the silicon substrate by dry oxidation.

[0126] An optional embodiment of the present invention may include the following steps after S85 and before S86:

[0127] A phosphosilicate glass layer is deposited on the front side of a silicon substrate, and the phosphosilicate glass layer is densified under high temperature. Contact holes for the emitter electrode and the gate electrode are formed by etching the phosphosilicate glass layer.

[0128] In an optional embodiment of the present invention, the annealing method in S87 above can be furnace tube annealing, laser annealing or other annealing methods.

[0129] Example 9

[0130] This invention provides a method for fabricating an IGBT with an added dummy gate structure, such as... Figure 16 As shown, the method may include the following steps:

[0131] S91. A carrier storage layer 4, a channel body region P-well 5, and an N+ emitter region 6 are sequentially formed on the front side of a silicon substrate.

[0132] S92. Trench etching is performed on the front side of the silicon substrate to form trench gate 20, trench 30 and dummy gate 50.

[0133] S93, A gate oxide layer 21 for trench gate 20, a gate oxide layer 31 for trench 30, and a gate oxide layer for dummy gate 50 are formed on the front side of a silicon substrate.

[0134] S94. Deposit heavily doped polysilicon filling trenches on the front side of the silicon substrate and etch back to form polysilicon layer 22 of trench gate 20, polysilicon layer 32 of trench 30 and polysilicon layer of dummy gate 50.

[0135] S95. The front side of the silicon substrate is etched back and P-type elements are implanted to form a P+ emitter region 7.

[0136] S96. Emitter electrode and gate electrode are formed on the front side of silicon substrate by metal deposition and etching;

[0137] S97. P-type ions are implanted on the back side of the silicon substrate and annealed to form a transparent collector region 1;

[0138] S98. Deposit metal on the back side of the silicon substrate to form a collector electrode.

[0139] In an optional embodiment of the present invention, before S91 described above, the following steps may also be included:

[0140] S90. N-type ion implantation and push-junction are performed on the back side of the silicon substrate to form an N-type field cutoff layer 2;

[0141] Furthermore, the concentration of the N-type field cutoff layer 2 is higher than the concentration of the drift region 3;

[0142] In an optional embodiment of the present invention, the above S91 may include the following steps:

[0143] S911. N-type ion implantation and push-junction are performed on the front side of the silicon substrate to form a carrier storage layer 4, wherein the concentration of the carrier storage layer 4 is higher than the concentration of the drift region 3.

[0144] S912. P-type ion implantation and push-junction are performed on the front side of the silicon substrate to form a channel body region P-well 5.

[0145] S913, N-type ion implantation is performed on the front side of the silicon substrate to form an N+ emitter region 6;

[0146] In an optional embodiment of the present invention, the above S93 may include the following steps:

[0147] The gate oxide layer 21 of the trench gate 20, the gate oxide layer 31 of the trench 30, and the gate oxide layer of the dummy gate 50 are formed on the front side of the silicon substrate by dry oxidation.

[0148] An optional embodiment of the present invention may include the following steps after S95 and before S96:

[0149] A phosphosilicate glass layer is deposited on the front side of a silicon substrate, and the phosphosilicate glass layer is densified under high temperature. Contact holes for the emitter electrode and the gate electrode are formed by etching the phosphosilicate glass layer.

[0150] In an optional embodiment of the present invention, the annealing method in S97 above can be furnace tube annealing, laser annealing or other annealing methods.

[0151] Those skilled in the art will understand that the above embodiments are not exhaustive, and features of one embodiment can be combined with features of other embodiments.

[0152] For ease of description, the various parts of the device described above are divided into modules or units according to their functions. Of course, in implementing this application, the functions of each module or unit can be implemented in one or more software or hardware components.

[0153] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0154] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0155] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0156] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0157] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Those skilled in the art can still make modifications or equivalent substitutions to the specific implementation of the present invention by referring to the above embodiments. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the present invention pending approval.

Claims

1. An IGBT with low on-state voltage and high latch-up resistance, comprising a collector electrode, an emitter electrode, and a gate electrode; characterized in that, The IGBT further includes: a transparent collector region (1), a drift region (3), a carrier storage layer (4), and a channel body region P-well (5); wherein the transparent collector region (1) is connected to the collector electrode; the drift region (3) is located above the transparent collector region (1); the carrier storage layer (4) is formed above the drift region (3) and has a higher doping concentration than the drift region (3); and the channel body region P-well (5) is located above the carrier storage layer (4). The IGBT further includes a trench gate (20) and separate trenches (30); wherein the trench gate (20) extends from the surface in a one-dimensional direction, passes through the channel body region P-well (5) and enters the drift region (3), the trench gate (20) is composed of a gate oxide layer (21) and a polysilicon layer (22), the polysilicon layer (22) is connected to the gate electrode; the trench (30) extends from the surface in a one-dimensional direction, passes through the channel body region P-well (5) and enters the drift region (3), is located between two trench gates (20) in a two-dimensional direction and is segmented in a three-dimensional direction, the trench (30) is composed of a gate oxide layer (31) and a polysilicon layer (32), the polysilicon layer (32) is connected to the gate electrode; The IGBT also includes a P+ emitter region (7) and an N+ emitter region (6); wherein the P+ emitter region (7) and the N+ emitter region (6) are both located above the channel body region P-well (5), the P+ emitter region (7) is located between separate trenches in the three-dimensional direction, and the N+ emitter region (6) is located between the trench (30) and the two trench gates (20), and the doping concentration of the P+ emitter region (7) and the N+ emitter region (6) is higher than that of the channel body region P-well (5); In the conducting state, the channel body region P-well (5) forms an N-type conductive channel along the trench direction, and the drift region (3) is modulated by the P-type carriers injected from the transparent collector (1) and the N-type carriers injected from the carrier storage layer (4).

2. The IGBT according to claim 1, characterized in that, At least one dummy gate (100) is provided between the two trench gates in a two-dimensional direction. The polysilicon layer of the dummy gate (100) is connected to the emitter electrode; At least one dummy gate (100) is provided in a two-dimensional direction between the two trench gates, and the polysilicon layer of the dummy gate (100) is connected to the gate electrode; At least one dummy gate (100) is provided in a two-dimensional direction between the two trench gates, and the polysilicon layer of the dummy gate (100) is floating and not connected to any electrode.

3. The IGBT according to claim 1 or 2, characterized in that, The IGBT also includes an N-type field cutoff layer (2); the N-type field cutoff layer (2) is located between the transparent collector region (1) and the drift region (3), and the concentration of the N-type field cutoff layer (2) is higher than that of the drift region (3).

4. The IGBT according to claim 1 or 2, characterized in that, The groove (30) includes at least two grooves (30) between two groove grids in the two-dimensional direction. At least two trenches (30) are used to increase the doping concentration of the carrier storage layer (4).

5. The IGBT according to claim 1 or 2, characterized in that, The polycrystalline silicon layer (32) of the trench (30) is connected to the emitter electrode; The polysilicon layer (32) of the trench (30) is connected to the gate electrode; The polysilicon layer (32) of the trench (30) is floating and not connected to any electrode; The P+ emitter region (7) and N+ emitter region (6) are connected to the emitter electrode only in the region between the multiple trench regions (30).

6. The IGBT according to claim 1 or 2, characterized in that, The distance between the trench (30) and the trench gate (20) is less than 2 micrometers, and the doping concentration of the carrier storage layer (4) is higher than 1E16cm. -3。 7. The IGBT according to claim 1 or 2, characterized in that, The distance between the trenches (30) is less than 2 micrometers, and the doping concentration of the carrier storage layer (4) is higher than 1E16cm. -3 .

8. The IGBT according to claim 1 or 2, characterized in that, The transparent collector region (1) contains at least one N-type region connected to the collector electrode, forming a reverse-conducting IGBT.

9. A method for manufacturing an IGBT as described in any one of claims 1, 3-8, characterized in that, The method includes: A carrier storage layer (4), a channel body region P-well (5), and an N+ emitter region (6) are sequentially formed on the front side of the silicon substrate. Trench gate (20) and trench (30) are formed by trench etching on the front side of the silicon substrate. A gate oxide layer (21) for a trench gate (20) and a gate oxide layer (31) for a trench (30) are formed on the front side of a silicon substrate. Heavy doped polysilicon filling trenches are deposited on the front side of the silicon substrate and then etched back to form a polysilicon layer (22) for the trench gate (20) and a polysilicon layer (32) for the trench (30). The front side of the silicon substrate is etched back and P-type elements are implanted to form a P+ emitter region (7). Emitter and gate electrodes are formed on the front side of a silicon substrate by metal deposition and etching. P-type ions were implanted on the back side of a silicon substrate and annealed to form a transparent current collector region (1). Metal is deposited on the back side of a silicon substrate to form a collector electrode.

10. A method for manufacturing an IGBT as described in any one of claims 2-8, characterized in that, The method includes: A carrier storage layer (4), a channel body region P-well (5), and an N+ emitter region (6) are sequentially formed on the front side of the silicon substrate. Trench etching is performed on the front side of the silicon substrate to form a trench gate (20), a trench (30), and a dummy gate (50). A gate oxide layer (21) for a trench gate (20), a gate oxide layer (31) for a trench (30), and a gate oxide layer for a dummy gate (50) are formed on the front side of a silicon substrate; Heavy doped polysilicon filling trenches are deposited on the front side of the silicon substrate and then etched back to form a polysilicon layer (22) for trench gate (20), a polysilicon layer (32) for trench (30), and a polysilicon layer for dummy gate (50). The front side of the silicon substrate is etched back and P-type elements are implanted to form a P+ emitter region (7). Emitter and gate electrodes are formed on the front side of a silicon substrate by metal deposition and etching. P-type ions were implanted on the back side of a silicon substrate and annealed to form a transparent current collector region (1). Metal is deposited on the back side of a silicon substrate to form a collector electrode.

11. The method according to claim 9 or 10, characterized in that, Before the carrier storage layer (4), the channel body region P-well (5), and the N+ emitter region (6) are sequentially formed on the front side of the silicon substrate, the method further includes: N-type ion implantation and push-junction are performed on the back side of the silicon substrate to form an N-type field stop layer (2). The concentration of the N-type field cutoff layer (2) is higher than that of the drift region (3).

12. The method according to claim 9 or 10, characterized in that, The formation of a carrier storage layer (4), a channel body region P-well (5), and an N+ emitter region (6) sequentially on the front side of the silicon substrate includes: N-type ion implantation and push junction formation are performed on the front side of the silicon substrate to form a carrier storage layer (4), wherein the concentration of the carrier storage layer (4) is higher than that of the drift region (3); P-type ion implantation and push-junction are performed on the front side of the silicon substrate to form a channel body region P-well (5). N-type ion implantation is performed on the front side of the silicon substrate to form an N+ emitter region (6).

13. The method according to claim 9 or 10, characterized in that, After the back etching and implantation of P-type elements to form a P+ emitter region (7) on the front side of the silicon substrate, and before the formation of the emitter electrode and gate electrode on the front side of the silicon substrate by metal deposition and etching, the method further includes: A phosphosilicate glass layer is deposited on the front side of a silicon substrate, and the phosphosilicate glass layer is densified under high temperature. Contact holes for the emitter electrode and the gate electrode are formed by etching the phosphosilicate glass layer. The annealing method used in the process of implanting P-type ions on the back side of the silicon substrate and annealing to form a transparent current collector region (1) is either furnace tube annealing or laser annealing.

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