Artificial intelligence computing semiconductor device and memory device including the same

Abstract

An artificial intelligence computing semiconductor device is provided. The artificial intelligence computing semiconductor device includes a control unit; and a MAC (Multiply Accumulator) calculator performing a homomorphic encryption calculation through the control unit, wherein the MAC calculator includes an NTT (Number Theoretic Transform) / INTT (Inverse NTT) circuit performing a homomorphic multiplication calculation through a transformation or an inverse transformation of data; a ciphertext multiplier performing a multiplication calculation between ciphertexts; a ciphertext adder / subtracter performing an addition and / or subtraction calculation between the ciphertexts; and a rotator performing a circular shift of a ciphertext slot.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0063361, filed on May 27, 2020, and all benefits derived therefrom, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an artificial intelligence computing semiconductor device and a memory device including the device. Background Technology

[0004] A cloud computing environment can be provided, in which personal information and / or data is stored on servers, and users access the data stored on the servers through user terminals when necessary. When personal information and / or data is stored on servers, the personal information and / or data can be encrypted to protect the personal information, such as by preventing data leakage.

[0005] In such an environment, if encrypted data is stored on a server, searching for data and / or performing tasks (e.g., by computation) can be very inefficient because the required search and / or tasks may need to be performed after decrypting the encrypted data one by one, and this may increase the possibility that decrypted personal information and / or data may be leaked to third parties.

[0006] To address this problem, homomorphic encryption methods have been extensively studied. According to homomorphic encryption, even if computation is performed on the ciphertext itself without decrypting the encrypted information or data, the computation can be performed even without decrypting the ciphertext, since the same computation is performed in the plaintext and subsequently yields the same result as the encrypted result.

[0007] Recently, a homomorphic encryption method has been applied in the field of artificial intelligence. Homomorphic encryption used in artificial intelligence requires high computation speed. Summary of the Invention

[0008] Various aspects of the present invention provide an artificial intelligence computing semiconductor device with improved computing speed.

[0009] Various aspects of the present invention also provide an electrical device and a storage device including an artificial intelligence computing semiconductor device with improved computing speed.

[0010] However, the aspects of the inventive concept are not limited to those set forth herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art upon reference to the following detailed description of the inventive concept.

[0011] According to one aspect of the present invention, an artificial intelligence computing semiconductor device is provided, comprising: a control unit; and a MAC (multiplier and accumulator) configured to perform homomorphic cryptographic computation via the control unit, wherein the MAC is configured to: generate ciphertext by performing homomorphic multiplication computation through data transformation or inverse transformation; perform multiplication computation between ciphertexts; perform addition and / or subtraction computation between ciphertexts; and perform cyclic shifting of slots of ciphertexts.

[0012] According to one aspect of the present invention, an electronic device is provided, comprising: a memory device including a data area configured to store data; a central processing unit (CPU) configured to control the memory device to send and receive data; and an artificial intelligence computing semiconductor device configured to perform artificial intelligence computation by performing homomorphic encryption computation, wherein the artificial intelligence computing semiconductor device includes a multiplier and accumulator calculator (MAC) configured to: perform homomorphic multiplication computation to generate ciphertext by performing a transformation or inverse transformation of the data; perform multiplication computation between ciphertexts; perform addition and / or subtraction computation between ciphertexts; and perform cyclic shifting of slots of the ciphertexts.

[0013] According to one aspect of the present invention, a storage device is provided, comprising: a non-volatile memory device including a data area configured to store data; a controller configured to control the non-volatile memory device to send and receive data; and an artificial intelligence computing semiconductor device configured to perform artificial intelligence computation by performing homomorphic cryptographic computation, wherein the artificial intelligence computing semiconductor device includes a multiplier and accumulator calculator (MAC) configured to: generate ciphertext by performing homomorphic multiplication computation through data transformation or inverse transformation; perform multiplication computation between ciphertexts; perform addition and / or subtraction computation between ciphertexts; and perform cyclic shifting of slots of the ciphertexts. Attached Figure Description

[0014] The above and other aspects and features of the present invention will become more apparent from the detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, in which: Figure 1 This is an example block diagram illustrating an artificial intelligence computing semiconductor device according to some example embodiments.

[0015] Figure 2 This is an example flowchart illustrating the operation of an artificial intelligence computing semiconductor device according to some example embodiments.

[0016] Figure 3This is an example diagram used to illustrate the coding operations of an artificial intelligence computing semiconductor device according to some example embodiments.

[0017] Figure 4 This is an example diagram used to illustrate some calculations of an artificial intelligence computing semiconductor device according to some example embodiments.

[0018] Figure 5 and 6 This is an example block diagram used to illustrate a mobile device including an artificial intelligence computing semiconductor device according to some example embodiments.

[0019] Figures 7 to 10 This is an example block diagram used to illustrate a storage device including an artificial intelligence computing semiconductor device according to some example embodiments. Detailed Implementation

[0020] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to illustrate various aspects. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one”, when preceding a list of elements, modify the entire list of elements without modifying any individual element in the list.

[0021] The terms “in some exemplary embodiments” and “in exemplary embodiments” as used herein do not necessarily refer to the same embodiments.

[0022] Some exemplary embodiments of the present invention can be represented by functional blocks and various processing operations. Some or all of these functional blocks can be implemented as various numbers of hardware and / or software components for performing a specific function. For example, the functional blocks of the present invention can be implemented using one or more microprocessors, or using circuitry for a predetermined function. Furthermore, for example, the functional blocks of the present invention can be implemented using various programming or scripting languages. The functional blocks can be implemented as algorithms executed by one or more processors. Furthermore, the present invention can employ typical techniques for electronic environment setup, signal processing, and / or data processing. Terms such as “mechanism,” “element,” “component,” and “configuration” are used extensively herein and are not limited to mechanical and physical configurations.

[0023] Figure 1 This is an example block diagram illustrating an artificial intelligence computing semiconductor device according to some example embodiments.

[0024] refer to Figure 1According to some embodiments, an artificial intelligence (AI) computing semiconductor device (referred to as an AI calculator in the accompanying drawings of this disclosure) 10 includes a control unit 100, a parameter memory 110, a boot strapping circuit 130, a bus 140, a multiply and accumulator calculator (MAC) 160, and a homomorphic activator 150.

[0025] The control unit 100 can be configured to generally control the operation of the artificial intelligence computing semiconductor device 10 according to some example embodiments. For example, the control unit 100 can interpret commands, etc., provided from a host (not shown), and control the operation of the artificial intelligence computing semiconductor device 10 based on the interpretation results. For example, program commands / addresses / data, etc., from the host can be provided to the control unit 100, and operations can be performed according to the commands of the artificial intelligence computing semiconductor device 10.

[0026] Parameter memory 110 can be configured to store data used by MAC 160. For example, parameter memory 110 can store data used for calculations by MAC 160 and send the data to MAC 160 via bus 140. The data stored in parameter memory 110 can be, for example, weights used in artificial intelligence calculations. The data stored in parameter memory 110 can also be, for example, parameter values ​​required for artificial intelligence calculations or intermediate values ​​of homomorphic calculations. Parameter memory 110 can include, but is not limited to, SRAM (Static Random Access Memory).

[0027] The boot circuit 130 can be configured to remove errors generated after a key switch is performed on data homomorphically encrypted by the MAC 160. For example, the boot circuit 130 can restart the homomorphically encrypted ciphertext when the MAC 160 performs calculations more than a predetermined number of times.

[0028] Homomorphic activator 150 can be configured to be used by MAC 160 to perform nonlinear computations. For example, homomorphic activator 150 can be configured to perform nonlinear computations using data homomorphically encrypted by MAC 160 in artificial intelligence computations. In this case, homomorphic activator 150 can perform nonlinear computations on the homomorphically encrypted data. To perform nonlinear computations on the homomorphically encrypted data, an approximate circuit model can be included in homomorphic activator 150. The approximate circuit model can be, for example, an approximate model that converts the homomorphically encrypted data into a Taylor series. Furthermore, homomorphic activator 150 can support various nonlinear functions, such as Corrected Linear Unit (ReLU), Gaussian Error Linear Unit (GeLU), Sigmoid, Tanh, and Square.

[0029] MAC 160 may include an NTT (numerical theory transform) / INTT (inverse NTT) circuit 161, a ciphertext multiplier 162, a ciphertext adder / subtractor 163, a rotator 164, a relinearizer 165, and a rescaler 166.

[0030] The NTT / INTT circuit 161 can be configured to process multiplication computations of homomorphic ciphertexts based on RLWE (Ring Learning With Errors). For example, the NTT / INTT circuit 161 can be configured to efficiently transform and / or inversely transform data to simplify the computational complexity of polynomial multiplications.

[0031] For example, RLWE-based homomorphic ciphertext can be generated in polynomial form. In this case, when performing multiplication on the polynomial form of the RLWE-based homomorphic ciphertext, convolution can be performed. Multiplication between polynomials can require a large amount of computation. For example, multiplication between n-term polynomials can require n... 2 The computational load.

[0032] However, when performing multiplication computations on RLWE-based homomorphic ciphertexts, the NTT / INTT circuit 161 can be configured to perform an NTT transform on the RLWE-based homomorphic ciphertext, followed by element-wise multiplication. Afterward, the NTT / INTT circuit 161 can perform multiplication between polynomials with low computational cost by performing multiplication on each element of the NTT-transformed RLWE-based homomorphic ciphertext, followed by the INTT transform. For example, by utilizing the NTT / INTT circuit 161, multiplication between n-term polynomials can be performed with only n... The computational complexity of log(n).

[0033] The ciphertext multiplier 162 can be configured to perform multiplication between homomorphic ciphertexts based on RLWE.

[0034] The ciphertext adder / subtractor 163 can be configured to perform addition and / or subtraction between RLWE-based homomorphic ciphertexts.

[0035] According to some embodiments, MAC 160 may also include circuitry for performing XOR, XNOR, AND, and other operations between password text, but is not limited thereto.

[0036] Rotator 164 can be configured to perform cyclic shifts on homomorphic ciphertext. For example, rotator 164 can perform cyclic shifts on slots of the ciphertext. These slots can include a portion of the ciphertext, in which homomorphic encryption is performed, by vectorizing the encapsulated data.

[0037] The relinearizer 165 can be configured to reduce the dimension of the ciphertext increased by the computational complexity of the NTT / INTT circuit 161 and / or the ciphertext multiplier 162. For example, the relinearizer 165 can restore the dimension of the ciphertext increased by the computational complexity of the NTT / INTT circuit 161 and / or the ciphertext multiplier 162 to the dimension before the multiplication between the ciphertexts.

[0038] The rescalar 166 can be configured to reduce the dimension of the multiplied ciphertext after multiplication between ciphertexts performed via NTT / INTT circuit 161 and / or ciphertext multiplier 162. The rescalar 166 can also be configured to perform rounding on the multiplied ciphertext.

[0039] According to some embodiments, the artificial intelligence computing semiconductor device 10 may have an architecture of a deep neural network (DNN) and / or an n-layer neural network. The DNN and / or n-layer neural network may correspond to a convolutional neural network (CNN), a recurrent neural network (RNN), a deep belief network, a restricted Boltzmann machine, etc. For example, the neural network 2 may be implemented as a CNN, an artificial neural network (ANN) system, a deep learning system, a deconvolutional neural network (DCNN), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine (RBM), but is not limited thereto.

[0040] Alternatively and / or additionally, such AI architecture systems may include other forms of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction (such as principal component analysis), and expert systems; and / or combinations thereof, including ensembles such as random forests. In some example embodiments, in addition to multiple convolutional layers, the AI ​​architecture system may also include pooling layers, fully connected layers, etc.

[0041] Control unit 100, boot circuit 130, homomorphic activator 150, and MAC 160 may include and / or be included in, for example, processing circuitry (such as hardware including logic circuitry; hardware / software combinations, such as a processor executing software; or combinations thereof). For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA) and programmable logic unit, a microprocessor, and an application-specific integrated circuit (ASIC). Instructions for the operation of the artificial intelligence computing semiconductor device 10 may be included in a computer-accessible medium (not shown), such as a non-transitory memory system. Generally, the term "non-transitory" as used herein refers to a limitation on the medium itself (e.g., as tangible rather than signaling), rather than a limitation on the persistence of data storage (e.g., RAM and ROM).

[0042] Figure 2 This is an example flowchart illustrating the operation of an artificial intelligence computing semiconductor device according to some example embodiments.

[0043] refer to Figure 1 and 2 First, MAC 160 encodes the first message, which is the target of homomorphic encryption, to generate the first plaintext (S100). For example, at this point, MAC 160 can vectorize and encode the first message. This will be achieved through... Figure 3 As an example, further explanation is needed.

[0044] Figure 3 This is an example diagram used to illustrate the coding operations of an artificial intelligence computing semiconductor device according to some example embodiments.

[0045] refer to Figure 3 It can be used for 4 The first message m, consisting of four matrices, is encoded. At this point, the first plain text c can be generated by encoding the first vector v obtained through vectorizing the first message m. The first vector v can be a slot to be rotated by the rotator 164. The first plain text c can be formed by filling multiple slots.

[0046] Refer again Figure 1 and 2 The first plain text is encrypted to generate a first ciphertext (S200). For example, the first ciphertext can be generated using a public key and / or a private key on the first plain text.

[0047] In the example embodiment, multiple password texts, including a first password text, can be generated in parallel.

[0048] Then, homomorphic computation can be performed on some of the multiple ciphertexts (S300). For example, homomorphic multiplication and / or addition / subtraction can be performed on some of the multiple ciphertexts through NTT / INTT circuit 161, ciphertext multiplier 162 and / or ciphertext adder / subtractor 163.

[0049] Homomorphic computation according to some embodiments is not limited thereto, and XOR, XNOR and / or AND operations can be performed between some of the multiple ciphertexts.

[0050] In the aforementioned homomorphic computation, performing homomorphic multiplication may require a large amount of computation. In other words, as the amount of computation increases, the computation speed of artificial intelligence computing devices may decrease.

[0051] To prevent this problem, rotation is performed via rotator 164 during the homomorphic computation of the semiconductor device 10 for artificial intelligence calculations according to some embodiments. This will be achieved through... Figure 4 This will be illustrated as an example.

[0052] Figure 4 This is an example diagram used to illustrate some calculations of an artificial intelligence computing semiconductor device according to some example embodiments.

[0053] refer to Figure 4 When directly performing a homomorphic multiplication between a first cryptographic text p1 encapsulated in multiple slots and a second cryptographic text p2 encapsulated in multiple slots ( When doing this, a lot of calculations may be required.

[0054] Therefore, in order to reduce the amount of computation, firstly, as Figure 4 As shown on the right, each rotated cipher text is prepared to be obtained by cyclically shifting each of the first cipher text p1 and the second cipher text p2 through the rotator 164. For example, the cipher text obtained by cyclically shifting the first cipher text p1 through the rotator 164 may include 1 st _1 Password text p1_1、1 st _2 Password text p1_2 and 1 st _3. Password text p1_3. Furthermore, the password text obtained by cyclically shifting the second password text p2 using rotator 164 can be 2. nd _1 Password text p2_1、2 nd _2 Password text p2_2 and 2 nd _3 Password text p2_3.

[0055] Then, simple matrix multiplication (⊙) can be performed between the corresponding rotated cipher texts. For example, 1 can be multiplied... st_1 Password text p1_1 and 2 nd _1 Password text p2_1, multiplied by 1 st _2 Password text p1_2 and 2 nd _2 Cipher text p2_2, and multiplied by 1 st _3 Password text p1_3 and 2 nd _3 Password text p2_3.

[0056] Finally, addition (+) can be performed on the values ​​obtained by simple matrix multiplication (⊙) between each rotated ciphertext. For example, addition (+) can be performed by multiplying by 1. st _1 Password text p1_1 and 2 nd The value obtained by multiplying the _1 password text p2_1 by 1 st _2 Password text p1_2 and 2 nd The value obtained from the ciphertext p2_2 and by multiplying by 1 st _3 Password text p1_3 and 2 nd The values ​​obtained from the _3 password text p2_3 are added together.

[0057] As described above, after performing a cyclic shift of each ciphertext by rotator 164, simple matrix multiplication can be performed, and the values ​​after simple matrix multiplication can be added together, thereby reducing the amount of computation required for multiplication between ciphertexts.

[0058] Refer again Figure 1 and 2 The second ciphertext can be obtained through homomorphic computation (S400). Then, the second ciphertext can be decrypted to generate the second plaintext (S500). Finally, the second plaintext can be decoded to generate the second message (S600).

[0059] Figure 5 and 6 This is an example block diagram used to illustrate an electronic device including an artificial intelligence computing semiconductor device according to some example embodiments.

[0060] Electronic devices 20 and / or 22 can be mobile electronic devices such as mobile phones, mobile computers, wearable computers, tablet computers, laptop computers, personal digital assistants, etc.

[0061] refer to Figure 5 According to some embodiments, an electronic device 20 including an artificial intelligence computing semiconductor device 10 includes an APU (application processing unit) 200 and a memory 220.

[0062] APU 200 may include CPU (Central Processing Unit) 210 and artificial intelligence computing semiconductor device 10 according to some embodiments.

[0063] According to some embodiments, CPU 210 can be configured to control APU 200 and / or control artificial intelligence computing semiconductor device 10. For example, CPU 210 can execute software for controlling APU 200 and / or artificial intelligence computing semiconductor device 10, and can perform various data processing and / or calculations. To this end, CPU 210 can load various data from data area 230 into memory 220. Alternatively, CPU 210 can write various data into data area 230 of memory 220.

[0064] Memory 220 may include, but is not limited to, non-volatile memory. A portion of memory 220 may be allocated to data area 230 for storing data sent to and received from CPU 210. When performing homomorphic encryption, since the dimension of the ciphertext becomes relatively larger than the dimension of the plaintext, homomorphic encryption can be performed more efficiently by allocating a dedicated area 240. According to some embodiments, another portion of memory 220 may be allocated to dedicated area 240 for sending data to and receiving data from AI computing semiconductor device 10.

[0065] By dividing the memory 220 into a data region 230 and a dedicated region 240, different encryption methods can be processed in parallel. For example, Rivest–Shamir–Adleman (RSA) encryption and homomorphic encryption can be processed in parallel.

[0066] The dedicated area 240 may include, for example, an area 250 for storing weights required for artificial intelligence calculations and / or an area 260 for storing public keys.

[0067] However, the configuration of the electronic device 20, including the artificial intelligence computing semiconductor device 10 according to some embodiments, is not limited thereto.

[0068] For example, refer to Figure 6 In an electronic device 22 that includes an artificial intelligence computing semiconductor device 10, according to some embodiments, the artificial intelligence computing semiconductor device 10 may be external to the APU 200-2.

[0069] In electronic devices 20 and 22, artificial intelligence computing semiconductor device 10 can be configured to operate with APU 200 and 200-2, and / or independently of APU 200 and 200-2.

[0070] Figures 7 to 10 These are example block diagrams illustrating a storage device including an artificial intelligence computing semiconductor device, based on some example embodiments.

[0071] For reference, according to some embodiments, the storage device including the artificial intelligence computing semiconductor device 10 can be implemented as, but is not limited to, a smart card, an SD (Secure Digital) card, a multimedia card (MMC), an embedded MMC (eMMC), an embedded multi-chip package (eMCP), a PPN (Perfect Page NAND), a universal flash memory (UFS), a USB flash drive, a solid-state drive (SSD), and / or an embedded SSD (eSSD).

[0072] refer to Figure 7 The storage device 30 of the artificial intelligence computing semiconductor device according to some embodiments may include a controller 310 and a non-volatile memory device 320.

[0073] The controller 310 can be configured to interpret commands, etc., from the host 300, and control the operation of the storage device 30, including the artificial intelligence computing semiconductor device 10 according to some embodiments, based on the interpretation results. For example, the controller 310 can be provided with program commands / addresses / data from the host 300, and can store the data in the address of the storage device 30, including the artificial intelligence computing semiconductor device 10. Furthermore, the controller 310 can be configured to receive read commands / addresses, etc., from the host 300, and read and output data stored in the address of the storage device 30, including the artificial intelligence computing semiconductor device 10, from the non-volatile memory device 320.

[0074] According to some example embodiments, controller 310 may include CPU 314, DRAM 318, and artificial intelligence computing semiconductor device 10.

[0075] CPU 314 can be configured to control the operation of artificial intelligence computing semiconductor device 10 by interpreting commands received from host 300, etc.

[0076] According to some embodiments, the artificial intelligence computing semiconductor device 10 can be configured to perform homomorphic encryption operations under the control of the CPU 314. In this case, according to some embodiments, the data used by the artificial intelligence computing semiconductor device 10 can be stored in DRAM 318. For example, DRAM 318 can be configured to store data used for homomorphic encryption calculations of the artificial intelligence computing semiconductor device 10, and to resend the stored data to the artificial intelligence computing semiconductor device 10.

[0077] A portion of the non-volatile memory device (NVM) 320 may be allocated to the data area 330. Another portion of the non-volatile memory device 320 may be allocated to the dedicated area 340.

[0078] Data area 330 and dedicated area 340 can be configured to include the same and / or different forms. For example, data area 330 can be configured to include MLC (Multi-Layer Cell), and dedicated area 340 can be configured to include SLC (Single-Layer Cell). However, this embodiment is not limited to this, and data area 330 can be configured to include TLC (Three-Layer Cell), and dedicated area 340 can be configured to include MLC (Multi-Layer Cell). Alternatively, data area 330 can be configured to include TLC (Three-Layer Cell), and dedicated area 340 can be configured to include SLC (Single-Layer Cell).

[0079] In an example embodiment, data region 330 may be configured to store data not used for calculations in the artificial intelligence computing semiconductor device 10, while dedicated region 340 may be configured to store some data from DRAM 318. The data stored in dedicated region 340 may, for example, be weights used for artificial intelligence calculations.

[0080] refer to Figure 8 In a storage device 32 including an artificial intelligence computing semiconductor device 10 according to some embodiments. In the description Figure 8 When, omission and Figure 7 The description overlaps with the description. In storage device 32, it includes descriptions according to... Figure 7 The storage device 30 of the AI ​​computing semiconductor device 10 in the example embodiment is different. The AI ​​computing semiconductor device 10 may be separate from the controller 310-2 and / or arranged outside the controller 310-2.

[0081] refer to Figure 9 In a storage device 34 including an artificial intelligence computing semiconductor device 10 according to some embodiments. In the description Figure 9 When, omission and Figure 7 and 8 The description overlaps with the description. In storage device 34, it includes descriptions according to... Figure 7 Unlike the memory device 30 of the artificial intelligence computing semiconductor device 10 in the example embodiment, the dedicated region 340-4 may be located inside the controller 310-4. For example, the controller 310 may include a non-transitory memory containing the dedicated region 340. (The last sentence appears to be incomplete and possibly refers to a different implementation.) Figure 7 In some embodiments, the non-volatile memory device 320, which includes a data region 330 and a dedicated region 340, differs from the non-volatile memory device 320-4, which can be allocated to the data region 330.

[0082] refer to Figure 10 In a memory device 36 including an artificial intelligence computing semiconductor device 10, according to some embodiments, and including according to Figure 9Unlike the memory device 34 of the artificial intelligence computing semiconductor device 10 in the example embodiment, the dedicated region 340-6 may be located within the DRAM 318-6. In the memory device 36, compared with the one including according to... Figure 8 The storage device 32 of the artificial intelligence computing semiconductor device 10 in the example embodiment differs from that of the controller 310-6. The artificial intelligence computing semiconductor device 10 may be located inside the controller 310-6. The non-volatile memory device 320-6 may be based on... Figure 9 Some embodiments of the non-volatile memory device 320-4.

[0083] In concluding this detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed herein are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. An artificial intelligence computing semiconductor device, comprising: Control unit; as well as The multiplier and accumulator calculator (MAC) is configured to perform homomorphic encrypted computations via the control unit. The MAC is configured to perform homomorphic multiplication to generate a second ciphertext through the following steps: Multiple rotated cryptographic texts are obtained by cyclically shifting the slots of each cryptographic text in the first cryptographic text, wherein each slot includes a portion of each cryptographic text in the first cryptographic text that has been vectorized by encapsulating data in which homomorphic encryption computation has been performed. Multiplication is performed between the rotated ciphertexts in the plurality of rotated ciphertexts to obtain a plurality of multiplied ciphertexts, wherein at least two of the rotated ciphertexts are multiplied, and the result is... Addition and subtraction calculations are performed among the multiple multiplied cryptographic texts.

2. The artificial intelligence computing semiconductor device according to claim 1, further comprising: The guiding circuit is configured to remove errors from either the first or the second password text.

3. The artificial intelligence computing semiconductor device according to claim 1, further comprising: A homomorphic activator is configured to perform nonlinear calculations on the first ciphertext or the second ciphertext.

4. The artificial intelligence computing semiconductor device according to claim 3, wherein, The homomorphic activator is configured to generate an approximation of the nonlinear calculation by combining the ciphertext calculated by the multiplication and the ciphertext calculated by the addition or subtraction.

5. The artificial intelligence computing semiconductor device according to claim 1, wherein, The MAC is also configured to reduce the size of either the first or the second password text.

6. The artificial intelligence computing semiconductor device according to claim 1, wherein, The MAC is also configured to reduce the dimension of the first or second ciphertext and exchange the relinear key.

7. The artificial intelligence computing semiconductor device according to claim 1, further comprising: The parameter memory is configured to store at least one of the parameter values ​​used for artificial intelligence computation and the intermediate values ​​of the homomorphic encryption computation.

8. The artificial intelligence computing semiconductor device according to claim 7, wherein, The parameter memory is a static random access memory (SRAM).

9. The artificial intelligence computing semiconductor device according to claim 7, wherein, The parameter value is the weight.

10. The artificial intelligence computing semiconductor device according to claim 7, wherein, The parameter values ​​are homomorphically encrypted and stored in the parameter memory.

11. The artificial intelligence computing semiconductor device according to claim 7, wherein, The parameter values ​​are stored as plain text in the parameter memory.

12. An electronic device, comprising: A memory device, including a data area configured to store data; A central processing unit (CPU) is configured to control the memory device to send and receive the data; as well as Artificial intelligence computing semiconductor devices are configured to perform artificial intelligence computations by performing homomorphic cryptographic computations. The artificial intelligence computing semiconductor device includes a multiplier and accumulator calculator (MAC), which is configured to perform homomorphic multiplication calculations to generate a second ciphertext through the following steps: Multiple rotated cryptographic texts are obtained by cyclically shifting the slots of each cryptographic text in the first cryptographic text, wherein each slot includes a portion of each cryptographic text in the first cryptographic text that has been vectorized by encapsulating data in which homomorphic encryption computation has been performed. Multiplication is performed between the rotated ciphertexts in the plurality of rotated ciphertexts to obtain a plurality of multiplied ciphertexts, wherein at least two of the rotated ciphertexts are multiplied, and the result is... Addition and subtraction calculations are performed among the multiple multiplied cryptographic texts.

13. The electronic device according to claim 12, wherein, The memory device includes a dedicated area for artificial intelligence computing, which is configured to store parameter values ​​for performing the homomorphic encryption computing.

14. The electronic device according to claim 13, wherein, The parameter values ​​include weight and public key.

15. The electronic device according to claim 12, wherein, The artificial intelligence computing semiconductor device also includes: The guiding circuit is configured to remove errors from either the first or second password text, and A homomorphic activator is configured to perform nonlinear calculations on the first ciphertext or the second ciphertext.

16. The electronic device according to claim 15, wherein, The MAC is also configured as follows: Reduce the dimension of the first or second ciphertext, and Reduce the dimension of the first or second ciphertext and exchange the relinear keys.

17. A storage device comprising: A non-volatile memory device, including a data area configured to store data; The controller is configured to control the non-volatile memory device to send and receive the data; as well as Artificial intelligence computing semiconductor devices are configured to perform artificial intelligence computations by performing homomorphic cryptographic computations. The artificial intelligence computing semiconductor device includes a multiplier and accumulator calculator (MAC), and... The MAC is configured to perform homomorphic multiplication to generate a second ciphertext through the following steps: Multiple rotated cryptographic texts are obtained by cyclically shifting the slots of each cryptographic text in the first cryptographic text, wherein each slot includes a portion of each cryptographic text in the first cryptographic text vectorized by encapsulating data in which homomorphic encryption computation is performed. Multiplication is performed between the rotated ciphertexts in the plurality of rotated ciphertexts to obtain a plurality of multiplied ciphertexts, wherein at least two of the rotated ciphertexts are multiplied, and the result is... Addition and subtraction calculations are performed among the multiple multiplied cryptographic texts.

18. The storage device according to claim 17, wherein, The non-volatile memory device includes a dedicated region for artificial intelligence computing, which is configured to store parameter values ​​for performing the homomorphic cryptographic computation.

19. The storage device according to claim 18, wherein, The data area is configured to include multi-layer cell (MLC), and The dedicated AI computing area is configured to include a single-layer cell (SLC).

20. The storage device according to claim 17, wherein, The artificial intelligence computing semiconductor device also includes: The guiding circuit is configured to remove errors from either the first or second password text, and A homomorphic activator is configured to perform nonlinear computations on either the first or the second ciphertext, and The MAC is further configured as follows: Reduce the dimension of the first or second ciphertext, and Reduce the dimension of the first or second ciphertext and exchange the relinear keys.

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