Display panel, display device and method of driving display panel

Abstract

Disclosed are a display panel, a display device, and a method of driving the display panel. The display panel includes a plurality of blocks. The block includes a plurality of first gate lines extending in a first direction and a plurality of second gate lines extending in a second direction different from the first direction. In the block, the first gate lines are one-to-one connected to the corresponding second gate lines. The second gate lines provided in a first area of the block are one-to-one connected to odd-numbered first gate lines among the plurality of first gate lines. The second gate lines provided in a second area of the block are one-to-one connected to even-numbered first gate lines among the plurality of first gate lines.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display panel, a display device including the display panel, and a method for driving the display panel using the display device. More specifically, embodiments of the present invention relate to a display panel that reduces bezel width and improves display quality, a display device including the display panel, and a method for driving the display panel using the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes gate lines and data lines. The display panel driver includes a drive controller, a gate driver, and a data driver.

[0003] Typically, the gate driver is located on the side of the display panel, and the gate line extends horizontally within the display panel. The data driver is located at the top or bottom of the display panel, and the data line extends vertically within the display panel.

[0004] The width of the side bezels of the display panel may increase due to the gate driver. Furthermore, the gate driver and data driver are manufactured and bonded separately, which may increase the manufacturing cost of the display device. Summary of the Invention

[0005] Embodiments of the present invention provide a display panel that reduces the bezel width of the display device and reduces the propagation delay of the gate signal in a structure with a reduced bezel width, thereby improving the display quality of the display panel.

[0006] Embodiments of the present invention also provide a display device including a display panel.

[0007] Embodiments of the present invention also provide a method for driving a display panel using a display device.

[0008] In an embodiment of the display panel according to the present invention, the display panel includes a plurality of blocks. Each block includes a plurality of first gate lines extending in a first direction and a plurality of second gate lines extending in a second direction different from the first direction. Within each block, the first gate lines are connected one-to-one to corresponding second gate lines. The block is divided into a first region and a second region. Second gate lines disposed in the first region of the block are connected one-to-one to odd-numbered first gate lines among the plurality of first gate lines. Second gate lines disposed in the second region of the block are connected one-to-one to even-numbered first gate lines among the plurality of first gate lines.

[0009] In an implementation, the block may also include multiple data lines extending in the second direction.

[0010] In this implementation, the first gate line can be disposed on a first layer. The second gate line and the data line can be disposed on a second layer different from the first layer. The first gate line can be connected to the corresponding second gate line through a contact hole.

[0011] In one implementation, three or six data lines may be provided between two adjacent second gate lines.

[0012] In one embodiment, a first virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the first region, and a second virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the second region, can form a V-shape.

[0013] In one implementation, the plurality of first gate lines include a first gate line to a 2Nth first gate line, and the plurality of second gate lines include a first second gate line to a 2Nth second gate line, where N is an integer equal to or greater than 2. In a first region, a first second gate line can be connected to a first first gate line, a second second gate line can be connected to a third first gate line, an (N-1)th second gate line can be connected to a 2N-3th first gate line, and an Nth second gate line can be connected to a 2N-1th first gate line. In a second region, an (N+1)th second gate line can be connected to a 2Nth first gate line, an (N+2)th second gate line can be connected to a 2N-2th first gate line, a 2N-1th second gate line can be connected to a fourth first gate line, and a 2Nth second gate line can be connected to a second first gate line.

[0014] In one embodiment, the first virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the first region, and the second virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the second region, can be parallel to each other.

[0015] In one implementation, the plurality of first gate lines include a first gate line to a 2Nth first gate line, and the plurality of second gate lines include a first second gate line to a 2Nth second gate line, where N is an integer equal to or greater than 2. In a first region, a first second gate line can be connected to a first first gate line, a second second gate line can be connected to a third first gate line, an (N-1)th second gate line can be connected to a 2N-3th first gate line, and an Nth second gate line can be connected to a 2N-1th first gate line. In a second region, an (N+1)th second gate line can be connected to a second first gate line, an (N+2)th second gate line can be connected to a fourth first gate line, a 2N-1th second gate line can be connected to a 2N-2th first gate line, and a 2Nth second gate line can be connected to a 2Nth first gate line.

[0016] In an embodiment of the display panel according to the present invention, the display panel includes a plurality of blocks. Each block includes a plurality of first gate lines extending in a first direction and a plurality of second gate lines extending in a second direction different from the first direction. Within each block, the first gate lines are connected one-to-one to corresponding second gate lines. The blocks are divided into first regions to fourth regions. Second gate lines disposed in the first region of the block are connected one-to-one to the 4X-3th first gate line among the plurality of first gate lines. Second gate lines disposed in the second region of the block are connected one-to-one to the 4X-1th first gate line among the plurality of first gate lines. Second gate lines disposed in the third region of the block are connected one-to-one to the 4X-2th first gate line among the plurality of first gate lines. Second gate lines disposed in the fourth region of the block are connected one-to-one to the 4Xth first gate line among the plurality of first gate lines. X is a natural number.

[0017] In one embodiment, a W-shape can be formed by connecting a first virtual line in a first region to the point where the first gate line and the corresponding second gate line are connected, a second virtual line in a second region to the point where the first gate line and the corresponding second gate line are connected, a third virtual line in a third region to the point where the first gate line and the corresponding second gate line are connected, and a fourth virtual line in a fourth region to the point where the first gate line and the corresponding second gate line are connected.

[0018] In one implementation, the plurality of first gate lines include a first gate line to a 4Nth first gate line, and the plurality of second gate lines include a first second gate line to a 4Nth second gate line, where N is an integer equal to or greater than 2. In a first region, a first second gate line can be connected to a first first gate line, a second second gate line can be connected to a fifth first gate line, an (N-1)th second gate line can be connected to a 4N-7th first gate line, and an Nth second gate line can be connected to a 4N-3th first gate line. In a second region, an (N+1)th second gate line can be connected to a 4N-1th first gate line, an (N+2)th second gate line can be connected to a 4N-5th first gate line, a 2N-1th second gate line can be connected to a seventh first gate line, and a 2Nth second gate line can be connected to a third first gate line. In the third region, the 2N+1th second gate line can be connected to the second first gate line, the 2N+2th second gate line can be connected to the sixth first gate line, the 3N-1th second gate line can be connected to the 4N-6th first gate line, and the 3Nth second gate line can be connected to the 4N-2th first gate line. In the fourth region, the 3N+1th second gate line can be connected to the 4Nth first gate line, the 3N+2th second gate line can be connected to the 4N-4th first gate line, the 4N-1th second gate line can be connected to the eighth first gate line, and the 4Nth second gate line can be connected to the fourth first gate line.

[0019] In an embodiment of a display device according to the present invention, the display device includes a display panel, a gate driver, and a data driver. The display panel is configured to display an image. The gate driver is configured to output a gate signal to the display panel. The data driver is configured to output a data voltage to the display panel. The display panel includes a plurality of blocks. Each block includes a plurality of first gate lines extending in a first direction and a plurality of second gate lines extending in a second direction different from the first direction. In each block, the first gate lines are connected one-to-one to corresponding second gate lines. The blocks are divided into a first region and a second region. Second gate lines disposed in the first region of the block are connected one-to-one to odd-numbered first gate lines among the plurality of first gate lines. Second gate lines disposed in the second region of the block are connected one-to-one to even-numbered first gate lines among the plurality of first gate lines.

[0020] In one implementation, the display panel block may include multiple data lines extending in a second direction.

[0021] In this implementation, the first gate line can be disposed on a first layer. The second gate line and the data line can be disposed on a second layer different from the first layer. The first gate line can be connected to the corresponding second gate line through a contact hole.

[0022] In one embodiment, a first virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the first region, and a second virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the second region, can form a V-shape.

[0023] In one implementation, the plurality of first gate lines include a first gate line to a 2Nth first gate line, and the plurality of second gate lines include a first second gate line to a 2Nth second gate line, where N is an integer equal to or greater than 2. In a first region, a first second gate line can be connected to a first first gate line, a second second gate line can be connected to a third first gate line, an (N-1)th second gate line can be connected to a 2N-3th first gate line, and an Nth second gate line can be connected to a 2N-1th first gate line. In a second region, an (N+1)th second gate line can be connected to a 2Nth first gate line, an (N+2)th second gate line can be connected to a 2N-2th first gate line, a 2N-1th second gate line can be connected to a fourth first gate line, and a 2Nth second gate line can be connected to a second first gate line.

[0024] In one implementation, gate signals can be sequentially applied to the second gate lines, such that odd-numbered first gate lines in the first region can be scanned during the first subframe, and even-numbered first gate lines in the second region can be scanned during the second subframe following the first subframe.

[0025] In one implementation, a gate signal can be alternately applied to a second gate line in a first region and a second gate line in a second region, so that the first gate line in the block can be scanned sequentially.

[0026] In one embodiment, the first virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the first region, and the second virtual line generated by connecting the points where the first gate line and the corresponding second gate line are connected in the second region, can be parallel to each other.

[0027] In one implementation, the plurality of first gate lines include a first gate line to a 2Nth first gate line, and the plurality of second gate lines include a first second gate line to a 2Nth second gate line, where N is an integer equal to or greater than 2. In a first region, a first second gate line can be connected to a first first gate line, a second second gate line can be connected to a third first gate line, an (N-1)th second gate line can be connected to a 2N-3th first gate line, and an Nth second gate line can be connected to a 2N-1th first gate line. In a second region, an (N+1)th second gate line can be connected to a second first gate line, an (N+2)th second gate line can be connected to a fourth first gate line, a 2N-1th second gate line can be connected to a 2N-2th first gate line, and a 2Nth second gate line can be connected to a 2Nth first gate line.

[0028] In one implementation, gate signals can be sequentially applied to the second gate lines, such that odd-numbered first gate lines in the first region can be scanned during the first subframe, and even-numbered first gate lines in the second region can be scanned during the second subframe following the first subframe.

[0029] In one implementation, a gate signal can be alternately applied to a second gate line in a first region and a second gate line in a second region, so that the first gate line in the block can be scanned sequentially.

[0030] In some embodiments, the display device may further include a flexible circuit substrate. The gate driver may include a gate driver chip. The data driver may include a first source driver chip and a second source driver chip. The first source driver chip, the gate driver chip, and the second source driver chip may be sequentially disposed on the flexible circuit substrate.

[0031] In an embodiment of the method for driving a display panel according to the present invention, the display panel includes a plurality of blocks. Each block includes a plurality of first gate lines extending in a first direction, a plurality of second gate lines extending in a second direction different from the first direction, and a plurality of data lines extending in the second direction. The method includes: applying gate signals to second gate lines disposed in a first region of a block of the display panel and to second gate lines disposed in a second region of a block of the display panel; and applying data voltages to the data lines of the display panel. Within each block, the first gate lines are connected one-to-one to corresponding second gate lines. The second gate lines disposed in the first region of the block are connected one-to-one to odd-numbered first gate lines among the plurality of first gate lines. The second gate lines disposed in the second region of the block are connected one-to-one to even-numbered first gate lines among the plurality of first gate lines.

[0032] According to the display panel, display device, and method of driving the display panel, the gate driver and data driver are disposed on one side of the display panel, which makes it possible to reduce the width of the side bezel of the display panel.

[0033] Furthermore, in the first region of the display panel block, the first gate line and the corresponding second gate line are connected one-to-one, and in the second region of the block, the first gate line and the corresponding second gate line are connected one-to-one, thereby reducing the propagation delay of the gate signal at the bottom side of the display panel. Therefore, the display quality of the display panel can be improved. Attached Figure Description

[0034] The above and other features and advantages of the present invention will become more apparent from the detailed description of embodiments of the present invention with reference to the accompanying drawings, in which:

[0035] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0036] Figure 2 It is shown Figure 1 A plan view of the display device;

[0037] Figure 3 It is shown Figure 1 A plan view of the flexible circuit board;

[0038] Figure 4A It is shown Figure 1 A plan view illustrating an example of the structure of the gate lines and data lines of a display panel;

[0039] Figure 4B It is shown Figure 1 A plan view illustrating an example of the structure of the gate lines and data lines of a display panel;

[0040] Figure 4C It is shown Figure 4B A plan view of the first layer of the structure of the gate lines and data lines of the display panel;

[0041] Figure 4D It is shown Figure 4B A plan view of the second layer of the structure of the gate lines and data lines of the display panel;

[0042] Figure 5 This is a schematic diagram showing the connection between the first gate line and the second gate line of a display panel according to a comparative embodiment.

[0043] Figure 6 It is shown Figure 5 A detailed diagram of the connection between the first gate line and the second gate line of the display panel;

[0044] Figure 7 It is shown Figure 1 A schematic diagram of the connection between the first gate line and the second gate line of the display panel;

[0045] Figure 8 It is shown Figure 7 A detailed diagram of the connection between the first gate line and the second gate line;

[0046] Figure 9 It shows that it is applied to Figure 8 A timing diagram of an example of the gate signal of the second gate line;

[0047] Figure 10 It shows that it is applied to Figure 8 Timing diagram of another example of the gate signal of the second gate line;

[0048] Figure 11 This is a schematic diagram illustrating the connection between the first gate line and the second gate line of a display panel according to an embodiment of the present invention.

[0049] Figure 12 It is shown Figure 11 A detailed diagram of the connection between the first gate line and the second gate line;

[0050] Figure 13 It shows that it is applied to Figure 12 A timing diagram of an example of the gate signal of the second gate line;

[0051] Figure 14 It shows that it is applied to Figure 12 A timing diagram of an example of the gate signal of the second gate line;

[0052] Figure 15 This is a schematic diagram illustrating the connection between the first gate line and the second gate line of a display panel according to an embodiment of the present invention; and

[0053] Figure 16 It is shown Figure 15 A detailed diagram of the connection between the first gate line and the second gate line. Detailed Implementation

[0054] It should be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings herein, “first element,” “first component,” “first region,” “first layer,” or “first portion” discussed below may be referred to as a second element, second component, second region, second layer, or second portion. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms "comprises" and / or "comprising" or "includes" and / or "including" specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof. The inventive concept will be explained in detail below with reference to the accompanying drawings.

[0055] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0056] refer to Figure 1 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0057] In some implementations, the drive controller 200 and the data driver 500 may be integrally formed. For example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 may be integrally formed. A drive module that includes at least the integrally formed drive controller 200 and data driver 500 may be referred to as a timing controller embedded data driver (“TED”).

[0058] The display panel 100 has a display area in which an image is displayed and a peripheral area adjacent to the display area.

[0059] The display panel 100 includes multiple gate lines HGL and VGL, multiple data lines DL, and multiple pixels P, which are electrically connected to the gate lines HGL and VGL and the data lines DL. A first gate line HGL may extend in a first direction D1, a second gate line VGL may extend in a second direction D2 intersecting the first direction D1, and the data lines DL may extend in the second direction D2. The first gate line HGL and the second gate line VGL may be connected to each other. For example, the first gate line HGL and the second gate line VGL may be connected in a one-to-one manner. For example, the number of first gate lines HGL may be substantially the same as the number of second gate lines VGL. The first gate line HGL may be referred to as a horizontal gate line. The second gate line VGL may be referred to as a vertical gate line.

[0060] The drive controller 200 receives input image data IMG and input control signal CONT from an external device. The input image data IMG may include red, green, and blue image data. The input image data IMG may also include white, magenta, yellow, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0061] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0062] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may also include a vertical start signal and a gate clock signal.

[0063] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0064] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0065] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0066] Gate driver 300 generates gate signals to drive gate lines HGL and VGL in response to a first control signal CONT1 received from drive controller 200. Gate driver 300 outputs the gate signals to gate lines HGL and VGL. For example, gate driver 300 can sequentially output the gate signals to gate lines HGL and VGL. Figure 1 As shown, the gate driver 300 can be located on the same side of the display panel 100 as the data driver 500.

[0067] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0068] In an implementation, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0069] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and receives a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage of analog type. The data driver 500 outputs this data voltage to the data line DL.

[0070] Figure 2 It is shown Figure 1 A plan view of the display device. Figure 3 It is shown Figure 1 A plan view of the flexible circuit board.

[0071] refer to Figures 1 to 3 The display device includes a display panel 100 and a display panel driver. The display panel driver may include a printed circuit board (“PCB”) 610 and a plurality of flexible circuit boards (flexible printed circuit boards, “FPC”) 620.

[0072] A first side of the flexible circuit board 620 is connected to the display panel 100, and a second side of the flexible circuit board 620 is connected to the printed circuit board 610. The second side of the flexible circuit board 620 is opposite to the first side.

[0073] The flexible circuit board 620 includes a flexible material. The flexible circuit board 620 can cover the side surface of the display panel 100. Therefore, the printed circuit board 610 can be bent toward the rear surface of the display panel 100.

[0074] In some embodiments, for example, the flexible circuit board 620 may be disposed on one side of the display panel 100. For example, the flexible circuit board 620 may be disposed on the upper side of the display panel 100.

[0075] A flexible circuit board 620 includes both a gate driver chip and a source driver chip. Therefore, the gate driver chip and the source driver chip are disposed on the same side relative to the display panel 100.

[0076] The printed circuit board 610 may include a drive controller 200.

[0077] like Figure 3 As shown, the gate driver 300 may include a gate driver chip GIC. The data driver 500 may include a first source driver chip SIC1 and a second source driver chip SIC2.

[0078] In one implementation, for example, a first source driver chip SIC1, a gate driver chip GIC, and a second source driver chip SIC2 can be sequentially disposed in the flexible circuit substrate 620. The lines outputting the data voltage generated by the first source driver chip SIC1 and the lines outputting the gate signal generated by the gate driver chip GIC can intersect in the flexible circuit substrate 620.

[0079] In this implementation, for example, the first, second, and third output signals of the first source driver chip SIC1 can be output through the first pad P1, second pad P2, and third pad P3 of the flexible circuit board 620, respectively. The first output signal of the gate driver chip GIC can be output through the fourth pad P4 of the flexible circuit board 620. The fourth, fifth, and sixth output signals of the first source driver chip SIC1 can be output through the fifth pad P5, sixth pad P6, and seventh pad P7 of the flexible circuit board 620, respectively. The second output signal of the gate driver chip GIC can be output through the eighth pad P8.

[0080] Figure 4A It is shown Figure 1 A plan view illustrating an example of the structure of the gate lines and data lines of a display panel.

[0081] refer to Figures 1 to 4A The first gate line HGL can be disposed on the first layer, and the second gate line VGL and data lines DL1, DL2 and DL3 can be disposed on a second layer different from the first layer.

[0082] The first gate line HGL can be connected to the second gate line VGL through the contact hole CNT.

[0083] In one implementation, for example, three data lines DL1, DL2 and DL3 are disposed between two adjacent second gate lines VGL.

[0084] Figure 4B It is shown Figure 1 A plan view illustrating an example of the structure of the gate lines and data lines of a display panel. Figure 4C It is shown Figure 4B A plan view of the first layer of the structure of the gate lines and data lines of the display panel. Figure 4D It is shown Figure 4B A plan view of the second layer of the structure of the gate lines and data lines of the display panel.

[0085] refer to Figures 1 to 3 as well as Figures 4B to 4D The first layer can be a gate metal layer in which the gate electrode of pixel P is disposed, and the second layer can be a source-drain metal layer in which the source-drain electrode of pixel P is disposed.

[0086] The first layer may include first gate lines HGL1 and HGL2, memory lines SL1 and SL2, a gate electrode GE, and second gate sub-electrodes VGS11 and VGS12. The first gate lines HGL1 and HGL2 may extend in a first direction D1. The memory lines SL1 and SL2 may include extension portions extending in the first direction D1 and protrusion portions protruding from the extension portions in a second direction D2.

[0087] The second layer may include second gate lines VGL1 and VGL2, data lines DL1 to DL6, a source electrode SE, and a drain electrode DE. The second gate lines VGL1 and VGL2 extend in the second direction D2. The data lines DL1 to DL6 extend in the second direction D2.

[0088] The first gate line HGL1 can be connected to the first second gate line VGL1 through the first contact hole CNT11 and the second contact hole CNT12. For example, the first gate line HGL1 may include two branch portions. The first branch portion of the first gate line HGL1 can be connected to the first second gate line VGL1 through the first contact hole CNT11. The second branch portion of the first gate line HGL1 can be connected to the first second gate line VGL1 through the second contact hole CNT12.

[0089] In the same manner, the second first gate line HGL2 can be connected to the second second gate line VGL2 through the third contact hole CNT21 and the fourth contact hole CNT22.

[0090] The first second gate line VGL1 can be connected to the second gate sub-electrodes VGS11 and VGS12 disposed on the first layer through sub-contact holes CNTS1 and CNTS2, respectively. The connection of the first second gate line VGL1 to the second gate sub-electrodes VGS11 and VGS12 through sub-contact holes CNTS1 and CNTS2 reduces the wiring resistance of the first second gate line VGL1.

[0091] exist Figure 4B In this embodiment, the six data lines DL1 to DL6 can be arranged between two adjacent second gate lines VGL1 and VGL2.

[0092] The gate electrode GE can be disposed in the first gate lines HGL1 and HGL2. The source electrode SE can protrude from the data lines DL1 to DL6 toward the gate electrode GE. In the plan view, the drain electrode DE overlaps with the gate electrode GE. The drain electrode DE is disposed adjacent to the source electrode SE. The gate electrode GE, the source electrode SE, and the drain electrode DE can form a switching element of the display panel 100.

[0093] Figure 5 This is a schematic diagram showing the connection between the first gate line and the second gate line of a display panel according to a comparative embodiment. Figure 6 It is shown Figure 5 A detailed diagram of the connection between the first gate line and the second gate line of the display panel.

[0094] according to Figure 5 The display panel 100 of the comparative embodiment may include a first block BL1, a second block BL2, and a third block BL3. Within a block (e.g., BL1), first gate lines H1 to H2N can be connected one-to-one to corresponding second gate lines V1 to V2N. Here, the total number of first gate lines can be 2N. For example, as... Figure 6 As shown, the first gate lines H1 to H2N can be connected to the second gate lines V1 to V2N respectively.

[0095] exist Figure 5 and Figure 6 In the diagram, the connection points between the first gate lines H1 to H2N and the corresponding second gate lines V1 to V2N are represented by dots. Figure 5 and Figure 6 In each block, the line connecting the dots where the first gate lines H1 to H2N and the corresponding second gate lines V1 to V2N are connected can be shown as a single diagonal line.

[0096] The propagation delay of the gate signal transmitted to the first position A1 (which is the bottom center position in the first block BL1) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to half the width of the first block BL1 in the first direction D1. Due to the propagation delay of the gate signal transmitted to the first position A1, the pixel P (reference) disposed at the first position A1 may be reduced. Figure 1 The charging rate may be affected, and a stain may be generated at the first position A1.

[0097] The propagation delay of the gate signal transmitted to the second position A2 (which is the lower rightmost position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to the width of the third BL3 in the first direction D1. The propagation delay of the gate signal transmitted to the second position A2 may be... Figure 5 The worst-case scenario for the structure. Due to the propagation delay of the gate signal transmitted to the second position A2, the pixel P (reference) located at the second position A2 may be reduced. Figure 1 The charging rate of ) and may produce a stain at the second position A2.

[0098] Figure 7 It is shown Figure 1 A schematic diagram of the connection between the first gate line and the second gate line of the display panel. Figure 8 It is shown Figure 7 A detailed diagram of the connection between the first gate line and the second gate line.

[0099] refer to Figures 1 to 4D , Figure 7 and Figure 8 The display panel 100 may include a first BL1, a second BL2, and a third BL3. Although the display panel 100 includes three BL1, BL2, and BL3 in this embodiment, the inventive concept is not limited to this number of BL1, BL2, and BL3.

[0100] In the first block BL1, the first gate lines H1 to H2N can be connected one-to-one to the corresponding second gate lines V1 to V2N. Similarly, in the second block BL2, the first gate lines H1 to H2N can be connected one-to-one to the corresponding second gate lines V1 to V2N. Likewise, in the third block BL3, the first gate lines H1 to H2N can be connected one-to-one to the corresponding second gate lines V1 to V2N. In each block, each of the first gate lines H1 to H2N can be connected to a corresponding second gate line V1 to V2N. Here, the total number of first gate lines can be 2N.

[0101] exist Figure 7 and Figure 8 In the diagram, the connection points between the first gate lines H1 to H2N and the corresponding second gate lines V1 to V2N are represented by dots. Figure 7 In this context, each of blocks BL1, BL2, and BL3 can be divided into two regions.

[0102] exist Figure 8 In this configuration, the second gate lines (e.g., V1 to VN) located in the first region of the block (e.g., BL1) can be connected one-to-one to the odd-numbered first gate lines H1, H3, H5, H7...H2N-7, H2N-5, H2N-3, and H2N-1 among the first gate lines H1 to H2N. Figure 8 In this block (e.g., BL1), the second gate lines (e.g., VN+1 to V2N) disposed in the second region can be connected one-to-one to the even-numbered first gate lines H2, H4, H6, H8...H2N-6, H2N-4, H2N-2, and H2N among the first gate lines H1 to H2N. The second region of the block (e.g., BL1) is adjacent to the first region of the block (e.g., BL1) in the first direction D1. The first region can be the right half of the block in which the second gate lines V1 to VN are disposed, and the second region can be the left half of the block in which the second gate lines VN+1 to V2N are disposed.

[0103] exist Figure 7 In each block, a first line (i.e., a first virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the first region, and a second line (i.e., a second virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the second region, can form a V-shape.

[0104] In implementation methods, for example, in Figure 8 In the first region, the first second gate line V1 can be connected to the first first gate line H1, the second second gate line V2 can be connected to the third first gate line H3, the (N-1)th second gate line VN-1 can be connected to the 2N-3 first gate line H2N-3, and the Nth second gate line VN can be connected to the 2N-1th first gate line H2N-1. In the second region, the (N+1)th second gate line VN+1 can be connected to the 2Nth first gate line H2N, the (N+2)th second gate line VN+2 can be connected to the 2N-2th first gate line H2N-2, the 2N-1th second gate line V2N-1 can be connected to the fourth first gate line H4, and the 2Nth second gate line V2N can be connected to the second first gate line H2.

[0105] Although the first region is located on the left side of the block (e.g., BL1) and the second region is located on the right side of the block (e.g., BL1), the concept of the invention is not limited thereto.

[0106] In this embodiment, the propagation delay of the gate signal transmitted to the first position A1 (which is the bottom center position in the first block BL1) can be a propagation delay corresponding to the height of the display panel 100 in the second direction D2. Therefore, compared with the propagation delay transmitted to... Figure 5 and Figure 6 Compared to the propagation delay of the gate signal at the first position A1 in the comparative embodiment, the propagation delay of the gate signal transmitted to the first position A1 can be reduced in this embodiment.

[0107] In this embodiment, the propagation delay of the gate signal transmitted to the second position A2 (which is the lower rightmost position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to half the width of the third BL3 in the first direction D1. Therefore, the propagation delay of the gate signal transmitted to the second position A2 (which is the lower rightmost position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to half the width of the third BL3 in the first direction D1. Figure 5 and Figure 6 Compared to the propagation delay of the gate signal at the second position A2 in the comparative embodiment, the propagation delay of the gate signal transmitted to the second position A2 can be reduced in this embodiment.

[0108] Figure 9 It shows that it is applied to Figure 8 A timing diagram of an example of the gate signal of the second gate line.

[0109] refer to Figures 7 to 9 When gate signals G1 to G2N are applied sequentially to Figure 8 When applying the first second gate line V1 to the 2Nth second gate line V2N, the odd-numbered first gate lines H1, H3, H5, H7...H2N-7, H2N-5, H2N-3 and H2N-1 in the first region (e.g., the right half region) can be scanned during the first subframe, and the even-numbered first gate lines H2, H4, H6, H8...H2N-6, H2N-4, H2N-2 and H2N in the second region (e.g., the left half region) can be scanned during the second subframe after the first subframe. When gate signals G1 to G2N are sequentially applied to... Figure 8 When the first second gate line V1 to the 2Nth second gate line V2N are used, the display panel 100 can be driven by an interlaced driving method.

[0110] Figure 10 It shows that it is applied to Figure 8 A timing diagram of another example of the gate signal of the second gate line.

[0111] refer to Figure 7 , Figure 8 and Figure 10 Gate signals G1 to G2N can be alternately applied to the second gate lines V1 to VN in the first region and the second gate lines VN+1 to V2N in the second region. When gate signals G1 to G2N are alternately applied to the second gate lines V1 to VN in the first region and the second gate lines VN+1 to V2N in the second region, the first gate lines H1 to H2N in the block (e.g., BL1) can be scanned sequentially. This sequential scanning of the first gate lines H1 to H2N in the block (e.g., BL1) is called a line-by-line driving method.

[0112] like Figure 10 As shown, for example, a first pulse can be output to the first second gate line V1 connected to the first first gate line H1, a second pulse can be output to the 2Nth second gate line V2N connected to the second first gate line H2, a third pulse can be output to the second second gate line V2 connected to the third first gate line H3, and a fourth pulse can be output to the 2N-1th second gate line V2N-1 connected to the fourth first gate line H4.

[0113] According to the embodiment, the gate driver 300 and the data driver 500 are disposed on one side of the display panel 100, so that the bezel width of the side of the display panel 100 can be reduced.

[0114] Furthermore, in the first region (e.g., the right half) of a block (e.g., BL1) of the display panel 100, odd-numbered first gate lines H1 to H2N-1 and second gate lines V1 to VN are connected one-to-one, and in the second region of the block (e.g., BL1), even-numbered first gate lines H2 to H2N and second gate lines VN+1 to V2N are connected one-to-one, thereby reducing the propagation delay of the gate signal at the bottom side of the display panel 100. Therefore, the display quality of the display panel 100 can be improved.

[0115] Figure 11 This is a schematic diagram illustrating the connection between the first gate line and the second gate line of a display panel according to an embodiment of the present invention. Figure 12 It is shown Figure 11 A detailed diagram of the connection between the first gate line and the second gate line.

[0116] Apart from the connection structure between the first gate line and the second gate line, the display panel, display device, and method for driving the display panel according to this embodiment are also referenced. Figures 1 to 10 The display panel, display device, and method of driving the display panel described in the foregoing embodiments are essentially the same. Therefore, the same reference numerals will be used to denote the same features as those described above. Figures 1 to 10The components described in the foregoing embodiments are the same as or similar to those described above, and any repeated explanations of the above-mentioned elements will be omitted.

[0117] refer to Figures 1 to 4D , Figure 11 and Figure 12 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0118] The display panel 100 may include a first BL1, a second BL2, and a third BL3. Although the display panel 100 includes three BL1, BL2, and BL3 in this embodiment, the inventive concept is not limited to this number of BL1, BL2, and BL3.

[0119] exist Figure 11 and Figure 12 In the diagram, the connection points between the first gate lines H1 to H2N and the corresponding second gate lines V1 to V2N are represented by dots. Figure 11 In this context, each of blocks BL1, BL2, and BL3 can be divided into two regions.

[0120] exist Figure 12 In this block (e.g., BL1), the second gate line (e.g., V1 to VN) located in the first region can be connected one-to-one to the odd-numbered first gate lines H1, H3, H5, H7...H2N-7, H2N-5, H2N-3, and H2N-1 among the first gate lines H1 to H2N. Figure 12 In this configuration, the second gate lines (e.g., VN+1 to V2N) located in the second region of the block (e.g., BL1) can be connected one-to-one to the even-numbered first gate lines H2, H4, H6, H8...H2N-6, H2N-4, H2N-2, and H2N. The second region of the block (e.g., BL1) is adjacent to the first region of the block (e.g., BL1) in the first direction D1. Here, the total number of first gate lines can be 2N.

[0121] exist Figure 11 In each block, the first line (i.e., the first virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the first region (e.g., the right half of the block) and the second line (i.e., the second virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the second region (e.g., the left half of the block) can be parallel to each other.

[0122] In implementation methods, for example, in Figure 12In the first region, the first second gate line V1 can be connected to the first first gate line H1, the second second gate line V2 can be connected to the third first gate line H3, the (N-1)th second gate line VN-1 can be connected to the (2N-3)th first gate line H2N-3, and the Nth second gate line VN can be connected to the (2N-1)th first gate line H2N-1. In the second region, the (N+1)th second gate line VN+1 can be connected to the second first gate line H2, the (N+2)th second gate line VN+2 can be connected to the fourth first gate line H4, the (2N-1)th second gate line V2N-1 can be connected to the (2N-2)th first gate line H2N-2, and the 2Nth second gate line V2N can be connected to the 2Nth first gate line H2N.

[0123] Although the first region is located on the left side of the block (e.g., BL1) and the second region is located on the right side of the block (e.g., BL1), the concept of the invention is not limited thereto.

[0124] In this embodiment, the propagation delay of the gate signal transmitted to the first position A1 (which is the bottom center position in the first block BL1) can be a propagation delay corresponding to the height of the display panel 100 in the second direction D2. Therefore, compared with the propagation delay transmitted to... Figure 5 and Figure 6 Compared to the propagation delay of the gate signal at the first position A1 in the comparative embodiment, the propagation delay of the gate signal transmitted to the first position A1 can be reduced in this embodiment.

[0125] In this embodiment, the propagation delay of the gate signal transmitted to the second position A2 (which is the lower rightmost position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to half the width of the third BL3 in the first direction D1. Therefore, the propagation delay of the gate signal transmitted to the second position A2 (which is the lower rightmost position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to half the width of the third BL3 in the first direction D1. Figure 5 and Figure 6 Compared to the propagation delay of the gate signal at the second position A2 in the comparative embodiment, the propagation delay of the gate signal transmitted to the second position A2 can be reduced in this embodiment.

[0126] Figure 13 It shows that it is applied to Figure 12 A timing diagram of an example of the gate signal of the second gate line.

[0127] refer to Figures 11 to 13 When gate signals G1 to G2N are sequentially applied to Figure 12When the first second gate line V1 to the 2Nth second gate line V2N are applied, the odd-numbered first gate lines H1, H3, H5, H7...H2N-7, H2N-5, H2N-3 and H2N-1 in the first region can be scanned during the first subframe, and the even-numbered first gate lines H2, H4, H6, H8...H2N-6, H2N-4, H2N-2 and H2N in the second region can be scanned during the second subframe after the first subframe. When gate signals G1 to G2N are sequentially applied to... Figure 12 When the first second gate line V1 to the 2Nth second gate line V2N are used, the display panel 100 can be driven by an interlaced driving method.

[0128] Figure 14 It shows that it is applied to Figure 12 A timing diagram of an example of the gate signal of the second gate line.

[0129] refer to Figure 11 , Figure 12 and Figure 14 Gate signals G1 to G2N can be alternately applied to the second gate lines V1 to VN in the first region and the second gate lines VN+1 to V2N in the second region. When gate signals G1 to G2N are alternately applied to the second gate lines V1 to VN in the first region and the second gate lines VN+1 to V2N in the second region, the first gate lines H1 to H2N in the block (e.g., BL1) can be scanned sequentially. When the first gate lines H1 to H2N in the block (e.g., BL1) are scanned sequentially, it is called the line-by-line driving method.

[0130] like Figure 14 As shown, for example, a first pulse can be output to the first second gate line V1 connected to the first first gate line H1, a second pulse can be output to the (N+1)th second gate line VN+1 connected to the second first gate line H2, a third pulse can be output to the second second gate line V2 connected to the third first gate line H3, and a fourth pulse can be output to the (N+2)th second gate line VN+2 connected to the fourth first gate line H4.

[0131] According to the embodiment, the gate driver 300 and the data driver 500 are disposed on one side of the display panel 100, so that the bezel width of the side of the display panel 100 can be reduced.

[0132] Furthermore, in the first region of a block (e.g., BL1) of the display panel 100, the first gate lines H1 to H2N-1 and the second gate lines V1 to VN are connected one-to-one, and in the second region of the block (e.g., BL1), the first gate lines H2 to H2N and the second gate lines VN+1 to V2N are connected one-to-one, thereby reducing the propagation delay of the gate signal at the bottom side of the display panel 100. Therefore, the display quality of the display panel 100 can be improved.

[0133] Figure 15 This is a schematic diagram illustrating the connection between the first gate line and the second gate line of a display panel according to an embodiment of the present invention. Figure 16 It is shown Figure 15 A detailed diagram of the connection between the first gate line and the second gate line.

[0134] Apart from the connection structure between the first gate line and the second gate line, the display panel, display device, and method for driving the display panel according to this embodiment are also referenced. Figures 1 to 10 The display panel, display device, and method of driving the display panel described in the foregoing embodiments are essentially the same. Therefore, the same reference numerals will be used to denote the same features as those described above. Figures 1 to 10 The components described in the foregoing embodiments are the same as or similar to those described above, and any repeated explanations of the above-mentioned elements will be omitted.

[0135] refer to Figures 1 to 4D , Figure 15 and Figure 16 The display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0136] The display panel 100 may include a first BL1, a second BL2, and a third BL3. Although the display panel 100 includes three BL1, BL2, and BL3 in this embodiment, the inventive concept is not limited to this number of BL1, BL2, and BL3.

[0137] exist Figure 15 and Figure 16 In the diagram, the connection points between the first gate lines H1 to H4N and the corresponding second gate lines V1 to V4N are represented by dots. Figure 15 In the middle, each of blocks BL1, BL2 and BL3 can be divided into four regions.

[0138] exist Figure 16In this block (e.g., BL1), the second gate lines (e.g., V1 to VN) located in the first region (e.g., the rightmost quarter region) can be connected one-to-one to the 4X-3th first gate lines H1, H5, H9...H4N-7 and H4N-3 among the first gate lines H1 to H4N. Here, X is an integer from 1 to N. Figure 16 In this configuration, the second gate lines (e.g., VN+1 to V2N) located in the second region of the block (e.g., BL1) can be connected one-to-one to the 4X-1th first gate lines H4N-1, H4N-5, H4N-9...H11, H7, and H3 among the first gate lines H1 to H4N. The second region of the block (e.g., BL1) is adjacent to the first region of the block (e.g., BL1) in the first direction D1. Figure 16 In this configuration, the second gate lines (e.g., V2N+1 to V3N) located in the third region of a block (e.g., BL1) can be connected one-to-one to the 4X-2th first gate lines H2, H6, H10...H4N-6 and H4N-2 among the first gate lines H1 to H4N. The third region of the block (e.g., BL1) is adjacent to the second region of the block (e.g., BL1) in the first direction D1. Figure 16 In this block (e.g., BL1), the second gate lines (e.g., V3N+1 to V4N) located in the fourth region (e.g., the leftmost quarter region) can be connected one-to-one to the 4Xth first gate lines H4N, H4N-4, H4N-8...H12, H8, and H4 among the first gate lines H1 to H4N. The fourth region of the block (e.g., BL1) is adjacent to the third region of the block (e.g., BL1) in the first direction D1. Here, the total number of first gate lines can be 4N. X can be an integer between 1 and N.

[0139] exist Figure 15 In each block, a first line (i.e., a first virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the first region, a second line (i.e., a second virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the second region, a third virtual line connecting the dots where the first gate line and the corresponding second gate line are connected in the third region, and a fourth line (i.e., a fourth virtual line) connecting the dots where the first gate line and the corresponding second gate line are connected in the fourth region can form a W shape.

[0140] In implementation methods, for example, in Figure 16In the first region, the first second gate line V1 can be connected to the first first gate line H1, the second second gate line V2 can be connected to the fifth first gate line H5, the (N-1)th second gate line VN-1 can be connected to the 4N-7th first gate line H4N-7, and the Nth second gate line VN can be connected to the 4N-3th first gate line H4N-3. In the second region, the (N+1)th second gate line VN+1 can be connected to the 4N-1th first gate line H4N-1, the (N+2)th second gate line VN+2 can be connected to the 4N-5th first gate line H4N-5, the (2N-1)th second gate line V2N-1 can be connected to the seventh first gate line H7, and the 2Nth second gate line V2N can be connected to the third first gate line H3. In the third region, the 2N+1th second gate line V2N+1 can be connected to the second first gate line H2, the 2N+2th second gate line V2N+2 can be connected to the sixth first gate line H6, the 3N-1th second gate line V3N-1 can be connected to the 4N-6th first gate line H4N-6, and the 3Nth second gate line V3N can be connected to the 4N-2th first gate line H4N-2. In the fourth region, the 3N+1th second gate line V3N+1 can be connected to the 4Nth first gate line H4N, the 3N+2th second gate line V3N+2 can be connected to the 4N-4th first gate line H4N-4, the 4N-1th second gate line V4N-1 can be connected to the eighth first gate line H8, and the 4Nth second gate line V4N can be connected to the fourth first gate line H4.

[0141] In this embodiment, the positions of the first region to the fourth region can be changed or switched. In the first region to the fourth region, the second gate lines V1 to V4N can be respectively connected to the 4Xth first gate line, which is a multiple of four; the 4X-3th first gate line, which leaves a remainder of one when divided by four; the 4X-2nd first gate line, which leaves a remainder of two when divided by four; and the 4X-1st first gate line, which leaves a remainder of three when divided by four.

[0142] In this embodiment, the propagation delay of the gate signal transmitted to the first position A1 (which is the bottom center position in the first block BL1) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to one-quarter of the width of the first block BL1 in the first direction D1. Therefore, the propagation delay of the gate signal transmitted to the first position A1 is the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to one-quarter of the width of the first block BL1 in the first direction D1. Figure 5 and Figure 6 Compared to the propagation delay of the gate signal at the first position A1 in the comparative embodiment, the propagation delay of the gate signal transmitted to the first position A1 can be reduced in this embodiment.

[0143] In this embodiment, the propagation delay of the gate signal transmitted to the second position A2 (which is the lower right position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to one-quarter of the width of the third BL3 in the first direction D1. Therefore, the propagation delay of the gate signal transmitted to the second position A2 (which is the lower right position in the third BL3) can be the sum of the propagation delay corresponding to the height of the display panel 100 in the second direction D2 and the propagation delay corresponding to one-quarter of the width of the third BL3 in the first direction D1. Figure 5 and Figure 6 Compared to the propagation delay of the gate signal at the second position A2 in the comparative embodiment, the propagation delay of the gate signal transmitted to the second position A2 can be reduced in this embodiment.

[0144] Figure 9 Interlaced driving method and Figure 10 The line-by-line driving method can be used with... Figure 9 and Figure 10 The method described herein is applied in a similar manner to that described in the previous section.

[0145] According to the embodiment, the gate driver 300 and the data driver 500 are disposed on one side of the display panel 100, so that the bezel width of the side of the display panel 100 can be reduced.

[0146] Furthermore, in the first region of a block (e.g., BL1) of the display panel 100, the 4X-1 first gate lines H1 to H4N-1 and the second gate lines V1 to VN are connected in a one-to-one manner; in the second region of the block (e.g., BL1), the 4X-3 first gate lines H3 to H4N-3 and the second gate lines VN+1 to V2N are connected in a one-to-one manner; in the third region of the block (e.g., BL1), the 4X-2 first gate lines H2 to H4N-2 and the second gate lines V2N+1 to V3N are connected in a one-to-one manner; and in the fourth region of the block (e.g., BL1), the 4X first gate lines H4 to H4N and the second gate lines V3N+1 to V4N are connected in a one-to-one manner. This reduces the propagation delay of the gate signals at the bottom side of the display panel 100. Therefore, the display quality of the display panel 100 can be improved.

[0147] According to the display panel, display device, and method for driving the display panel of this embodiment as explained above, the bezel width of the display device can be reduced and the display quality of the display panel can be improved.

[0148] The foregoing is a description of the inventive concept and should not be construed as limiting it. Although some embodiments of the inventive concept have been described, those skilled in the art will readily understand that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the clauses for "device plus function" are intended to cover structures described herein that perform the stated functions, and not only structural equivalences but also equivalent structures. Therefore, it should be understood that the foregoing is a description of the inventive concept and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, and equivalents of the claims are included therein.

Claims

1. A display panel, the display panel comprising a plurality of blocks of pixels, each of the plurality of blocks comprising a plurality of first gate lines extending in a first direction and sequentially numbered, and a plurality of second gate lines extending in a second direction different from the first direction and sequentially numbered. in, The plurality of first gate lines are arranged sequentially in the second direction, and the plurality of second gate lines are arranged sequentially in the first direction. Wherein, the plurality of first gate lines include a first gate line to a 4Nth first gate line, and the plurality of second gate lines include a first second gate line to a 4Nth second gate line, and N is an integer equal to or greater than 2. In each block, the first gate line is connected one-to-one to the corresponding second gate line. Each block is divided into a first region, a second region, a third region, and a fourth region in the first direction, and the first region, the second region, the third region, and the fourth region are arranged sequentially. Specifically, the first to Nth second gate lines in the first region of each block are connected one-to-one to each of the 4x-3th first gate lines among the plurality of first gate lines. Specifically, the N+1th to 2Nth second gate lines located in the second region of each block are connected one-to-one to each of the 4th (N-X+1)-1th first gate lines among the plurality of first gate lines. Specifically, the 2N+1th to 3Nth second gate lines located in the third region of each block are connected one-to-one to each of the 4X-2th first gate lines among the plurality of first gate lines. Specifically, the 3N+1th to the 4Nth second gate lines located in the fourth region of each block are connected one-to-one to each of the 4th (N-X+1)th first gate lines among the plurality of first gate lines, and In each of the first to the fourth regions, X is a natural number that takes values ​​from 1 to N sequentially. The first second gate line, the (N+1)th second gate line, the 2N+1th second gate line, and the 3N+1th second gate line are respectively connected to the 4X-3th first gate line, the 4(N-X+1)-1th first gate line, the 4X-2th first gate line, and the 4(N-X+1)th first gate line when X is 1. The Nth second gate line, the 2Nth second gate line, the 3Nth second gate line, and the 4Nth second gate line are respectively connected to the 4X-3th first gate line, the 4(N-X+1)-1th first gate line, the 4X-2th first gate line, and the 4(N-X+1)th first gate line when X is N.

2. The display panel according to claim 1, wherein, A W-shape is formed by connecting a first virtual line in the first region to the point where the first gate line and the corresponding second gate line are connected, a second virtual line in the second region to the point where the first gate line and the corresponding second gate line are connected, a third virtual line in the third region to the point where the first gate line and the corresponding second gate line are connected, and a fourth virtual line in the fourth region to the point where the first gate line and the corresponding second gate line are connected.

3. The display panel according to claim 2, in, In the first region, the first second gate line is connected to the first first gate line, the second second gate line is connected to the fifth first gate line, the (N-1)th second gate line is connected to the 4N-7th first gate line, and the Nth second gate line is connected to the 4N-3th first gate line. In the second region, the (N+1)th second gate line is connected to the (4N-1)th first gate line, the (N+2)th second gate line is connected to the (4N-5)th first gate line, the (2N-1)th second gate line is connected to the seventh first gate line, and the (2N)th second gate line is connected to the third first gate line. In the third region, the 2N+1th second gate line is connected to the second first gate line, the 2N+2th second gate line is connected to the sixth first gate line, the 3N-1th second gate line is connected to the 4N-6th first gate line, and the 3Nth second gate line is connected to the 4N-2th first gate line. In the fourth region, the 3N+1th second gate line is connected to the 4Nth first gate line, the 3N+2th second gate line is connected to the 4N-4th first gate line, the 4N-1th second gate line is connected to the eighth first gate line, and the 4Nth second gate line is connected to the fourth first gate line.

4. The display panel according to claim 1, wherein, The block also includes multiple data lines extending in the second direction.

5. The display panel according to claim 4, wherein, The first gate line is disposed on the first layer. The second gate line and the data line are disposed on a second layer different from the first layer. The first gate line is connected to the corresponding second gate line through a contact hole.

6. The display panel according to claim 4, wherein, Three or six of the multiple data lines are positioned between two adjacent second gate lines of the multiple second gate lines.

7. A display device, comprising: Display panel; displays images. A gate driver outputs a gate signal to the display panel; as well as The data driver outputs data voltage to the display panel; The display panel includes multiple blocks of pixels, each of which includes multiple first gate lines extending in a first direction and numbered sequentially, and multiple second gate lines extending in a second direction different from the first direction and numbered sequentially. Wherein, the plurality of first gate lines are arranged sequentially in the second direction, and the plurality of second gate lines are arranged sequentially in the first direction. Wherein, the plurality of first gate lines include a first gate line to a 4Nth first gate line, and the plurality of second gate lines include a first second gate line to a 4Nth second gate line, and N is an integer equal to or greater than 2. In each block, the first gate line is connected one-to-one to the corresponding second gate line. Each block is divided into a first region, a second region, a third region, and a fourth region in the first direction, and the first region, the second region, the third region, and the fourth region are arranged sequentially. Specifically, the first to Nth second gate lines in the first region of each block are connected one-to-one to each of the 4x-3th first gate lines among the plurality of first gate lines. Specifically, the N+1th to 2Nth second gate lines located in the second region of each block are connected one-to-one to each of the 4th (N-X+1)-1th first gate lines among the plurality of first gate lines. Specifically, the 2N+1th to 3Nth second gate lines located in the third region of each block are connected one-to-one to each of the 4X-2th first gate lines among the plurality of first gate lines. Specifically, the 3N+1th to the 4Nth second gate lines located in the fourth region of each block are connected one-to-one to each of the 4th (N-X+1)th first gate lines among the plurality of first gate lines, and In each of the first to the fourth regions, X is a natural number that takes values ​​from 1 to N sequentially. The first second gate line, the (N+1)th second gate line, the 2N+1th second gate line, and the 3N+1th second gate line are respectively connected to the 4X-3th first gate line, the 4(N-X+1)-1th first gate line, the 4X-2th first gate line, and the 4(N-X+1)th first gate line when X is 1. The Nth second gate line, the 2Nth second gate line, the 3Nth second gate line, and the 4Nth second gate line are respectively connected to the 4X-3th first gate line, the 4(N-X+1)-1th first gate line, the 4X-2th first gate line, and the 4(N-X+1)th first gate line when X is N.

8. The display device according to claim 7, wherein, A W-shape is formed by connecting a first virtual line in the first region to the point where the first gate line and the corresponding second gate line are connected, a second virtual line in the second region to the point where the first gate line and the corresponding second gate line are connected, a third virtual line in the third region to the point where the first gate line and the corresponding second gate line are connected, and a fourth virtual line in the fourth region to the point where the first gate line and the corresponding second gate line are connected.

9. The display device according to claim 8, in, In the first region, the first second gate line is connected to the first first gate line, the second second gate line is connected to the fifth first gate line, the (N-1)th second gate line is connected to the 4N-7th first gate line, and the Nth second gate line is connected to the 4N-3th first gate line. In the second region, the (N+1)th second gate line is connected to the (4N-1)th first gate line, the (N+2)th second gate line is connected to the (4N-5)th first gate line, the (2N-1)th second gate line is connected to the seventh first gate line, and the (2N)th second gate line is connected to the third first gate line. In the third region, the 2N+1th second gate line is connected to the second first gate line, the 2N+2th second gate line is connected to the sixth first gate line, the 3N-1th second gate line is connected to the 4N-6th first gate line, and the 3Nth second gate line is connected to the 4N-2th first gate line. In the fourth region, the 3N+1th second gate line is connected to the 4Nth first gate line, the 3N+2th second gate line is connected to the 4N-4th first gate line, the 4N-1th second gate line is connected to the eighth first gate line, and the 4Nth second gate line is connected to the fourth first gate line.

10. The display device according to claim 7, wherein, The block of the display panel includes multiple data lines extending in the second direction.

11. The display device according to claim 10, wherein, The first gate line is disposed on the first layer. The second gate line and the data line are disposed on a second layer different from the first layer. The first gate line is connected to the corresponding second gate line through a contact hole.

12. The display device according to claim 10, wherein, Three or six of the multiple data lines are positioned between two adjacent second gate lines of the multiple second gate lines.

13. The display device according to claim 7, further comprising a flexible circuit board, in, The gate driver includes a gate driver chip. The data driver includes a first source driver chip and a second source driver chip, and The first source driver chip, the gate driver chip, and the second source driver chip are sequentially disposed in the flexible circuit substrate.

14. A method of driving a display panel, the display panel comprising a plurality of blocks of pixels, each of the plurality of blocks comprising a plurality of first gate lines extending in a first direction and sequentially numbered, a plurality of second gate lines extending in a second direction other than the first direction and sequentially numbered, and a plurality of data lines extending in the second direction, the method comprising: A gate signal is applied to the second gate line disposed in the first region of each block of the display panel, the second gate line disposed in the second region of each block of the display panel, the second gate line disposed in the third region of each block of the display panel, and the second gate line disposed in the fourth region of each block of the display panel; as well as Apply a data voltage to the data lines of the display panel. Wherein, the plurality of first gate lines are arranged sequentially in the second direction, and the plurality of second gate lines are arranged sequentially in the first direction. Wherein, the plurality of first gate lines include a first gate line to a 4Nth first gate line, and the plurality of second gate lines include a first second gate line to a 4Nth second gate line, and N is an integer equal to or greater than 2. The first region, the second region, the third region, and the fourth region are arranged sequentially in the first direction. In each block, the first gate line is connected one-to-one to the corresponding second gate line. Specifically, the first to Nth second gate lines in the first region of each block are connected one-to-one to each of the 4x-3th first gate lines among the plurality of first gate lines. Specifically, the N+1th to 2Nth second gate lines located in the second region of each block are connected one-to-one to each of the 4th (N-X+1)-1th first gate lines among the plurality of first gate lines. Specifically, the 2N+1th to 3Nth second gate lines located in the third region of each block are connected one-to-one to each of the 4X-2th first gate lines among the plurality of first gate lines. Specifically, the 3N+1th to the 4Nth second gate lines located in the fourth region of each block are connected one-to-one to each of the 4th (N-X+1)th first gate lines among the plurality of first gate lines, and In each of the first to the fourth regions, X is a natural number that takes values ​​from 1 to N sequentially. The first second gate line, the (N+1)th second gate line, the 2N+1th second gate line, and the 3N+1th second gate line are respectively connected to the 4X-3th first gate line, the 4(N-X+1)-1th first gate line, the 4X-2th first gate line, and the 4(N-X+1)th first gate line when X is 1. The Nth second gate line, the 2Nth second gate line, the 3Nth second gate line, and the 4Nth second gate line are respectively connected to the 4X-3th first gate line, the 4(N-X+1)-1th first gate line, the 4X-2th first gate line, and the 4(N-X+1)th first gate line when X is N.

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