Semiconductor device and method of manufacturing a semiconductor device

Abstract

This disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device. A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has a second insulating film and a third insulating film that are adjacent to each other in a plan view, and in the gate length direction of the gate electrode, the second insulating film is located on the n-type source region side and the third insulating film is located on the n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a stack of films having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each of the three insulating films has a band gap larger than the band gap of the second insulating film.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-094212, filed on May 29, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices and methods for manufacturing the same, such as semiconductor devices having LDMOSFETs and methods for manufacturing semiconductor devices. Background Technology

[0004] LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) is used as a MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor). LDMOSFET has a high drain breakdown voltage.

[0005] One technique involves using a structure where the drain side is thicker than the source side (a stepped oxide (SOX) structure) as the gate insulating film of an LDMOSFET. This technique is exemplified by Non-Patent Literature 1 (Der-Gao Lin et al., “A Novel LDMOS Structure With A Step Gate Oxide”, IEDM 1995). By increasing the thickness of the gate insulating film on the drain side, rather than the source side, of the LDMOSFET, the breakdown voltage (dielectric breakdown voltage) can be improved. Summary of the Invention

[0006] In semiconductor devices with LDMOSFETs, it is desirable to improve their reliability as much as possible.

[0007] Other issues and new features will become apparent from the description and accompanying figures in this article.

[0008] According to one embodiment, a semiconductor device includes: a semiconductor substrate; a source region and a drain region of a first conductivity type formed in the semiconductor substrate; a first semiconductor region of a second conductivity type formed on the semiconductor substrate to surround the source region, the second conductivity type being opposite to the first conductivity type; and a gate electrode formed on the semiconductor substrate between the source and drain regions via a gate insulating film. The gate insulating film has a first gate insulating film and a second gate insulating film adjacent to each other in a plan view. In the gate length direction of the gate electrode, the first gate insulating film is located on the source region side, and the second gate insulating film is located on the drain region side. The first gate insulating film is thinner than the second gate insulating film. The second gate insulating film is made of a stack of films having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film. Each band gap of the first and third insulating films is larger than the band gap of the second insulating film.

[0009] According to one embodiment, the reliability of semiconductor devices can be improved. Attached Figure Description

[0010] Figure 1 This is a cross-sectional view of the main part of a semiconductor device according to one embodiment.

[0011] Figure 2 This is a cross-sectional view of the main part of the semiconductor device according to an embodiment during its manufacturing process.

[0012] Figure 3 It is the main part of semiconductor devices Figure 2 Cross-sectional view during subsequent manufacturing processes.

[0013] Figure 4 It is the main part of semiconductor devices Figure 3 Cross-sectional view during subsequent manufacturing processes.

[0014] Figure 5 It is the main part of semiconductor devices Figure 4 Cross-sectional view during subsequent manufacturing processes.

[0015] Figure 6 It is the main part of semiconductor devices Figure 5 Cross-sectional view during subsequent manufacturing processes.

[0016] Figure 7 It is the main part of semiconductor devices Figure 6 Cross-sectional view during subsequent manufacturing processes.

[0017] Figure 8 It is the main part of semiconductor devices Figure 7 Cross-sectional view during subsequent manufacturing processes.

[0018] Figure 9 It is the main part of semiconductor devices Figure 8 Cross-sectional view during subsequent manufacturing processes.

[0019] Figure 10 It is the main part of semiconductor devices Figure 9 Cross-sectional view during subsequent manufacturing processes.

[0020] Figure 11 It is the main part of semiconductor devices Figure 10 Cross-sectional view during subsequent manufacturing processes.

[0021] Figure 12 It is the main part of semiconductor devices Figure 11 Cross-sectional view during subsequent manufacturing processes.

[0022] Figure 13 It is the main part of semiconductor devices Figure 12 Cross-sectional view during subsequent manufacturing processes.

[0023] Figure 14 It is the main part of semiconductor devices Figure 13 Cross-sectional view during subsequent manufacturing processes.

[0024] Figure 15 It is the main part of semiconductor devices Figure 14 Cross-sectional view during subsequent manufacturing processes.

[0025] Figure 16 It is the main part of semiconductor devices Figure 15 Cross-sectional view during subsequent manufacturing processes.

[0026] Figure 17 This is a cross-sectional view of the main part of a semiconductor device according to one embodiment.

[0027] Figure 18 This is a cross-sectional view of the main part of a semiconductor device according to another embodiment.

[0028] Figure 19 This is a cross-sectional view of the main part of a semiconductor device according to yet another embodiment. Detailed Implementation

[0029] In the embodiments described below, for convenience, the invention will be described in multiple parts or embodiments as needed. However, unless otherwise stated, these parts or embodiments are not independent of each other, and one or more relate to all or part of another as examples of modifications, details, or supplementary descriptions. Furthermore, in the embodiments described below, when referring to the quantity of elements (including the number of pieces, values, quantities, ranges, etc.), the quantity of elements is not limited to a specific quantity unless otherwise stated or where the quantity is obviously limited to a specific quantity in principle, and quantities greater than or less than the specified quantity also apply. Furthermore, in the embodiments described below, it is obvious that components (including element steps) are not always essential unless otherwise stated or where they are obviously not required in principle. Similarly, in the embodiments described below, when referring to the shape of components, their positional relationships, etc., this includes substantially similar and analogous shapes, etc., unless otherwise stated or where it is obviously conceivable to exclude them in principle. The numerical values ​​and ranges described above also apply.

[0030] In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that in all the drawings used to describe the embodiments, components having the same function are denoted by the same reference numerals, and repeated descriptions will be omitted. Furthermore, unless specifically required in the following embodiments, descriptions of the same or similar parts will generally not be repeated.

[0031] Additionally, in some of the figures used in the following embodiments, shading lines are omitted even in cross-sectional views to facilitate observation. Furthermore, shading lines are used even in plan views to facilitate observation.

[0032] (First Embodiment)

[0033] <Structure of Semiconductor Devices>

[0034] A semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a cross-sectional view of the main part of the semiconductor device according to this embodiment, and shows a section that is substantially parallel to the gate length direction.

[0035] The semiconductor device in this embodiment is a semiconductor device with a MISFET (metal-insulator-semiconductor field-effect transistor). In this case, a semiconductor device with an LDMOSFET (laterally diffused metal-oxide-semiconductor field-effect transistor) is used as a MISFET.

[0036] Incidentally, when referring to MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or LDMOSFET in this application, this application includes not only MISFETs that use an oxide film (silicon oxide film) as the gate insulating film, but also MISFETs that use an insulating film other than an oxide film (silicon oxide film) as the gate insulating film. Furthermore, LDMOSFET is a type of MISFET device.

[0037] In the following text, reference will be made to Figure 1 The structure of the semiconductor device according to this embodiment will be described in detail.

[0038] like Figure 1 As shown, an LDMOSFET, acting as a MISFET, is formed on the main surface of a semiconductor substrate SUB. The semiconductor substrate SUB comprises: a substrate body SB, which serves as a semiconductor substrate made of p+ type single-crystal silicon or the like, to which p-type impurities such as boron (B) are introduced; and an epitaxial layer (semiconductor layer) EP, formed on the main surface of the substrate body SB, composed of p- type single-crystal silicon or the like. Therefore, the semiconductor substrate SUB is a so-called epitaxial wafer. The impurity concentration (p-type impurity concentration) of the substrate body SB is higher than the impurity concentration (p-type impurity concentration) of the epitaxial layer EP. The epitaxial layer EP can also be considered part of the semiconductor substrate SUB. Furthermore, an n-type intercalation layer (semiconductor layer) can be inserted between the substrate body SB and the epitaxial layer EP.

[0039] By using methods such as STI (shallow trench isolation) and LOCOS (local oxidation of silicon), a device separation region (not shown) made of an insulator (insulating film) is formed on the main surface of the epitaxial layer EP.

[0040] An n-type semiconductor region (n-type well) NW and a p-type semiconductor region (p-type body region, p-type well) PW are formed on the upper portion (upper layer) of the epitaxial layer EP. The n-type semiconductor region NW and the p-type semiconductor region PW are adjacent to each other. The impurity concentration (p-type impurity concentration) of the p-type semiconductor region PW is higher than that of the epitaxial layer EP. The p-type semiconductor region PW also functions as a punch-through barrier, which suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET. Between the n-type source region SR and the n-type drain region DR, the upper portion (upper layer) of the p-type semiconductor region PW, located below the gate electrode GE, becomes the channel formation region of the LDMOSFET.

[0041] An n-type source region (n-type semiconductor region) SR is formed within a p-type semiconductor region PW. Furthermore, a p-type semiconductor region BC is formed within the p-type semiconductor region PW, adjacent to the n-type source region SR. In other words, the p-type semiconductor region PW is formed to surround both the n-type source region SR and the p-type semiconductor region BC. Therefore, the bottom and side surfaces of the n-type source region SR (except for the side surface in contact with the p-type semiconductor region BC) are covered by the p-type semiconductor region PW. The n-type source region SR is the n-type semiconductor region used as the source region of an LDMOSFET. The impurity concentration (p-type impurity concentration) of the p-type semiconductor region BC is higher than the impurity concentration (p-type impurity concentration) of the p-type semiconductor region PW.

[0042] The n-type drain region (n-type semiconductor region) DR is formed within the n-type semiconductor region NW. In other words, the n-type semiconductor region NW is formed to surround the n-type drain region DR. Therefore, the bottom and side surfaces of the n-type drain region DR are covered by the n-type semiconductor region NW. The n-type drain region DR is the n-type semiconductor region used as the drain region of the LMOSFET. The impurity concentration (n-type impurity concentration) of the n-type drain region DR is higher than the impurity concentration (n-type impurity concentration) of the n-type semiconductor region NW. The n-type drain region DR and the n-type source region SR are separated from each other along the gate length direction of the gate electrode GE.

[0043] Along the gate length direction of the gate electrode GE, an n-type semiconductor region NW is inserted between the p-type semiconductor region PW and the n-type drain region DR, with a lower impurity concentration (n-type impurity concentration) than the n-type drain region DR. Therefore, an n-type semiconductor region NW with a lower impurity concentration than the n-type drain region DR exists between the channel formation region and the n-type drain region DR of the LDMOSFET, and the n-type semiconductor region NW can be used as an n-type drift region. Thus, along the gate length direction of the gate electrode GE, a channel formation region and an n-type semiconductor region NW exist between the n-type source region SR and the n-type drain region DR; the channel formation region is located on the n-type source region SR side; and the n-type semiconductor region NW is located on the n-type drain region DR side. The channel formation region is adjacent to both the n-type source region SR and the n-type semiconductor region NW.

[0044] The gate electrode GE of the LD MOSFET is formed on the surface of the epitaxial layer EP via an insulating film (gate insulating film) GF. That is, the n-type source region SR and the n-type drain region DR are formed on the epitaxial layer EP of the semiconductor substrate SUB, and the gate electrode GE is formed on the epitaxial layer EP via the insulating film GF, located between the n-type source region SR and the n-type drain region DR. The insulating film GF can be used as the gate insulating film of the LD MOSFET.

[0045] The gate electrode GE is composed of, for example, a single layer of n-type polysilicon film, or a stack of n-type polysilicon film and metal silicide layer. Sidewall spacers (sidewall insulating films) SW composed of insulating films (e.g., silicon oxide films) are formed on the sidewalls (side surfaces) of the gate electrode GE.

[0046] In a plan view, the gate electrode GE is disposed between the n-type source region SR and the n-type drain region DR. When a voltage equal to or higher than the threshold voltage is applied to the gate electrode GE, a channel (n-type inversion layer) is formed in the upper portion (upper layer portion) of the p-type semiconductor region PW located below the gate electrode GE, and the n-type source region SR and the n-type drain region DR are connected through the channel (n-type inversion layer) and the n-type semiconductor region NW.

[0047] The insulating film GF, located beneath the gate electrode GE, has a source-side portion composed of a relatively thin insulating film TZ, and a drain-side portion composed of a relatively thick insulating film SZ. Specifically, the insulating film GF has insulating films TZ and SZ adjacent to each other in a plan view, with insulating film TZ located on the n-type source region SR side and insulating film SZ located on the n-type drain region DR side along the gate length direction of the gate electrode GE. Insulating film SZ extends along the direction of the n-type drain region DR from its position connected to (adjacent to) insulating film TZ. The thickness of insulating film TZ is thinner than that of insulating film SZ.

[0048] The insulating film SZ is composed of a laminated film (laminated insulating film) in which multiple insulating films are stacked, preferably consisting of: a silicon oxide film OX1; a silicon nitride film NT on the silicon oxide film OX1; and a silicon oxide film OX2 on the silicon nitride film NT. The laminated film of silicon oxide film OX1, silicon nitride film NT, and silicon oxide film OX2 can also be considered an ONO (oxide-nitride-oxide) film. Each band gap of the silicon oxide film OX1 and the silicon oxide film OX2 is larger than the band gap of the silicon nitride film NT.

[0049] The silicon oxide film OX1 is preferably a thermally oxidized film or a CVD film, the silicon nitride film NT is preferably a CVD film, and the silicon oxide film OX2 is preferably a thermally oxidized film or a CVD film. Here, a thermally oxidized film corresponds to a film formed by using a thermal oxidation method, and a CVD film corresponds to a film formed by using a CVD method. The thickness of the silicon oxide film OX1 can be, for example, about 5 nm to 15 nm (more than 5 nm and less than 15 nm); the thickness of the silicon nitride film NT can be, for example, about 5 nm to 15 nm; and the thickness of OX2 can be, for example, about 5 nm to 15 nm.

[0050] The insulating film SZ has a charge retention (charge accumulation) function and therefore has the function of suppressing or preventing charge from being injected from the semiconductor substrate SUB to the gate electrode GE. Therefore, the insulating film SZ has a stacked structure of at least three layers, and the barrier height of the outer layer (here, the silicon nitride film NT) used as the charge retention portion becomes lower than the barrier height of each outer layer (here, the silicon oxide films OX1 and OX2) used as charge blocking layers.

[0051] Each band gap of the top insulating film (here, silicon oxide film OX2) and the bottom insulating film (here, silicon oxide film OX1) of the insulating film SZ is larger than the band gap of the charge retention layer (here, silicon nitride film NT) between the top and bottom insulating films. As a result, the top insulating film (here, silicon oxide film OX2) and the bottom insulating film (here, silicon oxide film OX1) sandwiching the charge retention layer (silicon nitride film NT) can each serve as a charge blocking layer for confining the charge within the charge retention layer (silicon nitride film NT).

[0052] The insulating film TZ is composed of a single layer of insulating film, preferably a silicon oxide film, and more preferably a thermally oxidized film (a silicon oxide film formed by thermal oxidation). The insulating film TZ can have a thickness of, for example, about 4 nm to 20 nm.

[0053] Sidewall spacers SW are formed on each side surface of the gate electrode GE. However, sidewall spacer SW1, formed on the n-type source region SR side, is located on the epitaxial layer EP, and sidewall spacer SW2, formed on the n-type drain region DR side, is located on the insulating film SZ. That is, the insulating film SZ has a portion that overlaps with the gate electrode GE in a plan view (i.e., the portion located below the gate electrode GE) and a portion that does not overlap with the gate electrode GE in a plan view (i.e., the portion protruding from the gate electrode GE in the direction of the n-type drain region DR). In the plan view, sidewall spacer SW2 is formed on the portion of the insulating film SZ that does not overlap with the gate electrode GE. Meanwhile, sidewall spacer SW1 is not formed on the insulating film SZ, but is formed on the epitaxial layer EP (thus contacting the epitaxial layer EP).

[0054] An insulating film (interlayer insulating film) IL is formed on the main surface of the semiconductor substrate SUB, i.e., on the main surface of the epitaxial layer EP, to cover the gate electrode GE and the sidewall spacers SW. The insulating film IL is made of silicon oxide film, for example. The insulating film IL can also be formed by forming a stack of relatively thin silicon nitride film and relatively thick silicon oxide film on silicon nitride. The upper surface of the insulating film IL is planarized.

[0055] Contact holes (through holes) are formed in the insulating film IL, and conductive plugs (contact plugs, embedded conductor portions for connection) PG, mainly composed of a tungsten (W) film, are embedded in the contact holes. Plugs PG are formed on each of the n-type source region SR, the n-type drain region DR, and the p-type semiconductor region BC. Here, a plug PG formed on and electrically connected to the n-type source region SR is called a plug PGS. Furthermore, a plug PG formed on and electrically connected to the n-type drain region DR is called a plug PGD. Additionally, a plug PG formed on and electrically connected to the p-type semiconductor region BC is called a plug PGB. Plugs PG can also be formed on the gate electrode GE, but... Figure 1 The plug PG on the gate electrode GE is not shown in the cross-sectional view.

[0056] On the insulating film IL in which the plug PG is embedded, a wiring (first layer wiring) M1 is formed, which is mainly composed of a conductive film made of aluminum (Al) or aluminum alloy. Wiring M1 is preferably aluminum wiring, but wiring made of other metal materials, such as tungsten wiring, can also be used.

[0057] Wiring M1 has: a source wiring M1S electrically connected to the n-type source region SR via a plug PGS; and a drain wiring M1D electrically connected to the n-type drain region DR via a plug PGD. Furthermore, the source wiring M1S is electrically connected to the p-type semiconductor region BC via a plug PGB. Therefore, a potential (source potential) identical to the potential supplied from the source wiring M1S to the n-type source region SR via the plug PGS is supplied from the source wiring M1S to the p-type semiconductor region BC via the plug PGB, and further supplied from the p-type semiconductor region BC to the p-type semiconductor region PW. Wiring M1 may further have a gate wiring electrically connected to the gate electrode GE via a plug PG, but in… Figure 1 The gate wiring is not shown in the cross-sectional view.

[0058] The illustrations and descriptions of the layer structure above the insulating film IL and wiring M1 will be omitted here.

[0059] Semiconductor device manufacturing processes

[0060] Next, the manufacturing process of the semiconductor device in this embodiment will be described with reference to the accompanying drawings. Figures 2 to 16 Each of these is a cross-sectional view of a major portion of the semiconductor device in this embodiment during the manufacturing process, and shows a cross-sectional view of the semiconductor device in this embodiment. Figure 1 Corresponding cross-sectional views. Incidentally, although a preferred example of the manufacturing process of the semiconductor device of this embodiment has been described herein, the invention is not limited thereto and various modifications are possible.

[0061] To manufacture semiconductor devices, firstly, as... Figure 2 As shown, a semiconductor substrate SUB is fabricated, having, for example, a substrate body SB made of p+ type single crystal silicon and an epitaxial layer EP formed on the main surface of the substrate body SB, made of p- type single crystal silicon or the like.

[0062] Next, a device separation region (not shown) is formed on the main surface of the epitaxial layer EP of the semiconductor substrate SUB using, for example, the STI method or the LOCOS method.

[0063] Next, as Figure 3 As shown, the n-type semiconductor region NW is formed by introducing n-type impurities into the upper portion (upper layer portion) of the epitaxial layer EP of the semiconductor substrate SUB using an ion implantation method.

[0064] Next, after cleaning the surface of the epitaxial layer EP on the semiconductor substrate SUB, as follows Figure 4 As shown, the insulating film SZ1 is formed on the main surface (front surface) of the epitaxial layer EP of the semiconductor substrate SUB. The insulating film SZ1 is composed of a stacked film (stacked insulating film) with multiple insulating films stacked on top of each other. The stacked film is preferably composed of a silicon oxide film OX1, a silicon nitride film NT on the silicon oxide film OX1, and a silicon oxide film OX2 on the silicon nitride film NT.

[0065] To form the insulating film SZ1, for example, firstly, a silicon oxide film OX1 is formed by thermal oxidation or CVD, then a silicon nitride film NT is deposited on the silicon oxide film OX1 by CVD, and a silicon oxide film OX2 is further formed on the silicon nitride film NT by CVD, thermal oxidation, or both. Therefore, an insulating film SZ1 composed of a stack of silicon oxide film OX1, silicon nitride film NT, and silicon oxide film OX2 can be formed. Furthermore, the silicon oxide film OX1 can also be formed prior to ion implantation for forming the n-type semiconductor region NW.

[0066] Next, as Figure 5 As shown, a photoresist pattern (not shown) is formed on the insulating film SZ1, and then the photoresist pattern is used as an etching mask to etch the insulating film SZ1. In this way, unwanted portions of the insulating film SZ1 (i.e., portions exposed from the photoresist pattern) are removed. Therefore, the insulating film SZ1 is patterned to form an insulating film SZ1 composed of the remaining insulating film SZ1 (the patterned insulating film SZ1).

[0067] Next, as Figure 6As shown, an insulating film TZ1 is formed on the surface of the epitaxial layer EP of the semiconductor substrate SUB. The insulating film TZ1 is preferably made of silicon oxide and can be formed by thermal oxidation. The insulating film TZ1 is formed in the region on the surface of the epitaxial layer EP where the insulating film SZ is not formed (i.e., the exposed surface of the epitaxial layer EP). Therefore, the surface of the epitaxial layer EP of the semiconductor substrate SUB has a region where the insulating film TZ1 is formed and a region where the insulating film SZ is formed, with the insulating film TZ1 formed adjacent to the insulating film SZ.

[0068] Next, as Figure 7 As shown, a silicon film PS is formed on the main surface of the semiconductor substrate SUB and thus on insulating films TZ1 and SZ, serving as a conductive film (conductor film) for the gate electrode GE. The silicon film PS is made of, for example, polycrystalline silicon and can be formed using methods such as CVD. In the region where the insulating film SZ is formed on the surface of the epitaxial layer EP, the silicon film PS is formed on the insulating film SZ, and in the region where the insulating film TZ1 is formed on the surface of the epitaxial layer EP, the silicon film PS is formed on the insulating film TZ1. In the region forming the device separation region, the silicon film PS is formed on the device separation region.

[0069] Next, as Figure 8 As shown, a photoresist pattern RP1 is formed on a silicon film PS. The photoresist pattern RP1 is then used as an etching mask to etch the silicon film PS. Therefore, the silicon film PS on the source side is removed.

[0070] Next, as Figure 9 As shown, p-type impurities are introduced into the epitaxial layer EP of the semiconductor substrate SUB via ion implantation using a photoresist pattern RP1 as a mask and a silicon film PS, and a p-type semiconductor region PW is formed in the epitaxial layer EP of the semiconductor substrate SUB. Diagonal ion implantation is used for this ion implantation. Therefore, in the plan view, a portion of the p-type semiconductor region PW overlaps with the gate electrode GE, and thus, this portion of the p-type semiconductor region PW exists below the gate electrode GE. Subsequently, the photoresist pattern RP1 is removed.

[0071] Next, as Figure 10 As shown, a photoresist pattern RP2 is formed on a silicon film PS. The p-type semiconductor region PW is covered by the photoresist pattern RP2. The photoresist pattern RP2 is then used as an etching mask to etch the silicon film PS. Therefore, the silicon film PS on the drain side is removed. The photoresist pattern RP2 is then removed, and... Figure 11The steps are illustrated. A silicon film PS is patterned using photoresist pattern RP1 and photoresist pattern RP2 to form a gate electrode GE. The gate electrode GE is made from the patterned silicon film PS. The source-side end (side surface) of the gate electrode GE is formed by etching using photoresist pattern RP1, and the drain-side end (side surface) of the gate electrode GE is formed by etching using photoresist pattern RP2. The remaining insulating film TZ1 below the gate electrode GE becomes the aforementioned insulating film TZ. The gate electrode GE is formed on the epitaxial layer EP of the semiconductor substrate SUB via the insulating films TZ and SZ.

[0072] Next, as Figure 12 As shown, the n-type drain region DR and n-type source region SR are formed by introducing n-type impurities into the epitaxial layer EP of the semiconductor substrate SUB using an ion implantation method. The p-type semiconductor region BC is formed by introducing p-type impurities into the epitaxial layer EP of the semiconductor substrate SUB using an ion implantation method. In the epitaxial layer EP, the n-type source region SR and the p-type semiconductor region BC are formed in the p-type semiconductor region PW, and the n-type drain region DR is formed in the n-type semiconductor region NW. The n-type drain region DR and the n-type source region SR can be formed by the same ion implantation step or by different ion implantation steps.

[0073] Next, as Figure 13 As shown, a sidewall spacer SW is formed on the sidewall of the gate electrode GE. For example, an insulating film used to form the sidewall spacer SW is formed on the main surface of a semiconductor substrate SUB using a CVD method or similar technique to cover the gate electrode GE. The sidewall spacer SW is then formed by etching the insulating film back and forth using an anisotropic etching technique. The sidewall spacer SW formed on the sidewall of the gate electrode GE is located on the insulating film SZ. That is, the bottom surface of the sidewall spacer SW (whose side surface is in contact with the gate electrode GE) is in contact with the upper surface of the insulating film SZ. After forming the sidewall spacer SW, one or both of an n-type drain region DR and an n-type source region SR can also be formed. Furthermore, an LDD (lightly doped drain) structure can be applied to the n-type source region SR.

[0074] Next, as Figure 14 As shown, the insulating film IL, serving as an interlayer insulating film, is formed on the main surface of the semiconductor substrate SUB by methods such as CVD, i.e., on the epitaxial layer EP, to cover the gate electrode GE and the sidewall spacers SW. After the insulating film IL is formed, its upper surface can be polished and planarized using methods such as CMP (chemical mechanical polishing).

[0075] Next, as Figure 15As shown, the insulating film IL is etched by using a photoresist pattern (not shown) formed on the insulating film IL as an etching mask, thereby forming a contact hole (through hole) in the insulating film IL. Then, a conductive plug PG, serving as a conductor portion for connection, is formed in the contact hole.

[0076] For example, after forming a barrier conductor film on an insulating film IL including the bottom surface and sidewalls(s) of the contact hole, a main conductor film (e.g., a tungsten film) is formed on the barrier conductor film, thereby filling the interior of the contact hole. Subsequently, the unwanted main conductor film and barrier conductor film outside the contact hole are removed by a CMP method or the like. This allows the plug PG to be formed.

[0077] Next, as Figure 16 As shown, wiring M1 is formed on an insulating film IL with an embedded plug PG. For example, a conductive film for forming wiring M1 is formed on the insulating film IL with the embedded plug PG; the conductive film is then patterned using photolithography and etching techniques; and wiring M1 made of the patterned conductive film can be formed. Illustrations and descriptions of subsequent steps are omitted here.

[0078] <Main Features and Effects>

[0079] Figure 17 This is a cross-sectional view of the main part of the semiconductor device in this embodiment, and Figure 1 A portion is magnified and shown. When a voltage (potential) equal to or higher than the threshold voltage is applied to the gate electrode GE, a channel (n-type inversion layer) CH is formed in the upper portion (upper layer portion) of the p-type semiconductor region PW located below the gate electrode GE. However, this channel CH... Figure 17 The diagram is shown using dotted shading. When the channel CH is formed, the n-type source region SR and the n-type drain region DR are turned on through the channel CH and the n-type semiconductor region NW.

[0080] The semiconductor device of this embodiment includes: an n-type source region SR and an n-type drain region DR formed separately in a semiconductor substrate SUB; a p-type semiconductor region PW (first semiconductor region) formed in the semiconductor substrate SUB surrounding the n-type source region SR; and a gate electrode GE formed on the semiconductor substrate SUB between the n-type source region SR and the n-type drain region DR via an insulating film GF (gate insulating film).

[0081] One of the key features of this embodiment is that the insulating film GF, which serves as the gate insulating film, has an insulating film TZ (first gate insulating film) and an insulating film SZ (second gate insulating film) adjacent to each other in a plan view. In the gate length direction of the gate electrode GE, the insulating film TZ (first gate insulating film) is located on the n-type source region SR side, and the insulating film SZ (second gate insulating film) is located on the n-type drain region DR side. The insulating film TZ (first gate insulating film) is thinner than the insulating film SZ (second gate insulating film). The insulating film SZ (second gate insulating film) is composed of a stack of films, including: a silicon oxide film OX1 (first insulating film) on the semiconductor substrate SUB; a silicon nitride film NT (second insulating film) on the silicon oxide film OX1; and a silicon oxide film OX2 (third insulating film) on the silicon nitride film NT. The band gaps of both the silicon oxide film OX1 (first insulating film) and the silicon oxide film OX2 (third insulating film) are larger than the band gap of the silicon nitride film NT (second insulating film).

[0082] Here, unlike in this embodiment, it is assumed that the insulating film SZ is composed of a single-layer insulating film (e.g., silicon oxide film) without changing the overall thickness. When a potential (here, a positive potential) is applied to the gate electrode GE to turn on the LDMOSFET, and a high potential (here, a positive high voltage) is applied to the n-type drain region DR, electron-hole pairs are formed at the electric field concentration point through collisional ionization. The resulting charge carriers (charge, e.g., electrons) can be injected into the gate electrode GE through the insulating film GF, and such injection causes the insulating film GF, which has already been degraded by the charge carriers, to operate and reduce the reliability of the insulating film GF. For example, the degradation of the insulating film GF can easily lead to leakage between the gate electrode GE and the semiconductor substrate SUB, resulting in a decrease in the reliability of the semiconductor device. Therefore, in order to improve the reliability of the semiconductor device, it is desirable to suppress the phenomenon of charge carriers generated by collisional ionization being injected into the gate electrode GE through the insulating film GF.

[0083] Conversely, in this embodiment, the insulating film GF, which serves as the gate insulating film, has insulating films TZ and SZ that are adjacent to each other in a plan view. The insulating film SZ located on the n-type drain region DR side is composed of a stack of films, which includes: a silicon oxide film OX1 (first insulating film) on the semiconductor substrate SUB; a silicon nitride film NT (second insulating film) on the silicon oxide film OX1; and a silicon oxide film OX2 (third insulating film) on the silicon nitride film NT.

[0084] As described above, charge carriers (charges, e.g., electrons) generated by impact ionization are injected into the gate electrode GE through the insulating film SZ. However, the band gaps of each of the silicon oxide films OX1 (first insulating film) and OX2 (third insulating film) are larger than the band gap of the silicon nitride film NT (second insulating film). Therefore, in the insulating film SZ, the barrier height of the inner layer (here, silicon nitride NT) serving as the charge retention portion is lower than the barrier height of the outer layers (here, silicon oxide films OX1 and OX2) serving as the charge blocking layers, and a potential well is formed. Therefore, even if charge carriers (charges, e.g., electrons) generated by impact ionization pass through (tunnel) the silicon oxide film OX1 (first insulating film) from the semiconductor substrate SUB and enter the silicon nitride film NT (second insulating film), the charge carriers have difficulty overcoming the barrier between the silicon oxide film OX2 (third insulating film) and the silicon nitride film NT (second insulating film), and the charge carriers are retained by the silicon nitride film NT. This allows for the suppression or prevention of charge carriers generated by impact ionization being injected into the gate electrode GE through the insulating film SZ. Therefore, the degradation of the insulating film GF(SZ) due to the passage of charge carriers can be suppressed or prevented, thereby improving the reliability of the insulating film GF and the overall reliability of the semiconductor device. For example, the increase in leakage current caused by the degradation of the insulating film GF can be suppressed or prevented.

[0085] For example, in Figure 17 In the process, electron-hole pairs are generated at the portion HE indicated by the asterisk (*) by collisional ionization, and the charge carriers (charges, e.g., electrons) CR generated by the electron-hole pairs pass through the silicon oxide film OX1, are injected into the silicon nitride film NT, and are retained by the silicon nitride film NT without passing through the silicon oxide film OX2. Figure 17 This state is illustrated schematically.

[0086] Furthermore, impact ionization is more likely to occur in regions of concentrated electric field, and more likely in regions closer to the n-type drain region DR than in regions closer to the n-type source region SR. Therefore, in the planar view of adjacent insulating films TZ and SZ, the insulating film SZ located on the n-type drain region DR side is more susceptible to the effects of charge carriers generated by impact ionization than the insulating film TZ located on the n-type source region SR side.

[0087] Therefore, in this embodiment, the insulating film SZ located on the n-type drain region DR side of the insulating film TZ and the insulating film SZ adopts the following structure: a silicon nitride film NT (second insulating film) with a relatively small band gap is sandwiched between silicon oxide films OX1 and OX2 (first and third insulating films) with relatively large band gaps, respectively. This allows the phenomenon of charge carriers generated by impact ionization being injected into the gate electrode GE through the insulating film SZ to suppress or prevent such injection, thereby enhancing the reliability of the insulating film GF as the gate insulating film and improving the reliability of the semiconductor device. Simultaneously, there is less concern about the phenomenon of charge carriers generated by impact ionization being injected into the gate electrode GE through the insulating film TZ and the insulating film TZ located on the n-type source region SR side of the insulating film SZ. Therefore, in this embodiment, the thickness of the insulating film TZ located on the n-type source region SR side is thinner than the thickness of the insulating film SZ located on the n-type drain region DR side. Reducing the thickness of the insulating film TZ located on the SR side of the n-type source region facilitates the formation of a channel CH beneath the insulating film TZ in the semiconductor substrate SUB. This makes it easier to control the LDMOSFET and, for example, reduces the threshold voltage of the LDMOSFET.

[0088] An insulating film TZ is inserted between the channel formation region (channel CH) of the LDMOSFET and the gate electrode GE. The gate insulating film SZ is preferably not disposed between the channel formation region (channel CH) of the LDMOSFET and the gate electrode GE. Therefore, instead of a thick insulating film SZ, a thinner insulating film TZ exists on the channel formation region (channel CH). Thus, the channel CH is easily formed by applying a voltage to the gate electrode GE, and the threshold voltage of the LDMOSFET can be effectively reduced. That is, reducing the thickness of the gate insulating film on the channel formation region has the effect of reducing the threshold voltage, and in this embodiment, instead of disposing the insulating film SZ on the channel formation region, a thinner insulating film TZ is disposed on the channel formation region to reduce the threshold voltage. Incidentally, the channel formation region is the region where the channel CH is formed when a voltage equal to or higher than the threshold voltage is applied to the gate electrode GE to turn on the LDMOSFET. Figure 17 It can be seen that the upper part of the p-type semiconductor region PW (first semiconductor region) between the n-type source region SR and the n-type drain region DR corresponds to the channel formation region.

[0089] Furthermore, in the gate length direction of the gate electrode GE, the connection portion (adjacent position) CP between the insulating film TZ and the gate insulating film SZ is located on the n-type drain region DR side of the channel formation region. Specifically, in the gate length direction of the gate electrode GE, the connection portion (adjacent position) CP between the insulating film TZ and the gate insulating film SZ is located closer to the n-type drain region DR side than the channel formation region. Specifically, in the gate length direction of the gate electrode GE, the connection portion (adjacent position) CP between the insulating film TZ and the gate insulating film SZ is not located on the channel formation region (correspondingly not on the p-type semiconductor region PW), but on the n-type semiconductor region NW. Therefore, instead of a thick insulating film SZ, a thinner insulating film TZ exists on the channel formation region (channel CH), making it easier to form the channel CH by applying a voltage to the gate electrode GE and effectively reducing the threshold voltage of the LDMOSFET.

[0090] Furthermore, the insulating film TZ is preferably made of a single layer of insulating film. This allows for precise reduction of the thickness of the insulating film TZ and facilitates control over its thickness. More preferably, the insulating film TZ is composed of a single layer of silicon oxide film, and in this case, the reliability of the insulating film TZ used as the gate insulating film can be further improved.

[0091] Furthermore, considering that insulating films TZ and SZ are adjacent to each other in a plan view and that SZ is thicker than TZ, a step (height difference of the upper surface position) exists at the connection portion (adjacent position) CP between TZ and SZ. The step at the connection portion CP is covered by the gate electrode GE.

[0092] Furthermore, in this embodiment, the insulating film SZ adopts a structure in which an intermediate layer (silicon nitride film NT) with a relatively small band gap is sandwiched between an upper layer (silicon oxide film OX1) and a lower layer (silicon oxide film OX2) with relatively large band gaps. To achieve this, the silicon nitride film NT is used as the intermediate layer with a relatively small band gap, and the silicon oxide films OX1 and OX2 are used as the upper and lower layers with relatively large band gaps. Alternatively, in the insulating film SZ, films other than the silicon nitride film can be used as the intermediate layer with a relatively small band gap, while films other than the silicon oxide film can be used as the upper and lower layers with relatively large band gaps. Even in that case, even if charge carriers generated by impact ionization pass through the lower layer of the insulating film SZ and are injected into the intermediate layer of the insulating film SZ, the charge carriers have difficulty overcoming the potential barrier between the intermediate and upper layers of the insulating film SZ, and the charge carriers are retained in the intermediate layer. This allows for the suppression or prevention of charge carriers generated by impact ionization being injected into the gate electrode GE through the insulating film SZ, thereby improving the reliability of the insulating film GF and the reliability of the semiconductor device.

[0093] However, silicon oxide and silicon nitride films are readily formed to achieve good film quality. Therefore, more preferably, in the insulating film SZ, the silicon nitride film NT serves as an intermediate layer with a relatively small band gap, and the silicon oxide films OX1 and OX2 serve as the upper and lower layers with relatively large band gaps. Thus, the reliability of the insulating film GF can be further improved, thereby further enhancing the reliability of the semiconductor device. Furthermore, the insulating film SZ can be readily formed.

[0094] Next, we will refer to Figure 17 The illustrations show various sizes, but the invention is not limited thereto.

[0095] The channel length CHL can be, for example, about 0.15 μm to 0.3 μm. Furthermore, the length GA of the insulating film TZ (the length of the gate electrode GE in the gate length direction) located beneath the gate electrode GE can be, for example, about 0.4 μm to 0.7 μm. The length GA increases (lengthens) as the breakdown voltage of the LDMOSFET increases. Additionally, the distance SP (the distance of the gate electrode GE in the gate length direction) from the connection portion CP between the insulating film TZ and the gate insulating film SZ to the n-type drain region DR can be, for example, about 0.2 μm to 1.5 μm. The distance SP increases (lengthens) as the breakdown voltage of the LDMOSFET increases. Furthermore, the length FP of the insulating film SZ (the length of the gate electrode GE in the gate length direction) located beneath the gate electrode GE can be varied according to the required characteristics of the LD MOSFET and can be set, for example, to approximately half the distance SP.

[0096] (Second Embodiment)

[0097] Figure 18 This is a cross-sectional view of the main portion of the semiconductor device according to the second embodiment, and is consistent with the above description. Figure 1 Correspondingly.

[0098] Second embodiment ( Figure 18 The semiconductor device of the first embodiment is similar to the semiconductor device of the first embodiment in the following aspects. Figure 1 The semiconductor devices are different. That is, Figure 18 The semiconductor device of the second embodiment shown includes not only the aforementioned plugs PGS, PGD and PGB, but also a plug (contact plug) PG1 for connecting it to the insulating film SZ, as plug PG.

[0099] In the gate length direction of the gate electrode GE, a plug PG1 is arranged between the n-type drain region DR and the gate electrode GE. The plug PG1 can serve as a field plate (field plate electrode). The plug PG1 is embedded in a contact hole (through hole) CT1 formed in the insulating film IL.

[0100] The insulating film SZ has: a portion that overlaps with the gate electrode GE in a plan view (i.e., the portion located below the gate electrode GE); and a portion that does not overlap with the gate electrode GE in a plan view (i.e., the portion protruding from the gate electrode GE along the direction of the n-type drain region DR). In the plan view, the plug PG1 is formed in the portion of the insulating film SZ that does not overlap with the gate electrode GE. In other words, the plug PG1 is formed in the portion of the insulating film SZ that is exposed from the gate electrode GE but not covered by the gate electrode GE.

[0101] The contact hole CT1, into which the plug PG1 is embedded, penetrates not only the insulating film IL but also the silicon oxide film OX2 of the insulating film SZ, and reaches the silicon nitride film NT of the insulating film SZ. In other words, the silicon oxide film OX2 has an opening OP communicating with the contact hole CT1 of the insulating film IL, and the silicon nitride film NT is exposed from the opening OP of the silicon oxide film OX2. The opening OP is an opening formed in the silicon oxide film OX2 to expose a portion of the silicon nitride film NT, but the portion formed in the silicon oxide film OX2 within the contact hole CT1 is also referred to as the opening OP. The plug PG1 is embedded in the contact hole CT1 of the insulating film IL and the opening OP of the silicon oxide film OX2, and the plug PG1 is connected to the silicon nitride film NT via the opening OP of the silicon oxide film OX2. That is, the bottom surface of the plug PG1 is connected to the silicon nitride film NT exposed from the opening OP of the silicon oxide film OX2, and more specifically, the bottom surface of the plug PG1 is in contact with the silicon nitride film NT exposed from the opening OP of the silicon oxide film OX2. In addition, plug PG1 is electrically connected to wiring M1 (M1F).

[0102] The semiconductor device of the second embodiment ( Figure 18 Another configuration of the semiconductor device in the first embodiment ( Figure 1 The configurations are almost identical, so repeated descriptions will be omitted here.

[0103] The semiconductor device of the second embodiment further includes a plug PG1 for connection to the insulating film SZ, and the plug PG1 is connected to the silicon nitride film NT via an opening OP in the silicon oxide film OX2. Therefore, when charge carriers generated by impact ionization are injected into the silicon nitride film NT through the silicon oxide film OX1 and retained by the silicon nitride film NT without passing through the silicon oxide film OX2, the charge carriers (charge) retained in the silicon oxide film OX2 can be extracted from the silicon oxide film OX2 through the plug PG1. Therefore, the amount of charge accumulated in the silicon nitride film NT of the insulating film SZ can be suppressed, allowing the accumulated charge in the silicon nitride film NT of the insulating film SZ to suppress or prevent it from affecting the operation of the LDMOSFET. Therefore, the reliability of the semiconductor device can be further improved.

[0104] Furthermore, since the plug PG1 can also be used as a field plate, the electric field mitigation effect caused by the plug PG1 can also be obtained. Therefore, the performance of semiconductor devices with LDMOSFETs can be improved.

[0105] (Third Embodiment)

[0106] Figure 19 This is a cross-sectional view of the main portion of the semiconductor device according to the third embodiment, and is consistent with the above description. Figure 1 and Figure 18 Correspondingly.

[0107] Third embodiment ( Figure 19 The semiconductor device of the first embodiment is similar to the semiconductor device of the first embodiment in the following aspects. Figure 1 The semiconductor devices are different. That is, such as... Figure 19 As shown, the semiconductor device of the third embodiment includes not only the aforementioned plugs PGS, PGD, and PGB, but also a plug (contact plug) PG2 for connecting it to the insulating film SZ as plug PG. Figure 19 As shown, the semiconductor device of the third embodiment also has an insulating film SC, which partially covers the insulating film SZ exposed from the gate electrode GE.

[0108] In the gate length direction of the gate electrode GE, a plug PG2 is arranged between the n-type drain region DR and the gate electrode GE. The plug PG2 can serve as a field plate (field plate electrode). The plug PG2 is embedded in a contact hole (through hole) CT2 formed in the insulating film IL.

[0109] The insulating film SZ has: a portion overlapping the gate electrode GE in a plan view (i.e., the portion located below the gate electrode GE); and a portion not overlapping the gate electrode GE in a plan view (i.e., the portion protruding from the gate electrode GE along the direction of the n-type drain region DR). In the plan view, the plug PG2 is formed within the portion of the insulating film SZ that does not overlap with the gate electrode GE. In other words, the plug PG2 is formed in the portion of the insulating film SZ that is exposed from the gate electrode GE but not covered by it. Furthermore, in the plan view, the insulating film SC is formed in the portion of the insulating film SZ that does not overlap with the gate electrode GE. In other words, the insulating film SC is formed in the portion of the insulating film SZ that is exposed from the gate electrode GE but not covered by it. Furthermore, the plug PG is electrically connected to wiring M1 (M1F).

[0110] In the plan view, the contact hole CT2 partially overlaps with the insulating film SC, and therefore, the plug PG2 also partially overlaps with the insulating film SC. In the portion not covered by the insulating film SC, the silicon oxide film OX2 of the insulating film SC and the insulating film SZ is exposed at the bottom of the contact hole CT2. Therefore, a portion of the bottom of the plug PG2 is connected to the silicon oxide film OX2 of the insulating film SZ, and another portion of the bottom of the plug PG2 is connected to the insulating film SC. That is, a portion of the bottom of the plug PG2 contacts the portion of the silicon oxide film OX2 of the insulating film SZ that is not covered by the insulating film SC, and another portion of the bottom of the plug PG2 contacts the insulating film SC. In other words, the bottom of the plug PG2 has the following portions: the portion located on the silicon oxide film OX2 of the insulating film SZ that is not covered by the insulating film SC, and the portion located on the insulating film SC.

[0111] The upper surface of the insulating film SC on the silicon oxide film OX2 is at a higher elevation than the upper surface of the silicon oxide film OX2. Therefore, a step is formed on the bottom surface of the plug PG2, and the portion of the bottom surface of the plug PG2 that connects (contacts) the insulating film SC is higher than the portion that connects (contacts) the silicon oxide film OX2. On the bottom surface of the plug PG2, the portion that connects (contacts) the silicon oxide film OX2 is located on the gate electrode GE side, while the portion that connects (contacts) the insulating film SC is located on the n-type drain region DR side. Therefore, on the bottom surface (bottom) of the plug PG2, the portion on the n-type drain region DR side (i.e., the portion connected to the silicon oxide film OX2) is at a higher position than the portion on the gate electrode GE side (i.e., the portion connected to the silicon oxide film OX2).

[0112] Here, the insulating film SC can be a silicide barrier film. A silicide barrier film corresponds to a film used to cover the areas (semiconductor regions) where the formation of a metal silicide layer should be prevented when forming a metal silicide layer using self-aligned silicide technology.

[0113] Third embodiment ( Figure 19 Another configuration of the semiconductor device compared to the first embodiment ( Figure 1 The configurations of the semiconductor devices are basically the same, so their repeated descriptions will be omitted here.

[0114] The semiconductor device of the third embodiment also includes a plug PG2 for connecting the insulating film SC and the silicon oxide film OX2 in a portion not covered by the insulating film SC. Since the plug PG2 can act as a field plate, an electric field mitigation effect can be achieved due to the plug PG2. Regarding the height position of the bottom surface (bottom) of the plug PG2, the portion on the DR side of the n-type drain region (i.e., the portion connected to the silicon oxide film OX2) is located at a higher position than the portion on the GE side of the gate electrode (i.e., the portion connected to the silicon oxide film OX2). Therefore, the distance from the semiconductor substrate SUB (epipolar layer EP) to the plug PG2 is set such that the portion on the DR side of the n-type drain region (i.e., the portion connected to the silicon oxide film OX2) on the bottom surface of the plug PG2 is greater than the portion on the GE side of the gate electrode (i.e., the portion connected to the silicon oxide film OX2). Since the plug PG2 acts as a field plate, the electric field mitigation effect can be further enhanced. Therefore, the performance of the semiconductor device with the LDMOSFET can be further improved.

[0115] As described above, the invention made by the inventors has been specifically described based on embodiments of the present invention. However, the present invention is not limited to the above embodiments, and it is obvious that various modifications can be made without departing from the scope of the present invention.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; The source region and the drain region of the first conductivity type of the MISFET are formed in the semiconductor substrate and are separated from each other. A first semiconductor region of a second conductivity type is formed in the semiconductor substrate, surrounding the source region, wherein the second conductivity type is opposite to the first conductivity type. as well as For the gate electrode of the MISFET, the gate electrode is formed on the semiconductor substrate between the source region and the drain region via a gate insulating film. The gate insulating film has a first gate insulating film and a second gate insulating film that are adjacent to each other in a plan view. In the gate length direction of the gate electrode, the first gate insulating film is located on the source region side, and the second gate insulating film is located on the drain region side. The first gate insulating film is thinner than the second gate insulating film. The second gate insulating film is made of a stacked film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film. The band gaps of the first insulating film and the third insulating film are larger than the band gap of the second insulating film. The semiconductor device further includes a first contact plug for connection to the second gate insulating film. The third insulating film has a first opening, which is formed to expose a portion of the second insulating film, and The first contact plug is connected to the second insulating film via the first opening.

2. The semiconductor device according to claim 1, The first gate insulating film is composed of a single layer of insulating film.

3. The semiconductor device according to claim 1, The MISFET mentioned therein is an LDMOSFET.

4. The semiconductor device according to claim 1, The first gate insulating film is inserted between the channel formation region of the MISFET and the gate electrode.

5. The semiconductor device according to claim 4, The second gate insulating film is not disposed between the channel forming region and the gate electrode.

6. The semiconductor device according to claim 5, The upper portion of the first semiconductor region between the source region and the drain region is the channel formation region.

7. The semiconductor device according to claim 4, In the gate length direction of the gate electrode, the connection portion between the first gate insulating film and the second gate insulating film is located closer to the drain region side than the channel forming region side.

8. The semiconductor device of claim 1, further comprising a second semiconductor region of a first conductivity type, wherein the second semiconductor region of the first conductivity type is inserted between the first semiconductor region and the drain region in the gate length direction of the gate electrode. The impurity concentration in the second semiconductor region is lower than that in the drain region.

9. The semiconductor device according to claim 1, The first insulating film and the third insulating film are each made of silicon oxide film, and The second insulating film is made of silicon nitride film.

10. The semiconductor device according to claim 9, The first insulating film has a thickness of 5 nm or more and 15 nm or less. The second insulating film has a thickness of 5 nm or more and 15 nm or less, and The third insulating film has a thickness of 5 nm or more and 15 nm or less.

11. The semiconductor device according to claim 9, The first gate insulating film is made of silicon oxide film.

12. The semiconductor device according to claim 11, The first gate insulating film has a thickness of 4 nm or more and 20 nm or less.

13. The semiconductor device according to claim 1, The connection between the first gate insulating film and the second gate insulating film has a step.

14. The semiconductor device according to claim 13, The step is covered by the gate electrode.

15. The semiconductor device of claim 1, further comprising sidewall spacers formed on the side surface of the gate electrode. The first sidewall spacer formed on the source region side is located on the semiconductor substrate, and the second sidewall spacer formed on the drain region side is located on the second gate insulating film.

16. The semiconductor device according to claim 1, further comprising: The second contact plug is connected to the second gate insulating film; as well as A fourth insulating film is formed to partially cover the second gate insulating film exposed from the gate electrode. A portion of the bottom of the second contact plug is connected to the third insulating film, and another portion of the bottom of the second contact plug is connected to the fourth insulating film.

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