A diffused high-voltage fast soft-recovery diode and a method for manufacturing the same

Abstract

The application discloses a diffusion type high-voltage fast soft recovery diode and a manufacturing method thereof. A N-base region is used as a substrate, and P+ / P doped regions are alternately arranged on the anode side of the N-base region and are formed by boron pre-deposition and AL diffusion respectively; the N-base region is a voltage resistance region; a P buffer layer is arranged between the anode P+ region and the N-base region; high-concentration N+ regions and slightly low-concentration P+ regions are alternately arranged on the cathode side; and a medium-doped-concentration N buffer layer is arranged between the N+ / P+ regions on the cathode side and the N-base region. An anode is arranged above the anode region, and a cathode is arranged below the cathode region. The application further discloses a preparation method of the diffusion type high-voltage fast soft recovery diode. The high-voltage fast soft recovery diode has the advantages of fast reverse recovery speed, large softness, simple process and low cost.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device manufacturing technology, and relates to a diffused high-voltage fast soft recovery diode and its manufacturing method. Background Technology

[0002] As DC power grids develop towards higher efficiency, higher density, higher reliability, and lower cost, pressure-connected IGBTs and IGCTs for medium and high voltage DC transmission are further developed. This places higher demands on the performance of large-size, circular freewheeling diodes connected in anti-parallel. These diodes are required to have high withstand voltage, low leakage current, fast soft recovery characteristics, and high resistance to dynamic avalanche.

[0003] To improve the fast soft recovery characteristics of high-voltage diodes, the anode P+ / P and cathode N+ / P+ region structures are combined, such as... Figure 1 As shown, during reverse recovery, the P+ region injects holes into the N- junction, maintaining the tail current at the end of the reverse recovery period. Typically, cathode structures with P+ regions are used in small-size, prismatic diodes, where the N+ and P+ regions are selectively formed via ion implantation, which is costly. Forming selective P+ regions in large-size, wafer-level high-voltage diodes requires not only additional photolithography processes but also high ion implantation energy and lengthy annealing to achieve the desired junction depth. Therefore, the process is complex and costly. Developing high-performance, low-cost high-voltage fast soft recovery diodes is urgently needed. Summary of the Invention

[0004] The purpose of this invention is to provide a diffused high-voltage fast soft recovery diode and its manufacturing method. This overcomes the shortcomings of existing high-voltage diodes, such as poor reverse recovery characteristics, complex processes, and high costs.

[0005] The technical solution of this invention is a diffusion-type high-voltage fast soft recovery diode, using an N-base region as a substrate. P+ and P regions are alternately formed on the anode side above the N-base region, respectively through boron pre-deposition and Al diffusion. The N-region serves as the breakdown voltage region. A P-buffer layer is disposed between the anode P+ and N-regions. High-concentration N+ regions and slightly lower-concentration P+ regions are alternately disposed on the cathode side. A moderately doped N-buffer layer is disposed above the N+ and P+ regions on the cathode side. An anode A is located above the anode region, and a cathode K is located below the cathode region.

[0006] The P+ regions on the anode and cathode sides are identical in size, and their positions correspond. The width of the P+ region occupies 1 / 4 to 1 / 3 of the width of the anode and cathode, respectively. The doping concentration of the P+ regions on both the anode and cathode sides is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The depths are all 2–5 μm.

[0007] A method for manufacturing a diffused high-voltage fast soft recovery diode, comprising the following steps:

[0008] (1) Select the original defect-free, dislocation-free, high-resistivity zone-melted single-crystal silicon wafer as the substrate material for the N-region;

[0009] (2) After cleaning the silicon wafer, aluminum is pre-deposited on both sides of the silicon single crystal wafer at a temperature of 900–1100℃ to form a shallow junction P + N - P + structure;

[0010] (3) The silicon wafer in step (2) is marked to distinguish between the anode and cathode. Then, the aluminum pre-deposited on the cathode surface is etched away to a depth of 5-10 μm to form a shallow junction P + N - structure;

[0011] (4) The silicon wafer in step (3) is oxidized at a temperature of 900 to 1200°C for 2 to 5 hours. The resulting silicon dioxide layer is used as a masking layer for subsequent phosphorus diffusion, with a thickness of 1 to 2 μm.

[0012] (5) Apply photoresist to the silicon wafer in step (4), expose and develop it to protect the anode silicon dioxide layer and remove the cathode silicon dioxide layer.

[0013] (6) Low-temperature phosphorus pre-deposition is performed on the cathode surface of the silicon wafer in step (5) at a temperature of 1000–1150°C, followed by high-temperature oxidation diffusion at a temperature of 1150–1250°C to form a deep junction PN junction. - N-structure, with N-type stratification depth of 20–40 μm;

[0014] (7) In step (6), P+ diffusion windows are photolithographically etched on the anode of the silicon wafer, and the cathode silicon dioxide layer is removed. Then, boron is pre-deposited on both sides at a low temperature of 900–1100℃ for 40–200 min to form a low-concentration boron with a junction depth of 2–5 μm, thus obtaining P+. + PN - NP + structure;

[0015] (8) The silicon wafer from step (7) is subjected to low-temperature oxidation at a temperature of 900 to 1100°C for 5 to 10 hours to form a silicon dioxide layer on the surface of the silicon wafer as a masking layer for subsequent phosphorus diffusion.

[0016] (9) In step (8), an N+ diffusion window is etched using a cathode photolithography technique on the silicon wafer. Then, phosphorus is pre-deposited at 1000–1150 °C for 1–2 hours. At this temperature and time, boron does not diffuse into the silicon wafer. Phosphorus has a higher impurity solid solubility and diffusion coefficient than boron, allowing the high concentration of phosphorus to completely compensate for the boron in step (7). The phosphorus depth is 5–15 μm, and the impurity concentration is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 The boron concentration was 2–5 μm and the concentration was 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Therefore, a regularly interlaced P+N+ structure is obtained on the cathode side;

[0017] (10) Aluminum is evaporated on both sides of the silicon wafer in step (9) with a thickness of 10-20 μm, and then metallized at a temperature of 400-600 °C.

[0018] (11) The silicon wafer from step (10) is laser-cut into a circular wafer with a diameter of 38-125mm. Then, the mesa is shaped, etched, and coated with adhesive for protection. This forms a complete chip and completes the initial measurement of the reverse blocking voltage.

[0019] (12) Irradiate the chip from step (11) with electrons and adjust the reverse recovery time t. rr The reverse recovery charge Q is 2–10 μs. rr The value ranges from 4000 to 10000 μAs, and a final measurement is performed.

[0020] Compared with existing conventional large-size wafer diode structures, the present invention has the following advantages:

[0021] (1) The P+ region on the surface of anode A corresponds to the P+ region on cathode K, and the P region on the surface of anode A corresponds to the N+ region on cathode K. The purpose is to improve the fast soft recovery characteristics of the high-voltage diode, such as... Figure 1 As shown.

[0022] (2) By rationally designing diffusion process conditions, the higher impurity solid solubility and diffusion coefficient of phosphorus are utilized to compensate for the boron in the cathode, resulting in a greater diffusion junction depth for phosphorus than for boron. This reduces process complexity, avoids the stepwise selective implantation of boron and phosphorus used in conventional processes, thus avoiding process errors caused by overlay precision, reducing the use of photomasks, and lowering manufacturing costs.

[0023] (3) Boron is pre-deposited at low temperature at both the anode and cathode, and after a long low-temperature oxidation process, the boron doping concentration of the anode is further reduced by utilizing the segregation effect of boron impurities in the silicon dioxide layer, which better controls the hole injection efficiency of the anode and obtains fast and soft recovery characteristics. Attached Figure Description

[0024] Figure 1 This is a cross-sectional view of the high-voltage fast soft recovery diode manufactured according to the present invention.

[0025] Figure 2 This is a schematic diagram of the doping distribution of the high-voltage fast soft recovery diode manufactured by this invention.

[0026] Figure 3 These are the manufacturing process steps for the high-voltage fast soft recovery diode manufactured according to the present invention. Detailed Implementation

[0027] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0028] The high-voltage fast soft recovery diode structure of the present invention is as follows: Figure 1 As shown, with N-region 3 as the substrate, P+ regions 21 and P-regions 22 are alternately arranged on the anode side above N-region 3, formed by boron pre-deposition and Al diffusion, respectively; N-region 3 is the withstand voltage region; a P buffer layer 22 is arranged between the anode P+ region 21 and N-region 3; a high-concentration N+ region 42 and a slightly lower-concentration P+ region 23 are alternately arranged on the cathode side; a medium-concentration N buffer layer 41 is arranged above the N+ region 42 and P+ region 23 on the cathode side. An anode A1 is arranged above the anode region, and a cathode K5 is arranged below the cathode region.

[0029] Figure 1 The P+ region 21 on the anode side and the P+ region 23 on the cathode side of the high-voltage fast soft recovery diode shown are identical in size, and their positions correspond. The width of the P+ region occupies 1 / 4 to 1 / 3 of the width of the anode and cathode, respectively. Since the anode and cathode P+ regions are formed using the same process, their doping concentration is 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 The depths are all 2–5 μm.

[0030] Figure 2 yes Figure 1 The diagram shows the doping distribution at the corresponding CC' and DD' longitudinal sections. The total device thickness is 500–1000 μm. The anode P-region junction depth is greater than the P+ junction depth, ranging from 60–120 μm; the junction depths of both the anode P+ and cathode P+ regions are 2–5 μm; the N-buffer layer is 20–40 μm deep; and the cathode N+ junction depth is 5–15 μm.

[0031] The working principle of the high-voltage fast soft recovery diode of this invention is as follows:

[0032] The cathode employs an alternating P+ / N+ structure. Holes are injected into the P+ region at the end of the reverse recovery phase, resulting in good reverse recovery softness. Below the anode P+ region, hole injection is strong; therefore, the cathode P+ region is positioned directly below the anode-side P+ region to achieve better softness. Conversely, below the anode P region, hole injection is weak, already providing good softness; therefore, the cathode N+ region is positioned directly below the anode-side P region. This design simultaneously balances surge characteristics and reverse recovery performance.

[0033] This invention provides a method for manufacturing a high-voltage fast soft recovery diode, specifically implemented according to the following steps: Figure 3 This is a schematic diagram of the corresponding manufacturing process.

[0034] (1) Select the original defect-free, dislocation-free, high-resistivity zone-melted single-crystal silicon wafer as the substrate material for the N-region;

[0035] (2) After cleaning the silicon wafer, aluminum is pre-deposited on both sides of the silicon single crystal wafer at a temperature of 900–1100℃ to form a shallow junction P + N - P + structure;

[0036] (3) The silicon wafer in step (2) is marked to distinguish between the anode and cathode. Then, the aluminum pre-deposited on the cathode surface is etched away to a depth of 5-10 μm to form a shallow junction P + N - structure;

[0037] (4) The silicon wafer in step (3) is oxidized at a temperature of 900 to 1200°C for 2 to 5 hours. The resulting silicon dioxide layer is used as a masking layer for subsequent phosphorus diffusion, with a thickness of 1 to 2 μm.

[0038] (5) Apply photoresist to the silicon wafer in step (4), expose and develop it to protect the anode silicon dioxide layer and remove the cathode silicon dioxide layer.

[0039] (6) Low-temperature phosphorus pre-deposition is performed on the cathode surface of the silicon wafer in step (5) at a temperature of 1000–1150°C, followed by high-temperature oxidation diffusion at a temperature of 1150–1250°C to form a deep junction PN junction. - N-structure, with N-type stratification depth of 20–40 μm;

[0040] (7) In step (6), P+ diffusion windows are photolithographically etched on the anode of the silicon wafer, and the cathode silicon dioxide layer is removed. Then, boron is pre-deposited on both sides at a low temperature of 900–1100℃ for 40–200 min to form a low-concentration boron with a junction depth of 2–5 μm, thus obtaining P+.+ PN - NP + structure;

[0041] (8) The silicon wafer from step (7) is subjected to low-temperature oxidation at a temperature of 900 to 1100°C for 5 to 10 hours to form a silicon dioxide layer on the surface of the silicon wafer as a masking layer for subsequent phosphorus diffusion.

[0042] (9) In step (8), an N+ diffusion window is etched using a cathode photolithography technique on the silicon wafer. Then, phosphorus is pre-deposited at 1000–1150 °C for 1–2 hours. At this temperature and time, boron does not diffuse into the silicon wafer. Phosphorus has a higher impurity solid solubility and diffusion coefficient than boron, allowing the high concentration of phosphorus to completely compensate for the boron in step (7). The phosphorus depth is 5–15 μm, and the impurity concentration is 5 × 10⁻⁶. 19 cm -3 ~5×10 20 cm -3 The boron concentration was 2–5 μm and the concentration was 5 × 10⁻⁶. 18 cm -3 ~1×10 19 cm -3 Therefore, a regularly interlaced P+N+ structure is obtained on the cathode side;

[0043] (10) Aluminum is evaporated on both sides of the silicon wafer in step (9) with a thickness of 10-20 μm, and then metallized at a temperature of 400-600 °C.

[0044] (11) The silicon wafer from step (10) is laser-cut into a circular wafer with a diameter of 38-125mm. Then, the mesa is shaped, etched, and coated with adhesive for protection. This forms a complete chip and completes the initial measurement of the reverse blocking voltage.

[0045] (12) Irradiate the chip from step (11) with electrons and adjust the reverse recovery time t. rr The reverse recovery charge Q is 2–10 μs. rr The value ranges from 4000 to 10000 μAs, and a final measurement is performed.

Claims

1. A method for manufacturing a diffused high-voltage fast soft recovery diode, characterized in that, Follow these steps: (1) Select original defect-free, dislocation-free, high-resistivity zone-melted single-crystal silicon wafers as the substrate material for the N-region; (2) After cleaning the silicon wafer, aluminum is pre-deposited on both sides of the monocrystalline silicon wafer at a temperature of 900~1100℃ to form a shallow junction P + N - P + structure; (3) The silicon wafer in step (2) is marked to distinguish between the anode and cathode. Then, the aluminum pre-deposited on the cathode surface is etched away to a depth of 5~10um to form a shallow junction P + N - structure; (4) The silicon wafer in step (3) is oxidized at a temperature of 900~1200℃ for 2~5h. The resulting silicon dioxide layer is used as a masking layer for subsequent phosphorus diffusion, with a thickness of 1~2um. (5) Apply photoresist to the silicon wafer in step (4), expose and develop it to protect the anode silicon dioxide layer and remove the cathode silicon dioxide layer; (6) Low-temperature phosphorus pre-deposition is performed on the cathode surface of the silicon wafer in step (5) at a temperature of 1000~1150℃, followed by high-temperature oxidation diffusion at a temperature of 1150~1250℃ to form a deep junction PN. - N-structure, with N-type stratification depth of 20~40um; (7) In step (6), P+ diffusion windows are photolithographically etched on the anode of the silicon wafer, and the cathode silicon dioxide layer is removed. Then, boron is pre-deposited on both sides at a low temperature of 900~1100℃ for 40~200min to form a low-concentration boron with a junction depth of 2~5um, thus obtaining P+. + PN - NP + structure; (8) The silicon wafer from step (7) is subjected to low-temperature oxidation at a temperature of 900~1100℃ for 5~10h to form a silicon dioxide layer on the surface of the silicon wafer as a masking layer for subsequent phosphorus diffusion. (9) In step (8), an N+ diffusion window is etched using a cathode photolithography technique on the silicon wafer. Then, phosphorus is pre-deposited at 1000~1150℃ for 1~2 hours. At this temperature and time, boron does not diffuse into the silicon wafer. Phosphorus has a higher impurity solid solubility and diffusion coefficient than boron, so that the high concentration of phosphorus completely compensates for the boron in step (7). The phosphorus depth is 5~15 μm, and the impurity concentration is 5×10⁻⁶. 19 cm -3 ~5×10 20 cm -3 The boron concentration was 2-5 μm and the depth was 5 × 10⁻⁶ μm. 18 cm -3 ~1×10 19 cm -3 Therefore, a regularly interlaced P+N+ structure is obtained on the cathode side; (10) In step (9), aluminum is evaporated on both sides of the silicon wafer to a thickness of 10~20um, and then metallized at a temperature of 400~600℃; (11) The silicon wafer from step (10) is laser-cut into a circular wafer with a diameter of 38~125mm. Then, the mesa is shaped, etched and coated with adhesive for protection. This forms a complete chip and completes the initial measurement of the reverse blocking voltage. (12) Irradiate the chip from step (11) with electrons and adjust the reverse recovery time t. rr The reverse recovery charge Q is 2~10µs. rr The values ​​range from 4000 to 10000 uAs, and a final test is then conducted.

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