Multilayer arrangement of integrated devices and method of forming sensing / access lines

Abstract

Some embodiments include an arrangement having a memory layer having memory cells on opposite sides of a coupling region. A first sense / access line is below the memory cell and electrically connected to the memory cell. A conductive interconnect is within the coupling region. A second sense / access line extends across the memory cell and across the conductive interconnect. The second sense / access line has a first region with a second conductive material above the first conductive material and has a second region with only the second conductive material. The first region is above the memory cell and electrically connected to the memory cell. The second region is above the conductive interconnect and electrically coupled to the conductive interconnect. An additional layer is below the memory layer and includes CMOS circuitry coupled to the conductive interconnect. Some embodiments include a method of forming a multilayer arrangement.

Description

[0001] Related patent data

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application Serial No. 16 / 400,572, filed on May 1, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to multi-layer arrangements of integrated devices and methods of forming sense / access lines. Background Art

[0004] Efforts are made to form multi-layer arrangements of integrated devices. For example, a layer including memory may be formed above a layer including drivers, sense amplifiers, etc. It may be desirable to form sense / access lines (e.g., bit lines) that couple with memory devices in the upper layer and also couple with components in the lower layer through interconnects extending through the upper layer. It would be desirable to develop structures that are specifically configured for such applications, and to develop methods of forming such structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a diagrammatic cross-sectional side view of an example assembly including an example arrangement of memory cells.

[0006] Figure 1A yes Figure 1 A diagrammatic top view of a region of an assembly. Figure 1 The cross section along Figure 1A Line 1-1.

[0007] Figure 1B It is replaceable Figure 1 Schematic cross-sectional side view of an example memory cell utilized by the example memory cell shown in .

[0008] Figure 2 is a diagrammatic cross-sectional side view of an example multi-layer configuration.

[0009] Figure 3 It is to illustrate the word lines and bit lines isolated from other components. Figure 1 A diagrammatic top view of a region of an assembly.

[0010] Figure 4 is a diagrammatic schematic of an example memory array.

[0011] Figure 5 is a diagrammatic cross-sectional side view of an assembly at an example process stage of an example embodiment.

[0012] Figure 6 is Figure 5 The example process stage after the process stage Figure 5A diagrammatic cross-sectional side view of an assembly of.

[0013] Fig. 6A yes Figure 6 A diagrammatic top view of a region of an assembly. Figure 6 The cross section along Fig. 6A Line 6-6.

[0014] Figure 7 is Figure 6 The example process stage after the process stage Figure 5 A diagrammatic cross-sectional side view of an assembly of.

[0015] Figure 8 is Figure 7 The example process stage after the process stage Figure 5 A diagrammatic cross-sectional side view of an assembly of.

[0016] Fig. 9 is Figure 8 The example process stage after the process stage Figure 5 A diagrammatic cross-sectional side view of an assembly of.

[0017] Fig.9A yes Fig. 9 A diagrammatic top view of a region of an assembly. Fig. 9 The cross section along Fig.9A Line 9-9. DETAILED DESCRIPTION

[0018] Some embodiments include a multi-layer architecture in which a memory layer is above a layer including CMOS circuitry, and in which components of the memory layer are electrically coupled to the CMOS circuitry through conductive interconnects. In some embodiments, sense / access lines (e.g., bit lines) may extend across memory cells and conductive interconnects, and may have a composite configuration above the memory cells but not above the conductive interconnects. In some applications, the region of the sense / access line above and directly against the conductive interconnect will have a lower resistance (i.e., higher conductivity) than the region above and directly against the electrode of the memory cell. Some embodiments include methods of forming a multi-layer architecture. Reference Figures 1 to 9 Example embodiments are described.

[0019] refer to Figure 1 , assembly 10 shows an example configuration for coupling a bit line (50) to a memory cell (12) and a conductive interconnect (46).

[0020] Assembly 10 includes a memory array 11, which includes memory cells 12. Memory cells 12 are supported by word lines (access lines) 14. The illustrated memory cells 12 may represent a large number of substantially identical memory cells within memory array 11; and in some embodiments memory array 11 may include hundreds, thousands, millions, hundreds of millions, etc. of memory cells. The term "substantially identical" means identical within reasonable manufacturing and measurement tolerances. The illustrated word lines 14 may represent a large number of substantially identical word lines within a memory array.

[0021] Word line 14 includes conductive material 16. Conductive material 16 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, conductive material 16 may include one or more metals and / or metal-containing compositions; and may, for example, include tungsten over tantalum nitride.

[0022] Each of the memory cells 12 includes a bottom electrode 18, a top electrode 20, and a programmable material 22 between the top and bottom electrodes. Electrodes 18 and 20 include conductive electrode materials 24 and 26, respectively. Electrode materials 24 and 26 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). Electrode materials 24 and 26 may be the same composition as one another, or may be different compositions relative to one another. In some example embodiments, electrode materials 24 and 26 may include, consist essentially of, or consist of one or more of TiSiN (titanium silicon nitride), TiAlN (titanium aluminum nitride), TiN (titanium nitride), WN (tungsten nitride), Ti (titanium), C (carbon), and W (tungsten); wherein the chemical formula indicates the components within the listed substances rather than specifying a particular stoichiometry of such components.

[0023] The bottom electrode 18 is electrically coupled to the word line 14 and, in the embodiment shown, directly against the word line.

[0024] Programmable material 22 may include any suitable composition. In some embodiments, programmable material 22 may be a bidirectional memory material, and in particular may be a chalcogenide. For example, programmable material 22 may include one or more of germanium (Ge), antimony (Sb), tellurium (Te), and indium (In). In a particular embodiment, programmable material 22 may, for example, include, consist essentially of, or consist of GeSbTe or InGeTe, where the chemical formula indicates the components within the listed substances, rather than specifying a particular stoichiometry of such components. In some embodiments, a memory cell may include a programmable material configured to be utilized in a self-select device; for example, a chalcogenide material may function as both a storage element and a selection device. Chalcogenides may be utilized alone in a self-select device, or may be utilized in combination with another composition. Example self-selecting PCM devices (where a PCM device is a device that includes a phase change material) are described in US Pat. Nos. 8,847,186 (Redaelli et al.) and 10,134,470 (Tortorelli et al.), which list Micron Technology, Inc. as assignee.

[0025] Memory cell 12 is an example memory cell that may be utilized in a memory array. In other embodiments, the memory cell may have other configurations. For example, Figure 1B A memory cell 12a having another example configuration is shown. The memory cell includes electrodes 18 and 20, and further includes a third electrode 28. In some embodiments, electrodes 28, 18, and 20 may be referred to as a bottom electrode, an intermediate electrode, and a top electrode, respectively. Electrode 28 includes electrode material 30. This electrode material may include any of the compositions described above with respect to electrode materials 24 and 26; and may have the same composition as one or both of electrode materials 24 and 26, or may differ in composition from at least one of electrode materials 24 and 26.

[0026] The bidirectional material 22 may be referred to as a first bidirectional material between the upper electrode 20 and the middle electrode 18. The second bidirectional material 32 is between the lower electrode 28 and the middle electrode 18. The second bidirectional material 32 may be incorporated into an on-off switch (OTS) of a select device 34. The memory cell 12a may therefore include the programmable material 22 in combination with the select device 34, rather than in a self-select configuration.

[0027] Bidirectional material 32 may include any suitable composition, and in some embodiments may include one or more of the compositions described above as suitable for programmable material 22 .

[0028] Reference again Figure 1, word lines 14 can be viewed as extending in and out of the page relative to the cross-sectional view. Insulating material 40 is between the word lines and separates the word lines from each other. Insulating material 40 also isolates adjacent memory cells 12 from each other. Insulating material 40 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon dioxide.

[0029] Figure 1 The cross-sectional view of shows memory cells 12 arranged to form a first group 36 and a second group 38. A coupling region 42 is between the first and second groups (36, 38) of memory cells.

[0030] Insulating material 44 extends across coupling region 42. Insulating material 44 may include any suitable composition; and in some embodiments may include, consist essentially of, or consist of silicon dioxide. In some applications described herein, insulating material 44 may be referred to as an intermediate insulating material.

[0031] Conductive interconnect 46 is within coupling region 42. The conductive interconnect includes conductive material 48. Conductive material 48 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). Conductive interconnect 46 may extend completely through a layer (i.e., a level, a tier, etc.) that includes memory array 11. Conductive interconnect 46 may include a variety of compositions, and may include different compositions at various locations throughout a layer. In some example embodiments, the illustrated portion of conductive interconnect 46 may include, consist essentially of, or consist of tungsten.

[0032] Memory cell 12 has an upper surface 15 along upper electrode 20, and interconnect 46 has an upper surface 47. The illustrated upper surface 15 is flat. In other embodiments, upper surface 15 may have other suitable configurations. The illustrated upper surface 47 is dome-shaped. In other embodiments, upper surface 47 may be flat, or may have any other suitable shape.

[0033] A bit line (digit line, sense line) 50 extends across the first and second groups (36, 38) of memory cells 12 and across conductive interconnects 46; and is electrically coupled to the memory cells 12 and conductive interconnects 46. The bit line includes a first region 52 and a second region 54, wherein such regions differ from one another in composition. The composition of the first region 52 may be referred to as a first composition, and the composition of the second region 54 may be referred to as a second composition.

[0034] In the illustrated embodiment, first region 52 includes two materials 56 and 58, and second region 54 includes only material 58. In other embodiments, regions 52 and 54 may include materials other than Figure 1 The illustrated materials 56 and 58 may be referred to as first and second materials, respectively. In some embodiments, materials 56 and 58 may be considered to correspond to first and second layers, respectively; or to lower and upper layers, respectively.

[0035] The first material 56 directly contacts the upper surface 15 of the memory cell. The first material 56 does not extend above the upper surface 47 of the conductive interconnect 46, while the second material 58 directly contacts the upper surface 47.

[0036] Conductive interconnect 46 has sidewall surfaces 49; and in the illustrated embodiment first material 56 directly contacts such sidewall surfaces. In other embodiments, only conductive material 58 may directly contact any surface of conductive interconnect 46.

[0037] In some embodiments, material 56 may have a higher resistivity (i.e., lower conductivity) than material 58. The combined materials 56 and 58 may be suitable for use as a bit line electrically coupled to memory cell 12, but it may be desirable to electrically connect to conductive interconnect 46 to utilize only low-resistivity (high-conductivity) material 58; wherein the terms "low-resistivity" and "high-conductivity" mean that material 58 has a lower resistivity (lower resistance) and correspondingly higher conductivity (higher conductivity) than material 56, rather than implying low resistivity or high conductivity in an absolute sense. Direct coupling of interconnect 48 to low-resistivity material 58 may enable enhanced transmission of signals from bit line 50 to conductive interconnect 48, which may improve speed and reliability relative to a configuration in which interconnect 46 is coupled to a higher-resistivity material.

[0038] Conductive materials 56 and 58 may include any suitable composition, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In some embodiments, first conductive material 56 includes, consists essentially of, or consists of one or more of C (carbon), WSiN (tungsten silicon nitride), WN (tungsten nitride), and TiN (titanium nitride), where the chemical formula indicates the composition rather than a particular stoichiometry, and second conductive material 58 includes, consists essentially of, or consists of one or more of Ta (tantalum), Pt (platinum), Cu (copper), W (tungsten), and Pd (palladium).

[0039] In some embodiments, first region 52 of bit line 50 may be considered to include two or more materials (e.g., materials 56 and 58), and second region 54 of the bit line may be considered to include a subset of the materials of the first region (e.g., only material 58 in the illustrated embodiment).

[0040] In some embodiments, first material 56 may include a first metal (e.g., tungsten or titanium) combined with one or more non-metallic elements (e.g., one or more of silicon, nitrogen, carbon, etc.); and second material 58 may be composed of a second metal (e.g., one or more of Ta, Pt, Cu, W, and Pd). The second metal of material 58 may be the same as the first metal of material 56, or may be different from the first metal of material 56. In some specific applications, first material 56 may be composed of WSiN (where the chemical formula indicates the composition rather than a specific stoichiometry), and second material 58 may be composed of W.

[0041] Figure 1A A top view of assembly 10 is shown. Figure 1A The view relative to Figure 1 The views are not drawn to scale and are not drawn using Figure 1 A diagrammatic representation of the assembly 10 utilized in FIG. Figure 1 The cross section can be understood as being roughly along Figure 1A Line 1-1.

[0042] The coupling region 42 includes a plurality of conductive interconnects 46. The conductive interconnects are arranged along a row, wherein the row is arranged along a line with respect to Figure 1 The plane of the cross section of extends in directions inward and outward of the page. The conductive interconnect may be circular in a top view (as shown), or may have any other suitable shape, including, for example, a square shape, a rectangular shape, an elliptical shape, etc.

[0043] It should be understood that even Figure 1 The cross-section of the coupling region 42 may include only one of the conductive interconnects 46 within the illustrated portion thereof, and in other embodiments, there may also be a plurality of conductive interconnects 46 disposed along the coupling region 42. Figure 1 Thus, even if Figure 1A A single row of interconnects 46 within coupling region 42 is shown, and in other embodiments there may be multiple rows of such interconnects arranged in a matrix or other suitable configuration. Furthermore, it should be understood that Figure 1A The illustrated interconnects 46 may represent a large number of substantially identical interconnects formed within the coupling region 42. For example, in some embodiments, there may be hundreds, thousands, millions, tens of thousands, etc. of conductive interconnects 46 formed within the coupling region 42.

[0044] Figure 1AA plurality of bit lines 50 are shown extending across the memory array 11 and the coupling region 42. Each of the bit lines extends across one of the illustrated conductive interconnects 46. The conductive interconnects 46 are located at Figure 1A 5 is shown in dashed view to indicate that it is below the bit line 50. The illustrated bit line 50 may represent a large number of substantially identical bit lines associated with the memory array 11. For example, in some embodiments, there may be hundreds, thousands, millions, tens of thousands, etc. of bit lines 50 associated with the memory array.

[0045] Figure 1 The description of indicates that word line 14 is below memory cell 12 and bit line 56 is above the memory cell. In other applications, the relative orientation of word lines and bit lines may be reversed so that bit lines are below memory cells and word lines are above memory cells. The terms "access / sense line," "bit line / word line," "word line / bit line," and "sense / access line" may be used herein to generally refer to bit lines and word lines in the context in which the indicated structure may be either a word line or a bit line.

[0046] Figure 1 and 1A The conductive interconnects 46 may be used to enable the circuitry of one layer within the multilayer stack to be electrically coupled to the circuitry of another layer. Figure 2 A multilayer stack 60 having two layers 62 and 64 is shown in a vertical stack. Figure 2 The vertical stacked arrangement of can be extended upward to include additional layers. Layers 62 and 64 can be considered as examples of levels stacked on each other. The levels can be within different semiconductor dies (wafers), or can be within the same semiconductor die. The bottom layer 62 can include control circuitry and / or sensing circuitry (e.g., can include word line drivers, sense amplifiers, etc.; and can include CMOS circuitry, as shown). The upper layer 64 can include a memory array, such as (for example) Figure 1 and 1A Memory array 11; and may be referred to as a memory layer.

[0047] Figure 1 Conductive interconnect 46 is illustrated as enabling circuitry associated with layer 64 to be electrically coupled to circuitry associated with layer 62, with this electrical coupling being diagrammatically shown with dashed arrow 61. In an example embodiment, sense / access lines 50 associated with memory array 11 are electrically coupled to circuitry of layer 62 via conductive interconnect 46. For example, bit lines associated with a memory array within layer 64 may be coupled to sense amplifiers within layer 62 via connection 61. As another example, word lines associated with a memory array within layer 64 may be coupled to word line drivers within layer 62 via connection 61.

[0048] Figure 1 and1A The memory array 11 includes a first direction (relative to Figure 1 A first series of sensing / access lines 14 extending in a cross section in and outside the page, and along a second direction (along Figure 1 A second series of sensing / access lines 50 extending in a plane of a cross section of the embodiment of the present invention, wherein the second direction is orthogonal to the first direction. Figure 3 exhibit Figure 1 and 1A Another diagrammatic top view of the assembly 10 of FIG. 1 and showing word lines 14 arranged as a first series of sense / access lines below the memory cells 12 and bit lines 50 arranged as a second series of sense / access lines above the memory cells 12. The memory cells 12 are arranged as a first series of sense / access lines below the memory cells 12 and a second series of sense / access lines above the memory cells 12. Figure 3 1, but should be understood to be at the intersection where sense / access line 50 crosses sense / access line 14 (with the dashed arrows diagrammatically illustrating example intersection locations for memory cell 12).

[0049] Figure 1 and 1A The memory array 11 may have any suitable configuration. Figure 4 Diagrammatically illustrates an example configuration of a memory array 11. This configuration includes memory cells 12 at the intersections where word lines (WL1-WL4) pass through bit lines (BL1-BL6). Each of the memory cells is uniquely addressed by a combination of one of the word lines and one of the bit lines.

[0050] Figure 1 and 1A The configuration may be formed by any suitable process. Figures 5 to 9 Describes instance processing.

[0051] refer to Figure 5 , capping material 66 is over the first and second groups (36, 38) of memory cells 12. Capping material 66 may include any suitable composition, and in some embodiments may include, consist essentially of, or consist of silicon nitride. Insulating material 44 is provided over capping material 66 and across coupling region 42. In some embodiments, insulating material 44 may be viewed as extending across an intermediate region between groups 36, 38 of memory cells 12; wherein this intermediate region corresponds to coupling region 42. In other embodiments, Figure 5 The memory cell 12 may be replaced by other memory cells (e.g., Figure 1A The memory cell 12a of the configuration is replaced by the memory cell).

[0052] refer to Figure 6, after forming a conductive interconnect 46 within the coupling region 42; and after one or more polishing processes have been utilized to expose the upper surface 15 of the memory cell 12 and the upper surface 47 of the conductive interconnect 46, the assembly 10 is shown.

[0053] The conductive interconnect 46 may be formed by any suitable process. For example, in some example embodiments, a via may be formed to extend through the material within the coupling region 42 , and then a suitable conductive material may be provided within the via to form the conductive interconnect 46 .

[0054] The upper surface 47 of the conductive interconnect 46 protrudes above the upper surface 45 of the polished material 44. This may be a natural result of polishing (e.g., chemical mechanical polishing, CMP) due to the relative hardness of the conductive material 48 compared to the silicon dioxide 44. The upper surface 47 of the conductive interconnect 48 is higher than the upper surface 45 of the insulating material 44 by a height H. This height may be at least about At least about At least about wait.

[0055] Fig. 6A Demonstrated in the use of similar Figure 1A The diagram of the diagram Figure 6 1 is a top view of the assembly 10 at a process stage. Fig. 6A View display Figure 6 The conductive interconnect 46 may be one of a plurality of substantially identical conductive interconnects, while the others of the conductive interconnects are formed in Figure 6 outside the plane of the cross section.

[0056] refer to Figure 7 , a conductive material 56 is formed along the upper surface of the assembly 10. The conductive material 56 extends across the memory cell 12 and across the conductive interconnect 46; and directly contacts the upper surface 15 of the memory cell 12 and the upper surface 47 of the conductive interconnect 46.

[0057] refer to Figure 8 , conductive material 56 is removed from above upper surface 47 of conductive interconnect 46, while leaving portions of conductive material 56 above memory cells 12 of first group 36 and second group 38. Conductive material 56 may be removed from above surface 47 by any suitable process; and in some embodiments is removed by a polishing process (e.g., CMP).

[0058] refer to Fig. 9 , a conductive material 58 is formed over the conductive material 56 , and the conductive materials 56 and 58 are patterned together into the bit line 50 . Fig. 9 The assembly 10 includes the above reference Figure 1 Configuration described. Fig.9A Demonstrated in the use of similar Figure 1AThe diagram of the diagram Fig. 9 1 is a top view of the assembly 10 at a process stage. Fig.9A The view showing position line 50 is available Figures 5 to 9 One of many substantially identical bit lines manufactured by a process of.

[0059] The assemblies and structures discussed above may be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and specific application modules, and may include multi-layer, multi-chip modules. The electronic systems may be any of a wide range of systems such as, for example, cameras, wireless devices, displays, chipsets, video converters, games, lighting devices, vehicles, timers, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0060] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed by any suitable method, now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0061] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In this disclosure, the terms are considered synonymous. The use of the term "dielectric" in some examples and the term "insulating" (or "electrically insulating") in other examples may provide language variation within the disclosure to simplify the premise basis within the appended claims and is not used to indicate any significant chemical or electrical differences.

[0062] Both the terms "electrically connected" and "electrically coupled" may be utilized in this disclosure. The terms are considered synonyms. The utilization of one term in some instances and the other term in other instances may provide language variation within this disclosure to simplify the premise basis within the appended claims.

[0063] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications the embodiments may be rotated relative to the orientation shown. The descriptions and appended claims provided herein are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0064] To simplify the drawings, cross-sectional views of the accompanying drawings show only features within the cross-sectional plane and do not show material behind the cross-sectional plane unless otherwise indicated.

[0065] When a structure is referred to above as being "on another structure," "adjacent to another structure," or "against another structure," it may be directly above the other structure or there may also be intervening structures. In contrast, when a structure is referred to as being "directly above," "directly adjacent to," or "directly against," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0066] A structure (e.g., layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure extends generally upward from an underlying substrate (e.g., substrate). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0067] Some embodiments include an arrangement having a first layer including a first group of memory cells on one side of a coupling region and a second group of memory cells on an opposite side of the coupling region. A first series of sense / access lines is below and electrically connected to the memory cells of the first and second groups. A conductive interconnect is within the coupling region of the memory layer. A second series of sense / access lines extends across the memory cells of the first and second groups and across the conductive interconnect. The sense / access lines of the second series have a first region of a first composition and a second region of a second composition. The first region is above and electrically connected to the memory cells of the first and second series. The second region is above and electrically coupled to the conductive interconnect. A second layer is vertically offset from the first layer. The second layer includes circuitry coupled to the conductive interconnect.

[0068] Some embodiments include an arrangement having a memory layer including a first group of memory cells on one side of a coupling region and a second group of memory cells on an opposite side of the coupling region. A first series of sense / access lines is below and electrically connected to the memory cells of the first and second groups. A conductive interconnect is within the coupling region of the memory layer. A second series of sense / access lines extends across the memory cells of the first and second groups and across the conductive interconnect. The sense / access lines of the second series have a first region with a second conductive material above the first conductive material and a second region with only the second conductive material. The first region is above and electrically connected to the memory cells of the first and second series. The second region is above and electrically coupled to the conductive interconnect. An additional layer is below the memory layer. The additional layer includes CMOS circuitry coupled to the conductive interconnect.

[0069] Some embodiments include a method of forming an arrangement. An assembly is formed to include, along a cross section, a first group of memory cells on one side of a coupling region and a second group of memory cells on an opposite side of the coupling region. An intervening insulating material is within the coupling region. The memory cells of the first group and the second group are above a first series of sense / access lines. A conductive interconnect is formed within the coupling region and extends through the intervening insulating material. A first conductive material is formed to extend across the first group and the second group of memory cells and across the conductive interconnect. The first conductive material directly contacts an upper surface of the memory cell and an upper surface of the conductive interconnect. The first conductive material is removed from above the upper surface of the conductive interconnect while leaving a remaining portion of the first conductive material above the memory cells of the first group and the second group. A second conductive material is formed above the remaining portion of the first conductive material and above the upper surface of the conductive interconnect. The first conductive material and the second conductive material are patterned into a second series of sense / access lines.

[0070] In accordance with the statute, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims should be given the full scope as literally intended and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated device comprising: a first layer comprising a first set of memory cells on one side of a coupling region and a second set of memory cells on an opposite side of the coupling region; a first series of sense / access lines underlying and electrically connecting the first and second groups of memory cells; a conductive interconnect within the coupling region of the first layer; a second series of sense / access lines extending across the first and second groups of memory cells and across the conductive interconnect; the second series of sense / access lines having a first region including a first composition and having a second region including a second composition different from the first composition; the first region being over and electrically connected to the first and second groups of memory cells; the second region being over and electrically coupled to the conductive interconnect, wherein the first composition is absent over at least a portion of the conductive interconnect; and A second layer is vertically offset from the first layer; the second layer includes circuitry coupled to the conductive interconnect.

2. The integrated device of claim 1, wherein the circuitry of the second layer is CMOS circuitry.

3. An integrated device comprising: a first layer comprising a first set of memory cells on one side of a coupling region and a second set of memory cells on an opposite side of the coupling region; a first series of sense / access lines underlying and electrically connecting the first and second groups of memory cells; a conductive interconnect within the coupling region of the first layer; a second series of sense / access lines extending across the memory cells of the first and second groups and across the conductive interconnect; the second series of sense / access lines having a first region comprising a first composition and having a second region comprising a second composition different from the first composition, the first composition comprising two or more materials and the second composition comprising a subset of the materials of the first composition; the first region being over and electrically connected to the memory cells of the first and second groups; the second region being over and electrically coupled to the conductive interconnect; and A second layer is vertically offset from the first layer; the second layer includes circuitry coupled to the conductive interconnect.

4. The integrated device of claim 3, wherein the second composition has a higher conductivity than the first composition.

5. An integrated device according to claim 4, wherein the first composition includes an upper layer above the lower layer, wherein the upper layer includes one or more of Ta, Pt, Cu, W and Pd; and wherein the second composition includes only the upper layer.

6. An integrated device according to claim 4, wherein the first composition includes one or more of Ta, Pt, Cu, W and Pd on one or more of carbon, WSiN, WN and TiN; and wherein the second composition includes only the one or more of Ta, Pt, Cu, W and Pd.

7. An integrated device comprising: a memory layer comprising a first set of memory cells on one side of a coupling region and a second set of memory cells on an opposite side of the coupling region; a first series of sense / access lines underlying and electrically connecting the first and second groups of memory cells; a conductive interconnect within the coupling region of the memory layer; a second series of sense / access lines extending across the memory cells of the first and second groups and across the conductive interconnect; the second series of sense / access lines having a first region including a second conductive material over the first conductive material and having a second region including only the second conductive material; the first region being over and electrically connected to the memory cells of the first and second groups; the second region being over and electrically coupled to the conductive interconnect; and An additional layer is below the memory layer; the additional layer includes CMOS circuitry coupled to the conductive interconnect.

8. The integrated device of claim 7, wherein the first conductive material has a higher resistance than the second conductive material.

9. The integrated device of claim 7, wherein the first conductive material comprises one or more of carbon, WSiN, WN, and TiN, wherein the chemical formulas WSiN, WN, and TiN indicate composition rather than specific stoichiometry; And wherein the second conductive material includes one or more of Ta, Pt, Cu, W and Pd.

10. The integrated device of claim 7, wherein the first and second conductive materials comprise metal.

11. The integrated device of claim 7, wherein the first conductive material comprises a first metal in combination with one or more non-metallic elements, and wherein the second conductive material consists of a second metal.

12. The integrated device of claim 11, wherein the first metal and the second metal are the same.

13. The integrated device of claim 12, wherein the first conductive material consists of WSiN, wherein the chemical formula WSiN indicates composition rather than a specific stoichiometry; and wherein the second conductive material consists of W.

14. The integrated device of claim 11, wherein the first metal and the second metal are different.

15. The integrated device of claim 7, wherein the second conductive material directly contacts a sidewall of the conductive interconnect but does not extend over a top of the conductive interconnect.

16. The integrated device of claim 7, wherein the conductive interconnect is one of many substantially identical conductive interconnects, and wherein the second series of the sense / access lines is one of many sense / access lines of the second series.

17. The integrated device of claim 16, wherein the sense / access lines of the first series are word lines, and wherein the sense / access lines of the second series are bit lines.

18. The integrated device of claim 7, wherein the memory cells of the first and second sets include a programmable material comprising one or more of germanium, antimony, tellurium, and indium.

19. The integrated device of claim 7, wherein the memory cells of the first and second groups are self-select memory cells comprising one or more of germanium, antimony, tellurium, and indium.

20. The integrated device of claim 7, wherein the memory cells of the first and second groups are self-select memory cells comprising chalcogenides.

21. The integrated device of claim 7, wherein each of the memory cells of the first and second sets includes a programmable material and a selection device.

22. A method of forming an integrated device, comprising: forming an assembly comprising, along a cross section, a first set of memory cells on one side of a coupling region and a second set of memory cells on an opposite side of the coupling region; an intervening insulating material within the coupling region; the memory cells of the first and second groups are over a first series of sense / access lines; forming a conductive interconnect within the coupling region and extending through the intervening insulating material; forming a first conductive material to extend across the first and second groups of the memory cells and across the conductive interconnect; The first conductive material directly contacts an upper surface of the memory cell and an upper surface of the conductive interconnect; removing the first conductive material from over the upper surface of the conductive interconnect while leaving remaining portions of the first conductive material over the first and second groups of memory cells; and A second conductive material is formed over the remaining portion of the first conductive material and over the upper surface of the conductive interconnect, and the first and second conductive materials are patterned into a second series of sense / access lines.

23. The method of claim 22, wherein the removing of the first conductive material utilizes a polishing process.

24. The method of claim 22, wherein: The cross section is along a plane; and The conductive interconnect is one of a number of substantially identical conductive interconnects, while others of the conductive interconnects are formed out of the plane of the cross-section.

25. The method of claim 24, wherein the sense / access line of the second series is one of many sense / access lines of the second series, while others of the sense / access lines of the second series are formed out of the plane of the cross-section.

26. The method of claim 25 wherein the sense / access lines of the first series are word lines, and wherein the sense / access lines of the second series are bit lines.

27. The method of claim 22, wherein the memory cells of the first and second groups are self-select memory cells comprising chalcogenides.

28. The method of claim 27 wherein the memory cells of the first and second groups include an upper electrode and a lower electrode, and wherein the chalcogenide is between the upper electrode and the lower electrode.

29. The method of claim 22, wherein each of the memory cells of the first and second sets includes a programmable material and a selection device.

30. A method according to claim 29, wherein the memory cells of the first group and the second group include an upper electrode, a lower electrode and an intermediate electrode between the upper electrode and the lower electrode; a first bidirectional material is between the upper electrode and the intermediate electrode, and a second bidirectional material is between the intermediate electrode and the lower electrode; one of the first bidirectional material and the second bidirectional material is the programmable material of the memory cell, and the other of the first bidirectional material and the second bidirectional material is incorporated into a bidirectional limit switch of the selection device.

31. The method of claim 22, wherein the memory cells of the first group and the second group are within one layer of a multilayer configuration; and wherein the conductive interconnect is coupled to circuitry in another layer of the multilayer configuration, wherein the other layer is vertically offset from the one layer.

32. The method of claim 31 , wherein the another layer is below the one layer, and wherein the circuitry in the another layer comprises CMOS circuitry.

33. The method of claim 22, wherein the first conductive material has a higher resistance than the second conductive material.

34. The method of claim 22, wherein the first conductive material comprises one or more of carbon, WSiN, WN, and TiN, wherein the chemical formulas WSiN, WN, and TiN indicate composition rather than a specific stoichiometry; and wherein the second conductive material comprises one or more of Ta, Pt, Cu, W, and Pd.

35. The method of claim 22, wherein the first and second conductive materials comprise metals.

36. The method of claim 22, wherein the first conductive material comprises a first metal combined with one or more non-metallic elements, and wherein the second conductive material consists of a second metal.

37. The method of claim 36, wherein the first metal and the second metal are the same.

38. The method of claim 37, wherein the first conductive material consists of WSiN, wherein the chemical formula WSiN indicates composition rather than a specific stoichiometry; and wherein the second conductive material consists of W.

39. The method of claim 36, wherein the first metal and the second metal are different.

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