Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device includes a plurality of memory cells connected with a match line, a word line driver connected with a word line, a valid cell configured to store a valid bit indicating a valid or invalid of an entry, a first pre-charge circuit connected with one end of the match line and configured to pre-charge the match line to a high level, and a second pre-charge circuit connected with the other end of the match line and configured to pre-charge the match line to the high level. The plurality of memory cells are arranged between the first pre-charge circuit and the second pre-charge circuit, and the second pre-charge circuit is arranged between the word line driver and the plurality of memory cells.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-095806, filed on June 11, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices and is applicable to semiconductor devices, such as those including content reference memory. Background Technology

[0004] The storage device used as a search memory (referred to as content-addressable memory or CAM) is configured to search for a data word that matches a search word in the stored data words, and output the address of the matching data word when it is found. Here, the data word is also referred to as an entry, and the search word is also referred to as search data.

[0005] As CAMs, there are BCAMs (Binary CAMs) and TCAMs (Trinity CAMs). Each memory cell in a BCAM stores information of either "0" or "1". On the other hand, in the case of a TCAM, in addition to "0" and "1", each memory cell can also store information of "x" (whatever it is). Note that "x" indicates that it can be either "0" or "1".

[0006] The CAM has match lines (MLs) used to compare information stored in memory cells with the data the user wants to search for, and to indicate whether the data matches or does not. The address information (hit index) corresponding to the matched match line is then output. Additionally, some CAMs store validity information indicating whether the contents of the CAM entry are valid.

[0007] The following technologies have been disclosed.

[0008] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2018-206451. Summary of the Invention

[0009] Increasing search access speed is crucial in CAM. Multiple memory cells constituting an entry are connected to mating lines, which are the critical path for search access. Therefore, as the wiring length of the mating lines increases, their load capacity also increases, making it difficult to improve search access speed.

[0010] In one aspect of this disclosure, pre-charging circuitry for the matching lines is arranged on both sides of the CAM unit array, and valid information is supplied to these pre-charging circuitries.

[0011] The aforementioned semiconductor devices can improve search access speed. Attached Figure Description

[0012] Figure 1 This is a circuit diagram illustrating an example configuration of the TCAM unit in the embodiment.

[0013] Figure 2 The storage contents of cells X and Y are displayed in the form of a table. Figure 1 The diagram shows the correspondence between the data of the TCAM units.

[0014] Figure 3 This is a block diagram illustrating the configuration of the TCAM device in the embodiment.

[0015] Figure 4 It shows Figure 3 The diagram shows the cell arrangement of the TCAM macrocell.

[0016] Figure 5 It shows the relationship with Figure 3 The diagram shows an example of the circuit configuration corresponding to one entry of the TCAM macrocell shown.

[0017] Figure 6 It shows the relationship with Figure 3 The diagram shows an example of the circuit configuration of the precharge circuit corresponding to one entry of the TCAM macrocell shown.

[0018] Figure 7 This is a diagram illustrating an example of the circuit configuration of the precharge circuit corresponding to an entry of the TCAM macrocell in the first modification.

[0019] Figure 8 This is a diagram illustrating an example of the circuit configuration of the matching line output circuit corresponding to an entry of the TCAM macrocell in the second modification.

[0020] Figure 9 It shows Figure 8 A diagram showing an example of the circuit configuration of the sensing amplifier.

[0021] Figure 10 This is a timing diagram used to describe the operation of the matching line output circuit in the second modification.

[0022] Figure 11 This is a block diagram of a semiconductor device in an application example. Detailed Implementation

[0023] In the following description, embodiments, modifications, and application examples will be described with reference to the accompanying drawings. In the following description, the same components are indicated by the same reference numerals, and repeated descriptions will be omitted. Note that the drawings are schematically shown in terms of the width, thickness, shape, and other aspects of each component compared to the actual aspects to make the description clearer; however, the drawings are merely illustrative and do not limit the interpretation of this disclosure. In the embodiments, TCAM is described as an example, but this disclosure is not limited thereto and can be applied to search memories using matching lines.

[0024] (Example)

[0025] Reference Figure 1 and Figure 2 To describe the configuration of the TCAM unit. Figure 1 This is a circuit diagram illustrating an example configuration of the TCAM unit in the embodiment. Figure 2 The storage contents of cells X and Y are shown in table form. Figure 1 The diagram shows the correspondence between the data of the TCAM units.

[0026] like Figure 1 As shown, the TCAM unit MC, serving as a memory unit, includes X unit 11, Y unit 12, and data comparison unit 13. X unit 11 and Y unit 12 are composed of SRAM (Static Random Access Memory) and are also referred to as SRAM units. X unit 11 stores complementary 1-bit data in internal storage nodes ND1 and ND1_n. Here, complementary means that when one is "1", the other is "0". Y unit 12 stores complementary 1-bit data in internal storage nodes ND2 and ND2_n.

[0027] The TCAM unit MC is connected to bit line pairs BT and BB, search line pairs ST and SB, match line ML, first word line WLA, and second word line WLB.

[0028] Cell X11 includes inverters INV1 and INV2, and N-channel MOS (metal-oxide-semiconductor) transistors Q1 and Q2. Inverter INV1 is connected between memory node ND1 and memory node ND1_n, such that the direction from memory node ND1_n to memory node ND1 is positive. Inverter INV2 is connected in parallel with inverter INV1 in the opposite direction. N-channel MOS transistor Q1 is connected between memory node ND1 and bit line BT. N-channel MOS transistor Q2 is connected between memory node ND1_n and bit line BB. The gates of N-channel MOS transistors Q1 and Q2 are connected to the first word line WLA.

[0029] Y-cell 12 includes inverters INV3 and INV4, and N-channel MOS transistors Q3 and Q4. Inverter INV3 is connected between memory node ND2 and memory node ND2_N, such that the direction from memory node ND2_n to memory node ND2 is positive. Inverter INV4 is connected in parallel with inverter INV3 in the opposite direction. N-channel MOS transistor Q3 is connected between memory node ND2 and bit line BT. N-channel MOS transistor Q4 is connected between memory node ND2_N and bit line BB. The gates of N-channel MOS transistors Q3 and Q4 are connected to the second word line WLB.

[0030] Data comparison unit 13 includes N-channel MOS transistors Q6 through Q9. N-channel MOS transistors Q6 and Q7 are connected in series between node ND3 and ground potential VSS, with node ND3 being the connection point to the matching line ML. N-channel MOS transistors Q8 and Q9 are connected in series between node ND3 and ground potential VSS, and in parallel with the series-connected N-channel MOS transistors Q6 and Q7. The gates of N-channel MOS transistors Q6 and Q8 are connected to storage nodes ND1 and ND2, respectively. The gates of N-channel MOS transistors Q7 and Q9 are connected to search line pairs ST and SB, respectively.

[0031] Each of inverters INV1, INV2, INV3, and INV4 has a P-channel MOS transistor and an N-channel MOS transistor. The source-drain paths of the P-channel MOS transistor and the source-drain paths of the N-channel MOS transistor are connected in series between a power supply potential VDD (a first potential) and a ground potential VSS (a second potential). The gates of the P-channel and N-channel MOS transistors are connected together to serve as the input terminal of the inverter. The drains of the P-channel and N-channel MOS transistors are connected together to serve as the output terminal of the inverter.

[0032] Note that this can be achieved, for example, by removing the second word line WLB and Y cell 12 and connecting the gate electrode of the N-channel MOS transistor Q8 to... Figure 1 The memory cells of BCAM are configured using the storage node Nd1_n of the X unit 11.

[0033] like Figure 1 and Figure 2As shown, the TCAM unit MC can store three values: "0", "1", and "X" using a 2-bit SRAM cell. Specifically, assuming "1" is stored in storage node ND1 of X unit 11 and "0" is stored in storage node ND2 of Y unit 12, then "0" is stored in the TCAM unit MC. Assuming "0" is stored in storage node ND1 of X unit 11 and "1" is stored in storage node ND2 of Y unit 12, then "1" is stored in the TCAM unit MC. Assuming "0" is stored in storage node ND1 of X unit 11 and "0" is stored in storage node ND2 of Y unit 12, then "X" is stored in the TCAM unit MC. When "1" is stored in storage node ND1 of X unit 11 and "1" is stored in storage node ND2 of Y unit 12, "X" is not used.

[0034] According to the configuration of the TCAM cell MC described above, when the search data is "1" and the TCAM data is "0", MOS transistors Q6 and Q7 are in the on state, and therefore the potential of the pre-charged matching line ML is pulled to the ground potential VSS. Here, when the search line ST is "1" and the search line SB is "0", the search data is set to "1". When the storage node ND1 is "1" and the storage node ND2 is "0", the TCAM data is set to "0".

[0035] When the search data is "0" and the TCAM data is "1", MOS transistors Q8 and Q9 are in the ON state, and therefore the potential of the pre-charged matching line ML is pulled to ground potential VSS. Here, the search data is set to "0" when the search line ST is "0" and the search line SB is "1". The TCAM data is set to "1" when memory node ND1 is "0" and memory node ND2 is "1".

[0036] That is, when the search data and TCAM data do not match, the potential of the matching line ML is pulled out to the ground potential VSS.

[0037] Conversely, when the input search data is "1" and the TCAM data is "1" or "X", the potential of the pre-charged matching line ML is maintained. When the input search data is "0" and the TCAM data is "0" or "X", the potential of the pre-charged matching line ML is maintained. That is, when the search data and TCAM data match, the potential of the pre-charged matching line ML is maintained. Here, the potential of the pre-charged matching line ML is at the level of the power supply potential VDD.

[0038] As described above, in TCAM, the charge stored in the matching line ML is pulled out unless the data of all TCAM cells MC connected to the matching line ML corresponding to an entry (memory cell row) matches the input search data.

[0039] Reference Figure 3 To describe the array configuration. Figure 3 This is a block diagram illustrating the configuration of the TCAM device in the embodiment.

[0040] TCAM device 1 includes a TCAM macrocell 100 and a priority encoder (PREN) 300. The TCAM macrocell 100 includes a TCAM cell array (CARY) 20, a valid bit unit 23, a match line output circuit unit (MO) 24, and a word line driver (WLD) 2. Here, the word line driver (WLD) 2 drives... Figure 1 The circuit units for the first word line WLA and the second word line WLB are shown.

[0041] The TCAM macrocell 100 also includes input / output circuit units IO, input / output circuit units VIO, and control logic circuitry (CNT) 25. The input / output circuit units IO include a write driver and read sense amplifier (WD / SA) 21, and a search line driver (SD) 22. The input / output circuit units VIO include a write driver and read sense amplifier (VWD / VSA) for the valid bit unit 23.

[0042] TCAM cell array 20 includes a plurality of TCAM cells MC arranged in a matrix. Bit line pairs BT and BB extend in the column direction of TCAM cell array 20 and are shared by the plurality of TCAM cells MC arranged in the column direction. Search line pairs ST and SB extend in the column direction of TCAM cell array 20 and are shared by the plurality of TCAM cells MC arranged in the column direction. Match line ML extends in the row direction of TCAM cell array 20 and is shared by the plurality of TCAM cells MC arranged in the row direction. First word line WLA and second word line WLB extend in the row direction of TCAM cell array 20 and are shared by the plurality of TCAM cells MC arranged in the row direction. Here, the row direction of TCAM cell array 20 is the X direction, and its column direction is the Y direction.

[0043] Figure 3The diagram illustrates a TCAM cell array 20 with M+1 rows (number of entries) (M is a positive integer) and n+1 columns (number of bits per entry) (n is a positive integer). For each column of the TCAM cell array 20, n+1 bit line pairs (BT[0] and BB[0] to BT[N] and BB[N]) and n+1 search line pairs (ST[0] and SB[0] to ST[n] and SB[n]) are set. For each row of the TCAM cell array 20, M+1 matching lines (ML[0] to ML[M]), M+1 first word lines (WLA[0] to WLA[M]) for cell X 11, and M+1 second word lines (WLB[0] to WLB[M]) for cell Y 12 are set.

[0044] The write driver and read sense amplifier 21 include a write driver WD and a read sense amplifier SA. During writing, the write driver WD supplies write data to each TCAM cell MC via bit line pairs BT and BB. The read sense amplifier SA amplifies the data read from each TCAM cell MC via bit line pairs BT and BB, and outputs the amplified data during reading.

[0045] During a search, the search line driver 22 supplies search data to each TCAM unit MC using search line pairs (ST[0] and SB[0] to ST[n] and SB[N]).

[0046] Control logic circuit 25 controls the operation of the entire TCAM macrocell 100. For example, control logic circuit 25 controls the operation of search line driver 22 by receiving search commands and outputting control signals to search line driver 22 during search. Control logic circuit 25 controls the operation of write driver WD and word line driver 2 by outputting control signals to write driver WD and word line driver 2 during write. Furthermore, control logic circuit 25 controls the operation of word line driver 2 and read sense amplifier SA by outputting control signals to word line driver 2 and read sense amplifier SA during read.

[0047] The valid bit unit 23 includes multiple valid units (VC0 to VCm). Each valid unit (VC0 to VCM) is connected to bit line pairs VBT and VBB. Each bit line in bit line pairs VBT and VBB is connected to the input / output circuit unit VIO. The third word line of each valid unit (VC0 to VCm) is connected via OR circuitry (OR[0] to OR[m]) to the first word line (WLA[0] to WLA[M]) and the second word line (WLB[0] to WLB[M]) of the corresponding entry. Furthermore, each valid unit (VC0 to VCm) stores a valid bit (VB0 to VBm) as information indicating whether the corresponding entry is valid or invalid. The multiple valid units (VC0 to VCm) are also connected to wiring RT, which provides a reset signal. By activating the reset signal, the valid bits (VB0 to VBm) stored in the multiple valid units (VC0 to VCm) can be collectively set to indicate invalid data. Here, the reset signal is activated, for example, by setting the reset signal to a high level. In addition, for example, the valid bits (VB0 to VBm) indicate invalidity when they are low.

[0048] When the first word line (WLA[0] to WLA[M]) or the second word line (WLB[0] to WLB[M]) of the corresponding entry enters the selected state, the output of the corresponding OR circuit (OR[0] to OR[M]) enters the selected state, causing multiple valid cells (VC0 to VCm) to enter the selected state. That is, the OR circuit (OR[0] to OR[m]) is a selection circuit connected to the first word line (WLA[0] to WLA[M]) and the second word line (WLB[0] to WLB[M]), and the OR circuit is configured to cause multiple valid cells (VC0 to VCm) to enter the selected state according to the selected state of the first word line (WLA[0] to WLA[M]) or the second word line (WLB[0] to WLB[M]). Therefore, the valid bits (VB0 to VBm) are written to the valid cells (VC0 to VCm) in the selected state by means of the bit line pairs VBT and VBB.

[0049] Matching line output circuit unit 24 has multiple matching line output circuits (MO0 to MOm) corresponding to each row of TCAM unit array 20. Each input of the matching line output circuit (MO0 to MOm) is connected to the corresponding matching line (ML[0] to ML[m]), and each output of the matching line output circuit (MO0 to MOm) is connected to the corresponding matching signal output line (MLO0 to MLOm). Each matching line output circuit (MO0 to MOm) receives a valid bit (VB0 to VBm) from the corresponding valid unit (VC0 to VCm). The operation of the matching line output circuit (MO0 to MOm) is controlled by the value of the valid bit (VB0 to VBm).

[0050] The matching line output circuit (MO0 to MOm) generates a detection signal based on the potential of the corresponding matching line (ML[0] to ML[M]), and outputs the signal to the corresponding matching signal output line (MLO0 to MLOm) during the search. The detection signal indicates whether the corresponding TCAM cell data and the input search data match or do not match. When the valid bit (VB0 to VBm) is valid, the signal level of the matching signal output line (MLO0 to MLOm) is set to the level of the detection signal indicating whether the corresponding TCAM cell data and the input search data match or do not match. On the other hand, when the valid bit (VB0 to VBm) is invalid, regardless of whether the detection signal indicates whether the corresponding part of the corresponding TCAM cell data and the input search data matches, the signal level of the matching signal output line (MLO0 to MLOm) is set to, for example, the signal level indicating a mismatch. Here, for example, the signal level of the matching signal output line (MLO0 to MLOm) is set to a high level when there is a match, and a low level when there is a mismatch.

[0051] The priority encoder (PREN) 300 is configured to select a matching signal output line according to a predetermined priority order when some of the multiple matching signal output lines (MLO0 to MLOm) are set to indicate the signal level of matching during the search.

[0052] Reference Figure 4 To describe the cell arrangement of TCAM macrocell 100. Figure 4 It shows Figure 3 A layout diagram of a portion of the TCAM macrocells.

[0053] The TCAM macrocell 100 is configured by arranging each unit of the word line driver (WLD) 2, the second precharge circuit unit (PC2) 27, the TCAM cell array (CARY) 20, the valid bit unit (VC) 23, the first precharge circuit unit (PC1) 26, and the matching line output circuit unit (MO) 24 in this order in the X direction. That is, the first precharge circuit unit 26 and the second precharge circuit unit 27 are arranged on both sides of the TCAM cell array 20. The valid bit VB is supplied from the valid bit unit 23 to the first precharge circuit unit 26 and the second precharge circuit unit 27 arranged on both sides of the TCAM cell array 20 via the wiring connection of the valid bit line VBL. Here, as... Figure 5 As shown, the effective bit line VBL is arranged in parallel with the matched signal output line. Figure 3 The second pre-charge circuit unit 27 is omitted from the illustration. Furthermore, the first pre-charge circuit unit 26 is shown as being included in the matching line output circuit unit 24.

[0054] Reference Figure 5 Here is an example to describe the circuit configuration of the TCAM macrocell 100. Figure 5 It shows the relationship with Figure 3 The diagram shows an example of the circuit configuration corresponding to one entry of the TCAM macrocell shown.

[0055] TCAM units (MC00 to MC0n) are connected to the first word line WLA[0], the second word line WLB[0], and the match line ML[0]. Each TCAM unit (MC00 to MC0n) is connected to the corresponding bit line pair (BT[0] and BB[0] to BT[n] and BB[n]) and the corresponding search line pair (ST[0] and SB[0] to ST[n] and SB[n]).

[0056] The active cell VC0 includes a third word line VWL[0] and bit line pairs VBT and VBB. The active cell VC0 includes inverters IV1 and IV2, transfer MOS transistors (access transistors) TM1 and TM2, inverter IV3, and reset MOS transistor MRT. Here, transfer MOS transistors TM1 and TM2 and reset MOS transistor MRT are composed of N-channel MOS transistors. Inverter IV1 is connected between memory node VMT and memory node VMB such that the direction from memory node VMT to memory node VMB is positive. Inverter IV2 is connected in parallel to inverter IV1 in the opposite direction. The source-drain path of transfer MOS transistor TM1 is connected between memory node VMT and bit line VBT. The source-drain path of transfer MOS transistor TM2 is connected between memory node VMB and bit line VBB. The gates of transfer MOS transistors TM1 and TM2 are connected to the third word line VWL[0]. The drain of reset MOS transistor MRT is further connected to memory node VMT. The source of the reset MOS transistor MRT is connected to ground potential VSS. The gate of the reset MOS transistor MRT is connected to wiring RT, and a reset signal is supplied to wiring RT.

[0057] Note that each inverter in IV1 and IV2 has a P-channel MOS transistor and an N-channel MOS transistor. The source-drain paths of the P-channel MOS transistor and the N-channel MOS transistor are connected in series between the power supply potential VDD and the ground potential VSS. The gates of the P-channel MOS transistor and the N-channel MOS transistor are connected together to serve as the input terminal of the inverter. The drains of the P-channel MOS transistor and the N-channel MOS transistor are connected together to serve as the output terminal of the inverter.

[0058] The third word line VWL[0] is connected to the output of the OR[0] circuit. The input of the OR circuit OR[0] is connected to the first word line WLA[0] and the second word line WLB[0]. That is, the OR circuit OR[0] can be regarded as a selection circuit connected to the first word line WLA[0] and the second word line WLB[0], and is configured to cause the third word line VWL[0] to enter the selected state according to the selected state of the first word line WLA[0] or the second word line WLB[0].

[0059] The value of the storage node VMB of the valid cell VC0 is supplied to the matching line output circuit MO0 via inverter IV3 as the valid bit VB0. Inverter IV3 can be regarded as the output circuit of storage node VMB.

[0060] The matching line output circuit MO0 includes a NAND circuit Na10, a P-channel MOS transistor PM10, an N-channel MOS transistor NM10, and inverters IV5, IV6, and IV7. Here, the NAND circuit Na10 and the P-channel MOS transistor PM10 constitute the first pre-charge circuit PC10.

[0061] The first input of NAND circuit NA10 is connected to the output of inverter IV3 via the active bit line VBL[0] and receives the active bit VB0. The second input of NAND circuit NA10 receives the non-inverted signal of precharge control signal PCE via buffer circuit BF1. The output of NAND circuit NA10 is connected to the gate of P-channel MOS transistor PM10. The gate of N-channel MOS transistor NM10 receives the inverted signal of active bit VB0 via inverter IV5. The N-channel MOS transistor NM10 is configured to prevent the following operational problem: when active bit VB0 is low, the matching line ML[0] becomes a floating node because it is not precharged during the precharge period.

[0062] The source-drain paths of the P-channel MOS transistor PM10 and the N-channel MOS transistor NM10 are connected between the power supply potential VDD and the ground potential VSS. The matching line ML[0] is connected to the drains of the P-channel MOS transistor PM10 and the N-channel MOS transistor NM10. The drains of the P-channel MOS transistor PM10 and the N-channel MOS transistor NM10 are also connected to the matching signal output line MLO0 via inverters IV6 and IV7.

[0063] Reference Figure 6 This describes a configuration example for the pre-charge circuit. Figure 6 It shows the relationship with Figure 3 The diagram shows an example of the circuit configuration of the precharge circuit corresponding to an entry of a TCAM macrocell.

[0064] The active bit VB0 is connected from the active cell VC0 to the first precharge circuit PC10 and the second precharge circuit PC20 arranged on both sides of the TCAM cell array 20 via the active bit line VBL[0], which serves as the wiring. The configuration of the first precharge circuit PC10 is as described above.

[0065] The second precharge circuit PC20 of the second precharge circuit unit 27 includes a NAND circuit NA20 and a P-channel MOS transistor PM20. The first input of the NAND circuit NA20 is connected to the output of the inverter IV3 of the valid cell VCO via the valid bit line VBL[0], and receives the valid bit VB0. The second input of the NAND circuit NA20 receives the non-inverted signal of the precharge control signal PCE via the buffer circuit BF2. The output of the NAND circuit NA20 is connected to the gate of the P-channel MOS transistor PM20. The source-drain path of the P-channel MOS transistor PM20 is connected between the power supply potential VDD and the matching line ML[0].

[0066] The second pre-charge circuit PC20 is arranged on the matching line ML[0] near the word line driver 2. The first pre-charge circuit PC10 is arranged on the matching line ML[0] near the matching line output circuit MO0. Therefore, the matching line ML[0] is pre-charged from both sides by the first pre-charge circuit PC10 and the second pre-charge circuit PC20.

[0067] That is, the second pre-charge circuit PC20 is connected to one end of the matching line ML[0] near the word line driver 2, and pre-charges the matching line ML[0] to the pre-charge potential from one end of the matching line ML[0]. On the other hand, the first pre-charge circuit PC10 is connected to the other end of the matching line ML[0] near the matching line output circuit unit 24, and pre-charges the matching line ML[0] to the pre-charge potential from the other end of the matching line ML[0]. Here, the pre-charge potential is the high-level power supply potential VDD. That is, the direction of the pre-charge current of the first pre-charge circuit PC10 and the direction of the pre-charge current of the second pre-charge circuit PC20 are opposite to each other.

[0068] In wiring electromigration (EM), if the current does not flow continuously in one direction but in the opposite direction, the moved metal returns to its original position and the EM resistance is improved. If the TCAM memory cell MC driving the matching line ML is far from the precharge circuit, the current path will be unidirectional. However, by connecting the first precharge circuit PC10 and the second precharge circuit PC20 to the two ends of the matching line ML, the current path becomes bidirectional, thus improving the EM resistance of the TCAM macrocell.

[0069] Next, we will refer to Figure 5 To describe the write operation.

[0070] When entry data is written to TCAM units MC00 to MC0n, the first word line WLA[0] or the second word line WLB[0] enters the selected state, and the writing is performed by supplying write data to bit lines BT[0] and BB[0] to BT[n] and BB[n]. At this time, since the third word line VWL[0] of the valid unit VC0 is also introduced into the selected state through the OR circuit OR[0], the valid bit can be written to the valid unit VC0 by supplying write data to the valid unit VC0 using bit lines VBT and VBB. When the memory node VMT is high and the memory node VMB is low, that is, when the valid bit VB0 is high, the valid unit VC0 indicates that the entry is valid. On the other hand, when the memory node VMT is low and the memory node VMB is high, that is, when the valid bit VB0 is low, the valid unit VC0 indicates that the entry is invalid.

[0071] Reference Figure 5 and Figure 6 To describe the search operation.

[0072] The comparison operation between the entry data and the search data stored in the TCAM units (MC00 to MC0n) is performed by supplying the search data to the search line pairs (ST[0] and SB[0] to ST[n] and SB[n]).

[0073] When the active bit VB0 is high and the precharge control signal PCE enters standby mode (high level), P-channel MOS transistors PM10 and PM20 are turned on, and N-channel MOS transistor NM0 is turned off. Therefore, the matching line ML[0] is precharged to a high level.

[0074] When the valid bit VB0 is high and the precharge control signal PCE is active (low), P-channel MOS transistors PM10 and PM20 are off, and N-channel MOS transistor NM0 is off. Therefore, the matching line ML[0] enters a floating state. In this state, when the entry data and search data match, the precharge potential of the matching line ML[0] is held high. As a result, the matching signal output line MLO0 enters a high level indicating a match. On the other hand, when the entry data and search data do not match, the precharge potential of the matching line ML[0] becomes low. As a result, the matching signal output line MLO0 enters a low level indicating a mismatch.

[0075] On the other hand, when the active bit VB0 is low, P-channel MOS transistors PM10 and PM20 are off, and N-channel MOS transistor NM0 is on. Therefore, the potential of the matching line ML[0] goes low, and the matching signal output line MLO0 also goes low, indicating a mismatch.

[0076] When the stored contents of the valid cell VCO are reset, the reset signal supplied to the wiring RT goes high. As a result, since the reset MOS transistor MRT goes to the on state, the storage node VMT goes low and the storage node VMB goes high, causing invalid data to be stored in the valid cell VCO.

[0077] although Figure 5 The document describes an entry, but when the number of entries is as follows... Figure 3 When M+1 is shown, a third word line (VWL[0] to VWL[M]) is provided because multiple valid units (VC0 to VCm) are set.

[0078] (Revise)

[0079] In the following description, some typical modifications to the embodiments will be described. In the following description of the modifications, the same reference numerals as in the above embodiments are used for components having the same configuration and function as those described in the above embodiments. Furthermore, for the description of such components, the descriptions in the above embodiments can be appropriately incorporated into the scope of technical inconsistencies. Additionally, some and all or part of the above embodiments and multiple modifications can be appropriately applied within the scope of technical inconsistencies.

[0080] (First revision)

[0081] Reference Figure 7 This describes the pre-charge circuit in the first modification. Figure 7 This is a diagram illustrating an example of the circuit configuration of the precharge circuit corresponding to an entry of the TCAM macrocell in the first modification.

[0082] In TCAM cell arrays, the capacitance of the matching line ML is large, and the EM problem becomes apparent when the wiring width decreases due to miniaturization. Therefore, in the first modification, diode-connected P-channel MOS transistors PD10 and PD20 are placed between the P-channel MOS transistors PM10 and PM20 and the matching line ML[0]. As a result, the current can be mitigated by reducing the pre-charge level of the matching line ML[0].

[0083] (Second revision)

[0084] Reference Figures 8 to 10To describe the matching line output circuit in the second modification. Figure 8 This is a diagram illustrating an example of the circuit configuration of the matching line output circuit corresponding to an entry of the TCAM macrocell in the second modification. Figure 9 It shows Figure 8 A diagram showing an example of the circuit configuration of the sensing amplifier. Figure 10 This is a timing diagram used to describe the operation of the matching line output circuit in the second modification.

[0085] like Figure 8 As shown, the matching line output circuit MO0 includes transmission gates 40 and 41, a sensing amplifier 50, a power switch 51, a capacitor 60, and a latching circuit 70.

[0086] Transmission gate 40 is positioned between the matching line ML[0] and the input node CTM of the sense amplifier 50. Transmission gate 40 operates according to the control signal SWE1 / SWE1. Transmission gate 41 is positioned between the matching line ML[0] and the input node CBM. Transmission gate 41 operates according to the control signals SWE2 and / SWE2. Here, transmission gates 40 and 41 are configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in parallel. Control signals SWE1 and SWE2 are connected to the gate of the N-channel MOS transistor, and control signals / SWE1 and / SWE2 are connected to the gate of the P-channel MOS transistor.

[0087] When control signals SWE1 and SWE2 are set to high and control signals / SWE1 and / SWE2 are set to low, transmission gates 40 and 41 are turned on. As a result, the matching line ML[0] and input nodes CTM and CBM are connected.

[0088] On the other hand, when control signals SWE1 and SWE2 are set low and control signals / SWE1 and / SWE2 are set high, transmission gates 40 and 41 are turned off. As a result, the electrical connection between the matching line ML and the input nodes CTM and CBM either enters or exits contact.

[0089] The sensing amplifier 50 amplifies the potential difference between the input node CTM and the input node CBM, and outputs the amplified signal to the latch circuit 70.

[0090] The latch circuit 70 latches the low-level or high-level signal amplified by the sense amplifier 50 and outputs it to the match signal output line MLO0. When the match signal output line MLO0 is high, it indicates that the search data matches. On the other hand, when the match signal output line MLO0 is low, it indicates that the search data does not match.

[0091] A capacitor 60 is disposed between the input node CBM and the signal wiring 42, to which the control signal SWE1 is input. One end of the capacitor 60 is connected to the input node CBM, and the other end is connected to the signal wiring 42 that inputs the control signal SWE1. The capacitor 60 can adjust the potential of the input node CBM.

[0092] like Figure 9 As shown, the sense amplifier 50 includes P-channel MOS transistors 52 and 53, and N-channel MOS transistors 54 to 56.

[0093] P-channel MOS transistor 52 is disposed between power node N0 and input node CBM, and its gate is connected to input node CTM. P-channel MOS transistor 53 is disposed between power node N0 and input node CTM, and its gate is connected to input node CBM.

[0094] An N-channel MOS transistor 56 is provided between ground potential VSS and ground node N1, and its gate receives the input of control signal SAE. An N-channel MOS transistor 54 is disposed between ground node N1 and input node CBM, and its gate is connected to input node CTM. An N-channel MOS transistor 55 is disposed between ground node N1 and input node CTM, and its gate is connected to input node CBM.

[0095] A power switch 51, composed of a P-channel MOS transistor, is positioned between the power supply potential VDD and the power supply node N0. Its gate receives the input of a control signal / VB0, which is the inverted signal of the valid bit VB0. The sense amplifier 50 is activated based on whether the control signal SAE and / VB0 are at a high or low level. The sense amplifier 50 is deactivated based on whether the control signal SAE and / VB0 are at a low or high level.

[0096] Reference Figure 10 This describes situations where the search data does not match.

[0097] Before time T10, the potential of the matching line ML[0] is pre-charged to a high level (power supply potential VDD level). Furthermore, control signals SWE1 and SWE2 are set to high level, and control signals / SWE1 and / SWE2 are set to low level. Therefore, transmission gates 40 and 41 are turned on, and the matching line ML[0] is connected to the input nodes CTM and CBM.

[0098] At time T10, the search is initiated and search data is supplied to search line pairs ST and SB. As search line pairs ST and SB rise by coupling the capacitors C1 and C2 of search line pairs ST and SB, the entry data, and the matching line ML[0], the potential of the matching line ML[0] increases and becomes higher than the power supply potential VDD. Due to the search data mismatch, the potential of the matching line ML[0] decreases at time T11. Furthermore, control signal SWE1 is set to high level, and control signal / SWE1 is set to low level. Control signal SWE2 is set to low level, and control signal / SWE2 is set to high level. Therefore, transmission gate 40 is turned on, and the matching line ML[0] is connected to the input node CTM. Further, transmission gate 41 is turned off, and the input node CBM is set to the off state. Therefore, as the potential of the matching line ML[0] decreases, the potential of the input node CTM of the sensing amplifier 50 decreases. On the other hand, the potential of the input node CBM is maintained.

[0099] At time T12, control signal SWE1 is set to low, and control signal / SWE1 is set to high. Therefore, transmission gate 40 is turned off. Furthermore, the potential at the other end of capacitor 60 connected to input node CBM is set to low. As a result, the potential of input node CBM drops to a predetermined potential level.

[0100] Next, at time T13, the control signal SAE is set to high. Therefore, the sense amplifier 50 is activated. With the sense amplifier 50 activated, the potential difference between input node CTM and input node CBM is amplified, and input node CTM is set to ground potential VSS as the second potential, while input node CBM is set to power supply potential VDD as the first potential.

[0101] Next, we will refer to Figure 10 To describe the matching of search data.

[0102] Before time T20, the potential of the matching line ML[0] is pre-charged to a high level (power supply potential VDD level). Furthermore, control signals SWE1 and SWE2 are set to high level, and control signals / SWE1 and / SWE2 are set to low level. Therefore, transmission gates 40 and 41 are turned on, and the matching line ML is connected to the input nodes CTM and CBM.

[0103] At time T20, the search begins, and search data is supplied to search line pairs ST and SB. As search line pairs ST and SB rise by coupling the capacitors C1 and C2 of search line pairs ST and SB, the entry data, and the matching line ML[0], the potential of the matching line ML[0] increases and becomes higher than the power supply potential VDD. The potential of the matching line ML[0] is maintained because the entry data and search data are matched. In addition, control signal SWE1 is set to high level, and control signal / SWE1 is set to low level. Control signal SWE2 is set to low level, and control signal / SWE2 is set to high level. Therefore, transmission gate 40 is turned on, and the matching line ML[0] and input node CTM are connected. In addition, transmission gate 41 is turned off, and input node CBM is set to the off state. Therefore, while the potential of the matching line ML[0] is maintained, the potentials of the input nodes CTM and CBM of the sensing amplifier 50 are set to the power supply potential VDD.

[0104] At time T22, control signal SWE1 is set to low, and control signal / SWE1 is set to high. Therefore, transmission gate 40 is turned off. Furthermore, the potential at the other end of capacitor 60 connected to input node CBM is set to low. As a result, the potential of input node CBM drops to a predetermined potential level.

[0105] Next, at time T23, the control signal SAE is set to high. Therefore, the sense amplifier 50 is activated. With the sense amplifier 50 activated, the potential difference between input node CTM and input node CBM is amplified, and input node CTM is set to the power supply potential VDD, while input node CBM is set to the ground potential VSS.

[0106] The second modified sensing amplifier 50 asserts the search line pairs ST and SB, and then generates the reference potential of the input node CBM to be compared from the matching line ML. Therefore, by coupling the search line pairs ST and SB, it is possible to handle situations where the matching line ML moves or the pre-charge level changes. Furthermore, a voltage generation circuit for generating the reference voltage to be compared is not required, and the area can be reduced.

[0107] Note that the power supply potential VDD is supplied to the sense amplifier of the matching line output circuit MO0 via the control signal / VB0, not the inverted signal of the control signal SAE. When the entry becomes invalid (VB0=0), the matching line ML goes low, and the input node CTM goes low. This results in the input node CBM becoming negative, and the sense output going high, causing the match to be output. To prevent this erroneous reading, the control signal / VB0 stops the supply of the power supply potential VDD to the sense amplifier.

[0108] [Application Example]

[0109] Figure 11 This is a block diagram of a semiconductor device in an application example.

[0110] Semiconductor device 400 is formed on a semiconductor chip. Semiconductor device 400 has functions such as a data processing device for a network (such as a packet router).

[0111] Semiconductor device 400 includes input / output circuitry (I / O_PRT) 401, processor (PRC) 402, and pipeline control circuitry (PPL_CNT) 403. Semiconductor device 400 also includes TCAM control circuitry (TCAM_CNT) 404, TCAM macrocell (TCAM_MCR) 100, priority encoder (PREN) 300, and SRAM 405 as a memory device. As TCAM macrocell 100, any configuration of the embodiment, the first modification, and the second modification, or a combination thereof, can be applied as needed.

[0112] Input / output circuit 401 is connected to the outside of semiconductor device 400 via input / output bus BUS1. Input / output circuit 401 is also connected to processor 402, TCAM control circuit 404, and SRAM 405 via internal bus BUS2. Input / output circuit 401 is also connected to pipeline control circuit 403 via internal bus BUS3. Pipeline control circuit 403 is connected to processor 402 and TCAM control circuit 404 via internal bus BUS4 and controls the operation of processor 402 and TCAM control circuit 404. Processor 402 is connected to TCAM control circuit 404 via internal bus BUS5. Furthermore, priority encoder 300 is connected to SRAM 405 via internal bus BUS6, and SRAM 405 is connected to the outside of semiconductor device 400 via input / output bus BUS7.

[0113] The TCAM control circuit 404 controls the operation of the TCAM macrocell 100 and instructs the TCAM macrocell 100 to store or update entries and perform search operations. The TCAM control circuit 404 stores the search key (search data) used for the search operation.

[0114] The priority encoder 300 acquires the search results from the TCAM macrocell 100 and outputs the search results to the SRAM 405 according to a predetermined priority order. The SRAM 405 accesses the SRAM 405 by address based on the search results from the priority encoder 300 and outputs the access results to an external device, such as the semiconductor device 400, via the input / output bus BUS7.

[0115] Although the disclosure of this disclosure has been specifically described above based on embodiments and modifications, it is self-evident that this disclosure is not limited to the above embodiments and modifications, and can be modified in various ways.

Claims

1. A semiconductor device, comprising: Matching line; Multiple memory cells are connected to the matching line; Word lines are connected to each of the plurality of memory cells; Word line driver, connected to the word line; The output circuit is connected to the matching line; The valid unit is configured to store a valid bit indicating whether an entry is valid or invalid. A first pre-charge circuit is connected to one end of the matching line and is configured to pre-charge the matching line to a high level based on a pre-charge control signal when the valid bit indication stored in the valid cell is valid. as well as A second pre-charge circuit is connected to the other end of the matching line and is configured to pre-charge the matching line to a high level based on the pre-charge control signal when the valid bit indication stored in the valid cell is valid. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit. The second precharge circuit is arranged between the word line driver and the plurality of memory cells. The word line driver, the second precharge circuit, the plurality of memory cells, the active cell, the first precharge circuit, and the output circuit are arranged in this order in a first direction. The semiconductor device further includes signal wiring, to which the valid bit is transmitted. The signal wiring and the matching line extend along the first direction between the first precharge circuit and the second precharge circuit, and Each of the first pre-charge circuit and the second pre-charge circuit includes: i) a first P-channel MOS transistor, wherein the source-drain path of the first P-channel MOS transistor is electrically connected between the power supply and the matching line; And ii) a second P-channel MOS transistor, which is connected in a diode manner between the first P-channel MOS transistor and the matching line.

2. A semiconductor device, comprising: Multiple search memory units arranged in a matrix; Multiple matching lines are each set to correspond to a row of memory cells and configured to determine a match / mismatch between the data stored in the search memory cell and the search data; Multiple valid information units are each configured to correspond to the memory cell row and to store information indicating whether the memory cell row is valid. A plurality of first precharge circuits are each configured to correspond to the row of memory cells and to supply a first potential to one end of the matching line; Multiple second precharge circuits are each configured to correspond to the row of memory cells and to supply the first potential to the other end of the matching line; Each of the matching line output circuits is configured to correspond to the row of memory cells and is connected to the matching line. When the information stored in the corresponding valid information unit is valid, the first pre-charging circuit and the second pre-charging circuit pre-charge the corresponding matching line to the first potential before data search, and set the corresponding matching line to an open state during data search. When the search data does not match, the matching line is electrically connected to a second potential lower than the first potential via the corresponding row of the search memory cell. The first pre-charge circuit and the second pre-charge circuit operate according to the pre-charge control signal. The second pre-charge circuit, the search memory unit, the valid information unit, the first pre-charge circuit, and the matching line output circuit are arranged in this order in the first direction. The semiconductor device further includes a plurality of signal lines, each of which is configured to correspond to a row of memory cells, and the information is transmitted to the plurality of signal lines. The signal wiring and the matching line extend along the first direction between the first precharge circuit and the second precharge circuit. Each of the first pre-charge circuit and the second pre-charge circuit includes: i) a first P-channel MOS transistor having one end electrically connected to a first power supply potential and the other end electrically connected to the matching line; and ii) a second P-channel MOS transistor being connected in a diode manner between the other end of the first P-channel MOS transistor and the matching line.

3. The semiconductor device according to claim 2 further includes a matching signal output line connected to the matching line output circuit. When the information stored in the corresponding valid information unit indicates validity, the matching line output circuit outputs a high or low level of the matching line to the matching signal output line; and When the information stored in the corresponding valid information unit is invalid, the matching line output circuit sets the matching signal output line to a low level.

4. A semiconductor device, comprising: Multiple search memory units arranged in a matrix; Multiple matching lines are each set to correspond to a row of memory cells and configured to determine a match / mismatch between the data stored in the search memory cell and the search data; Multiple valid information units are each configured to correspond to the memory cell row and to store information indicating whether the memory cell row is valid. A plurality of first precharge circuits are each configured to correspond to the row of memory cells and to supply a first potential to one end of the matching line; Multiple second precharge circuits are each configured to correspond to the row of memory cells and to supply the first potential to the other end of the matching line; Each of the matching line output circuits is configured to correspond to the row of memory cells and is connected to the matching line. When the information stored in the corresponding valid information unit is valid, the first pre-charging circuit and the second pre-charging circuit pre-charge the corresponding matching line to the first potential before data search, and set the corresponding matching line to an open state during data search. The matching line output circuit includes a differential sensing amplifier. The differential sense amplifier outputs a signal obtained by amplifying a potential difference based on a comparison between the potential of the corresponding matching line and a reference potential to be compared. The differential sensing amplifier has an input node and an input reference node. The potential of the corresponding matching line is input to the input node, and the reference potential to be compared is input to the input reference node. The semiconductor device further includes: A capacitor having one end connected to the input reference node; as well as The first control signal is wired and connected to the other end of the capacitor.

5. The semiconductor device according to claim 4, further comprising: A first switch is configured to electrically connect the matching line and the input node according to a first control command wired by the first control signal. as well as The second switch is configured to electrically connect the matching line and the input reference node according to the second control command.

6. The semiconductor device according to claim 5, The first control instruction and the second control instruction have different input timings.

Images