Display device

Abstract

A display device is provided. The display device includes a main display area in which a main display element is disposed, and an assembly area in which an auxiliary display element and a transmissive area are disposed, and includes: a first pixel definition layer disposed in the main display area, the first pixel definition layer being located between first pixel electrodes of the main display element; a second pixel definition layer disposed in the assembly area, the second pixel definition layer being located between second pixel electrodes of the auxiliary display element; a black matrix disposed on the main display element, the black matrix being located around an emission area of the main display element; and a color filter disposed on the main display element and the auxiliary display element, the color filter being disposed to correspond to the emission area of the main display element and the emission area of the auxiliary display element, respectively.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2020-0066018, filed on June 1, 2020, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention generally relate to a display device, and more specifically, to a display panel and a display device including the display panel, wherein transmittance is ensured in areas where electronic components are arranged. Background Technology

[0003] Recently, the applications of display devices have diversified. Furthermore, with the reduction in the thickness and weight of display devices, their applications have increased.

[0004] Because display devices are used in different ways, there are various ways to design the shape of the display device and to apply or link an increased number of functions to the display device.

[0005] The information disclosed in this background section is only for understanding the background art of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] An apparatus constructed according to exemplary embodiments of the invention can provide a display panel and a display device including the display panel, wherein transmittance is ensured in areas where components as electronic elements are arranged. However, it should be understood that the embodiments described herein should be considered in a descriptive sense only and not as limiting embodiments.

[0007] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the embodiments presented.

[0008] According to one or more embodiments, a display device includes a main display region in which a main display element is disposed and an assembly region in which an auxiliary display element and a transmissive region are disposed. The display device includes: a first pixel defining layer disposed in the main display region, the first pixel defining layer being located between first pixel electrodes of the main display element; a second pixel defining layer disposed in the assembly region, the second pixel defining layer being located between second pixel electrodes of the auxiliary display element; a black matrix disposed on the main display element, the black matrix being located around the emission region of the main display element; and a color filter disposed on the main display element and the auxiliary display element, the color filter being arranged to correspond to the emission region of the main display element and the emission region of the auxiliary display element, respectively.

[0009] The first pixel defining layer may include an opaque material, and the second pixel defining layer may include a transparent material.

[0010] The display device may further include: a first spacer located on a first pixel defining layer; an insulating pattern disposed in a component region; and a second spacer located on the insulating pattern.

[0011] The second pixel defining layer may cover the insulating pattern, and the second spacer may be part of the second pixel defining layer arranged on the insulating pattern.

[0012] The second pixel defining layer can be separated from the insulating pattern, and the slit can surround the insulating pattern between the second pixel defining layer and the insulating pattern.

[0013] The display device may further include: a first spacer located on the first pixel defining layer; and a second spacer as part of the second pixel defining layer, the second spacer being a portion protruding from the second pixel defining layer.

[0014] Each of the first pixel-defining layer and the second pixel-defining layer may include opaque material.

[0015] The second pixel defining layer may include a first insulating pattern surrounding the edge of the second pixel electrode.

[0016] The display device may further include: a first spacer located on a first pixel defining layer; a second insulating pattern located between the first insulating patterns, the second insulating pattern being spaced apart from the first insulating pattern; and a second spacer located on the second insulating pattern.

[0017] The second insulating pattern may include an opaque material, and each of the first spacer and the second spacer may include a transparent material.

[0018] The first pixel defining layer may include a third insulating pattern surrounding the edge of the first pixel electrode.

[0019] The display device may further include: a fourth insulating pattern located between the third insulating patterns and spaced apart from the third insulating patterns; a first spacer located on the fourth insulating pattern; a second insulating pattern located between the first insulating patterns and spaced apart from the first insulating patterns; and a second spacer located on the second insulating pattern.

[0020] Each of the second and fourth insulating patterns may include an opaque material, and each of the first and second spacers may include a transparent material.

[0021] The display device may further include: a first spacer as part of a first pixel defining layer, the first spacer being a portion protruding from the first pixel defining layer; and a second spacer located between the first insulating patterns, the second spacer being spaced apart from the first insulating patterns and including portions with different heights.

[0022] The second spacer may include an opaque material.

[0023] The display device may further include: a first spacer located between the third insulating patterns, the first spacer being spaced apart from the third insulating patterns and including portions of different heights; and a second spacer located between the first insulating patterns, the second spacer being spaced apart from the first insulating patterns and including portions of different heights.

[0024] Each of the first spacer and the second spacer may include an opaque material.

[0025] The edge of the second pixel-defined layer in the component area can overlap with the edge of the first pixel-defined layer in the main display area.

[0026] According to one or more embodiments, a display device includes a main display region in which a main display element is disposed and an assembly region in which an auxiliary display element and a transmissive region are disposed. The display device includes: a first pixel defining layer disposed in the main display region and covering the edge of a first pixel electrode of the main display element; a first spacer located between the first pixel electrodes of the main display element; a second pixel defining layer disposed in the assembly region and covering the edge of a second pixel electrode of the auxiliary display element; and a second spacer located between the second pixel electrodes of the auxiliary display element.

[0027] The second spacer can be arranged on an insulating pattern between the second pixel electrodes of the auxiliary display element.

[0028] The second pixel defining layer may include an insulating pattern surrounding the edge of the second pixel electrode.

[0029] The second spacer can be located between insulating patterns and can include portions with different heights.

[0030] The second spacer may be part of the second pixel defining layer, and the second spacer is a portion protruding from the second pixel defining layer.

[0031] The display device may further include: a thin-film encapsulation layer disposed on the main display element and the auxiliary display element; a black matrix disposed on the thin-film encapsulation layer, the black matrix being located around the emission area of ​​the main display element; and a color filter disposed on the thin-film encapsulation layer, the color filter corresponding to the emission area of ​​the main display element and the emission area of ​​the auxiliary display element, respectively.

[0032] Further features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description or may be learned by practice of the inventive concept.

[0033] It will be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the invention as claimed. Attached Figure Description

[0034] The accompanying drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. The drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification.

[0035] Figure 1 and Figure 2 This is a schematic plan view of a display panel according to an exemplary embodiment of the invention.

[0036] Figure 3 and Figure 4 This is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment of the invention.

[0037] Figure 5 This is a schematic plan view of a display panel according to an exemplary embodiment of the invention.

[0038] Figure 6A and Figure 6B This is an equivalent circuit diagram of a pixel circuit for driving a main sub-pixel and an auxiliary sub-pixel according to an exemplary embodiment of the invention.

[0039] Figure 7 This is a schematic layout diagram of the pixel arrangement structure in the main display area according to an exemplary embodiment of the invention.

[0040] Figure 8A and Figure 8B This is a schematic layout diagram of the pixel arrangement structure in the component area according to an exemplary embodiment of the invention.

[0041] Figure 9 It is a schematic cross-sectional view of a portion of the display panel according to an embodiment, which is a schematic cross-sectional view of the main display area and the component area.

[0042] Figure 10 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the invention.

[0043] Figure 11 yes Figure 10 A schematic plan view of the display layer of the main display area.

[0044] Figure 12 yes Figure 10A schematic plan view of the touchscreen layer in the main display area.

[0045] Figure 13A and Figure 13B yes Figure 10 A schematic plan view of the optical functional layer of the main display area.

[0046] Figure 14 yes Figure 10 A schematic plan view of the display layer of the second component area.

[0047] Figure 15 yes Figure 10 A schematic plan view of the optical functional layer of the second component region.

[0048] Figure 16A , Figure 16B , Figure 16C and Figure 16D It is based on Figure 10 The cross-sectional view of the display panel showing the manufacturing process of the display device is shown.

[0049] Figure 17A This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the invention.

[0050] Figure 17B yes Figure 17A A schematic plan view of the optical functional layers of the second and third component regions.

[0051] Figure 18A and Figure 18B This is a cross-sectional view of the second spacer according to an exemplary embodiment of the invention.

[0052] Figure 19A and Figure 19B These are a plan view and a cross-sectional view of the arrangement of the pixel-limiting layer at the boundary between the main display area and the second component area.

[0053] Figure 20 This is a schematic plan view of a portion of a display panel according to an exemplary embodiment of the invention.

[0054] Figure 21 yes Figure 20 A schematic plan view of the display layer of the second component area.

[0055] Figure 22 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the invention.

[0056] Figure 23 yes Figure 22 A schematic plan view of the display layer of the second component area.

[0057] Figure 24 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the invention.

[0058] Figure 25 yes Figure 24 A schematic plan view of the display layer of the main display area.

[0059] Figure 26 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the invention.

[0060] Figure 27A yes Figure 26 A schematic plan view of the display layer of the main display area.

[0061] Figure 27B yes Figure 26 A schematic plan view of the display layer of the second component area.

[0062] Figure 28 This is a schematic cross-sectional view of a portion of a display panel according to an exemplary embodiment of the invention.

[0063] Figure 29 yes Figure 28 A schematic plan view of the display layer of the main display area.

[0064] Figure 30A and Figure 30B Is Figure 26 and Figure 28 An exemplary view of the method of forming a first insulating pattern and spacers in the display panel shown. Detailed Implementation

[0065] In the following description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods applying one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, construction, and characteristic of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0066] Unless otherwise stated, the exemplary embodiments shown should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter, individually or collectively referred to as “elements”) of various embodiments may be additionally combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0067] Crosshairs and / or shading are typically used in accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, or any other characteristics, properties, etc. Furthermore, in the accompanying drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of the described sequence. Moreover, the same reference numerals denote the same elements.

[0068] When a component or layer is referred to as being "on," "connected to," or "bonded to" another component or layer, the component or layer may be directly on, connected to, or bonded to the other component or layer, or there may be intermediate components or layers present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another component or layer, there are no intermediate components or layers present. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without intermediate components. Furthermore, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system but can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “selection of at least one from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0069] Although the terms “first,” “second,” etc., may be used here to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the publicly stated teachings, the first element discussed below may be referred to as the second element.

[0070] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in a “sidewall”) may be used herein to describe the relationship of one element to another (other) element as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would subsequently be positioned “above” said other elements or features. Thus, the exemplary term “below” can include both above and below orientations. Furthermore, the device may be positioned alternatively (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0071] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well. Furthermore, when the terms “comprising” and variations thereof and / or “including” and variations thereof are used in this specification, it indicates the presence of stated features, integrals, steps, operations, elements, components, and / or groups thereof, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than as terms of degree, thus explaining the inherent biases in measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0072] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. Thus, shape variations in the illustrations will be expected, for example, due to manufacturing techniques and / or tolerances. Therefore, the exemplary embodiments disclosed herein are not necessarily to be construed as limited to the shapes of the specifically shown areas, but will include shape deviations caused, for example, by manufacturing processes. In this way, the areas shown in the figures can be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, thus not necessarily intended to be limiting.

[0073] In accordance with the conventions of the art, exemplary embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.) formed using semiconductor-based manufacturing techniques or other manufacturing techniques. When blocks, units, and / or modules are implemented using microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and the blocks, units, and / or modules can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing certain functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of some exemplary embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, some exemplary embodiments of blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules.

[0074] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms (such as those defined in general dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0075] Figure 1 and Figure 2 This is a schematic plan view of the display panel according to an embodiment.

[0076] The display panel can be a light-emitting display panel that includes light-emitting elements. For example, the display panel can be an organic light-emitting display panel that uses organic light-emitting diodes (LEDs) that include organic emission layers, a micro-LED display panel that uses micro-LEDs, a quantum dot light-emitting display panel that uses quantum dot LEDs that include quantum dot emission layers, or an inorganic light-emitting display panel that uses inorganic light-emitting elements that include inorganic semiconductors.

[0077] The display panel can be a rigid display panel that is not easily bendable due to its rigidity, or a flexible display panel that is easily bendable, foldable, or rollable due to its flexibility. For example, the display panel can be a foldable display panel that can be folded and unfolded, a curved display panel with a curved display surface, a curved display panel with a curved area other than the display surface, a rollable display panel that can be rolled and unfolded, or a stretchable display panel that can be stretched.

[0078] The display panel includes a display area DA in which an image is displayed and a peripheral area DPA in which no image is displayed. The display area DA includes a main display area MDA and a component area CA. The main display area MDA and the component area CA can display images individually or together. The peripheral area DPA can be a non-display area in which no display elements are arranged. The display area DA can be completely surrounded by the peripheral area DPA. Components, as electronic components, can be arranged under the component area CA.

[0079] The component may be a camera using infrared or invisible light and may include an imaging device. Alternatively, the component may be a solar cell, a flash, an illuminance sensor, a proximity sensor, or an iris sensor. Alternatively, the component may receive sound. To minimize functional limitations of the component, the component region CA may include a transmission area through which light and / or sound traveling from the component output to the outside or from the outside toward the component can be transmitted.

[0080] In an embodiment, the component region CA may have a higher transmittance and / or sound transmittance than the main display region MDA. In an embodiment, when light is transmitted through the component region CA, the transmittance may be about 10% or more, more preferably 25% or more, 30% or more, 50% or more, 75% or more, 80% or more, 85% or more, or 90% or more.

[0081] Component regions (CAs) can be placed inside and surrounded by the main display area (MDA). Furthermore, component regions (CAs) can be circular in shape and can be a single component region (CA) or multiple component regions (CAs). As an example, Figure 1 A component region CA is shown, and Figure 2Three component areas CA are shown: a first component area CA1, a second component area CA2, and a third component area CA3. Each of the first to third component areas CA3 is surrounded by a main display area MDA. The first component can be arranged to correspond to the first component area CA1, the second component to correspond to the second component area CA2, and the third component to correspond to the third component area CA3. The first to third components can have different functions. In an embodiment, a camera can be arranged in the first component area CA1, an illuminance sensor can be arranged in the second component area CA2, and a proximity sensor can be arranged in the third component area CA3.

[0082] exist Figure 1 and Figure 2 The example shows a component region CA with a circular shape, but the embodiment is not limited to this. For example, the component region CA may have an elliptical shape or a polygonal shape such as a triangle or pentagon, and the position and size of the component region CA may be modified in various ways.

[0083] Figure 3 and Figure 4 This is a schematic cross-sectional view of a portion of the cross-section of the display device 1 according to an embodiment.

[0084] Reference Figure 3 and Figure 4 The display device 1 may include a display panel 10 and a component 40 stacked with the display panel 10. A cover window (not shown) protecting the display panel 10 may be further arranged on the display panel 10.

[0085] Display panel 10 may include a component area CA superimposed on component 40 and a main display area MDA displaying the main image thereon. Display panel 10 may include a substrate 100, a display layer DISL, a touch screen layer TSL, an optical functional layer OFL, and a panel protection member PB located under the substrate 100.

[0086] The display layer DISL may include: a circuit layer PCL, including thin-film transistors TFT and TFT'; a display element layer EDL, including light-emitting elements ED and ED' as display elements; and an encapsulation component ENCM, such as a thin-film encapsulation layer TFEL or a sealing substrate (not shown). Insulating layers IL and IL' may be located between the substrate 100 and the display layer DISL, and are located inside the display layer DISL.

[0087] The main sub-pixel Pm, including the main light-emitting element ED, and the main thin-film transistor TFT connected to the main sub-pixel Pm can be arranged in the main display area MDA of the display panel 10, and the auxiliary sub-pixel Pa, including the auxiliary light-emitting element ED', and the auxiliary thin-film transistor TFT' connected to the auxiliary sub-pixel Pa can be arranged in the component area CA.

[0088] Additionally, the transmissive region TA, where no display element is disposed, can be disposed within the component region CA. The transmissive region TA can be the area through which light / signal emitted from the component 40 arranged corresponding to the component region CA, or light / signal incident on the component 40, is transmitted.

[0089] A bottom metal layer (BML) can be disposed within the component region CA. The bottom metal layer (BML) can be positioned corresponding to the lower portion of the auxiliary thin-film transistor (TFT) '. For example, the bottom metal layer (BML) can be located between the auxiliary thin-film transistor (TFT) ' and the substrate 100. The bottom metal layer (BML) can block external light from reaching the auxiliary thin-film transistor (TFT). In some embodiments, a constant voltage or signal can be applied to the bottom metal layer (BML).

[0090] The display element layer (EDL) may be covered by a thin-film encapsulation layer (TFEL) or a sealing substrate. In some embodiments, the TFEL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the TFEL may include a first inorganic encapsulation layer 161, a second inorganic encapsulation layer 163, and an organic encapsulation layer 162 located therebetween.

[0091] When the display element layer EDL is sealed by a sealing substrate (not shown), the sealing substrate may be arranged facing the substrate 100, and the display element layer EDL may be located between the sealing substrate and the substrate 100. A gap may exist between the sealing substrate and the display element layer EDL. The sealing substrate may include glass. A sealant formed from glass may be located between the substrate 100 and the sealing substrate, and the sealant may be disposed in the aforementioned peripheral region DPA. The sealant disposed in the peripheral region DPA may surround the display area DA and prevent moisture from penetrating through the side surface of the display panel 10.

[0092] A touchscreen layer (TSL) can obtain coordinate information based on external input (e.g., touch events). A TSL may include touch electrodes and wiring connected to them. The TSL can sense external input using either self-capacitance or mutual capacitance methods.

[0093] The touchscreen layer TSL can be formed on the thin-film encapsulation layer TFEL. Alternatively, the touchscreen layer TSL can be formed separately on the touch substrate and then bonded to the thin-film encapsulation layer TFEL via an adhesive layer such as an optically clear adhesive (OCA). In an embodiment, the touchscreen layer TSL can be formed directly on the thin-film encapsulation layer TFEL, and in this case, the adhesive layer may not be located between the touchscreen layer TSL and the thin-film encapsulation layer TFEL.

[0094] The optical functional layer OFL may include an anti-reflective layer. The anti-reflective layer can reduce the reflectivity of light (external light) incident on the display device 1.

[0095] In some embodiments, the optical functional layer OFL may include a polarizing film. The OFL may include an opening OFL_OP corresponding to the transmission region TA. Therefore, the transmittance in the transmission region TA can be significantly improved. The opening OFL_OP may be filled with a transparent material, such as optically transparent resin (OCR).

[0096] In some embodiments, such as Figure 4 As shown, the optical functional layer OFL can be configured as a filter plate 180 including a black matrix and color filters. The filter plate 180 may include a color filter 182, a black matrix 183, and an outer coating 184. The color filter 182 can be arranged considering the color of light emitted from the pixels of the display panel 10. For example, depending on the color of light emitted from the light-emitting elements ED and ED', the color filter 182 may be red, green, or blue. The color filter 182 and the black matrix 183 may not be located in the transmission region TA. For example, the layer including the color filter 182 and the black matrix 183 may include holes 183OP corresponding to the transmission region TA, and the holes 183OP may be at least partially filled with the outer coating 184. The outer coating 184 may include an organic material such as resin, and the aforementioned organic material may be transparent.

[0097] Compared to display devices that include polarizing plates, display devices that include an optical functional layer OFL with color filter 182 and black matrix 183 can have a significantly reduced thickness.

[0098] A cover window (not shown) can be arranged on the display panel 10 to protect the display panel 10. The optical functional layer OFL can be attached to the cover window using an OCA or can be attached to the touch screen layer TSL using an OCA.

[0099] The panel protection member PB can be attached to the lower part of the substrate 100 to support and protect the substrate 100. The panel protection member PB may include an opening PB_OP corresponding to the component region CA. Because the panel protection member PB includes the opening PB_OP, the light transmittance in the component region CA can be increased. The panel protection member PB may include polyethylene terephthalate (PET) or polyimide (PI).

[0100] The area of ​​component region CA can be larger than the area where component 40 is arranged. Therefore, the area of ​​the opening PB_OP in the panel protection component PB does not necessarily correspond to the area of ​​component region CA.

[0101] Figure 5 This is a schematic plan view of the display panel 10 according to an embodiment.

[0102] Reference Figure 5 Various components constituting the display panel 10 can be arranged on the substrate 100. The substrate 100 includes a display area DA and a peripheral area DPA surrounding the display area DA. The display area DA includes a main display area MDA on which the main image is displayed and a component area CA on which an auxiliary image is displayed. The component area CA includes a transmissive area TA. The auxiliary image can form a whole image together with the main image or it can be an image independent of the main image.

[0103] Multiple primary sub-pixels Pm are arranged in the main display area MDA. Each primary sub-pixel Pm can be implemented using a display element such as an organic light-emitting diode (OLED). Each primary sub-pixel Pm can emit, for example, red, green, blue, or white light. The main display area MDA can be covered by an encapsulation component ENCM, thus protecting it from external air or moisture.

[0104] As described above, the component region CA can be located on one side of the main display region MDA, or it can be arranged inside the display region DA and surrounded by the main display region MDA. Multiple auxiliary subpixels Pa are arranged within the component region CA. Each auxiliary subpixel Pa can be implemented using a display element such as an OLED. Each auxiliary subpixel Pa can emit, for example, red, green, blue, or white light. The component region CA can be covered by an encapsulation component ENCM and is therefore protected from external air or moisture.

[0105] The component region CA may have a transmission region TA. The transmission region TA may be arranged around the auxiliary sub-pixel Pa. Alternatively, the transmission region TA and the auxiliary sub-pixel Pa may be arranged in a grid pattern.

[0106] The component area CA includes the transmission area TA; therefore, the resolution of the component area CA can be lower than the resolution of the main display area MDA. For example, the resolution of the component area CA can be approximately 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, or 1 / 16 of the resolution of the main display area MDA. For example, the resolution of the main display area MDA can be approximately 400 ppi or higher, and the resolution of the component area CA can be approximately 200 ppi or approximately 100 ppi.

[0107] The pixel circuits driving the main sub-pixel Pm and the auxiliary sub-pixel Pa can be electrically connected to external circuits arranged in the peripheral area DPA. The first scan drive circuit SDRV1, the second scan drive circuit SDRV2, the terminal part PAD, the drive voltage supply line 11, and the common voltage supply line 13 can be arranged in the peripheral area DPA.

[0108] The first scan drive circuit SDRV1 can be configured to apply a scan signal to each pixel circuit driving the main sub-pixel Pm and the auxiliary sub-pixel Pa via the scan line SL. The first scan drive circuit SDRV1 can be configured to apply an emission control signal to each pixel circuit via the emission control line EL. The second scan drive circuit SDRV2 can be located on the opposite side of the first scan drive circuit SDRV1 relative to the main display area MDA, and can be substantially parallel to the first scan drive circuit SDRV1. Some pixel circuits of the main sub-pixel Pm in the main display area MDA can be electrically connected to the first scan drive circuit SDRV1, and the remaining pixel circuits can be electrically connected to the second scan drive circuit SDRV2. Some pixel circuits of the auxiliary sub-pixel Pa in the component area CA can be electrically connected to the first scan drive circuit SDRV1, and the remaining pixel circuits can be electrically connected to the second scan drive circuit SDRV2. The second scan drive circuit SDRV2 can be omitted.

[0109] The terminal portion PAD can be disposed on one side of the substrate 100. The terminal portion PAD is exposed without being covered by an insulating layer and is connected to the display circuit board 30. The display driver 32 can be disposed on the display circuit board 30.

[0110] The display driver 32 can be configured to generate control signals that are transmitted to the first scan drive circuit SDRV1 and the second scan drive circuit SDRV2. The display driver 32 can be configured to generate data signals, and the generated data signals can be transmitted to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa via the fan-out wiring FW and the data line DL connected to the fan-out wiring FW.

[0111] Display driver 32 can be configured to drive voltage ELVDD (see...). Figure 6A) is supplied to drive voltage supply line 11, and can be configured to supply the common voltage ELVSS (see Figure 6A The driving voltage ELVDD can be applied to the pixel circuits of the main sub-pixel Pm and the auxiliary sub-pixel Pa through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS can be applied to the counter electrode of the display element through the common voltage supply line 13.

[0112] The drive voltage supply line 11 can be connected to the terminal portion PAD and can extend in the x direction from below the main display area MDA. The common voltage supply line 13 can be connected to the terminal portion PAD and can have a shape in which one side is open in a ring and thus partially surrounds the main display area MDA.

[0113] Figure 6A and Figure 6B This is an equivalent circuit diagram of the pixel circuit PC that drives the main sub-pixel Pm and the auxiliary sub-pixel Pa according to an embodiment.

[0114] Reference Figure 6A The pixel circuit PC (hereinafter, it may also be referred to as the main pixel circuit PC or the auxiliary pixel circuit PC') can be connected to a light-emitting element to enable the sub-pixel to emit light. The light-emitting element may be an OLED. The pixel circuit PC may include a driving transistor T1, a switching transistor T2, and a capacitor Cst (hereinafter, it may also be referred to as the main capacitor Cst or the auxiliary capacitor Cst'). The switching transistor T2 can be connected to the scan line SL and the data line DL, and can be configured to transmit the data signal Dm input through the data line DL to the driving transistor T1 according to the scan signal Sn input through the scan line SL.

[0115] The capacitor Cst can be connected to the switching transistor T2 and the drive voltage line PL, and can be configured to store a voltage corresponding to the difference between the voltage received from the switching transistor T2 and the drive voltage ELVDD supplied to the drive voltage line PL.

[0116] The driving transistor T1 can be connected to the driving voltage line PL and the capacitor Cst, and can be configured to control the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) (hereinafter, it can also be referred to as the main OLED or the auxiliary OLED) in response to the value of the voltage stored in the capacitor Cst. The OLED can emit light with a certain brightness according to the driving current.

[0117] exist Figure 6A The pixel circuit PC has been described as including two thin-film transistors and a storage capacitor, but the embodiments are not limited thereto.

[0118] Reference Figure 6B The pixel circuit PC may include first transistors to seventh transistors T1, T2, T3, T4, T5, T6, and T7, and depending on the type of transistor (p-type or n-type) and / or operating conditions, each of the first transistors T1 to the seventh transistor T7 may include a first terminal as a source terminal or a drain terminal and a second terminal as a terminal different from the first terminal. For example, when the first terminal is a source terminal, the second terminal may be a drain terminal.

[0119] The pixel circuit PC can be connected to a first scan line SL configured to transmit a first scan signal Sn, a second scan line SL-1 configured to transmit a second scan signal Sn-1, a third scan line SL+1 configured to transmit a third scan signal Sn+1, a transmit control line EL configured to transmit a transmit control signal En, a data line DL configured to transmit a data signal Dm, a drive voltage line PL configured to transmit a drive voltage ELVDD, and an initialization voltage line VL configured to transmit an initialization voltage Vint.

[0120] The first transistor T1 includes a gate terminal connected to the second node N2, a first terminal connected to the first node N1, and a second terminal connected to the third node N3. The first transistor T1 functions as a driving transistor and is configured to supply driving current to a light-emitting element by receiving a data signal Dm, according to the switching operation of the second transistor T2. The light-emitting element may be an OLED.

[0121] The second transistor T2 (switching transistor) includes a gate terminal connected to the first scan line SL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1 (or the first terminal of the first transistor T1). The second transistor T2 can be turned on in response to a first scan signal Sn transmitted through the first scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted to the data line DL to the first node N1.

[0122] The third transistor T3 (compensation transistor) includes a gate terminal connected to the first scan line SL, a first terminal connected to the second node N2 (or the gate terminal of the first transistor T1), and a second terminal connected to the third node N3 (or the second terminal of the first transistor T1). The third transistor T3 can be turned on in response to a first scan signal Sn transmitted through the first scan line SL, thereby connecting the first transistor T1 diode. The third transistor T3 may have a structure in which at least two transistors are connected in series.

[0123] The fourth transistor T4 (the first initialization transistor) includes a gate terminal connected to the second scan line SL-1, a first terminal connected to the initialization voltage line VL, and a second terminal connected to the second node N2. The fourth transistor T4 can be turned on in response to a second scan signal Sn-1 transmitted through the second scan line SL-1, and can transmit the initialization voltage Vint to the gate terminal of the first transistor T1, thereby initializing the gate voltage of the first transistor T1. The fourth transistor T4 may have a structure in which at least two transistors are connected in series.

[0124] The fifth transistor T5 (or the first emitter control transistor) includes a gate terminal connected to the emitter control line EL, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first node N1. The sixth transistor T6 (the second emitter control transistor) includes a gate terminal connected to the emitter control line EL, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light-emitting diode (OLED). The fifth transistor T5 and the sixth transistor T6 are simultaneously turned on in response to the emitter control signal En transmitted through the emitter control line EL, thus allowing current to flow in the OLED.

[0125] The seventh transistor T7 (the second initialization transistor) includes a gate terminal connected to the third scan line SL+1, a second terminal connected to the sixth transistor T6 and the first terminal of the pixel electrode of the OLED, and a second terminal connected to the initialization voltage line VL. The seventh transistor T7 can be turned on in response to the third scan signal Sn+1 transmitted through the third scan line SL+1, and can initialize the voltage of the pixel electrode of the OLED by transmitting the initialization voltage Vint to the pixel electrode. The seventh transistor T7 can be omitted.

[0126] The capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the drive voltage line PL.

[0127] An organic light-emitting diode (OLED) may include pixel electrodes and a common electrode facing the pixel electrodes, and the common electrode may receive a common voltage ELVSS. After receiving a drive current from a first transistor T1, the OLED emits light of a specific color, thus enabling image display. The common electrode may be disposed together with multiple sub-pixels, i.e., integrally disposed.

[0128] exist Figure 6BThe diagram shows that the fourth transistor T4 and the seventh transistor T7 are connected to the second scan line SL-1 and the third scan line SL+1, respectively, but the embodiment is not limited to this. In another embodiment, both the fourth transistor T4 and the seventh transistor T7 can be connected to the second scan line SL-1 and driven according to the second scan signal Sn-1.

[0129] The pixel circuits PC that drive the primary sub-pixel Pm and the auxiliary sub-pixel Pa can be the same or different from each other. For example, the pixel circuits PC that drive the primary sub-pixel Pm and the auxiliary sub-pixel Pa can be set to... Figure 6B The pixel circuit PC shown is illustrated. In another embodiment, the pixel circuit PC that drives the master sub-pixel Pm can be... Figure 6B The pixel circuit PC shown, and for the pixel circuit PC that drives the auxiliary sub-pixel Pa, can be used Figure 6A The pixel circuit PC shown.

[0130] exist Figure 6A and Figure 6B The diagram shows that the transistors in the pixel circuit PC are p-type transistors, but the embodiments are not limited to this. For example, the transistors in the pixel circuit PC can be n-type transistors, or some transistors can be p-type transistors while others can be n-type transistors. Various embodiments are possible.

[0131] Figure 7 This is a schematic layout diagram of the pixel arrangement structure in the main display area MDA according to an embodiment.

[0132] Reference Figure 7 Multiple main subpixels Pm can be arranged in the main display area MDA. In this specification, a subpixel refers to the emission region that serves as the smallest unit for realizing an image. When an OLED is used as a display element, the emission region of a subpixel can be defined by an opening in the emission layer or the pixel-defining layer. This will be described later.

[0133] Figure 7 Each region in the main display area MDA, divided by solid lines, is the pixel circuit area PCA, in which pixel circuits connected to the main sub-pixel Pm are arranged.

[0134] The main sub-pixel Pm can include a red sub-pixel Pr, a green sub-pixel Pg, and a blue sub-pixel Pb, and the red sub-pixel Pr, the green sub-pixel Pg, and the blue sub-pixel Pb can respectively realize red, green, and blue.

[0135] Red subpixels Pr and blue subpixels Pb are alternately arranged in the first sub-row 1SN of each row N, and green subpixels Pg are arranged at intervals in the adjacent second sub-row 2SN. This arrangement of pixels can be repeated up to the Nth row. In this case, the blue subpixels Pb and red subpixels Pr can be set to be greater than the green subpixels Pg. The red subpixels Pr and blue subpixels Pb arranged in the first sub-row 1SN and the green subpixels Pg arranged in the second sub-row 2SN can be arranged offset. Therefore, red subpixels Pr and blue subpixels Pb are alternately arranged in the first column 1M, green subpixels Pg are arranged at intervals in the adjacent second column 2M, blue subpixels Pb and red subpixels Pr are alternately arranged in the adjacent third column 3M, and green subpixels Pg are arranged at intervals in the adjacent fourth column 4M. This arrangement of pixels can be repeated up to the Mth column.

[0136] When this pixel arrangement structure is represented differently, in a virtual rectangle VS centered on the green sub-pixel Pg, the red sub-pixel Pr is placed at the first and third vertices facing each other, and the blue sub-pixel Pb is placed at the second and fourth vertices, which are the remaining vertices. In this case, the virtual rectangle VS can be modified in various ways, such as into a rectangle, rhombus, square, etc.

[0137] This pixel arrangement structure is called a pentile matrix structure or pentile structure, and by applying a rendering-driven method that uses shared adjacent pixels to represent colors, high resolution can be achieved with a small number of pixels.

[0138] exist Figure 7 The illustration shows the principal sub-pixels Pm arranged in a pentile structure, but the embodiment is not limited to this. For example, the principal sub-pixels Pm can be arranged in various shapes such as striped structures, mosaic arrangements, triangular arrangements, etc.

[0139] Figure 8A and Figure 8B This is a schematic layout diagram of the pixel arrangement structure in the component region CA according to an embodiment.

[0140] Reference Figure 8A Multiple auxiliary sub-pixels Pa can be arranged in the component region CA. Each auxiliary sub-pixel Pa can emit any one of red, green, blue, and white light.

[0141] The component region CA may have a sub-pixel region ADA and a transmission region TA. The sub-pixel region ADA may be a region in which auxiliary sub-pixels Pa are arranged. A pixel group PG, including at least one auxiliary sub-pixel Pa, may be arranged in the sub-pixel region ADA. For example, the sub-pixel region ADA and the transmission region TA may be arranged alternately in the x and y directions, and may be arranged in a grid shape. In this case, the component region CA may have multiple sub-pixel regions ADA and multiple transmission regions TA.

[0142] Figure 8A Each region in the sub-pixel region ADA, divided by solid lines, is the pixel circuit region PCA, in which pixel circuits connected to auxiliary sub-pixels Pa are arranged.

[0143] A pixel group PG can be defined as a set (or group) of subpixels in which multiple auxiliary subpixels Pa are grouped within a preset unit. For example, as Figure 8A As shown, a pixel group PG can include eight auxiliary sub-pixels Pa arranged in a pentile structure. That is, a pixel group PG can include two red sub-pixels Pr, four green sub-pixels Pg, and two blue sub-pixels Pb.

[0144] In the component region CA, the basic unit U, in which a certain number of pixel groups PG and a certain number of transmission regions TA are combined with each other, can be repeatedly arranged in the x and y directions. Figure 8A In this basic unit U, there can be a shape in which two pixel groups PG and two transmissive regions TA arranged around it are combined with each other in a square shape. In the basic unit U, regions of repeating shapes are divided, but this does not represent a break between elements.

[0145] like Figure 7 As shown, a corresponding unit U' with an area equal to that of the basic unit U can be set in the main display area MDA. In this case, the number of main sub-pixels Pm included in the corresponding unit U' can be greater than the number of auxiliary sub-pixels Pa included in the basic unit U. That is, there are 16 auxiliary sub-pixels Pa included in the basic unit U and 32 main sub-pixels Pm included in the corresponding unit U', and the number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm arranged per equal area can be set in a 1:2 ratio.

[0146] Similar to the arrangement of the primary sub-pixels Pm in the main display area MDA, the four auxiliary sub-pixels Pa can be arranged at the vertices of the virtual rectangle VS'. The resolution of the component area CA is half the resolution of the main display area MDA, and the pixel arrangement structure of the component area CA is called a 1 / 2 pentile structure. The number and arrangement of auxiliary sub-pixels Pa included in the pixel group PG can be modified according to the resolution of the component area CA.

[0147] Reference Figure 8B The pixel arrangement structure of the component region CA can be configured in a 1 / 4 pentile structure. In this embodiment, eight auxiliary sub-pixels Pa are arranged in a pentile structure within pixel group PG, and only one pixel group PG can be included in the basic unit U. The remaining area of ​​the basic unit U can be set as a transmission region TA. Therefore, the number of auxiliary sub-pixels Pa and the number of main sub-pixels Pm arranged per equal area can be set in a 1:4 ratio. In this case, a pixel group PG can be surrounded by the transmission region TA.

[0148] exist Figure 8A and Figure 8B The illustration shows an auxiliary sub-pixel Pa arranged in a pentile structure, but the embodiment is not limited to this. For example, the auxiliary sub-pixel Pa can be arranged in various shapes such as stripe structures, mosaic arrangements, triangular arrangements, etc.

[0149] In addition, Figure 8A and Figure 8B The diagram shows that the size of the auxiliary sub-pixel Pa is equal to the size of the main sub-pixel Pm, but the embodiment is not limited to this. The size of the auxiliary sub-pixel Pa can be larger than the size of the main sub-pixel Pm that emits the same color as the auxiliary sub-pixel Pa. For example, the size of the blue sub-pixel Pb of the auxiliary sub-pixel Pa can be larger than the size of the blue sub-pixel Pb of the main sub-pixel Pm. The size difference can be designed considering the difference in brightness and / or resolution between the component area CA and the main display area MDA.

[0150] Figure 9 This is a schematic cross-sectional view of a portion of the display panel 10 according to an embodiment, which is a schematic cross-sectional view of the main display area MDA and the component area CA.

[0151] Reference Figure 9The display panel 10 may include a main display area MDA and a component area CA. A main sub-pixel Pm is disposed in the main display area MDA, and an auxiliary sub-pixel Pa and a transmissive area TA are disposed in the component area CA. A main pixel circuit PC and a main organic light-emitting diode (OLED) serving as a display element connected to the main pixel circuit PC may be disposed in the main display area MDA. The main pixel circuit PC includes a main thin-film transistor (TFT) and a main capacitor Cst. An auxiliary pixel circuit PC' and an auxiliary organic light-emitting diode (OLED) 'serving as a display element connected to the auxiliary pixel circuit PC' may be disposed in the component area CA. The auxiliary pixel circuit PC' includes an auxiliary thin-film transistor (TFT) ' and an auxiliary capacitor Cst '.

[0152] In this embodiment, as an example, an OLED is used as a display element; however, in another embodiment, an inorganic light-emitting element or a quantum dot light-emitting element can be used as a display element.

[0153] The following will describe the structure including the component stack in the display panel 10. The display panel 10 can be configured by stacking a substrate 100, a buffer layer 111, a circuit layer PCL, and a display element layer EDL. For example... Figure 3 As shown, the encapsulation component ENCM and the optical functional layer OFL can be further stacked on the display element layer EDL.

[0154] The substrate 100 may include an insulating material, such as glass, quartz, or polymer resin. The substrate 100 may be a rigid substrate or a flexible substrate that is bendable, foldable, or rollable.

[0155] A buffer layer 111 may be located on the substrate 100 to reduce or block the penetration of foreign matter, moisture, or outside air from beneath the substrate 100 and to provide a flat surface on the substrate 100. The buffer layer 111 may comprise inorganic materials, organic materials, or organic-inorganic composites such as oxides or nitrides, and may have a single-layer or multi-layer structure of inorganic and organic materials. A barrier layer (not shown) that blocks the penetration of outside air may further be located between the substrate 100 and the buffer layer 111. In some embodiments, the buffer layer 111 may comprise silicon oxide (SiO2). x ), silicon nitride (SiN) x ) or silicon oxynitride (SiO) x N y The buffer layer 111 may have a structure in which the first buffer layer 111a and the second buffer layer 111b are stacked.

[0156] In the component region CA, the bottom metal layer BML may be located between the first buffer layer 111a and the second buffer layer 111b. In another embodiment, the bottom metal layer BML may be located between the substrate 100 and the first buffer layer 111a. The bottom metal layer BML may be located below the auxiliary pixel circuit PC', thereby preventing the characteristics of the auxiliary thin-film transistor TFT' from being degraded due to light emitted from the component, etc. Furthermore, the bottom metal layer BML can prevent light emitted from the component, etc., or light traveling toward the component, from diffracting through the narrow gap between the wiring connected to the auxiliary pixel circuit PC'. The bottom metal layer BML may not be located in the transmission region TA.

[0157] Additionally, the bottom metal layer (BML) can be connected to the wiring GCL arranged on different layers via contact holes. The bottom metal layer (BML) can receive a constant voltage or signal from the wiring GCL. For example, the bottom metal layer (BML) can receive a bias voltage.

[0158] The bottom metal layer (BML) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and / or doped silicon (doped Si). The bottom metal layer (BML) may include a single layer or multiple layers of the aforementioned materials.

[0159] The circuit layer PCL can be arranged on the buffer layer 111 and can include the main pixel circuit PC and the auxiliary pixel circuit PC', the first gate insulating layer 112, the second gate insulating layer 113, the interlayer insulating layer 115, and the planarization layer 117.

[0160] The main thin-film transistor (TFT) and the auxiliary thin-film transistor (TFT') can be disposed on the buffer layer 111. The main thin-film transistor (TFT) may include a first semiconductor layer A1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The auxiliary thin-film transistor (TFT') may include a second semiconductor layer A2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The main thin-film transistor (TFT) can be connected to the main organic light-emitting diode (OLED) to drive the main OLED. The auxiliary thin-film transistor (TFT') can be connected to the auxiliary organic light-emitting diode (OLED') to drive the auxiliary OLED.

[0161] The first semiconductor layer A1 and the second semiconductor layer A2 may be disposed on the buffer layer 111 and may comprise polycrystalline silicon. In another embodiment, the first semiconductor layer A1 and the second semiconductor layer A2 may comprise amorphous silicon. In another embodiment, both the first semiconductor layer A1 and the second semiconductor layer A2 may comprise an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), Cr, Ti, and zinc (Zn). Both the first semiconductor layer A1 and the second semiconductor layer A2 may comprise a drain region and a source region doped with impurities.

[0162] The second semiconductor layer A2 can be stacked with the bottom metal layer BML, and the second buffer layer 111b is located between the second semiconductor layer A2 and the bottom metal layer BML. In an embodiment, the width of the second semiconductor layer A2 can be smaller than the width of the bottom metal layer BML, so that when projected in a direction perpendicular to the substrate 100, the second semiconductor layer A2 can be completely stacked with the bottom metal layer BML.

[0163] The first gate insulating layer 112 may be configured to cover the first semiconductor layer A1 and the second semiconductor layer A2. The first gate insulating layer 112 may include an inorganic insulating material, such as SiO2. x SiN x The materials used may be silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The first gate insulating layer 112 may include a single layer or multiple layers containing the aforementioned inorganic insulating materials.

[0164] The first gate electrode G1 and the second gate electrode G2 are disposed on the first gate insulating layer 112, and are stacked with the first semiconductor layer A1 and the second semiconductor layer A2, respectively. Both the first gate electrode G1 and the second gate electrode G2 may comprise Mo, Al, Cu, Ti, etc., and may comprise a single layer or multiple layers. As an example, both the first gate electrode G1 and the second gate electrode G2 may comprise a single Mo layer.

[0165] The second gate insulating layer 113 may be configured to cover the first gate electrode G1 and the second gate electrode G2. The second gate insulating layer 113 may include an inorganic insulating material, such as SiO2. x SiN x The inorganic insulating layer 113 may contain a single layer or multiple layers of the aforementioned inorganic insulating material, such as SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO.

[0166] The first upper electrode CE2 of the main capacitor Cst and the second upper electrode CE2' of the auxiliary capacitor Cst' can be arranged on the second gate insulating layer 113.

[0167] In the main display area MDA, the first upper electrode CE2 can be stacked with the first gate electrode G1 below it. The first gate electrode G1 and the first upper electrode CE2, which are stacked together and with the second gate insulating layer 113 located therebetween, can form the main capacitor Cst. The first gate electrode G1 can be the first lower electrode CE1 of the main capacitor Cst.

[0168] In the component region CA, the second upper electrode CE2' can be stacked with the lower second gate electrode G2. The second gate electrode G2 and the second upper electrode CE2', which are stacked together and with the second gate insulating layer 113 located therebetween, can form an auxiliary capacitor Cst'. The second gate electrode G2 can be the second lower electrode CE1' of the auxiliary capacitor Cst'.

[0169] Both the first upper electrode CE2 and the second upper electrode CE2' may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Ca, Mo, Ti, W and / or Cu, and may include a single layer or multiple layers of the aforementioned materials.

[0170] The interlayer insulating layer 115 can be formed to cover the first upper electrode CE2 and the second upper electrode CE2'. The interlayer insulating layer 115 may include SiO2. x SiN x The materials used are SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. The interlayer insulation layer 115 may include a single layer or multiple layers containing the aforementioned inorganic insulating materials.

[0171] When the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IIL, the inorganic insulating layer IIL may include a first aperture H1 corresponding to the transmission region TA. The first aperture H1 may expose a portion of the upper surface of the buffer layer 111 or the substrate 100. The first aperture H1 may be stacked with the openings of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115, which are formed to correspond to the transmission region TA. The openings may be formed individually by separate processes or simultaneously by the same process. When the openings are formed by separate processes, the inner surface of the first aperture H1 may not be smooth and may have stepped surfaces.

[0172] Alternatively, the inorganic insulating layer IIL may include a groove instead of the first hole H1 that exposes the buffer layer 111. Alternatively, the inorganic insulating layer IIL may not include the first hole H1 or the groove corresponding to the transmission region TA. Because the inorganic insulating layer IIL typically comprises an inorganic insulating material with excellent light transmittance, it has sufficient transmittance without the hole or groove corresponding to the transmission region TA, thereby allowing the component 40 to transmit / receive a sufficient amount of light.

[0173] The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can be disposed on the interlayer insulating layer 115. The first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can all comprise conductive materials containing Mo, Al, Cu, Ti, etc., and can comprise multiple layers or a single layer containing the aforementioned materials. As an example, the first source electrode S1, the second source electrode S2, the first drain electrode D1, and the second drain electrode D2 can all have a Ti / Al / Ti multilayer structure.

[0174] The planarization layer 117 may be arranged to cover the first source electrode S1 and the second source electrode S2, as well as the first drain electrode D1 and the second drain electrode D2. The planarization layer 117 may include a flat upper surface, such that the first pixel electrode 121 and the second pixel electrode 121' disposed thereon are formed flat.

[0175] Planarization layer 117 may comprise organic or inorganic materials and may have a single-layer or multi-layer structure. Planarization layer 117 may comprise general-purpose polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives with phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, or vinyl alcohol polymers. x SiN x The materials used are SiON, Al2O3, TiO2, Ta2O5, HfO2, or ZnO. When the planarization layer 117 is formed, chemical mechanical polishing can be performed on the upper surface of the layer to provide a flat upper surface after the layer is formed.

[0176] The main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') are arranged on the planarization layer 117. The first pixel electrode 121 of the main organic light-emitting diode (OLED) and the second pixel electrode 121' of the auxiliary organic light-emitting diode (OLED') can be connected to the main pixel circuit PC and the auxiliary pixel circuit PC', respectively.

[0177] The planarization layer 117 may include a second aperture H2 corresponding to the transmission region TA. The second aperture H2 may be stacked with the first aperture H1. Figure 9 The diagram shows that the second hole H2 is formed larger than the first hole H1. In another embodiment, the planarization layer 117 is configured to cover the edge of the first hole H1 covering the inorganic insulating layer 111, so the area of ​​the second hole H2 can be formed smaller than the area of ​​the first hole H1.

[0178] The planarization layer 117 may include a via that exposes either the first source electrode S1 or the first drain electrode D1 of the main thin-film transistor TFT, and the first pixel electrode 121 may contact the first source electrode S1 or the first drain electrode D1 through the via to be electrically connected to the main thin-film transistor TFT. Additionally, the planarization layer 117 may include a via that exposes either the second source electrode S2 or the second drain electrode D2 of the auxiliary thin-film transistor TFT', and the second pixel electrode 121' may contact the second source electrode S2 or the second drain electrode D2 through the via to be electrically connected to the auxiliary thin-film transistor TFT'.

[0179] Both the first pixel electrode 121 and the second pixel electrode 121' may include conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). Both the first pixel electrode 121 and the second pixel electrode 121' may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or mixtures thereof. For example, both the first pixel electrode 121 and the second pixel electrode 121' may have a structure comprising layers of ITO, IZO, ZnO, or In2O3 located on / below the aforementioned reflective layer. In this case, both the first pixel electrode 121 and the second pixel electrode 121' may have a structure in which ITO / Ag / ITO are stacked.

[0180] A first pixel defining layer 119a may be disposed on planarization layer 117 in main display area MDA, and a second pixel defining layer 119b may be disposed on planarization layer 117 in component area CA. The first pixel defining layer 119a may cover the edge of first pixel electrode 121 and includes a first opening OP1 that exposes a portion of the first pixel electrode 121. The second pixel defining layer 119b may cover the edge of second pixel electrode 121' and includes a second opening OP2 that exposes a portion of the second pixel electrode 121'. The size and shape of the emission regions of the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED) ' (i.e., the size and shape of the main sub-pixel Pm and the auxiliary sub-pixel Pa) may be defined by the first opening OP1 and the second opening OP2.

[0181] The first pixel defining layer 119a and the second pixel defining layer 119b can increase the distance between the edges of the first pixel electrode 121 and the second pixel electrode 121' and the counter electrode 123 located above the first pixel electrode 121 and the second pixel electrode 121', thereby preventing arcing at the edges of the first pixel electrode 121 and the second pixel electrode 121'. The first pixel defining layer 119a and the second pixel defining layer 119b may include organic insulating materials, such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin, and can be formed by spin coating or the like. In one embodiment, the first pixel defining layer 119a may include an opaque insulating material, and the second pixel defining layer 119b may include a transparent insulating material. In another embodiment, both the first pixel defining layer 119a and the second pixel defining layer 119b may include opaque insulating materials. Spacers including organic insulating materials may be further disposed on each of the first pixel defining layer 119a and the second pixel defining layer 119b.

[0182] The second pixel defining layer 119b may include a third aperture H3 located in the transmissive region TA. The third aperture H3 may be stacked with the first aperture H1 and the second aperture H2. The light transmittance in the transmissive region TA can be increased by the first aperture H1 through the third aperture H3. Figure 9 The diagram shows a buffer layer 111 continuously arranged to correspond to the transmission region TA, but the buffer layer 111 may include holes located in the transmission region TA. A portion of the counter electrode 123, which will be described later, may be disposed on the inner surfaces of the first hole H1 to the third hole H3.

[0183] A first emitting layer 122b and a second emitting layer 122b', respectively corresponding to the first pixel electrode 121 and the second pixel electrode 121', are disposed inside the first opening OP1 of the first pixel defining layer 119a and the second opening OP2 of the second pixel defining layer 119b. Both the first emitting layer 122b and the second emitting layer 122b' may comprise polymer materials or low molecular weight materials, and emit red light, green light, blue light, or white light.

[0184] The organic functional layer 122e may be disposed on and / or below the first emission layer 122b and the second emission layer 122b'. The organic functional layer 122e may include the first functional layer 122a and / or the second functional layer 122c. The first functional layer 122a or the second functional layer 122c may be omitted.

[0185] The first functional layer 122a may be located below the first emission layer 122b and the second emission layer 122b'. The first functional layer 122a may comprise a single layer or multiple layers of organic material. The first functional layer 122a may comprise a hole transport layer (HTL) having a single-layer structure. Alternatively, the first functional layer 122a may comprise a hole injection layer (HIL) and an HTL. The first functional layer 122a may be formed as a single unit to correspond to the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') respectively included in the main display area MDA and the component area CA.

[0186] The second functional layer 122c may be disposed on the first emission layer 122b and the second emission layer 122b'. The second functional layer 122c may comprise a single layer or multiple layers of organic material. The second functional layer 122c may comprise an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 122c may be formed as a single unit to correspond to the main organic light-emitting diode (OLED) and the auxiliary organic light-emitting diode (OLED') respectively included in the main display area MDA and the component area CA.

[0187] Counter electrode 123 is disposed on the second functional layer 122c. Counter electrode 123 may include a conductive material having a low work function. For example, counter electrode 123 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, lithium (Li), Ca, or alloys thereof. Alternatively, counter electrode 123 may also include a layer such as ITO, IZO, ZnO, or In2O3 located on the (semi-)transparent layer. Counter electrode 123 may be formed as a single unit to correspond to the main organic light-emitting diode (OLED) and auxiliary organic light-emitting diode (OLED') respectively included in the main display region MDA and component region CA.

[0188] The layer formed in the main display area MDA from the first pixel electrode 121 to the counter electrode 123 can form a main organic light-emitting diode (OLED). The layer formed in the component area CA from the second pixel electrode 121' to the counter electrode 123 can form an auxiliary organic light-emitting diode (OLED').

[0189] An upper layer 150, comprising organic material, can be formed on the counter electrode 123. The upper layer 150 can protect the counter electrode 123 and improve light extraction efficiency. The upper layer 150 may comprise an organic material having a refractive index higher than that of the counter electrode 123. Alternatively, the upper layer 150 can be configured by stacking layers with different refractive indices. For example, the upper layer 150 can be configured by stacking a high-refractive-index layer / a low-refractive-index layer / a high-refractive-index layer. In this case, the refractive index of the high-refractive-index layer may be 1.7 or greater, and the refractive index of the low-refractive-index layer may be 1.3 or less.

[0190] The upper layer 150 may additionally include lithium fluoride (LiF). Alternatively, the upper layer 150 may additionally include materials such as SiO2. x SiN x Inorganic insulating materials such as...

[0191] The first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may include a through-hole TAH corresponding to the transmission region TA. That is, the first functional layer 122a, the second functional layer 122c, the counter electrode 123, and the upper layer 150 may all have an opening corresponding to the transmission region TA. The openings may have substantially the same area. For example, the area of ​​the opening of the counter electrode 123 may be substantially equal to the area of ​​the through-hole TAH.

[0192] It is understandable that the through-hole TAH corresponding to the transmission region TA indicates that the through-hole TAH is superimposed on the transmission region TA. In this case, the area of ​​the through-hole TAH can be smaller than the area of ​​the first hole H1 formed in the inorganic insulating layer IIL. Therefore, in Figure 9 The diagram shows that the width Wt of the through hole TAH is smaller than the width of the first hole H1. Here, the area of ​​the through hole TAH can be defined as the area of ​​the opening with the narrowest area among the openings constituting the through hole TAH. The area of ​​the first hole H1 can also be defined as the area of ​​the opening with the narrowest area among the openings constituting the first hole H1.

[0193] By using a through-hole TAH, a portion of the counter electrode 123 may not be located within the transmission region TA, thus significantly increasing the transmittance within the transmission region TA. The counter electrode 123 with the through-hole TAH can be formed using various methods. In one embodiment, after the material forming the counter electrode 123 is formed on the front surface of the substrate 100, a portion corresponding to the transmission region TA can be removed by laser lift-off, thereby forming the counter electrode 123 including the through-hole TAH. In another embodiment, the counter electrode 123 including the through-hole TAH can be formed using a metal self-patterning (MSP) method. In yet another embodiment, the counter electrode 123 including the through-hole TAH can also be formed by depositing the counter electrode 123 using a fine metal mask (FMM).

[0194] The bottom metal layer BML in the component region CA can be configured to correspond to the entire component region CA. In this case, the bottom metal layer BML may include a bottom hole BMLH superimposed on the transmission region TA. In some embodiments, the shape and size of the transmission region TA can be defined by the shape and size of the bottom hole BMLH.

[0195] Figure 10 This is a schematic cross-sectional view of a portion of the display panel 10a according to an embodiment. Figure 10 It can be Figure 2 A schematic cross-sectional view of the main display area MDA, the second component area CA2, and the third component area CA3. Figure 11 yes Figure 10 A schematic plan view of the display layer DISL of the main display area MDA. Figure 12 yes Figure 10 A schematic plan view of the touchscreen layer TSL of the main display area MDA.

[0196] Figure 13A and Figure 13B yes Figure 10 A schematic plan view of the optical functional layer OFL of the main display area MDA. Figure 14 yes Figure 10 A schematic plan view of the display layer DISL of the second component area CA2. Figure 15 yes Figure 10 A schematic plan view of the optical functional layer OFL in the second component region CA2.

[0197] The second component region CA2 can be a region where the transmittance of light in a first wavelength band incident on the second component is high, and the third component region CA3 can be a region where the transmittance of light in a second wavelength band incident on the third component is high. For example, an illuminance sensor can be arranged in the second component region CA2, and the second component region CA2 can be a region where the transmittance of visible light (e.g., light with a wavelength of 550 nm) is high. A proximity sensor can be arranged in the third component region CA3, and the third component region CA3 can be a region where the transmittance of infrared light (e.g., light with a wavelength of 940 nm) is high. Figure 10 The sub-pixel region ADA, excluding the transmission region TA, is shown in the second component region CA2 and the third component region CA3.

[0198] Reference Figure 10 The buffer layer 111, the inorganic insulating layer 111, and the planarization layer 117 can be sequentially stacked on the substrate 100. The buffer layer 111, the inorganic insulating layer 111, and the planarization layer 117 can be common layers arranged together in the sub-pixel regions ADA of the main display area MDA and the second component area CA2 and the third component area CA3. Figure 9 As shown, the main pixel circuit PC and the auxiliary pixel circuit PC' can be located between the buffer layer 111 and the planarization layer 117. The display elements of the main sub-pixel Pm and the auxiliary sub-pixel Pa can be arranged on the planarization layer 117. Both the main sub-pixel Pm and the auxiliary sub-pixel Pa can include a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0199] First, the main display area (MDA) will be described. A first pixel electrode 121 of the main sub-pixel Pm can be disposed in the main display area (MDA). The first pixel electrode 121 may include a first pixel electrode 121a for a red sub-pixel, a first pixel electrode 121b for a green sub-pixel, and a first pixel electrode 121c for a blue sub-pixel. A first pixel defining layer 119a may cover the edges of the first pixel electrodes 121a, 121b, and 121c, and may be located between the first pixel electrodes 121a, 121b, and 121c. The first pixel defining layer 119a may include a first opening OP1 that exposes a portion of the first pixel electrodes 121a, 121b, and 121c. Figure 11 As shown, the first opening OP1 may correspond to the emission region EA in which the first emission layer 122b is disposed. The first pixel defining layer 119a may be arranged to correspond to the non-emission region NEA between the emission regions EA. The first pixel defining layer 119a may include an opaque insulating material.

[0200] The first spacer SPC1 may be disposed on the first pixel defining layer 119a. The first spacer SPC1 may be disposed at certain intervals in the non-emitting region NEA. Each of the first spacers SPC1 may comprise a material different from the material of the first pixel defining layer 119a. For example, each of the first spacers SPC1 may comprise a transparent insulating material.

[0201] The emission region EA may include a first emission region EA1 that emits red light, a second emission region EA2 that emits green light, and a third emission region EA3 that emits blue light. The first emission layer 122b that emits red light may be arranged in the first emission region EA1, the first emission layer 122b that emits green light may be arranged in the second emission region EA2, and the first emission layer 122b that emits blue light may be arranged in the third emission region EA3.

[0202] Counter electrode 123 can be disposed on the first emitter layer 122b. Counter electrode 123 can cover the first pixel defining layer 119a and the first spacer SPC1. Although Figure 10 Not shown in the image, but as... Figure 9 As shown, the first functional layer 122a and / or the second functional layer 122c may be further arranged on and / or below the first emission layer 122b.

[0203] The upper layer 150 can be disposed on the counter electrode 123. The thin-film encapsulation layer TFEL can be disposed on the upper layer 150, and the thin-film encapsulation layer TFEL can include a first inorganic encapsulation layer 161, a second inorganic encapsulation layer 163, and an organic encapsulation layer 162 located therebetween.

[0204] The touchscreen layer (TSL) can be placed on the thin-film encapsulation layer (TFEL). For example... Figure 12 As shown, the touch electrode TPE can be disposed in the touch screen layer TSL. The touch electrode TPE may include a first touch electrode 171 and a second touch electrode 172. The first touch electrode 171 can be connected to each other through a first connection electrode 171b disposed on the same layer. The second touch electrode 172 can be connected to each other through a second connection electrode 172b disposed on a different layer and a contact hole CNT of the insulating layer 174.

[0205] The first touch electrode 171 may have a mesh structure (or grid structure) including multiple holes 171H. Each hole 171H may be arranged to overlap with the emission region EA of the main sub-pixel Pm. Similarly, the second touch electrode 172 may have a mesh structure (or grid structure) including multiple holes 172H. Each hole 172H may be arranged to overlap with the emission region EA of the main sub-pixel Pm. The holes 171H and 172H may have different areas. The width of each mesh line may be several micrometers.

[0206] The optical functional layer (OFL) can be disposed on the touchscreen layer (TSL). The OFL may include a color filter 182, a black matrix 183, and an outer coating 184. For example... Figure 13A As shown, the black matrix 183 may surround the emission region EA and may be positioned to correspond to the first pixel defining layer 119a. That is, the black matrix 183 may include an opening 183OP corresponding to each emission region EA. The size of the opening 183OP may be larger than the size of each emission region EA. The black matrix 183 may cover the first touch electrode 171 and the second touch electrode 172.

[0207] Color filter 182 may include a first color filter 182a that selectively transmits only red light, a second color filter 182b that selectively transmits only green light, and a third color filter 182c that selectively transmits only blue light. The first color filter 182a may be arranged to correspond to a first emission region EA1, the second color filter 182b may be arranged to correspond to a second emission region EA2, and the third color filter 182c may be arranged to correspond to a third emission region EA3. The first color filter 182a, the second color filter 182b, and the third color filter 182c may be arranged adjacent to each other. In an embodiment, the edges of the first color filter 182a, the second color filter 182b, and the third color filter 182c may overlap with the edges of the first color filter 182a, the second color filter 182b, and the third color filter 182c respectively adjacent to them. The edges of each of the first color filter 182a, the second color filter 182b, and the third color filter 182c can be partially superimposed on the black matrix 183. Each of the first color filter 182a, the second color filter 182b, and the third color filter 182c can have an independent pattern structure. Each of the first color filter 182a, the second color filter 182b, and the third color filter 182c can be partially superimposed on the first pixel defining layer 119a.

[0208] Next, the second component region CA2 will be described. The second pixel electrode 121' of the auxiliary sub-pixel Pa can be disposed in the second component region CA2. The second pixel electrode 121' may include the second pixel electrode 121a' of the red sub-pixel, the second pixel electrode 121b' of the green sub-pixel, and the second pixel electrode 121c' of the blue sub-pixel. The second pixel defining layer 119b may cover the edges of the second pixel electrodes 121a', 121b', and 121c', and may be located between the second pixel electrodes 121a', 121b', and 121c'. The second pixel defining layer 119b may include a second opening OP2 that exposes a portion of the second pixel electrodes 121a', 121b', and 121c'. Figure 14 As shown, the second opening OP2 may correspond to the emission region EA in which the second emission layer 122b' is disposed. The second pixel defining layer 119b may be arranged to correspond to the non-emission region NEA between the emission regions EA. The second pixel defining layer 119b may include a material different from that of the first pixel defining layer 119a. In an embodiment, the second pixel defining layer 119b may include the same material as the first spacer SPC1.

[0209] The second spacers SPC2 can be arranged at certain intervals in the non-emitting region NEA. Each second spacer SPC2 can be arranged on a corresponding insulating pattern BP. The insulating patterns BP can be arranged at certain intervals in the non-emitting region NEA. The insulating patterns BP can be arranged on the planarization layer 117, and the second spacers SPC2 can be the portion of the second pixel defining layer 119b that covers the upper part of the insulating pattern BP. That is, each second spacer SPC2 can cover each insulating pattern BP. The insulating pattern BP can include the same material as the first pixel defining layer 119a.

[0210] The emission region EA may include a first emission region EA1 that emits red light, a second emission region EA2 that emits green light, and a third emission region EA3 that emits blue light. The second emission layer 122b' that emits red light may be arranged in the first emission region EA1, the second emission layer 122b' that emits green light may be arranged in the second emission region EA2, and the second emission layer 122b' that emits blue light may be arranged in the third emission region EA3.

[0211] Counter electrode 123 can be disposed on the second emitter layer 122b'. Counter electrode 123 can cover the second pixel defining layer 119b and the second spacer SPC2. Although Figure 10 Not shown in the image, but as... Figure 9 As shown, the first functional layer 122a and / or the second functional layer 122c may be further arranged on and / or below the second emission layer 122b'.

[0212] The upper layer 150 can be disposed on the counter electrode 123. The thin-film encapsulation layer TFEL can be disposed on the upper layer 150. For example... Figure 12 As shown, the touchscreen layer TSL can be disposed on the thin-film encapsulation layer TFEL. The optical functional layer OFL can be disposed on the touchscreen layer TSL.

[0213] The optical functional layer OFL may include a color filter 182 and an outer coating 184. For example... Figure 10 As shown, black matrix 183 may not be arranged in the second component region CA2. Figure 15As shown, the first color filter 182a can be arranged to correspond to the first emission region EA1, the second color filter 182b can be arranged to correspond to the second emission region EA2, and the third color filter 182c can be arranged to correspond to the third emission region EA3. The first color filter 182a, the second color filter 182b, and the third color filter 182c can be arranged adjacent to each other. In an embodiment, the edges of the first color filter 182a, the second color filter 182b, and the third color filter 182c can be superimposed on the edges of adjacent first color filters 182a, second color filters 182b, and third color filters 182c, respectively. The first color filter 182a, the second color filter 182b, and the third color filter 182c can each have an independent pattern structure. The first color filter 182a, the second color filter 182b, and the third color filter 182c can each be partially superimposed on the second pixel defining layer 119b.

[0214] Next, the third component region CA3 will be described. The second pixel electrode 121' of the auxiliary sub-pixel Pa can be disposed in the third component region CA3. The second pixel electrode 121' may include the second pixel electrode 121a' of the red sub-pixel, the second pixel electrode 121b' of the green sub-pixel, and the second pixel electrode 121c' of the blue sub-pixel. The third pixel defining layer 119c may cover the edges of the second pixel electrodes 121a', 121b', and 121c', and may be located between the second pixel electrodes 121a', 121b', and 121c'. The third pixel defining layer 119c may include a second opening OP2 that exposes a portion of the second pixel electrodes 121a', 121b', and 121c'. A third spacer SPC3 may be disposed on the third pixel defining layer 119c. The third pixel defining layer 119c may include the same material as the first pixel defining layer 119a. The third spacer SPC3 may include the same material as the first spacer SPC1.

[0215] The arrangement of the third pixel limiting layer 119c and the third spacer SPC3 in the third component region CA3 can be related to... Figure 11 The arrangement of the first pixel defining layer 119a and the first spacer SPC1 in the main display area MDA shown is the same. The optical functional layer OFL arranged in the third component area CA3 is the same as... Figure 15 The optical functional layer OFL shown is the same as that arranged in the second component region CA2.

[0216] Figures 16A to 16D It is based on Figure 10 The manufacturing process of the display panel 10a shown is illustrated in the cross-sectional view of the display panel 10a. In the following text, references to the diagram will be omitted. Figures 10 to 15 The description is the same as the detailed description.

[0217] Reference Figure 16A The buffer layer 111, the inorganic insulating layer 111, and the planarization layer 117 can be sequentially stacked on the substrate 100. For example... Figure 9 As shown, the main pixel circuit PC and the auxiliary pixel circuit PC' can be located between the buffer layer 111 and the planarization layer 117.

[0218] A conductive material layer is formed on the planarization layer 117 and then patterned, so that the first pixel electrodes 121a, 121b and 121c of the main sub-pixel Pm can be formed in the main display area MDA, and the second pixel electrodes 121a', 121b' and 121c' of the auxiliary sub-pixel can be formed in each of the second component area CA2 and the third component area CA3.

[0219] A first insulating layer can be formed in the main display area MDA, the second component area CA2, and the third component area CA3, and can be exposed using a mask. The first insulating layer may include a negative photosensitive material. The exposed first insulating layer can be developed to form a first pixel defining layer 119a in the main display area MDA, an insulating pattern BP in the second component area CA2, and a third pixel defining layer 119c in the third component area CA3.

[0220] The first insulating layer may include an opaque material. The first insulating layer may also include a coloring material. For example, the first pixel defining layer 119a, the insulating pattern BP, and the third pixel defining layer 119c formed from the first insulating layer may include coloring pigments, such as white, black, or other coloring pigments. In an embodiment, the first insulating layer may include a black pigment. For example, the first pixel defining layer 119a, the insulating pattern BP, and the third pixel defining layer 119c may include a polyimide (PI) adhesive and a pigment mixed therewith with red, green, and blue pigments. Alternatively, the first pixel defining layer 119a, the insulating pattern BP, and the third pixel defining layer 119c may include a cardo-based adhesive resin and a mixture of lactam-based black and blue pigments. Alternatively, the first pixel defining layer 119a, the insulating pattern BP, and the third pixel defining layer 119c may include carbon black.

[0221] The first pixel defining layer 119a may include a first opening OP1 that exposes a portion of the first pixel electrodes 121a, 121b, and 121c, and may directly cover the first pixel electrodes 121a, 121b, and 121c by overlapping with the edges of the first pixel electrodes 121a, 121b, and 121c. The third pixel defining layer 119c may include a second opening OP2 that exposes a portion of the second pixel electrodes 121a', 121b', and 121c', and may directly cover the second pixel electrodes 121a', 121b', and 121c' in the third component region CA3. An insulating pattern BP may be located between the second pixel electrodes 121a', 121b', and 121c' in the second component region CA2.

[0222] Reference Figure 16B A second insulating layer can be formed on the first pixel defining layer 119a, the insulating pattern BP, and the third pixel defining layer 119c, and the second insulating layer can be exposed using a mask. The second insulating layer may include a positive photosensitive material. The exposed second insulating layer can be developed, thereby forming a first spacer SPC1 in the main display area MDA, a second pixel defining layer 119b and a second spacer SPC2 in the second component area CA2, and a third spacer SPC3 in the third component area CA3.

[0223] The first spacer SPC1 may be located on the first pixel defining layer 119a, and the third spacer SPC3 may be located on the third pixel defining layer 119c.

[0224] The second pixel defining layer 119b may include a second opening OP2 that exposes a portion of the second pixel electrodes 121a', 121b', and 121c', and may directly cover the second pixel electrodes 121a', 121b', and 121c' by overlapping with the edges of the second pixel electrodes 121a', 121b', and 121c' in the second component region CA2. The second pixel defining layer 119b may cover the insulating pattern BP and has steps with partially different heights through the insulating pattern BP. The relatively higher portion of the second pixel defining layer 119b (i.e., the portion disposed on the insulating pattern BP) may serve as a second spacer SPC2.

[0225] By using the mask used in the process of forming the first emission layer 122b and the second emission layer 122b', which will be described later, the first spacer SPC1, the second spacer SPC2 and the third spacer SPC3 can prevent damage to the layers arranged under the mask (e.g., the first pixel electrode 121 and the second pixel electrode 121', etc.).

[0226] The second insulating layer may include a material different from that of the first insulating layer. The second insulating layer may include a transparent insulating material. For example, the second pixel defining layer 119b, the first spacer SPC1, the second spacer SPC2, and the third spacer SPC3 formed by the second insulating layer may include a polyimide resin, such as a photosensitive polyimide resin.

[0227] Next, as Figure 16C As shown, a first emission layer 122b and a second emission layer 122b' can be formed in the first opening OP1 of the first pixel limiting layer 119a and the second opening OP2 of the second pixel limiting layer 119b and the third pixel limiting layer 119c, and a counter electrode 123 can be formed on the first emission layer 122b and the second emission layer 122b'.

[0228] like Figure 9 As shown, a first functional layer 122a and / or a second functional layer 122c may be further arranged on and / or below the first emitting layer 122b and the second emitting layer 122b'. The first emitting layer 122b and the second emitting layer 122b' may be formed to be superimposed only on the first pixel electrodes 121a, 121b, and 121c and the second pixel electrodes 121a', 121b', and 121c', respectively. The first functional layer 122a, the second functional layer 122c, and the counter electrode 123 may be formed to completely cover the substrate 100. The first functional layer 122a, the second functional layer 122c, and the counter electrode 123 may not be disposed in the transmission regions TA of the second component region CA2 and the third component region CA3.

[0229] An upper layer 150 can be formed on the counter electrode 123, and a thin film encapsulation layer TFEL and a touch screen layer TSL can be sequentially formed on the upper layer 150.

[0230] The thin-film encapsulation layer TFEL may include a first inorganic encapsulation layer 161, a second inorganic encapsulation layer 163, and an organic encapsulation layer 162 located therebetween. The first inorganic encapsulation layer 161 and the second inorganic encapsulation layer 163 may include one or more inorganic insulating materials, such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, etc. The organic encapsulation layer 162 may include polymeric materials. Examples of polymeric materials may include acrylic resin, epoxy resin, polyimide, polyethylene, etc.

[0231] like Figure 10 As shown, the touch screen layer TSL may include a first touch electrode 171 and a second touch electrode 172, a first connection electrode 171b and a second connection electrode 172b, and an insulating layer 174.

[0232] A black matrix 183 can be formed on the touchscreen layer TSL. The black matrix 183 can be formed in the main display area MDA and can be arranged to overlap with the first pixel definition layer 119a.

[0233] Reference Figure 16D Color filters 182 and outer coating 184 can be formed on the touch screen layer TSL. The first color filter 182a, the second color filter 182b and the third color filter 182c can be arranged to be superimposed on the first opening OP1 of the first pixel limiting layer 119a and the second opening OP2 of the second pixel limiting layer 119b and the third pixel limiting layer 119c, respectively.

[0234] Figure 17A This is a schematic cross-sectional view of a portion of the display panel 10b according to an embodiment. Figure 17B yes Figure 17A A schematic plan view of the optical functional layer OFL of the second component region CA2 and the third component region CA3.

[0235] Figure 17A The display panel 10b shown can have the same as Figure 10 The second component region CA2 and the third component region CA3 of the display panel 10a shown are different from the optical functional layers OFL of the second component region CA2 and the third component region CA3, and other components are... Figure 10 The components of the display panel 10a shown are the same.

[0236] Reference Figure 17A and Figure 17B The optical functional layer OFL of the second component region CA2 and the third component region CA3 may include a color filter 182. The color filter 182 may include a first color filter 182a, a second color filter 182b', and a third color filter 182c. The first color filter 182a and the third color filter 182c may have independent pattern structures, and the second color filter 182b' may have a grid structure. The first color filter 182a, the second color filter 182b', and the third color filter 182c may all be partially superimposed on the second pixel defining layer 119b and the third pixel defining layer 119c. In this case, the area where the second color filter 182b' is superimposed on the second pixel defining layer 119b and the third pixel defining layer 119c may be larger than the area where each of the first color filter 182a and the third color filter 182c is superimposed on the second pixel defining layer 119b and the third pixel defining layer 119c.

[0237] Figure 18A and Figure 18B This is a cross-sectional view of the second spacer SPC2 according to an embodiment.

[0238] In an embodiment, such as Figure 18A As shown, the second pixel defining layer 119b can cover the insulating pattern BP and can be formed on the insulating pattern BP. The second pixel defining layer 119b can have steps with different heights through the insulating pattern BP, and a portion of the second pixel defining layer 119b located on the insulating pattern BP can be used as a second spacer SPC2.

[0239] In another embodiment, such as Figure 18B As shown, the second pixel defining layer 119b on the insulating pattern BP can be patterned to form a second spacer SPC2 on the insulating pattern BP. Therefore, the second spacer SPC2 can be separated from the second pixel defining layer 119b and formed as an independent pattern. The second pixel defining layer 119b may also include an opening surrounding the insulating pattern BP, so a slit SLIT surrounding the insulating pattern BP can be formed between the second pixel defining layer 119b and the insulating pattern BP. The upper surface of the planarization layer 117 can be exposed through the slit SLIT. Figure 18B In the embodiment shown, the step formed by the insulating pattern BP and the second spacer SPC2 is larger than that in Figure 18A In the embodiment shown, the step is formed by the insulating pattern BP and the second pixel defining layer 119b, therefore, Figure 18B The embodiments shown may be more advantageous for subsequent processes.

[0240] Figure 19A and Figure 19B These are a plan view and a cross-sectional view of the arrangement of the pixel-limiting layer located at the boundary between the main display area MDA and the second component area CA2. Figure 19B It is along Figure 19A The sectional view taken from line II-II'.

[0241] Refer to together Figure 19A and Figure 19B As shown in region A, the edge of the second pixel defining layer 119b arranged in the second component region CA2 can overlap with and contact the edge of the first pixel defining layer 119a arranged in the main display region MDA.

[0242] Figure 20 This is a schematic plan view of a portion of the display panel 10c according to an embodiment. Figure 21 yes Figure 20 A schematic plan view of the display layer DISL of the second component area CA2.

[0243] Figure 20 The display panel 10c shown can have the same as Figure 10The second component region CA2 of the display panel 10a shown is different from the display layer DISL of the second component region CA2, and other components are... Figure 10 The components of the display panel 10a shown are the same.

[0244] A first pixel defining layer 119a covering the edges of the first pixel electrodes 121a, 121b and 121c can be disposed in the main display area MDA, and a first spacer SPC1 can be disposed on the first pixel defining layer 119a.

[0245] The third pixel defining layer 119c covering the edges of the second pixel electrodes 121a', 121b' and 121c' can be arranged in the third component region CA3, and the third spacer SPC3 can be arranged on the third pixel defining layer 119c.

[0246] like Figure 20 and Figure 21 As shown, a second pixel defining layer 119b covering the edges of the second pixel electrodes 121a', 121b', and 121c' can be disposed in the second component region CA2. The second pixel defining layer 119b can have steps with partially different heights. The relatively high protruding portion of the second pixel defining layer 119b can serve as a second spacer SPC2. The second pixel defining layer 119b and the second spacer SPC2 can be formed as a single unit.

[0247] The first pixel defining layer 119a and the third pixel defining layer 119c can be formed in the main display area MDA and the third component area CA3, respectively, by a first insulating layer comprising an opaque material. In this case, with Figure 16A Unlike other components, the insulating pattern BP is not formed in the second component region CA2.

[0248] Next, the first spacer SPC1 and the third spacer SPC3 can be formed in the main display area MDA and the third component area CA3, respectively, by a second insulating layer including a transparent material, and the second pixel defining layer 119b and the second spacer SPC2 can be formed in the second component area CA2. Figure 16B Unlike other components, the second pixel defining layer 119b and the second spacer SPC2, having different heights, can be formed in the second component region CA2 by an exposure and development process using a mask (such as a halftone mask) with different transmittance for each region. In this specification, height refers to the height from the upper surface of the substrate 100. The height of the second spacer SPC2 from the substrate 100 can be greater than the height of the second pixel defining layer 119b from the substrate 100.

[0249] Figure 22This is a schematic cross-sectional view of a portion of the display panel 10d according to an embodiment. Figure 23 yes Figure 22 A schematic plan view of the display layer DISL of the second component area CA2.

[0250] Figure 22 The display panel 10d shown can have the same characteristics as... Figure 10 The second component region CA2 of the display panel 10a shown is different from the display layer DISL of the second component region CA2, and other components are... Figure 10 The components of the display panel 10a shown are the same.

[0251] A first pixel defining layer 119a covering the edges of the first pixel electrodes 121a, 121b and 121c can be disposed in the main display area MDA, and a first spacer SPC1 can be disposed on the first pixel defining layer 119a.

[0252] The third pixel defining layer 119c covering the edges of the second pixel electrodes 121a', 121b' and 121c' can be arranged in the third component region CA3, and the third spacer SPC3 can be arranged on the third pixel defining layer 119c.

[0253] A second pixel defining layer 119b' covering the edges of the second pixel electrodes 121a', 121b', and 121c' can be arranged in the second component region CA2. For example... Figure 23 As shown, the second pixel defining layer 119b' may include a first insulating pattern surrounding the edges of the second pixel electrodes 121a', 121b', and 121c'. A second insulating pattern BP may be further disposed between the second pixel electrodes 121a', 121b', and 121c' in the second component region CA2. The second insulating pattern BP may be located between and spaced apart from the first insulating patterns. A corresponding second spacer SPC2 may be disposed on each of the second insulating patterns BP.

[0254] The first pixel limiting layer 119a, the second pixel limiting layer 119b', the second insulating pattern BP, and the third pixel limiting layer 119c can be formed by the first insulating layer, which includes an opaque material, in the main display area MDA, the second component area CA2, and the third component area CA3, respectively.

[0255] Next, the first spacer SPC1 and the third spacer SPC3 can be formed in the main display area MDA and the third component area CA3 respectively by a second insulating layer including transparent material, and the second spacer SPC2 can be formed in the second component area CA2.

[0256] In this embodiment, since the area occupied by the second pixel defining layer 119b' in the second component region CA2 is limited to the vicinity of the second pixel electrode 121', the light transmittance of the second component region CA2 can be ensured even if the second pixel defining layer 119b' includes an opaque insulating material.

[0257] Figure 24 This is a schematic cross-sectional view of a portion of the display panel 10e according to an embodiment. Figure 25 yes Figure 24 A schematic plan view of the display layer DISL of the main display area MDA.

[0258] Reference Figure 24 and Figure 25 The first pixel defining layer 119a' in the main display area MDA may include a third insulating pattern surrounding the edges of the first pixel electrodes 121a, 121b, and 121c. Similarly, the second pixel defining layer 119b' of the second component area CA2 and the third pixel defining layer 119c' of the third component area CA3 may include a first insulating pattern surrounding the edges of the second pixel electrodes 121a', 121b', and 121c'.

[0259] The fourth insulating pattern BP can be located between the third insulating patterns in the main display area MDA, and the fourth insulating pattern BP is spaced apart from the third insulating pattern. The second insulating pattern BP can be located between the first insulating patterns in the second component area CA2 and the third component area CA3, and the second insulating pattern BP is spaced apart from the first insulating pattern. The corresponding first spacer SPC1 can be arranged on each fourth insulating pattern BP, and the corresponding second spacer SPC2 and third spacer SPC3 can be arranged on each second insulating pattern BP.

[0260] The first pixel defining layer 119a', the second pixel defining layer 119b', the third pixel defining layer 119c', and the second insulating pattern BP and the fourth insulating pattern BP may each include opaque material. The first spacer SPC1, the second spacer SPC2, and the third spacer SPC3 may include transparent material.

[0261] Figure 26 This is a schematic cross-sectional view of a portion of the display panel 10f according to an embodiment. Figure 27A yes Figure 26 A schematic plan view of the display layer DISL of the main display area MDA. Figure 27B yes Figure 26 A schematic plan view of the display layer DISL of the second component area CA2.

[0262] Reference Figure 26 and Figure 27AThe first pixel defining layer 119a in the main display area MDA can cover the edges of the first pixel electrodes 121a, 121b, and 121c, and can have steps with partially different heights. The relatively high protruding portion of the first pixel defining layer 119a can serve as the first spacer SPC1. The first pixel defining layer 119a and the first spacer SPC1 can be formed as a single unit.

[0263] Similarly, the third pixel defining layer 119c in the third component region CA3 can cover the edges of the second pixel electrodes 121a', 121b', and 121c', and can have steps with slightly different heights. The relatively high protruding portion of the third pixel defining layer 119c can serve as the third spacer SPC3. The third pixel defining layer 119c and the third spacer SPC3 can be formed as a single unit.

[0264] Reference Figure 26 and Figure 27B The second pixel defining layer 119b' in the second component region CA2 may include a first insulating pattern surrounding the edges of the second pixel electrodes 121a', 121b', and 121c'. A second spacer SPC2 may be located between the first insulating patterns, spaced apart from them. The second spacer SPC2 may have steps of varying heights. The relative height from the substrate 100 to the upper surface of the protrusion of the second spacer SPC2 may be greater than the height from the substrate 100 to the upper surface of the second pixel defining layer 119b'.

[0265] The first pixel limiting layer 119a, the second pixel limiting layer 119b', the third pixel limiting layer 119c, the first spacer SPC1, the second spacer SPC2, and the third spacer SPC3 may each include opaque materials.

[0266] Figure 28 This is a schematic cross-sectional view of a portion of the display panel 10g according to an embodiment. Figure 29 yes Figure 28 A schematic plan view of the display layer DISL of the main display area MDA.

[0267] Reference Figure 28 and Figure 29 The first pixel defining layer 119a' in the main display area MDA may include a third insulating pattern surrounding the edges of the first pixel electrodes 121a, 121b, and 121c. Similarly, the second pixel defining layer 119b' of the second component area CA2 and the third pixel defining layer 119c' of the third component area CA3 may include a first insulating pattern surrounding the edges of the second pixel electrodes 121a', 121b', and 121c'.

[0268] The first spacer SPC1 may be located between the third insulating patterns in the main display area MDA, and the first spacer SPC1 is spaced apart from the first insulating patterns. The second spacer SPC2 and the third spacer SPC3 may be located between the first insulating patterns in the second component area CA2 and the third component area CA3, respectively, and the second spacer SPC2 and the third spacer SPC3 are spaced apart from the first insulating patterns. The first spacer SPC1, the second spacer SPC2, and the third spacer SPC3 may have steps with different heights. The height of the upper surface of the protrusion from the substrate 100 to the first spacer to the third spacer SPC1, SPC2, and SPC3 may be higher than the height of the upper surface from the substrate 100 to the first pixel defining layer to the third pixel defining layer 119a', 119b', and 119c'.

[0269] The first pixel limiting layer 119a', the second pixel limiting layer 119b', the third pixel limiting layer 119c', the first spacer SPC1, the second spacer SPC2, and the third spacer SPC3 may each include opaque materials.

[0270] Figure 30A and Figure 30B Is Figure 26 and Figure 28 An exemplary view of the method of forming a first insulating pattern and spacers in the display panels 10f and 10g shown.

[0271] In an embodiment, such as Figure 30A As shown, an insulating layer with a different height for each portion can be formed by using an exposure and development process of a halftone mask M1 comprising a light-shielding portion Ma, a transmissive portion Mb, and a semi-transmissive portion Mc. For example, the transmissive portion Mb can be positioned to correspond to the second pixel defining layer 119b', and the transmissive portion Mb and the semi-transmissive portion Mc can be positioned to correspond to the second spacer SPC2 having a step.

[0272] In another embodiment, such as Figure 30B As shown, in the exposure and development process using a full-tone mask M2 that includes a light-shielding portion Ma and a transmissive portion Mb, an insulating layer with a different height for each portion according to its width can be formed by using an insulating layer including a negative photosensitive material. For example, the second width LW2 of the second spacer SPC2 can be greater than the first width LW1 of the second pixel defining layer 119b', and therefore, the height H2 of the second spacer SPC2 can be formed to be greater than the height H1 of the second pixel defining layer 119b'.

[0273] According to one or more embodiments, in a display device including a main display area (MDA) and a component area (CA), an optical functional layer including a color filter and a black matrix, as well as an opaque pixel defining layer, is used. Therefore, compared to a display device using a polarizer, the thickness of the display device can be reduced, and the reflection of external light can be decreased. Furthermore, according to one or more embodiments, in the component area (CA), an optical functional layer without a black matrix and a transparent or opaque pixel defining layer with a minimal area are used. Therefore, the degradation of light transmittance (especially visible light transmittance) in the component area (CA) due to the black matrix and opaque pixel defining layer can be minimized, thereby maximizing the function of the component. Additionally, an image can be implemented in the component area (CA) without altering the image quality.

[0274] In the foregoing embodiments, component regions in which an illuminance sensor in which visible light is incident and component regions in which infrared light is incident have been described as examples, but similar applications can be made to component regions in which visible light and / or infrared light is incident.

[0275] As described above, in the display panel and display device according to the given embodiments, a color filter is used to prevent reflection of external light and minimize the thickness of the display device. The pixel defining layer and spacers in the component region where the components are arranged are constructed differently from the pixel defining layer and spacers in the main display region, thereby ensuring transmittance in the component region. However, the scope of the embodiments is not limited to the effects described above.

[0276] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as will be apparent to those skilled in the art.

Claims

1. A display device, the display device comprising a main display area in which a main display element is disposed, and an assembly area in which an auxiliary display element and a transmissive area are disposed, the display device comprising: A first pixel defining layer is disposed in the main display area, and the first pixel defining layer is disposed between the first pixel electrodes of the main display element; A second pixel defining layer is disposed in the component region, and the second pixel defining layer is disposed between the second pixel electrodes of the auxiliary display element; A black matrix is ​​arranged on the main display element, the black matrix is ​​disposed around the emission area of ​​the main display element, and is not arranged in the component area; as well as Color filters are disposed on the main display element and the auxiliary display element, and the color filters correspond to the emission areas of the main display element and the auxiliary display element, respectively. The transmission region is the area through which light and / or sound emitted from the display device to the outside or traveling from the outside toward the display device are transmitted.

2. The display device according to claim 1, wherein, The first pixel defining layer comprises an opaque material, and The second pixel defining layer includes a transparent material.

3. The display device according to claim 2, further comprising: A first spacer is disposed on the first pixel defining layer; An insulating pattern is arranged in the component area; as well as A second spacer is disposed on the insulating pattern. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

4. The display device according to claim 3, wherein, The second pixel defining layer covers the insulating pattern, and The second spacer is part of the arrangement of the second pixel defining layer on the insulating pattern.

5. The display device according to claim 3, wherein, The second pixel defining layer is configured to be spaced apart from the insulating pattern, and The slit surrounds the insulating pattern between the second pixel defining layer and the insulating pattern.

6. The display device according to claim 2, further comprising: A first spacer is disposed on the first pixel defining layer; as well as The second spacer, as part of the second pixel defining layer, is a portion protruding from the second pixel defining layer. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

7. The display device according to claim 1, wherein, Each of the first pixel-defining layer and the second pixel-defining layer includes an opaque material.

8. The display device according to claim 7, wherein, The second pixel defining layer includes a first insulating pattern surrounding the edge of the second pixel electrode.

9. The display device according to claim 8, further comprising: A first spacer is disposed on the first pixel defining layer; A second insulating pattern is disposed between the first insulating patterns, and the second insulating pattern is configured to be separated from the first insulating patterns; as well as The second spacer is disposed on the second insulating pattern. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

10. The display device according to claim 9, wherein, The second insulating pattern includes an opaque material, and Each of the first spacer and the second spacer comprises a transparent material.

11. The display device according to claim 8, wherein, The first pixel defining layer includes a third insulating pattern surrounding the edge of the first pixel electrode.

12. The display device according to claim 11, further comprising: A fourth insulating pattern is disposed between the third insulating patterns, and the fourth insulating pattern is configured to be separated from the third insulating patterns; A first spacer is disposed on the fourth insulating pattern; A second insulating pattern is disposed between the first insulating patterns, and the second insulating pattern is configured to be separated from the first insulating patterns; as well as The second spacer is disposed on the second insulating pattern. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

13. The display device according to claim 12, wherein, Each of the second and fourth insulating patterns includes an opaque material, and Each of the first spacer and the second spacer comprises a transparent material.

14. The display device according to claim 8, further comprising: A first spacer, as part of the first pixel defining layer, is a portion protruding from the first pixel defining layer; as well as A second spacer is disposed between the first insulating patterns, the second spacer being configured to be spaced apart from the first insulating patterns and including portions of different heights. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

15. The display device according to claim 14, wherein, The second spacer comprises an opaque material.

16. The display device according to claim 11, further comprising: A first spacer is disposed between the third insulating patterns, the first spacer being configured to be spaced apart from the third insulating patterns and including portions of different heights; as well as A second spacer is disposed between the first insulating patterns, the second spacer being configured to be spaced apart from the first insulating patterns and including portions of different heights. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

17. The display device according to claim 16, wherein, Each of the first spacer and the second spacer comprises an opaque material.

18. The display device according to claim 1, wherein, The edge of the second pixel defining layer in the component area overlaps with the edge of the first pixel defining layer in the main display area.

19. A display device comprising a main display area in which a main display element is disposed and an assembly area in which an auxiliary display element and a transmissive area are disposed, the display device comprising: A first pixel defining layer is disposed in the main display area and covers the edge of the first pixel electrode of the main display element; A first spacer is disposed between the first pixel electrodes of the main display element; A second pixel defining layer is disposed in the component region and covers the edge of the second pixel electrode of the auxiliary display element; A second spacer is disposed between the second pixel electrodes of the auxiliary display element; A thin-film encapsulation layer is disposed on the main display element and the auxiliary display element; as well as A black matrix is ​​disposed on the thin-film encapsulation layer, the black matrix being positioned around the emission region of the main display element but not within the component region. The transmission region is the area through which light and / or sound emitted from the display device to the outside or traveling from the outside toward the display device are transmitted. The first spacer and the second spacer are configured to prevent damage to the first pixel electrode and the second pixel electrode.

20. The display device according to claim 19, wherein, The second spacer is arranged on an insulating pattern between the second pixel electrodes of the auxiliary display element.

21. The display device according to claim 19, wherein, The second pixel defining layer includes an insulating pattern surrounding the edge of the second pixel electrode.

22. The display device according to claim 21, wherein, The second spacer is disposed between the insulating patterns and includes portions with different heights.

23. The display device according to claim 19, wherein, The second spacer is a portion of the second pixel defining layer, and the second spacer is a portion protruding from the second pixel defining layer.

24. The display device according to claim 19, further comprising: Color filters are arranged on the thin-film encapsulation layer, and the color filters correspond to the emission areas of the main display element and the auxiliary display element, respectively.

Images