Display device

Abstract

A display device is provided, including: a first substrate including a display portion and a non-display portion located around the display portion; a second substrate disposed on the first substrate; a pixel disposed between the display portion and the second substrate; a quantum dot layer disposed between the second substrate and the pixel; a bank layer disposed around the quantum dot layer, and the bank layer overlaps with the non-display portion when viewed on a plane; a color filter disposed between the second substrate and the quantum dot layer; a dummy color filter overlapping with the non-display portion when viewed on the plane, and disposed between the bank layer and the second substrate; and a sealant disposed between the non-display portion and the bank layer.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2020-0067810, filed on June 4, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device. Background Technology

[0004] Typically, a display device includes a plurality of pixels for displaying an image. Each pixel includes an image display element and a driving element connected to the image display element. The driving element drives the image display element, and the image display element generates predetermined light to provide an image to the user.

[0005] Recently, to improve color purity, display devices incorporating light conversion layers have been developed. These light conversion layers are disposed on pixels and convert the light generated from the image display element of each pixel into light with different wavelengths. The light conversion layer includes quantum dot layers corresponding to the pixels. Each quantum dot in the quantum dot layer includes quantum dots for converting the wavelength of light.

[0006] A pixel is disposed on a first substrate, and a quantum dot layer is disposed on a second substrate. The pixel and quantum dot layer are disposed between the first and second substrates, facing each other. The first and second substrates are bonded by a sealant, and thus, the pixel and quantum dot layer are sealed by the sealant. The sealant is typically disposed in a peripheral region of the second substrate (where multiple layers formed on the second substrate terminate), and poor bonding between the first and second substrates through the sealant may occur due to pressure applied to the second substrate. Summary of the Invention

[0007] The present invention provides a display device capable of reducing the difference in gap between a first substrate and a second substrate.

[0008] According to an exemplary embodiment of the present invention, a display device includes: a first substrate including a display portion and a non-display portion surrounding the display portion; a second substrate disposed on the first substrate; a pixel disposed between the display portion and the second substrate; a quantum dot layer disposed between the second substrate and the pixel; a embankment layer disposed around the quantum dot layer and overlapping the non-display portion when viewed in a plane; a color filter disposed between the second substrate and the quantum dot layer; a dummy color filter overlapping the non-display portion when viewed in the plane and disposed between the embankment layer and the second substrate; and a sealant disposed between the non-display portion and the embankment layer.

[0009] According to an exemplary embodiment of the present invention, a display device includes: a display portion and a non-display portion surrounding the display portion; a second substrate disposed on a first substrate; pixels disposed between the display portion and the second substrate; a quantum dot layer disposed between the second substrate and the pixels; a embankment layer disposed around the quantum dot layer and overlapping the non-display portion when viewed in a plane; a support layer disposed on the non-display portion; a dam disposed on the non-display portion and spaced apart from the support layer; and a sealant disposed between the non-display portion and the embankment layer, wherein the sealant may be disposed between the support layer and the dam.

[0010] According to an exemplary embodiment of the present invention, a display device includes: a first substrate, the first substrate including a display portion and a non-display portion surrounding the display portion; a second substrate disposed on the first substrate; pixels disposed between the display portion and the second substrate; a quantum dot layer disposed between the second substrate and the pixels; a color filter disposed between the second substrate and the quantum dot layer; a embankment layer disposed around the quantum dot layer, and overlapping the non-display portion when viewed in a plane; and a dummy color filter, which, when viewed in a plane... When viewed, the dummy color filter overlaps with the non-display portion and is disposed between the embankment layer and the second substrate; a support layer is disposed on the non-display portion; a thin-film encapsulation layer is disposed on the display portion to cover the pixels and extends to the non-display portion to cover the support layer; and a sealant is disposed between the thin-film encapsulation layer and the embankment layer, wherein the sealant may be disposed between the support layer and the display portion, and the edge of the thin-film encapsulation layer adjacent to and spaced apart from the edge of the first substrate may be disposed between the edge of the first substrate and the support layer. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this application. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0012] Figure 1 This is a perspective view of a display device DD according to an exemplary embodiment of the present invention;

[0013] Figure 2 This is an example shown Figure 1 A cross-sectional view of the display device DD shown in the figure;

[0014] Figure 3 This is an example shown Figure 2 A cross-sectional view of the display panel DP shown in the image;

[0015] Figure 4 It includes Figure 3 The plan view of the display device DD of the display panel DP is shown in the figure;

[0016] Figure 5 This is an example shown Figure 4 The image shows a cross-sectional view of a pixel PX.

[0017] Figure 6 This is an example illustrating the inclusion of Figure 3 The image shows a cross-sectional view of the display panel DP with the color filter layer CFL and the light conversion layer LCL.

[0018] Figure 7 Is it shown with Figure 3 The image shows a cross-sectional view of a portion of the non-display portion NDA and the display panel DP that overlaps with the adjacent display portion DA.

[0019] Figure 8 It is used to show Figure 7 The view shown illustrates the functionality of the support layer SUP;

[0020] Figure 9 It is shown that... Figure 4 The diagram shows a view of the second power line PL2, the first control line CSL1, and some data lines DL1 and DL2 overlapping with the sealant SAL; and

[0021] Figures 10 to 14 This is a cross-sectional view showing the non-display portion NDA of the display panels DP_1 to DP_4, each according to an exemplary embodiment of the present invention.

[0022] because Figures 1 to 14 The accompanying drawings are intended for illustrative purposes, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0023] In the present invention, when an element (or region, layer, part, etc.) is referred to as being "on" another element, "connected to" or "coupled to" another element, this means that the element can be directly disposed on / connected to / coupled to the other element, or a third element can be disposed between the element and the other element.

[0024] The same reference numerals denote the same elements.

[0025] The term "and / or" includes any and all combinations that can define one or more related configurations.

[0026] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. The terms are used only to distinguish one element from another. For example, without departing from the scope of the inventive concept, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless the context clearly indicates otherwise, singular terms may include plural forms.

[0027] Furthermore, terms such as “below,” “down,” “above,” and “above” are used to describe the relationships of the configurations shown in the accompanying drawings. These terms are used as relative concepts and are described with reference to the directions indicated in the drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the apparatus during use or operation.

[0028] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that, unless expressly defined herein, terms such as those defined in a general dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and should not be interpreted in an idealized or overly formalized sense.

[0029] It should be understood that, in the present invention, the terms “comprising” or “having” are intended to describe the presence of the stated features, integrals, steps, operations, elements, components or combinations thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components or combinations thereof.

[0030] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0031] Figure 1 This is a perspective view of a display device DD according to an exemplary embodiment of the present invention.

[0032] Reference Figure 1 According to an exemplary embodiment of the present invention, the display device DD may have a rectangular shape, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR1. Alternatively, the display device DD may have an approximate quadrilateral shape, and the four corners of the quadrilateral shape may have rounded shapes with predetermined curvatures. However, the present invention is not limited thereto. The display device DD may have various shapes, such as circular or polygonal shapes.

[0033] In the following text, the direction that intersects substantially perpendicularly with the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, in the present invention, "when viewed on a plane" is defined as being viewed from the third direction DR3.

[0034] The top surface of the display device DD can be defined as a display surface DS, and can have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated in the display device DD can be provided to the user via the display surface DS. The display surface DS can be a flat surface. However, the inventive concept is not limited thereto. For example, the display surface DS can be a curved surface or a three-dimensional surface. A three-dimensional display surface that generates an image within a display volume rather than on a stationary surface can include multiple display areas, such as a polygonal prism surface. The multiple display areas can be oriented in different directions.

[0035] The display surface DS may include a display portion DA and a non-display portion NDA surrounding the display portion DA. The display portion DA displays an image, while the non-display portion NDA may not display an image. The non-display portion NDA surrounds the display portion DA and may define an edge of the display device DS printed with a predetermined color.

[0036] The display device DD can be used in large electronic devices such as televisions, monitors, or external billboards. Furthermore, the display device DD can be used in small to medium-sized electronic devices, such as personal computers, laptops, personal digital terminals, car navigation systems, game consoles, smartphones, tablets, smartwatches, or cameras. However, these are merely exemplary embodiments, and the display device DD can be used in other electronic devices, provided that such other electronic devices do not depart from the scope of the inventive concept.

[0037] Figure 2 This is an example shown Figure 1 The image shows a cross-sectional view of the display device DD.

[0038] Illustratively, Figure 2 A cross-section of the display device DD as viewed from the first direction DR1 is shown.

[0039] Reference Figure 2 The display device DD may include a display panel DP, an input sensing unit ISP, a window WIN, a panel protective film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2. The first adhesive layer AL1 and the second adhesive layer AL2 may be formed from a pre-coated film or from a liquid paste. Typically, the first adhesive layer AL1 and the second adhesive layer AL2 may have optical transparency and provide impact resistance. The display panel DP may be a flexible display panel. For example, the display panel DP may include multiple electronic components disposed on a flexible substrate that is bendable, foldable, or rollable. However, the inventive concept is not limited thereto. For example, the display panel DP may be of a rigid type.

[0040] The display panel DP according to an exemplary embodiment of the present invention can be a light-emitting display panel. For example, the display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots or quantum rods, etc. Quantum dots and quantum rods can be small semiconductor particles with a size of a few nanometers. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0041] The input sensing unit (ISP) can be disposed on the display panel (DP) and can include multiple sensors for capacitively sensing external input. Alternatively, the multiple sensors of the input sensing unit (ISP) can sense external input using electromagnetic induction or pressure sensing methods. The input sensing unit (ISP) may also include multiple signal lines connected to the multiple sensors and at least one electrically insulating layer. When manufacturing the display device (DD), the input sensing unit (ISP) can be directly fabricated on the display panel (DP). However, the inventive concept is not limited thereto. For example, the input sensing unit (ISP) can be fabricated as a panel separate from the display panel (DP) and then attached to the display panel (DP) via an adhesive layer. Alternatively, the input sensing unit (ISP) can be omitted.

[0042] The window (WIN) can be mounted on the input sensing unit (ISP) and can protect the display panel (DP) and the input sensing unit (ISP) from external scratches and impacts. The window (WIN) can be formed of an insulating material such as glass, quartz, and / or polymer resin.

[0043] The panel protective film (PPF) can be placed below the display panel (DP) to protect the lower part of the DP and support it. The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET) or polyimide (PI).

[0044] The first adhesive layer AL1 is disposed between the display panel DP and the panel protective film PPF to bond the display panel DP and the panel protective film PPF together. The second adhesive layer AL2 is disposed between the window WIN and the input sensing unit ISP to bond the window WIN and the input sensing unit ISP together.

[0045] Figure 3 This is an example shown Figure 2 The image shows a cross-sectional view of the display panel DP.

[0046] Illustratively, Figure 3 A cross-section of the display panel DP as viewed from the first direction DR1 is shown.

[0047] Reference Figure 3The display panel DP may include a first substrate SUB1, a second substrate SUB2, a circuit element layer DP-CL, a display element layer DP-OLED, a thin film encapsulation layer TFE, a color filter layer CFL, a light conversion layer LCL, a light blocking layer LSL, a filler FL, and a sealant SAL.

[0048] The second substrate SUB2 can be disposed on the first substrate SUB1 facing the first substrate SUB1. The circuit element layer DP-CL, the display element layer DP-OLED, the thin film encapsulation layer TFE, the color filter layer CFL, the light conversion layer LCL, the light blocking layer LSL, the filler FL, and the sealant SAL can be disposed between the first substrate SUB1 and the second substrate SUB2.

[0049] The first substrate SUB1 and the second substrate SUB2 may comprise a flexible plastic material such as polyimide (PI) or glass. When viewed in a planar surface, the first substrate SUB1 may comprise a display portion DA and a non-display portion NDA surrounding the display portion DA. The display portion DA may be an area in which pixels are arranged. The non-display portion NDA may be an area in which no pixels are arranged; however, signal lines and drivers for supporting the operation of the pixels may be arranged therein. Each of the pixels may comprise a light-emitting element, such as an organic light-emitting diode (OLED) to be described (see [link to OLED description]). Figure 5 ).

[0050] The circuit element layer DP-CL can be disposed on the first substrate SUB1. The display element layer DP-OLED can be disposed on the circuit element layer DP-CL. In addition, the display element layer DP-OLED can be disposed on the display section DA.

[0051] Multiple pixels can be disposed in the DP-CL circuit element layer and the DP-OLED display element layer. Each pixel may include a transistor disposed in the DP-CL circuit element layer and a light-emitting element disposed in the DP-OLED display element layer to connect to the transistor. The configuration of the pixels will be described in detail below. The DP-OLED display element layer may include at least an organic light-emitting diode (OLED) (see [link to OLED display element layer]). Figure 5 As a light-emitting element, it may also include an organic layer, such as a pixel-defining film (PDL) to be described (see Figure 5 The circuit element layer DP-CL may include at least one electrically insulating layer and at least one circuit element. The electrically insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element includes the signal lines and drive circuitry of the pixel.

[0052] A thin-film encapsulation layer (TFE) can be disposed on the circuit element layer (DP-CL) to cover the display element layer (DP-OLED) and can protect the pixels from moisture, oxygen, and foreign matter. The TFE can include at least one organic encapsulation layer and at least one inorganic encapsulation layer. In exemplary embodiments of the present invention, the number of organic and inorganic encapsulation layers, as well as the order in which the organic and inorganic encapsulation layers are stacked, can be varied.

[0053] The color filter layer (CFL) can be positioned below the second substrate (SUB2). When viewed on a flat surface, the color filter layer (CFL) can overlap with the display portion (DA). The light conversion layer (LCL) can be positioned below the color filter layer (CFL). When viewed on a flat surface, the light conversion layer (LCL) can overlap with the display portion (DA).

[0054] A light-blocking layer LSL can be disposed below the second substrate SUB2, and when viewed in a flat surface, the light-blocking layer LSL can overlap with the non-display portion NDA. The light-blocking layer LSL can be disposed around the color filter layer CFL and the light conversion layer LCL. For example, when viewed in a flat surface, the light-blocking layer LSL can surround the color filter layer CFL and the light conversion layer LCL. The color filter layer CFL, according to an exemplary embodiment of the present invention, can include a plurality of color filters. The color filters can have a predetermined arrangement. The arrangement of the color filters can be determined by considering the emitted colors of the pixels included in the display panel DP. Therefore, a desired color can be achieved by using color filters to filter the light emitted through each pixel.

[0055] The sealant SAL can overlap with the non-display portion NDA and can be disposed between the first substrate SUB1 and the second substrate SUB2. The first substrate SUB1 and the second substrate SUB2 can be bonded to each other by the sealant SAL. The sealant SAL can be disposed between the thin-film encapsulation layer TFE and the light-blocking layer LSL, and can include an ultraviolet (UV) curable material. For example, the sealant SAL can include a thermocurable resin or a photocurable resin. Alternatively, in exemplary embodiments of the inventive concept, the sealant SAL can include an inorganic material such as a glass frit, and the glass frit can include a crystalline (fully and / or partially crystalline) matrix glass or mother glass.

[0056] In exemplary embodiments of the present invention, the sealant SAL may comprise an epoxy resin, including, for example, bisphenol A epoxy resin, bisphenol F epoxy resin, aromatic epoxy resin, hydrogenated bisphenol epoxy resin, cycloaliphatic epoxy resin, phenolic varnish epoxy resin, dicyclopentadiene epoxy resin, or any combination thereof. However, the present invention is not limited thereto, and any other suitable thermocurable or photocurable resin may be used in the sealant SAL.

[0057] Sealant SAL may also include one or more of the following: thermosetting agents, photoinitiators, coupling agents, curing accelerators, inorganic fillers, antioxidants, and spacers.

[0058] The filler FL can overlap with the display portion DA and can be disposed between the light conversion layer LCL and the thin-film encapsulation layer TFE. The filler FL can extend toward the non-display portion NDA to contact the sealant SAL. The filler FL can comprise, for example, silicon-based, epoxy-based, and / or acrylic-based thermosetting materials. For example, the first substrate SUB1 and the second substrate SUB2 can be assembled together by means of the sealant SAL positioned on the non-display portion NDA surrounding the display portion DA, and can also be assembled together by means of the filler FL filling the space inside the sealant SAL. For example, the filler FL can fill the space surrounded by the sealant SAL.

[0059] The light generated in the DP-OLED display element layer can be provided to the light conversion layer LCL. The light conversion layer LCL can convert the color of the light provided from the DP-OLED display element layer. The light whose color has been converted by the light conversion layer LCL can be emitted to the outside through the color filter layer CFL and the second substrate SUB2.

[0060] The color filter layer (CFL) prevents reflection of external light supplied to the display panel (DP). This function of the CFL will be described in detail below. The CFL may include different color filters, each selectively transmitting light within a specified wavelength range and blocking light outside that range. The light blocking layer (LSL) blocks light from the non-display portion (NDA).

[0061] Figure 4 It includes Figure 3 The plan view of the display device DD with display panel DP shown in the figure.

[0062] Reference Figure 4 The display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light-emitting driver EDV, and multiple pads PD.

[0063] The display panel DP may have a rectangular shape, having a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but the shape of the display panel DP is not limited to this. The display panel DP may include a display portion DA and a non-display portion NDA surrounding the display portion DA.

[0064] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple light emission lines EL1 to Elm, a first control line CSL1 and a second control line CSL2, a first power line PL1 and a second power line PL2, and a connecting line CNL. In the above figure reference numerals, m and n are natural numbers.

[0065] Pixels (PX) can be set in the display portion (DA). Scan driver (SDV) and light-emitting driver (EDV) can be set in the non-display portion (NDA) adjacent to each of the long sides of the display panel (DP). For example, when viewed on a flat surface, the scan driver (SDV) can be positioned opposite the light-emitting driver (EDV), the display portion (DA) is located between the scan driver (SDV) and the light-emitting driver (EDV), and the scan driver (SDV) can be substantially parallel to the light-emitting driver (EDV).

[0066] The data driver DDV can be mounted on a flexible printed circuit board (FPCB). The FPCB can be connected to a non-display portion NDA adjacent to any of the short sides of the display panel DP. When viewed in a flat surface, the FPCB can be connected to the lower end of the display panel DP. The data driver DDV can be connected to the display panel DP via the FPCB. However, the inventive concept is not limited thereto. For example, the data driver DDV can be directly disposed within the non-display portion NDA.

[0067] Scan lines SL1 to SLm can extend in the second direction DR2 to connect to the scan driver SDV. Data lines DL1 to DLn can extend in the first direction DR1 to connect to the pixel PX. Data lines DL1 to DLn can be connected to the data driver DDV via a flexible printed circuit board (FPCB). Light emission lines EL1 to ELm can extend in the second direction DR2 to connect to the pixel PX and the light emission driver EDV.

[0068] The first power line PL1 may extend along the first direction DR1 and may be disposed in the non-display portion NDA. The first power line PL1 may be disposed between the display portion DA and the light-emitting driver EDV, but the inventive concept is not limited thereto. For example, the first power line PL1 may be disposed between the display portion DA and the scan driver SDV.

[0069] The connecting line CNL can extend along the second direction DR2 and can be arranged along the first direction DR1. The connecting line CNL can be connected to the first power line PL1 and the pixel PX. A first voltage can be applied to the pixel PX through the first power line PL1 and the connecting line CNL connected to each other.

[0070] A second power line PL2 can be provided in the non-display portion NDA, and the second power line PL2 can extend along the long side of the display panel DP and the other short side of the display panel DP where the data driver DDV is not connected. For example, the second power line PL2 can partially surround the display portion DA and can extend along all sides of the display panel DP except for the side of the display panel DP adjacent to the flexible printed circuit board FPCB and connected to the data driver DDV. The second power line PL2 can be located at a periphery further outward than the scan driver SDV and the light-emitting driver EDV.

[0071] The second power line PL2 can extend toward the display section DA to connect to the pixel PX. A second voltage with a lower level than the first voltage can be applied to the pixel PX through the second power line PL2.

[0072] The first control line CSL1 is connected to the scan driver SDV, and when viewed on a flat surface, the first control line CSL1 can extend towards the lower end of the display panel DP. The second control line CSL2 is connected to the light-emitting driver EDV, and when viewed on a flat surface, the second control line CSL2 can extend towards the lower end of the display panel DP.

[0073] The pad PD can be set on the display panel DP. The pad PD can be adjacent to the bottom of the display panel DP. Data lines DL1 to DLn, first power line PL1, second power line PL2, first control line CSL1, and second control line CSL2 can be connected to the pad PD. Multiple connection pads can be set on the flexible printed circuit board (FPCB) to connect to the pad PD.

[0074] The pads PD connected to the data lines DL1 to DLn can be connected to the data driver DDV via a flexible printed circuit board (FPCB). The display device DD may include a timing controller for controlling the operation of the scan driver SDV, the data driver DDV, and the light-emitting driver EDV, as well as a voltage generation unit for generating a first voltage and a second voltage. In an exemplary embodiment of the present invention, the flexible printed circuit board (FPCB) can be electrically connected to the pads PD, which are positioned on the side of the non-display portion NDA adjacent to the lower end of the display panel DP. The flexible printed circuit board (FPCB) can be bent and electrically connected to the display panel DP. Therefore, the flexible printed circuit board (FPCB), acting as a controller, can output signals to or receive signals from the display panel DP via the pads PD.

[0075] The timing controller and voltage generation unit can be mounted on a printed circuit board (PCB) and connected to a flexible printed circuit board (FPCB). The timing controller can be connected to the data driver (DDV) via the PCB and FPCB. The first power line PL1 and the second power line PL2, as well as the first control line CSL1 and the second control line CSL2, can be connected to the timing controller and voltage generation unit via the FPCB and the PCB. For example, the timing controller and voltage generation unit can output signals and voltages to the first control line CSL1 and the second control line CSL2, and the first power line PL1 and the second power line PL2, respectively, via pads PD.

[0076] The sealant SAL can be disposed in the non-display portion NDA to surround the display portion DA, and can be adjacent to the edge of the display panel DP. Illustratively, the sealant SAL is disposed at a peripheral location further outward than the second power line PL2, and can be disposed at a peripheral location further inward than the pad PD.

[0077] The scan driver SDV generates multiple scan signals, which can be applied to pixel PX via scan lines SL1 to SLm. The data driver DDV generates multiple data voltages, which can be applied to pixel PX via data lines DL1 to DLn. The light-emitting driver EDV generates multiple light-emitting signals, which can be applied to pixel PX via light-emitting lines EL1 to ELm. For example, the data driver DDV can receive vertical synchronization signals, horizontal synchronization signals, and clock signals, generate control signals for controlling the operation of the scan driver SDV and the light-emitting driver EDV, and transmit the relevant control signals to the relevant components.

[0078] A pixel PX can be supplied with a data voltage in response to a scan signal, and can display an image by emitting light with a brightness corresponding to the data voltage in response to a light emission signal. The duration of light emission of a pixel PX can be controlled by the light emission signal.

[0079] Figure 5 This is an example shown Figure 4 The image shows a cross-sectional view of a pixel PX.

[0080] Reference Figure 5 A pixel (PX) may include a transistor (TR) and a light-emitting element (OLED, i.e., an organic light-emitting diode). The light-emitting element (OLED) may include a first electrode (AE), a hole control layer (HCL), a light-emitting layer (EML), an electron control layer (ECL), and a second electrode (CE). The first electrode (AE) may be an anode electrode, and the second electrode (CE) may be a cathode electrode.

[0081] A transistor TR and a light-emitting element OLED can be disposed on a first substrate SUB1. Illustratively, one transistor TR is shown, but essentially, a pixel PX may include multiple transistor TRs for driving the light-emitting element OLED and at least one capacitor. In an exemplary embodiment of the inventive concept, the driving circuitry of the pixel PX, included in the circuit element layer DP-CL, may include at least two transistor TRs and at least one capacitor. The number of transistor TRs and the number of capacitors can be varied in various ways depending on the design of the driving circuitry of the pixel PX. For example, the driving circuitry of the pixel PX may include two, three, four, five, six, seven, or more transistor TRs.

[0082] The display portion DA may include a light-emitting region PA corresponding to each pixel PX and a non-light-emitting region NPA surrounding the light-emitting region PA. The light-emitting element OLED may be disposed in the light-emitting region PA.

[0083] A buffer layer BFL is disposed on a first substrate SUB1, and the buffer layer BFL may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon (p-Si). However, the inventive concept is not limited thereto. For example, the semiconductor pattern may include amorphous silicon (a-Si) or a metal oxide. The metal oxide may include an oxide of at least one material selected from, for example, indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn).

[0084] The electrical properties of a semiconductor pattern can vary depending on whether it is doped. A semiconductor pattern can include doped and undoped regions. Doped regions can be doped with N-type or P-type dopants. For example, N-type dopants can include, for example, phosphorus (P), arsenic (As), or antimony (Sb), and P-type dopants can include, for example, aluminum (Al), boron (B), or indium (In). Doped regions have higher conductivity than undoped regions and can essentially serve as the source and drain electrodes of a transistor TR. Undoped regions can essentially correspond to the active region (or channel region) of a transistor TR.

[0085] The source region S, active region A, and drain region D of transistor TR can be formed from a semiconductor pattern. A first electrically insulating layer INS1 can be disposed on the semiconductor pattern. The gate electrode G of transistor TR can be disposed on the first electrically insulating layer INS1. A second electrically insulating layer INS2 can be disposed on the gate electrode G. A third electrically insulating layer INS3 can be disposed on the second electrically insulating layer INS2.

[0086] The connecting electrode CNE can be disposed between the transistor TR and the light-emitting element OLED to connect the transistor TR and the light-emitting element OLED. The connecting electrode CNE may include a first connecting electrode CNE1 and a second connecting electrode CNE2.

[0087] A first connecting electrode CNE1 is disposed on a third electrically insulating layer INS3 and can be connected to the drain region D through a first contact hole CH1 defined in the first electrically insulating layers INS1 to INS3. A fourth electrically insulating layer INS4 can be disposed on the first connecting electrode CNE1. A fifth electrically insulating layer INS5 can be disposed on the fourth electrically insulating layer INS4. A second connecting electrode CNE2 can be disposed on the fifth electrically insulating layer INS5. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through a second contact hole CH2 defined in the fourth electrically insulating layer INS4 and the fifth electrically insulating layer INS5.

[0088] A sixth electrically insulating layer INS6 can be disposed on the second connecting electrode CNE2. The layer from the buffer layer BFL to the sixth electrically insulating layer INS6 can be defined as a circuit element layer DP-CL. The first electrically insulating layer INS1 to the sixth electrically insulating layer INS6 can be inorganic or organic layers. In an exemplary embodiment of the present invention, the first electrically insulating layer INS1 to the sixth electrically insulating layer INS6 can each comprise an inorganic electrically insulating layer such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), or can comprise an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyl disiloxane (HMDSO), or phenolic resin.

[0089] A first electrode AE ​​can be disposed on the sixth electrical insulating layer INS6. The first electrode AE ​​can be connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the sixth electrical insulating layer INS6. A pixel defining film PDL exposing a predetermined portion of the first electrode AE ​​can be disposed on the first electrode AE ​​and the sixth electrical insulating layer INS6. An opening PX_OP for exposing the predetermined portion of the first electrode AE ​​can be defined on the pixel defining film PDL.

[0090] The hole control layer HCL can be disposed on the first electrode AE ​​and the pixel defining film PDL. The hole control layer HCL can be disposed together in the light-emitting region PA and the non-light-emitting region NPA, and can include a hole transport layer and a hole injection layer.

[0091] The luminescent layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (PX_OP) and can include organic and / or inorganic materials. In an exemplary embodiment of the present invention, the EML can include a fluorescent or phosphorescent material. The EML can generate a first light. The first light can be blue light.

[0092] The electronic control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL can be disposed together in the light-emitting region (PA) and the non-light-emitting region (NPA), and can include an electron transport layer and an electron injection layer.

[0093] The second electrode CE can be disposed on the electronic control layer ECL and can be disposed together in the pixel PX. The layer in which the light-emitting element OLED is disposed can be defined as a display element layer DP-OLED. For example, the layer from the first electrode AE ​​to the second electrode CE can be defined as a display element layer DP-OLED.

[0094] A thin-film encapsulation layer (TFE) can be disposed on the second electrode (CE) to cover the pixel (PX). The thin-film encapsulation layer (TFE) may include a first encapsulation layer (EN1) disposed on the second electrode (CE), a second encapsulation layer (EN2) disposed on the first encapsulation layer (EN1), and a third encapsulation layer (EN3) disposed on the second encapsulation layer (EN2).

[0095] The first encapsulation layer EN1 and the third encapsulation layer EN3 can be inorganic layers, and the second encapsulation layer EN2 can be an organic layer. The first encapsulation layer EN1 and the third encapsulation layer EN3 can protect the pixel PX from moisture / oxygen. The second encapsulation layer EN2 can protect the pixel PX from foreign matter such as dust particles. In this exemplary embodiment, each of the first encapsulation layer EN1, the second encapsulation layer EN2, and the third encapsulation layer EN3 is shown as a single layer, but the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, at least one of the first encapsulation layer EN1, the second encapsulation layer EN2, and the third encapsulation layer EN3 can be provided as multiple layers.

[0096] A first voltage can be applied to the first electrode AE ​​via transistor TR, and a second voltage can be applied to the second electrode CE. Holes from the first electrode AE ​​(anode electrode) and electrons from the second electrode CE (cathode electrode) are injected into the light-emitting layer EML and recombine to form excitons. When the excitons transition to the ground state, the light-emitting element OLED can emit light.

[0097] Figure 6 This is an example illustrating the inclusion of Figure 3 The image shows a cross-sectional view of the display panel DP, which has a color filter layer (CFL) and a light conversion layer (LCL).

[0098] Illustratively, Figure 6 The diagram shows the circuit element layer DP-CL, the display element layer DP-OLED, the thin-film encapsulation layer TFE and the filler FL, as well as the color filter layer CFL and the light conversion layer LCL. Additionally, illustratively, in... Figure 6 In this paper, the transistor TR, which is disposed on the circuit element layer DP-CL, and the light-emitting element OLED, which is disposed on the display element layer DP-OLED, are omitted.

[0099] Reference Figure 6 The display portion DA may include a first light-emitting area PA1, a second light-emitting area PA2, a third light-emitting area PA3, and a non-light-emitting area NPA disposed around each of the first light-emitting area PA1, the second light-emitting area PA2, and the third light-emitting area PA3.

[0100] Figure 5 The luminescent region PA shown can be any one of the first luminescent region PA1, the second luminescent region PA2, and the third luminescent region PA3. The first luminescent region PA1, the second luminescent region PA2, and the third luminescent region PA3 can generate a first light L1. Illustratively, the first light L1 can be blue light.

[0101] The color filter layer CFL may include a first color filter CF1, a second color filter CF2, a third color filter CF3, a low-refractive layer LRL, and a first insulating layer IL1. Illustratively, although each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 is shown as one, in essence, each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be provided as multiples.

[0102] In an exemplary embodiment of the present invention, the light conversion layer (LCL) may include quantum dots. Quantum dots are particles having a crystal structure with a size of several nanometers to tens of nanometers and may comprise hundreds to thousands of atoms. When used in display devices, quantum dot fluorescent or phosphorescent materials can generate pure monochromatic red, green, and blue light. A desired wavelength range of light can be obtained by controlling the composition of the quantum dots (e.g., controlling the band gap of the quantum dots). On the other hand, even quantum dots comprising the same material may emit different wavelengths depending on the particle size of the quantum dots. Therefore, the color of the emitted light can be controlled according to the particle size of the quantum dots.

[0103] The light conversion layer LCL may include a first quantum dot layer QDL1, a second quantum dot layer QDL2, a light-transmitting layer LTL, a dam layer BNK, and a second insulating layer IL2. Illustratively, although each of the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL is shown as one, in practice, each of the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL may be provided as multiples.

[0104] A first color filter CF1, a second color filter CF2, and a third color filter CF3 may be disposed below the second substrate SUB2. When viewed in a plane, the first color filter CF1 may overlap with the first emitting region PA1, the second color filter CF2 may overlap with the second emitting region PA2, and the third color filter CF3 may overlap with the third emitting region PA3. The first color filter CF1 may include a red color filter for transmitting light in the red wavelength range. The second color filter CF2 may include a green color filter for transmitting light in the green wavelength range. The third color filter CF3 may include a blue color filter for transmitting light in the blue wavelength range.

[0105] A low-refractive-index layer (LRL) can be disposed below the second substrate SUB2 to cover the first color filter CF1, the second color filter CF2, and the third color filter CF3, and can have a refractive index lower than that of the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL. The LRL may include an organic layer and multiple scattering particles that can be disposed within the organic layer to scatter light. A first insulating layer IL1 can be disposed below the LRL and can be an inorganic layer.

[0106] The embankment layer BNK can be disposed below the first insulating layer IL1. When viewed in a plane, the embankment layer BNK can overlap with the non-luminous region NPA. An opening QOP can be defined on the embankment layer BNK that overlaps with the first luminous region PA1, the second luminous region PA2, and the third luminous region PA3. The embankment layer BNK can be black.

[0107] A first quantum dot layer (QDL1), a second quantum dot layer (QDL2), and a light-transmitting layer (LTL) can be disposed within the open-ended quantum dot plate (QOP). Therefore, when viewed on a plane, the first quantum dot layer (QDL1), the second quantum dot layer (QDL2), and the light-transmitting layer (LTL) can overlap with the first light-emitting region (PA1), the second light-emitting region (PA2), and the third light-emitting region (PA3), respectively. For example, the first quantum dot layer (QDL1) can overlap with the first light-emitting region (PA1), the second quantum dot layer (QDL2) can overlap with the second light-emitting region (PA2), and the light-transmitting layer (LTL) can overlap with the third light-emitting region (PA3).

[0108] The second insulating layer IL2 can be disposed below the embankment layer BNK, the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL. The second insulating layer IL2 can be an inorganic layer.

[0109] The first light L1 generated in the first emitting region PA1, the second emitting region PA2, and the third emitting region PA3 can be provided to the first quantum dot layer QDL1, the second quantum dot layer QDL2, and the light-transmitting layer LTL, respectively. For example, the first light L1 generated in the first emitting region PA1 can be provided to the first quantum dot layer QDL1, and the first light L1 generated in the second emitting region PA2 can be provided to the second quantum dot layer QDL2. The first light L1 generated in the third emitting region PA3 can be provided to the light-transmitting layer LTL.

[0110] The first quantum dot layer QDL1 can convert a first light L1 into a second light L2. The second quantum dot layer QDL2 can convert the first light L1 into a third light L3. Illustratively, the second light L2 can be red light, and the third light L3 can be green light. The first quantum dot layer QDL1 may include a first quantum dot, and the second quantum dot layer QDL2 may include a second quantum dot. The light-transmitting layer LTL may include light-scattering particles.

[0111] The first quantum dot can convert a first light L1 with a blue wavelength band into a second light L2 with a red wavelength band. The second quantum dot can convert the first light L1 with a blue wavelength band into a third light L3 with a green wavelength band. The first and second quantum dots can scatter the second light L2 and the third light L3. In an exemplary embodiment of the present invention, the first and second quantum dots can each have a full width at half maximum (FWHM) of a spectrum with an emission wavelength of approximately 45 nm or less, approximately 40 nm or less, or approximately 30 nm or less. When the FWHM of each of the first and second quantum dots is within this range, color purity or color reproducibility can be improved. In addition, since the light emitted by each of the first and second quantum dots is emitted in all directions, the optical viewing angle can be improved.

[0112] The light-transmitting layer LTL can transmit first light L1 without performing a light conversion operation. First light L1 can be scattered and emitted by light-scattering particles in the light-transmitting layer LTL. In this case, the amount of unconverted light emitted through the light-transmitting layer LTL is greater than the amount of color-converted light emitted through the first quantum dot layer QDL1 and the second quantum dot layer QDL2. Light-scattering particles can be included in at least one of the first quantum dot layer QDL1 and the second quantum dot layer QDL2.

[0113] The first quantum dot layer QDL1 can emit a second light L2, the second quantum dot layer QDL2 can emit a third light L3, and the light-transmitting layer LTL can emit a first light L1. Therefore, a predetermined image can be displayed by displaying the second light L2, the third light L3, and the first light L1 in red, green, and blue, respectively.

[0114] The first light L1, the second light L2, and the third light L3 can be provided to the user via transmission through the first color filter CF1, the second color filter CF2, the third color filter CF3, and the second substrate SUB2. The first light L1, the second light L2, and the third light L3 are refracted in the low-refractive layer LRL and can then be further scattered by scattering particles disposed in the low-refractive layer LRL.

[0115] A portion of the first light L1 can be transmitted through the first quantum dot layer QDL1 without being converted by the first quantum dots and provided to the first color filter CF1. That is, there may be a portion of the first light L1 that does not come into contact with the first quantum dots and is therefore not converted into the second light L2. The first color filter CF1 can block light of different colors. For example, the first color filter CF1 can block light that is not in the red wavelength range. The first light L1 that is not converted in the first quantum dot layer QDL1 can be blocked in the first color filter CF1 with a red color filter and thus not emitted to the upper part.

[0116] A portion of the first light L1 can be transmitted through the second quantum dot layer QDL2 without being converted by the second quantum dots and provided to the second color filter CF2. That is, there may be first light L1 that does not come into contact with the second quantum dots and is therefore not converted into third light L3. The second color filter CF2 can block light of different colors. For example, the second color filter CF2 can block light that is not in the green wavelength range. The first light L1 that is not converted in the second quantum dot layer QDL2 can be blocked in the second color filter CF2, which has a green color filter, and thus not emitted to the upper part.

[0117] External light can be provided to the display device DD (see Figure 1 The external light is the display panel DP located above the display panel DP. The external light can be white light. White light can include red, green, and blue light. When the first color filter CF1, the second color filter CF2, and the third color filter CF3 are not used, the external light can be provided to the external user as is after being reflected by a metal layer (e.g., wiring) located inside the display panel DP. In this case, similar to light reflected from a mirror, the external light will be visible to the user.

[0118] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can prevent the reflection of external light. For example, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can filter external light into red, green, and blue, respectively.

[0119] Green and blue light from the external light supplied to the first color filter CF1 can be blocked in the first color filter CF1, which includes a red color filter. Therefore, the external light supplied to the first color filter CF1 can be filtered by the first color filter CF1 to be the same red light emitted from the first quantum dot layer QDL1. Thus, the external light reflected by the metal layer may be indistinguishable from the light emitted from the first quantum dot layer QDL1, and therefore may be invisible to the user.

[0120] Red and blue light from the external light supplied to the second color filter CF2 can be blocked in the second color filter CF2, which acts as a green color filter. Therefore, the external light supplied to the second color filter CF2 can be filtered by the second color filter CF2 into the same green light emitted from the second quantum dot layer QDL2. Thus, the external light reflected by the metal layer may be indistinguishable from the light emitted from the second quantum dot layer QDL2, and therefore may be invisible to the user.

[0121] Red and green light from the external light supplied to the third color filter CF3 can be blocked in the third color filter CF3, which acts as a blue color filter. Therefore, the external light supplied to the third color filter CF3 can be filtered by the third color filter CF3 into the same blue light emitted from the light-transmitting layer LTL. Thus, the external light reflected by the metal layer may be indistinguishable from the light emitted from the light-transmitting layer LTL, and therefore may be invisible to the user. Therefore, the external light is blocked in the first color filter CF1, the second color filter CF2, and the third color filter CF3, thereby reducing the reflection of external light.

[0122] A black embankment layer (BNK) can block unwanted light in the non-luminescent area (NPA). In an exemplary embodiment of the present invention, the embankment layer (BNK) may comprise a metal film, or may comprise an inorganic film or organic resin film containing a black dye or black pigment. For example, the embankment layer (BNK) can prevent color mixing of the first light L1, the second light L2, and the third light L3.

[0123] Figure 7 It is shown that... Figure 3 The image shows a cross-sectional view of a portion of the non-display portion NDA and the display panel DP that overlaps with the adjacent display portion DA.

[0124] Figure 7An exemplary illustration shows a pixel PX, a first color filter CF1, and a first quantum dot layer QDL1 adjacent to the non-display portion NDA. However, the inventive concept is not limited thereto. For example, a second color filter CF2 and a second quantum dot layer QDL2 may be provided on the display portion DA adjacent to the non-display portion NDA, or a third color filter CF3 and a light-transmitting layer LTL may be provided.

[0125] Reference Figure 7 In the display portion DA, the buffer layer BFL and the first electrically insulating layers INS1 to INS5 disposed on the first substrate SUB1 can extend to the first substrate SUB1 located in the non-display portion NDA. A sixth electrically insulating layer INS6 and a pixel defining film PDL can be disposed on the display portion DA. The pad PD can be disposed on the fifth electrically insulating layer INS5. When viewed in a planar plane, the second substrate SUB2 may not overlap with the pad PD. For example, the pad PD can be positioned on the side of the first substrate SUB1 located on the non-display portion NDA. The pad PD is exposed and not covered by any electrically insulating layer, and the pad PD can be connected to the flexible printed circuit board FPCB (see [link to FPCB]). Figure 4 ).

[0126] Pixel PX is disposed between the first substrate SUB1 and the second substrate SUB2, and the first quantum dot layer QDL1 may be disposed between the second substrate SUB2 and the pixel PX. A first color filter CF1 may be disposed between the second substrate SUB2 and the first quantum dot layer QDL1.

[0127] The display panel DP may include a plurality of dams DM1 and DM2 disposed on the non-display portion NDA, and a support layer SUP also disposed on the non-display portion NDA. Dams DM1 and DM2 and the support layer SUP are disposed on a fifth electrical insulating layer INS5 and may be spaced apart from each other. Dams DM1 and DM2 may include a first dam DM1 and a second dam DM2 spaced apart from each other. The first dam DM1 may be more adjacent to the display portion DA than the second dam DM2. For example, the first dam DM1 may be disposed between the second dam DM2 and the display portion DA. The support layer SUP may be more adjacent to the edge of the first substrate SUB1 than the first dam DM1 and the second dam DM2. For example, the support layer SUP may be disposed between the edge of the second dam DM2 and the first substrate SUB1. On the non-display portion NDA, the first dam DM1 may be spaced apart from the second dam DM2, and the first dam DM1 and the second dam DM2 each surround the display portion DA.

[0128] Each of the first dam DM1 and the second dam DM2 may include multiple layers stacked on top of each other. For example, the first dam DM1 may include two layers, and the second dam may include three layers. However, the layers constituting the first dam DM1 and the second dam DM2 are not limited thereto, and the number of layers and the materials of the layers may vary. Illustratively, the height of the second dam DM2 may be greater than the height of the first dam DM1, but the heights of the second dam DM2 and the first dam DM1 are not limited thereto.

[0129] The thin-film encapsulation layer TFE, disposed on the display portion DA to cover the pixel PX, can extend toward the non-display portion NDA to overlap with it. The thin-film encapsulation layer TFE can be disposed on the fifth electrically insulating layer INS5 to cover the first dam DM1 and the second dam DM2. The thin-film encapsulation layer TFE can be adjacent to the support layer SUP and can contact the side surfaces of the support layer SUP facing the first dam DM1 and the second dam DM2. However, the inventive concept is not limited thereto. For example, the thin-film encapsulation layer TFE can be spaced apart from the side surfaces of the support layer SUP.

[0130] The first encapsulation layer EN1 disposed on pixel PX can extend toward the non-display portion NDA to overlap with it. The first encapsulation layer EN1 disposed on the non-display portion NDA can be disposed on the fifth electrical insulating layer INS5 and the first dam DM1 and the second dam DM2. For example, the first encapsulation layer EN1 can be disposed on the fifth electrical insulating layer INS5 to cover the first dam DM1 and the second dam DM2.

[0131] When viewed on a flat surface, the second encapsulation layer EN2 can be disposed on the first encapsulation layer EN1 by overlapping with the display portion DA. The first dam DM1 and the second dam DM2 can separate the formation area of ​​the second encapsulation layer EN2 containing organic material. The flowing organic material can be cured to form the second encapsulation layer EN2. Even when the flowing organic material flows towards the non-display portion NDA, the organic material is blocked by the first dam DM1. Therefore, the second encapsulation layer EN2 can be positioned up to the first dam DM1. The second dam DM2 can also block organic material overflowing from the first dam DM1. For example, the second dam DM2 can be higher than the first dam DM1. Since the height of the second dam DM2 is higher than the height of the first dam DM1, overflow of the second encapsulation layer EN2 across the second dam DM2 to create an edge tail can be prevented.

[0132] A third encapsulation layer EN3 may be disposed on the first encapsulation layer EN1 to cover the second encapsulation layer EN2. The first encapsulation layer EN1 and the third encapsulation layer EN3 may contact each other on the non-display portion NDA to be adjacent to the support layer SUP. The first encapsulation layer EN1 may directly contact the third encapsulation layer EN3 outside the second dam DM2 to prevent external moisture or impurities from propagating into the display device through the second encapsulation layer EN2, which is an organic material. The first encapsulation layer EN1 and the third encapsulation layer EN3, which are in contact with each other, may contact the side surface of the support layer SUP, but the inventive concept is not limited thereto. For example, the first encapsulation layer EN1 and the third encapsulation layer EN3 may be spaced apart from the side surface of the support layer SUP.

[0133] The embankment layer BNK disposed around the first quantum dot layer QDL1 can extend toward the edge of the second substrate SUB2 and can be disposed below the second substrate SUB2. Therefore, when viewed in a plane, the embankment layer BNK can overlap with the non-display portion NDA.

[0134] The display panel DP may include multiple dummy color filters DCF1 and DCF2 of different colors stacked on top of each other. The light blocking layer LSL may include a embankment layer BNK overlapping the dummy color filters DCF1 and DCF2 and the non-display portion NDA. For example, the embankment layer BNK and the dummy color filters DCF1 and DCF2 may form the light blocking layer LSL over the non-display portion NDA of the first substrate SUB1.

[0135] Dummy color filters DCF1 and DCF2 can be disposed between the embankment layer BNK and the second substrate SUB2, and when viewed in a plane, dummy color filters DCF1 and DCF2 can overlap with the non-display portion NDA. Dummy color filters DCF1 and DCF2 can include a first dummy color filter DCF1 disposed below the second substrate SUB2 and a second dummy color filter DCF2 disposed below the first dummy color filter DCF1.

[0136] Illustratively, two dummy color filters, DCF1 and DCF2, are shown, but the number of dummy color filters is not limited to this. Illustratively, the first dummy color filter DCF1 may include the same blue color filter as the third color filter CF3. Additionally, the second dummy color filter DCF2 may include the same red color filter as the first color filter CF1. The first dummy color filter DCF1 and the second dummy color filter DCF2 may have a function similar to that of the first color filter CF1 and the third color filter CF3 in preventing external light reflection. In an exemplary embodiment of the inventive concept, in addition to the first dummy color filter DCF1 and the second dummy color filter DCF2, a third dummy color filter may be provided between the embankment layer BNK and the second substrate SUB2, the third dummy color filter having a function similar to that of the second color filter CF2 in preventing external light reflection.

[0137] The low-refractive-index layer LRL extends toward the edge of the second substrate SUB2, and when viewed in a plane, the low-refractive-index layer LRL can overlap with the non-display portion NDA. The low-refractive-index layer LRL can be disposed below the second substrate SUB2 to cover the first dummy color filter DCF1 and the second dummy color filter DCF2.

[0138] The first insulating layer IL1 may extend toward the edge of the second substrate SUB2 and may be disposed below the low-refractive layer LRL. The second insulating layer IL2 may extend toward the edge of the second substrate SUB2 and may be disposed below the embankment layer BNK. The low-refractive layer LRL, the first insulating layer IL1, and the second insulating layer IL2 may extend to the edge of the second substrate SUB2.

[0139] The sealant SAL can be disposed between the thin-film encapsulation layer TFE and the embankment layer BNK in the non-display portion NDA. For example, the sealant SAL can be disposed between the second insulating layer IL2 and the thin-film encapsulation layer TFE in the non-display portion NDA. Multiple spherical spacers BSP can be disposed in the sealant SAL to enhance its support strength. The spherical spacers BSP can comprise organic or inorganic materials.

[0140] The sealant SAL can be disposed on the thin-film encapsulation layer TFE. For example, the sealant SAL can be disposed on the first encapsulation layer EN1 and the third encapsulation layer EN3 that are in contact with each other. For example, the sealant SAL can overlap with the first encapsulation layer EN1 and the third encapsulation layer EN3 on the third-direction DR3 and can be in direct contact with the third encapsulation layer EN3. The sealant SAL can be disposed between the second dam DM2 and the support layer SUP. The second dam DM2 can be disposed between the sealant SAL and the first dam DM1. The support layer SUP can be disposed between the edge of the first substrate SUB1 and the sealant SAL.

[0141] When viewed in a plane, the edges of the embankment layer BNK and the edges of the first dummy color filter DCF1 and the second dummy color filter DCF2 adjacent to the edge of the embankment layer BNK can be positioned between the edge of the second substrate SUB2 and the sealant SAL. For example, the sealant SAL can overlap with the first dummy color filter DCF1, the second dummy color filter DCF2, and the embankment layer BNK on the third-direction DR3. The edges of the embankment layer BNK and the edges of the first dummy color filter DCF1 and the second dummy color filter DCF2 can be more adjacent to the sealant SAL than the edge of the second substrate SUB2. The second insulating layer IL2 can be positioned below the first insulating layer IL1 to cover the embankment layer BNK. For example, the sealant SAL can be in direct contact with the second insulating layer IL2.

[0142] The filler FL is disposed between the pixel PX and the first quantum dot layer QDL1, and may extend toward the non-display portion NDA to overlap with it. The filler FL may be disposed between the second insulating layer IL2 and the third encapsulation layer EN3, and may cover the first dam DM1 and the second dam DM2. The sealant SAL may contact the filler FL. For example, the sealant SAL may be positioned on the non-display portion NDA and may surround the display portion DA, with the filler FL filling the space surrounded by the sealant SAL. This space may cover the entire display portion DA and a portion of the non-display portion NDA.

[0143] In one example, the sealant SAL is disposed at a periphery further outward than the support layer SUP, and the first dummy color filter DCF1 and the second dummy color filter DCF2, the embankment layer BNK, the first insulating layer IL1 and the second insulating layer IL2, and the low-refractive layer LRL may not be disposed between the second substrate SUB2 and the sealant SAL. Therefore, the sealant SAL can directly contact the second substrate SUB2.

[0144] When the first substrate SUB1 and the second substrate SUB2 are joined together by the sealant SAL, the second substrate SUB2 can compress the sealant SAL in a downward direction by the pressure applied to the second substrate SUB2. When the sealant SAL is insufficient to support the second substrate SUB2, the sealant SAL may contract due to the pressure.

[0145] When the sealant SAL shrinks, the gap between the first substrate SUB1 and the second substrate SUB2 that overlap with the sealant SAL may be smaller than the gap between the first substrate SUB1 and the second substrate SUB2 that overlap with the display portion DA. Therefore, the gap between the first substrate SUB1 and the second substrate SUB2 may not remain constant.

[0146] In an exemplary embodiment of the present invention, multiple layers, such as a first dummy color filter DCF1 and a second dummy color filter DCF2, a embankment layer BNK, a first insulating layer IL1 and a second insulating layer IL2, and a low-refractive-index layer LRL, can be provided beneath a second substrate SUB2, and a sealant SAL can be disposed beneath these multiple layers. When the first substrate SUB1 and the second substrate SUB2 are joined together, the multiple layers and the sealant SAL can firmly support the second substrate SUB2 together, even when a predetermined pressure is applied to the second substrate SUB2. That is, the portion of the display panel DP that overlaps with the sealant SAL can become more robust. Therefore, the sealant SAL will not shrink.

[0147] Because shrinkage of the sealant SAL is prevented, the difference between the gap between the first substrate SUB1 and the second substrate SUB2 overlapping with the sealant SAL and the gap between the first substrate SUB1 and the second substrate SUB2 overlapping with the display portion DA can be reduced. As a result, the gap between the first substrate SUB1 and the second substrate SUB2 can be kept more constant. Furthermore, according to an exemplary embodiment of the present invention, since multiple layers such as the first dummy color filter DCF1 and the second dummy color filter DCF2, the embankment layer BNK, the first insulating layer IL1 and the second insulating layer IL2, and the low refractive layer LRL provided under the second substrate SUB2 extend from the position overlapping with the display portion DA to the position overlapping with the non-display portion NDA by providing the sealant SAL beneath these multiple layers, a constant gap between the first substrate SUB1 and the second substrate SUB2 from the position overlapping with the display portion DA to the position overlapping with the sealant SAL can be maintained even when the second substrate SUB2 is under pressure, due to the continuity of the multiple layers providing a uniform structure.

[0148] When an inorganic layer is further added, moisture penetration can be further prevented. Below the sealant SAL, a first encapsulation layer EN1 and a third encapsulation layer EN3, including the inorganic layer, can be provided. Therefore, moisture penetration can be further prevented through the first encapsulation layer EN1 and the third encapsulation layer EN3.

[0149] Figure 7 This can be a cross-section of the non-display portion of NDA containing pads (PD). The cross-section of the non-display portion of NDA without pads (PD) can be... Figure 7 The same. For example, the non-display portion of the NDA is the same as... Figure 3 The left, right, and top adjacent sections of the display panel DP in the middle can be connected with... Figure 7 same.

[0150] Figure 8 It is used to describe Figure 7 The view shown illustrates the functionality of the support layer SUP.

[0151] Reference Figure 8 You can use the method to form a pixel PX (see Figure 5 The second electrode CE (see) Figure 5 The mask MSK can be disposed on the support layer SUP. The support layer SUP can support the mask MSK. The support layer SUP can be formed of the same material as the sixth electrical insulating layer INS6, and can be formed in the same process as forming the sixth electrical insulating layer INS6, but the material of the support layer SUP is not limited to this.

[0152] The mask MSK can be disposed on the first substrate SUB1 by being supported by the support layer SUP. Within the mask MSK, an opening MOP can be defined that overlaps with the display portion DA. The opening MOP can be used to provide a second electrode CE for formation on the electronic control layer ECL (see [link to documentation]). Figure 5 The material MAL is used to form the second electrode CE by deposition using a mask MSK (see [reference]). Figure 5 In the material MAL process, the support layer SUP can maintain the spacing between the mask MSK and the first substrate SUB1, which has multiple electrical insulating layers, to prevent the second electrode CE (see...) Figure 5 During the deposition process, it is cut or torn by the mask MSK.

[0153] Illustratively, the method for forming the second electrode CE is described (see [link]). Figure 5 The mask MSK is used to form the pixel PX (see [link]). Figure 5 The masks for other layers can be supported by a support layer SUP. For example, a mask MSK can be used to form a hole control layer HCL, an electron control layer ECL, and / or a light-emitting layer EML.

[0154] Figure 9 It is shown that... Figure 4 The image shows a view of the second power line PL2, the first control line CSL1, and some data lines DL1 and DL2 overlapping with the sealant SAL.

[0155] Illustratively, Figure 9 The diagram shows the planar view of the sealant SAL, second power line PL2, first control line CSL1, and data lines DL1 and DL2 as viewed from a third party to DR3. Hereinafter, the second power line PL2, the first control line CSL1, and the data lines DL1 and DL2 are referred to as signal lines.

[0156] Reference Figure 9Signal lines PL2, CSL1, DL1, and DL2 can be positioned on the first substrate SUB1 and below the sealant SAL. Multiple openings OP can be defined in some signal lines PL2, CSL1, DL1, and DL2 that overlap with the sealant SAL. Other data lines such as DL3 (not shown) to DLn (see...) can also be... Figure 4 Multiple openings OP that overlap with sealant SAL are defined in the signal lines of the first power line PL1 and the second control line CSL2.

[0157] Sealant SAL can include ultraviolet (UV) light-curable materials. (See reference...) Figure 7 and Figure 9 The sealant SAL is disposed between the first substrate SUB1 and the second substrate SUB2, and ultraviolet light for curing the sealant SAL can then irradiate the sealant SAL from below the first substrate SUB1. Signal lines PL1, PL2, CSL1, CSL2, DL1 to DLn (see...) Figure 4 It can block ultraviolet light.

[0158] In an exemplary embodiment of the present invention, the opening OP overlapping with the sealant SAL is defined on signal lines PL1, PL2, CSL1, CSL2, DL1 to DLn (see...). Figure 4 In this configuration, ultraviolet light can be further supplied to the sealant SAL through the opening OP. Therefore, the sealant SAL can cure more easily.

[0159] Figures 10 to 14 This is a cross-sectional view showing the non-display portion NDA of display panels DP_1 to DP_4, each according to an exemplary embodiment of the present invention. Figures 10 to 14 In each of the components, a plurality of layers are provided beneath the second substrate SUB2, including a first dummy color filter DCF1 and a second dummy color filter DCF2, a embankment layer BNK, a first insulating layer IL1 and a second insulating layer IL2, and a low refractive index layer LRL, and a sealant SAL is disposed beneath the plurality of layers. When the first substrate SUB1 and the second substrate SUB2 are joined together, the plurality of layers and the sealant SAL can together firmly support the second substrate SUB2 even when a predetermined pressure is applied to the second substrate SUB2.

[0160] Illustratively, Figures 10 to 14 It shows the relationship with Figure 7 The corresponding cross-section. In the following text, the focus is on... Figure 7 The different configurations shown will describe Figures 10 to 14 The configuration is shown in the figure, and the same components are indicated using the same reference numerals.

[0161] Reference Figure 10The sealant SAL of the display panel DP_1 can be disposed between the support layer SUP and the second dam DM2, and can be formed between the second insulating layer IL2 and the third encapsulation layer EN3. The sealant SAL does not contact the filler FL and can be spaced apart from the filler FL.

[0162] Reference Figure 11 When viewed on a flat surface, the edge of the low-refractive-index layer LRL of the display panel DP_2 can be positioned between the edge of the second substrate SUB2 and the sealant SAL. The sealant SAL of the display panel DP_2 can be positioned between the support layer SUP and the second dam DM2, and can be formed between the second insulating layer IL2 and the third encapsulation layer EN3. The edge of the low-refractive-index layer LRL can be more adjacent to the sealant SAL than the edge of the second substrate SUB2.

[0163] The first insulating layer IL1 can be disposed below the second substrate SUB2 by being spaced apart from the edge of the second substrate SUB2 to cover the low refractive index layer LRL. The second insulating layer IL2 can be disposed below the second substrate SUB2 by being spaced apart from the edge of the second substrate SUB2 to cover the embankment layer BNK and the first insulating layer IL1.

[0164] The first insulating layer IL1, the second insulating layer IL2, and the low-refractive layer LRL may not be configured to extend to the edge of the second substrate SUB2. Figure 7 The structure shown is different, which can reduce the area where the low-refractive-index layer (LRL) is located. The first insulating layer IL1 and the second insulating layer IL2, which are inorganic layers, can cover the low-refractive-index layer (LRL), which is an organic layer. Therefore, external moisture that may be injected through the low-refractive-index layer (LRL) can be blocked by the first insulating layer IL1 and the second insulating layer IL2.

[0165] Reference Figure 12 The support layer SUP, located on the non-display portion NDA of the display panel DP_3, can be adjacent to the second dam DM2. The thin-film encapsulation layer TFE can be adjacent to the support layer SUP.

[0166] The sealant SAL, located on the non-display portion NDA, can be positioned further outwards from the support layer SUP. That is, the sealant SAL can be positioned between the edge of the first substrate SUB1 and the support layer SUP. Figure 7 The structure shown differs from the one depicted; the sealant SAL may not be disposed on the thin-film encapsulation layer TFE, and may be formed between the second insulating layer IL2 and the fifth electrical insulating layer INS5. The sealant SAL does not contact the filler FL and may be spaced apart from the filler FL.

[0167] Reference Figure 13Multiple support layers SUP1, SUP2 and SUP3 can be set on the non-display portion NDA of the display panel DP_4. Figure 8 The mask MSK shown can be set on the support layers SUP1, SUP2 and SUP3. Figure 13 The cross-section shown can be a cross-section of the non-display portion NDA of the display panel DP_4, where no pads PD are provided. For example, Figure 13 The cross-section of the display panel DP_4 shown in the figure can be the same as that of the display panel DP_4 shown in the figure. Figure 4 The cross-sections of the left and right sides of the display panel DP and the adjacent non-display portion NDA on the top side.

[0168] Support layers SUP1, SUP2, and SUP3 may include a first support layer SUP1, a second support layer SUP2, and a third support layer SUP3. The first support layer SUP1 may be adjacent to the sealant SAL. The sealant SAL may be disposed on the thin-film encapsulation layer TFE between the first support layer SUP1 and the display portion DA. For example, the sealant SAL of the display panel DP_4 may be formed between the second insulating layer IL2 and the third encapsulation layer EN3. The third support layer SUP3 may be adjacent to the edge of the first substrate SUB1. The second support layer SUP2 may be disposed between the first support layer SUP1 and the third support layer SUP3.

[0169] A thin-film encapsulation layer (TFE) adjacent to the first support layer (SUP1) can be further disposed on the first support layer (SUP1). For example, when the first encapsulation layer (EN1) and the third encapsulation layer (EN3) are deposited on the first substrate (SUB1), the first encapsulation layer (EN1) and the third encapsulation layer (EN3) can be further deposited on the first support layer (SUP1). Therefore, the first encapsulation layer (EN1) and the third encapsulation layer (EN3) can be disposed on the non-display portion (NDA) to cover the first support layer (SUP1). The second support layer (SUP2) and the third support layer (SUP3) can be spaced apart from the first encapsulation layer (EN1) and the third encapsulation layer (EN3).

[0170] Reference Figure 13 and Figure 14 The first substrate SUB1 and the second substrate SUB2 are bonded together using a sealant SAL, and then the portions adjacent to the edges of the first substrate SUB1 and the second substrate SUB2 can be cut and polished. For example, the first substrate SUB1 and the second substrate SUB2 can be cut and polished along a cut line CL that overlaps with the end of the second support layer SUP2 facing the first support layer SUP1. The cutting process can be performed first, and then the polishing process can be performed.

[0171] In an exemplary embodiment of the present invention, a single support layer is disposed on the non-display portion NDA, and a first encapsulation layer EN1 and a third encapsulation layer EN3 may be disposed on the non-display portion NDA to cover the single support layer. In this case, cutting and polishing processes are performed only on the portion adjacent to the single support layer, and the polishing tool contacts the first encapsulation layer EN1 and the third encapsulation layer EN3, thereby causing damage to the first encapsulation layer EN1 and the third encapsulation layer EN3.

[0172] In an exemplary embodiment of the present invention, the second support layer SUP2 can provide reference lines for performing cutting and polishing processes thereon. Since the cutting and polishing processes are performed along the second support layer SUP2, which is spaced apart from the first encapsulation layer EN1 and the third encapsulation layer EN3, the polishing tool will not come into contact with the first encapsulation layer EN1 and the third encapsulation layer EN3. Therefore, damage to the first encapsulation layer EN1 and the third encapsulation layer EN3 can be prevented. For example, after polishing, the edges of the thin-film encapsulation layers TFE (e.g., the first encapsulation layer EN1 and the third encapsulation layer EN3) can be adjacent to and spaced apart from the edges of the first substrate SUB1, and can be disposed between the edges of the first substrate SUB1 and the first support layer SUP1.

[0173] Illustratively, the cutting and polishing process is performed along the second support layer SUP2, but the inventive concept is not limited thereto. For example, the cutting and polishing process can be performed along the third support layer SUP3.

[0174] According to an exemplary embodiment of the present invention, a plurality of layers such as a dummy color filter, a low-refractive layer, an insulating layer, and a embankment layer are provided under the second substrate, and a sealant is disposed under the plurality of layers, such that the gap between the first substrate and the second substrate can be kept more constant.

[0175] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. Although the inventive concept has been described with reference to exemplary embodiments thereof, those skilled in the art will understand that various modifications and changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A display device, wherein, The display device includes: A first substrate, the first substrate including a display portion and a non-display portion located around the display portion; A second substrate, wherein the second substrate is disposed on the first substrate; A pixel, wherein the pixel is disposed between the display portion and the second substrate; A quantum dot layer, when viewed in a plane, overlaps with the display portion, and the quantum dot layer is disposed between the second substrate and the pixel; A embankment layer is disposed around the quantum dot layer and overlaps with the non-display portion when viewed in the plane; A color filter disposed between the second substrate and the quantum dot layer; A dummy color filter, when viewed on the plane, overlaps with the non-display portion and is disposed between the embankment layer and the second substrate; A sealant is disposed between the non-display portion and the embankment layer, and the sealant overlaps with the embankment layer and the dummy color filter. A support layer is disposed on the non-display portion; and A thin-film encapsulation layer is disposed on the display portion to cover the pixels and extend into the non-display portion, and when viewed in the plane, the thin-film encapsulation layer overlaps with the non-display portion. The sealant is completely disposed on the thin film encapsulation layer between the support layer and the display portion, and the thin film encapsulation layer is adjacent to the support layer.

2. The display device according to claim 1, wherein, The sealant includes a plurality of spherical spacers, and / or The portion of the thin-film encapsulation layer beneath the sealant is flat.

3. The display device according to claim 1, wherein, The support layer is disposed between the edge of the first substrate and the sealant.

4. The display device according to claim 3, wherein, The thin-film encapsulation layer includes: A first encapsulation layer is disposed on the pixel and extends toward the non-display portion, and when viewed in the plane, the first encapsulation layer overlaps with the non-display portion; A second encapsulation layer is disposed on the first encapsulation layer, and when viewed in the plane, the second encapsulation layer overlaps with the display portion; and A third encapsulation layer is disposed on the first encapsulation layer to cover the second encapsulation layer. The first encapsulation layer and the third encapsulation layer are in contact with each other on the non-display portion, so as to be adjacent to the support layer, and The sealant is applied to the first and third encapsulation layers that are in contact with each other.

5. The display device according to claim 3, wherein, The display device further includes: a dam disposed on the non-display portion. Wherein, the thin film encapsulation layer covers the dam, and The sealant is disposed between the dam and the support layer.

6. The display device according to claim 1, wherein, The display device further includes a filler disposed between the pixel and the quantum dot layer and extending toward the non-display portion, and overlapping the non-display portion when viewed on the plane.

7. The display device according to claim 6, wherein, The sealant comes into contact with the filler.

8. The display device according to claim 6, wherein, The sealant is spaced apart from the filler.

9. The display device according to claim 1, wherein, The display device further includes: A low-refractive-index layer is disposed beneath the second substrate to cover the color filter and the dummy color filter; A first insulating layer, wherein the first insulating layer is disposed beneath the low-refractive layer; and A second insulating layer is disposed beneath the embankment layer and the quantum dot layer. The sealant is disposed between the second insulating layer and the non-display portion.

10. The display device according to claim 9, wherein, When viewed on the plane, the edge of the embankment layer and the edge of the dummy filter adjacent to the edge of the embankment layer are positioned between the edge of the second substrate and the sealant, and are more adjacent to the sealant than the edge of the second substrate.

11. The display device according to claim 10, wherein, The low-refractive-index layer, the first insulating layer, and the second insulating layer extend to the edge of the second substrate, and The second insulating layer is disposed below the first insulating layer to cover the embankment layer.

12. The display device according to claim 10, wherein, When viewed on the plane, the edge of the low-refractive layer is disposed between the edge of the second substrate and the sealant, and is more adjacent to the sealant than to the edge of the second substrate.

13. The display device according to claim 12, wherein, The first insulating layer is disposed beneath the second substrate, spaced apart from the edge of the second substrate, and covers the low-refractive layer. The second insulating layer is disposed below the second substrate, spaced apart from the edge of the second substrate, and covers the embankment layer and the first insulating layer.

14. The display device according to claim 1, wherein, The display device further includes: a plurality of signal lines disposed on the first substrate and connected to the pixels. Multiple openings are defined in the portions of the multiple signal lines that overlap with the sealant.

15. The display device according to claim 1, wherein, The embankment layer is black.

16. The display device according to claim 1, wherein, The dummy color filter is provided as a plurality of dummy color filters, and the plurality of dummy color filters are deposited with different colors.

17. The display device according to claim 5, wherein, The dam surrounds the display section. The dam includes a first dam and a second dam, and each of the first dam and the second dam includes multiple layers stacked on top of each other.

18. The display device according to any one of claims 1 to 17, wherein, The thin-film encapsulation layer is disposed on the support layer.

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