Display device

Abstract

A display device includes a fan-out portion including a first fan-out portion including first conductive lines and a second fan-out portion including second conductive lines. The first conductive lines are spaced apart from each other by a first pitch in a bending area of a substrate of the display device. The second conductive lines are spaced apart from each other by a second pitch in the bending area.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0066705, filed on June 2, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to display devices with improved visibility. Background Technology

[0004] Organic light-emitting diode (OLED) displays are attracting attention as the next generation of display devices due to their wide viewing angle, excellent contrast ratio, and fast response speed.

[0005] Typically, organic light-emitting display devices can include thin-film transistors and organic light-emitting diodes (OLEDs) located on a substrate. OLEDs operate by emitting their own light. Such organic light-emitting display devices can be used in the display sections of small products such as mobile phones, or in the display sections of large products such as televisions.

[0006] Display devices, such as organic light-emitting display devices, may have a display portion located on a substrate and a fan-out portion in which lines can extend to one side of the display portion. At least a portion of such a display device may be flexible to improve visibility at various angles or reduce the area of ​​the non-display region.

[0007] It should be understood that this background section is intended to provide, in part, useful background for understanding the technology. However, this background section may also include ideas, concepts, or knowledge that were known or understood by a person skilled in the art prior to the corresponding valid application date, but do not constitute the subject matter disclosed herein. Summary of the Invention

[0008] One or more embodiments include a display device in which dead zones can be significantly reduced and emission uniformity between adjacent pixels can be improved. However, these problems are exemplary, and the scope of this disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows and will be apparent in part from the description, or may be understood by practice of the embodiments of the present disclosure presented.

[0010] According to an embodiment, the display device may include a substrate, the substrate including: a display area; and a non-display area including a first non-display area, a second non-display area, and a curved area disposed between the first non-display area and the second non-display area, the first non-display area being adjacent to the display area. The display device may further include a display portion disposed in the display area, a driving circuit disposed in the non-display area, and fan-out portions disposed in the first non-display area, the curved area, and the second non-display area. The first non-display area, the curved area, and the second non-display area may be disposed between the display portion and the driving circuit. The fan-out portions may deliver data signals applied from the driving circuit to the display portion. The fan-out portions may include a first fan-out portion including a first conductive line and a second fan-out portion including a second conductive line. The first conductive lines may be spaced apart by a first spacing in the curved area. The second conductive lines may be spaced apart by a second spacing in the curved area.

[0011] According to an embodiment, the first fan-out portion and the second fan-out portion can be spaced apart from each other in the curved region.

[0012] According to an embodiment, the first conductive line may include a first line to an nth line, and the second conductive line may include a first line to an mth line. Among the first lines to an nth line of the first conductive line and the first lines to an mth line of the second conductive line, the nth line of the first conductive line and the first line of the second conductive line may be arranged to be closest to each other.

[0013] According to an embodiment, the first spacing may be smaller than the second spacing.

[0014] According to an embodiment, the fan-out portion may include a third fan-out portion containing a third conductive line, and the third conductive lines may be spaced apart from each other by a third spacing in the curved region.

[0015] According to an embodiment, the third spacing can be greater than the first spacing.

[0016] According to an embodiment, the third spacing can be equal to the first spacing.

[0017] According to an embodiment, the third spacing may be smaller than the second spacing.

[0018] According to an embodiment, the third spacing can be equal to the second spacing.

[0019] According to an embodiment, in a plan view, the first conductive wire and the second conductive wire can be bent two or more times.

[0020] According to an embodiment, the first conductive wire and the second conductive wire may remain unbent in the bending region.

[0021] According to an embodiment, the portions of the first and second conductive lines arranged in the curved region may be arranged on different insulating films as the portions of the first and second conductive lines arranged in the first and second non-display regions, and the portions of the fan-out portion corresponding to the curved region may be arranged on different insulating films as the portions of the fan-out portion corresponding to the first and second non-display regions.

[0022] According to an embodiment, the display portion may include a thin-film transistor and a light-emitting element electrically connected to the thin-film transistor. The thin-film transistor may include a semiconductor layer, a gate electrode, and a connection electrode electrically connected to the semiconductor layer. The portion of the fan-out portion corresponding to the curved region may be made of the same material as the connection electrode, and the portion of the fan-out portion corresponding to the first non-display area and the second non-display area may be made of the same material as the gate electrode.

[0023] According to an embodiment, the display device may further include an insulating layer disposed on a substrate, wherein the insulating layer may include openings corresponding to the curved regions.

[0024] According to an embodiment, the display device may further include an organic insulating layer disposed in an opening in the insulating layer.

[0025] According to an embodiment, the portion of the fan-out section corresponding to the curved area can be arranged on an organic insulating layer.

[0026] According to an embodiment, the first conductive line and the second conductive line may include data lines.

[0027] According to another aspect of this disclosure, the display device may include a substrate, the substrate including a display area, a first non-display area adjacent to the display area, a second non-display area, and a curved area disposed between the first non-display area and the second non-display area. The display device may further include fan-out portions disposed in the first non-display area, the curved area, and the second non-display area, the fan-out portions including conductive lines, the conductive lines being disposed in the curved area with separating regions located between them. The conductive lines may be spaced apart from each other at different intervals.

[0028] According to an embodiment, the conductive lines arranged in the outer part of the fan-out portion can be spaced apart by a first gap, and the conductive lines arranged in the central part of the fan-out portion can be spaced apart by a second gap.

[0029] According to an embodiment, the first spacing may be smaller than the second spacing.

[0030] Other aspects, features, and advantages besides those described above will now become apparent from the accompanying drawings, claims, and detailed description of this disclosure below. Attached Figure Description

[0031] The above and other aspects, features and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a schematic perspective view of a display device according to an embodiment;

[0033] Figure 2 This is a schematic plan view of a display device according to an embodiment;

[0034] Figure 3 and Figure 4 This is a schematic equivalent circuit diagram of pixels in a display device according to an embodiment;

[0035] Figure 5 This is a schematic cross-sectional view of a display device according to an embodiment;

[0036] Figure 6 This is a schematic plan view of a display device according to an embodiment;

[0037] Figure 7 This is a schematic plan view of a display device according to an embodiment;

[0038] Figure 8 This is a schematic cross-sectional view of a display device according to an embodiment;

[0039] Figure 9 This is a schematic cross-sectional view of a display device according to an embodiment;

[0040] Figure 10 This is a schematic plan view of a display device according to an embodiment;

[0041] Figure 11 This is a schematic plan view of a display device according to an embodiment;

[0042] Figure 12 This is a schematic plan view of a display device according to an embodiment;

[0043] Figure 13 This is a schematic plan view of a display device according to an embodiment;

[0044] Figure 14 This is a schematic cross-sectional view of a display device according to an embodiment; and

[0045] Figure 15 This is a schematic cross-sectional view of a display device according to an embodiment. Detailed Implementation

[0046] Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, embodiments may have different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below with reference to the accompanying drawings only to explain aspects of the specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, “A and / or B” can be understood to mean “A, B, or A and B”. The terms “and” and “or” can be used in a combined or separate sense and can be understood as equivalent to “and / or”. Throughout the disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0047] Because this disclosure allows for various modifications and several embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of this disclosure, as well as methods of implementing them, will be apparent from the embodiments and drawings described in detail below. However, this disclosure may be embodied in many different forms and should not be construed as limiting itself to the embodiments set forth herein.

[0048] In the following embodiments, although terms such as “first” and “second” may be used to describe various elements, these elements are not necessarily limited to the terms described above.

[0049] In the following embodiments, singular expressions are used to cover plural expressions, unless they have a distinctly different meaning herein.

[0050] It should be understood that terms such as “comprising,” “including,” and “having” are intended to indicate the presence of a feature or element disclosed in this disclosure and are not intended to exclude the possibility that one or more other features or elements may be present or may be added.

[0051] It will be understood that when a layer, area, or component is referred to as being formed "on" another layer, area, or component, it can be formed directly or indirectly on that other layer, area, or component. For example, intermediate layers, areas, or components may exist.

[0052] For ease of illustration, the dimensions of the components in the accompanying drawings may be exaggerated. In other words, since the dimensions and thicknesses of the components in the accompanying drawings can be arbitrarily illustrated for ease of illustration, the following embodiments are not limited thereto.

[0053] In this disclosure, "A and / or B" may include "A", "B" or "A and B". In this disclosure, "at least one of A and B" may include "A", "B" or "A and B".

[0054] In the following disclosure, it will be understood that when wiring is referred to as “extending in a first direction or a second direction”, it can extend not only in a straight line shape, but also in a zigzag or curved shape in the first direction or the second direction.

[0055] In the following disclosure, a "plan view" indicates a portion of the target object viewed from above, and a "section view" indicates a portion of the target object cut perpendicularly and viewed from the side. In the following disclosure, the term "overlap" includes overlapping in a plan view or section view. The term "overlap" can include layering, stacking, facing, extending above, extending below, covering, or partially covering, or any other suitable term as understood and appreciated by one of ordinary skill in the art. The expression "non-overlap" can include spaced apart, positioned next to, or offset, and any other suitable equivalent as understood and appreciated by one of ordinary skill in the art.

[0056] Unless otherwise specified or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0057] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated, and the same reference numerals in the drawings denote the same elements.

[0058] Figure 1 This is a schematic perspective view of the display device 1 according to an embodiment, and Figure 2 This is a schematic plan view of the display device 1 according to an embodiment.

[0059] refer to Figure 1 The display device 1 according to an embodiment may include a display area DA and a non-display area NDA surrounding the display area DA. Furthermore, the non-display area NDA may include a curved area BA, a portion of which may be curved within the curved area BA. The remaining area, excluding the curved area BA, may be an area with a substantially flat surface. Figure 1 As shown, the bending region BA can be bent relative to the bending axis BAX extending in the first direction D1.

[0060] The substrate 100 may include a variety of flexible, bendable, or rollable materials. For example, the substrate 100 may include polymeric resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or combinations thereof.

[0061] Various modifications can be made. For example, substrate 100 may have a multilayer structure comprising two layers and a barrier layer between the two layers, the two layers comprising a polymer resin, and the barrier layer comprising an inorganic material such as silicon oxide, silicon nitride, or silicon oxynitride. According to another embodiment, in which the substrate 100 does not require a curved display, substrate 100 may comprise glass.

[0062] In the substrate 100, the width of the non-display area NDA, including the curved area BA, in the first direction D1 can be smaller than the width of the portion where the display area DA is located in the first direction D1. The corner portion 100c of the edge of the substrate 100 can have a circular shape. A circular shape can also be applied to the display area DA, such as... Figure 2 As shown in the image.

[0063] refer to Figure 2 The display device 1 may include a display area DA in which pixels P can be disposed, and a non-display area NDA outside the display area DA. The substrate 100 can be understood as having the display area DA and the non-display area NDA. The non-display area NDA may include a pad area PDA, which may be an area on one side of the display area DA that can be electrically attached to various types of electronic devices such as integrated circuits (ICs) or printed circuit boards.

[0064] Figure 2 This is a plan view illustrating the state of the substrate 100, etc., during the manufacturing operation of the display device 1. In the final display device or an electronic device including the display device (such as a smartphone), a portion of the substrate 100, etc., may be bent to minimize the area of ​​the non-display area NDA that is identifiable by the user, such as... Figure 1 As shown. For example, as Figure 1 and Figure 2 As shown, the substrate 100 may have portions with different widths in the first direction D1, and the substrate 100 may be bent relative to a bending axis BAX parallel to the first direction D1 in the portion with a narrow width.

[0065] At least a portion of the pad area PDA can overlap with the display area DA. The bending direction can be set such that the pad area PDA does not cover the display area DA, and the pad area PDA is behind the display area DA. Therefore, the user can recognize that the display area DA occupies most of the display device 1.

[0066] The edges of the display area DA can generally have a shape similar to a rectangle or square. Specifically, the display area DA may include a first edge E1 and a second edge E2 facing each other, as well as a third edge E3 and a fourth edge E4 that may be between the first edge E1 and the second edge E2. The pad area PDA may be adjacent to the fourth edge E4 among the first edge E1 to the fourth edge E4. The first portion F1 connecting the first edge E1 to the fourth edge E4 may have a circular shape. The display area DA may also have a circular shape in the second portion F2 connecting the second edge E2 to the fourth edge E4. The display area DA may have a circular shape in other portions of its edges.

[0067] A display unit 10, including pixel P, can be arranged (e.g., disposed) in a display area DA. A fan-out portion 20, in which conductive lines can extend and be arranged, can be arranged in a pad area PDA. One side of the fan-out portion 20 can be electrically connected to the display unit 10, and the other side of the fan-out portion 20 can be electrically connected to a driving circuit 30. The driving circuit 30 can include various types of electronic devices, such as integrated circuits (ICs).

[0068] The scan drive circuitry can be further arranged to the left and / or right of the display area DA. The scan drive circuitry can provide scan signals to each pixel P via scan lines, and can also provide emission control signals to each pixel P via emission control lines.

[0069] This will be described later in this article. Figure 2 Area A.

[0070] Figure 3 and Figure 4 This is a schematic equivalent circuit diagram of a pixel P included in a display device according to an embodiment.

[0071] refer to Figure 3 The pixel circuit PC can be electrically connected to an organic light-emitting diode (OLED) to enable pixel P to emit light. The pixel circuit PC may include a driving thin-film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 can be electrically connected to the scan line SL and the data line DL, and can deliver the data signal Dm input through the data line DL to the driving TFT T1 according to the scan signal Sn input through the scan line SL.

[0072] The storage capacitor Cst can be electrically connected to the switching thin-film transistor T2 and the drive voltage line PL, and can store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor T2 and the voltage supplied to the drive voltage line PL.

[0073] The driving thin-film transistor T1 can be electrically connected to the driving voltage line PL and the storage capacitor Cst, and the driving current flowing from the driving voltage line PL to the organic light-emitting diode (OLED) can be controlled according to the voltage value stored in the storage capacitor Cst. The OLED can emit light with a specific brightness according to the driving current.

[0074] although Figure 3 The illustration shows a pixel circuit PC comprising two thin-film transistors and a storage capacitor, but this disclosure is not limited thereto.

[0075] refer to Figure 4 The pixel circuit PC may include a driving thin-film transistor T1, a switching thin-film transistor T2, a compensation thin-film transistor T3, a first initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, a second initialization thin-film transistor T7, and a storage capacitor Cst.

[0076] although Figure 4 The illustration shows that each pixel circuit PC can be provided with signal lines SL, SL-1, SL+1, EL, and DL, an initialization voltage line VL, and a drive voltage line PL, but this disclosure is not limited thereto. As another embodiment, at least one of the signal lines SL, SL-1, SL+1, EL, and DL and / or the initialization voltage line VL can be shared by adjacent pixel circuits.

[0077] The drain electrode of the driving thin-film transistor T1 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. The driving thin-film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin-film transistor T2, and can supply driving current to the OLED.

[0078] The gate electrode of the switching thin-film transistor T2 can be electrically connected to the scan line SL, and the source electrode of the switching thin-film transistor T2 can be electrically connected to the data line DL. The drain electrode of the switching thin-film transistor T2 can be electrically connected to the source electrode of the driving thin-film transistor T1, and can be electrically connected to the driving voltage line PL via the operation control thin-film transistor T5.

[0079] The switching thin-film transistor T2 can be turned on according to the scan signal Sn received through the scan line SL, and can perform a switching operation to transmit the data signal Dm transmitted to the data line DL to the source electrode of the driving thin-film transistor T1.

[0080] The gate electrode of the compensation thin-film transistor T3 can be electrically connected to the scan line SL. The source electrode of the compensation thin-film transistor T3 can be electrically connected to the drain electrode of the driving thin-film transistor T1, and can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The drain electrode of the compensation thin-film transistor T3 can be electrically connected to any electrode of the storage capacitor Cst, the source electrode of the first initialization thin-film transistor T4, and the gate electrode of the driving thin-film transistor T1. The compensation thin-film transistor T3 can be turned on according to the scan signal Sn received via the scan line SL, and the gate electrode of the driving thin-film transistor T1 is connected to the drain electrode of the driving thin-film transistor T1, thereby diode-connecting the driving thin-film transistor T1.

[0081] The gate electrode of the first initialization thin-film transistor T4 can be electrically connected to the previous scan line SL-1. The drain electrode of the first initialization thin-film transistor T4 can be electrically connected to the initialization voltage line VL. The source electrode of the first initialization thin-film transistor T4 can be electrically connected to either electrode of the storage capacitor Cst, the drain electrode of the compensation thin-film transistor T3, and the gate electrode of the driving thin-film transistor T1. The first initialization thin-film transistor T4 can be turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1, and delivers the initialization voltage Vint to the gate electrode of the driving thin-film transistor T1 to perform the initialization operation of the voltage of the gate electrode of the driving thin-film transistor T1.

[0082] The gate electrode of the operating control thin-film transistor T5 can be electrically connected to the emitter control line EL. The source electrode of the operating control thin-film transistor T5 can be electrically connected to the drive voltage line PL. The drain electrode of the operating control thin-film transistor T5 can be electrically connected to the source electrode of the driving thin-film transistor T1 and the drain electrode of the switching thin-film transistor T2.

[0083] The gate electrode of the emitter control thin-film transistor T6 can be electrically connected to the emitter control line EL. The source electrode of the emitter control thin-film transistor T6 can be electrically connected to the drain electrode of the driving thin-film transistor T1 and the source electrode of the compensation thin-film transistor T3. The drain electrode of the emitter control thin-film transistor T6 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The operation control thin-film transistor T5 and the emitter control thin-film transistor T6 can be simultaneously turned on according to the emitter control signal En received through the emitter control line EL, and the driving voltage ELVDD can be transmitted to the OLED to allow the driving current to flow through the OLED.

[0084] The gate electrode of the second initialization thin-film transistor T7 can be electrically connected to the subsequent scan line SL+1. The source electrode of the second initialization thin-film transistor T7 can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The drain electrode of the second initialization thin-film transistor T7 can be electrically connected to the initialization voltage line VL. The second initialization thin-film transistor T7 can be turned on according to the subsequent scan signal Sn+1 received through the subsequent scan line SL+1, and initialize the pixel electrode of the organic light-emitting diode (OLED).

[0085] although Figure 4 The illustration shows that the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can be electrically connected to the previous scan line SL-1 and the subsequent scan line SL+1, respectively, but this disclosure is not limited thereto. As another embodiment, the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7 can both be electrically connected to the previous scan line SL-1 and driven according to the previous scan signal Sn-1.

[0086] The other electrode of the storage capacitor Cst can be electrically connected to the drive voltage line PL. Either electrode of the storage capacitor Cst can be electrically connected to the gate electrode of the driving thin-film transistor T1, the drain electrode of the compensation thin-film transistor T3, and the source electrode of the first initialization thin-film transistor T4.

[0087] The counter electrode (e.g., the cathode electrode) of an organic light-emitting diode (OLED) can receive a common voltage ELVSS. The OLED receives a drive current from the driving thin-film transistor T1 to emit light.

[0088] Pixel circuit PC is not limited to reference Figure 4 The number of thin-film transistors and storage capacitors and the circuit design are described, and the number of thin-film transistors and storage capacitors and the circuit design can be varied.

[0089] Figure 5 This is a schematic cross-sectional view of the display device 1 according to an embodiment. Figure 5 Corresponding to along Figure 2 The cross-sectional view of display device 1 taken by line I-I'.

[0090] refer to Figure 5 Thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs) can be arranged above the substrate 100.

[0091] A buffer layer 101 may be disposed on a substrate 100. The buffer layer 101 may be disposed on the substrate 100 to reduce or block the penetration of foreign matter, moisture, or external air from beneath the substrate 100, and to provide a flat surface on the substrate 100. The buffer layer 101 may comprise inorganic materials such as oxides or nitrides, organic materials, or composite materials of organic and inorganic materials. The buffer layer 101 may comprise a single-layer structure or a multi-layer structure containing inorganic and organic materials.

[0092] A thin-film transistor (TFT) can be disposed on a buffer layer 101. The TFT may include a semiconductor layer 134, a gate electrode 136 overlapping the semiconductor layer 134, and a connection electrode electrically connected to the semiconductor layer 134. The TFT can be electrically connected to and drive an organic light-emitting diode (OLED).

[0093] Semiconductor layer 134 may be disposed on buffer layer 101 and may include a channel region 131 overlapping with gate electrode 136, and source region 132 and drain region 133 disposed on opposite sides of channel region 131 and containing impurities at a higher concentration than those in channel region 131. In this document, impurities may include N-type or P-type impurities. Source region 132 and drain region 133 may be electrically connected to the connection electrodes of thin-film transistor (TFT).

[0094] Semiconductor layer 134 may comprise oxide semiconductors and / or silicon semiconductors. When semiconductor layer 134 comprises an oxide semiconductor, it may comprise an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, semiconductor layer 134 may comprise In-Sn-Zn-O (ITZO) or In-Ga-Zn-O (IGZO). When semiconductor layer 134 comprises a silicon semiconductor, it may comprise, for example, amorphous silicon (a-Si) or low-temperature polycrystalline silicon (LTPS) in which amorphous silicon (a-Si) can be crystallized.

[0095] The first insulating layer 103 may be disposed on the semiconductor layer 134. The first insulating layer 103 may comprise materials including silicon oxide (SiO2) and silicon nitride (SiN). x The first insulating layer 103 may comprise at least one inorganic insulating material selected from the group consisting of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0096] The gate electrode 136 may be disposed on the first insulating layer 103. The gate electrode 136 may comprise a single layer or multiple layers of at least one metal selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 136 may be electrically connected to a gate line to which an electrical signal is applied.

[0097] The second insulating layer 105 can be disposed on the gate electrode 136. The second insulating layer 105 may comprise materials including silicon oxide (SiO2) and silicon nitride (SiN). x The second insulating layer 105 may comprise at least one inorganic insulating material selected from the group consisting of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO).

[0098] A storage capacitor Cst may be disposed on a first insulating layer 103. The storage capacitor Cst may include a lower electrode 144 and an upper electrode 146 overlapping the lower electrode 144. The lower electrode 144 and the upper electrode 146 of the storage capacitor Cst may overlap each other, wherein a second insulating layer 105 is located between the lower electrode 144 and the upper electrode 146.

[0099] The lower electrode 144 of the storage capacitor Cst may overlap with the gate electrode 136 of the thin-film transistor TFT, and the lower electrode 144 of the storage capacitor Cst may be arranged as a single unit with the gate electrode 136 of the thin-film transistor TFT. As an embodiment, the storage capacitor Cst may not overlap with the thin-film transistor TFT, and the lower electrode 144 of the storage capacitor Cst may be an independent component separate from the gate electrode 136 of the thin-film transistor TFT.

[0100] The upper electrode 146 of the storage capacitor Cst may include Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W and / or Cu, and may include a single layer or multiple layers each comprising the aforementioned materials.

[0101] The third insulating layer 107 can be disposed on the upper electrode 146 of the storage capacitor Cst. The third insulating layer 107 can comprise materials including silicon oxide (SiO2) and silicon nitride (SiN). xThe third insulating layer 107 may comprise at least one inorganic insulating material selected from the group consisting of silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO2).

[0102] The source electrode 137 and drain electrode 138, which are connecting electrodes, can be disposed on the third insulating layer 107. The source electrode 137 and drain electrode 138 can include conductive materials containing Mo, Al, Cu, or Ti, or combinations thereof, and can be a multilayer or a single layer containing the above materials. The source electrode 137 and drain electrode 138 can include a Ti / Al / Ti multilayer.

[0103] A first planarization layer 111 may be disposed on the source electrode 137 and the drain electrode 138. The first planarization layer 111 may comprise a single layer or multiple layers containing organic or inorganic materials. As an example, the first planarization layer 111 may comprise benzocyclobutene (BCB), polyimide (PI), hexamethyl disilicide (HMDSO), common commercial polymers such as poly(methyl methacrylate) (PMMA) or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof. The first planarization layer 111 may comprise silicon oxide (SiO2), silicon nitride (SiN2), etc. x Materials may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), or combinations thereof. After forming the first planarization layer 111, chemical mechanical polishing may be performed to provide a flat top surface.

[0104] The contact metal layer CM can be disposed on the first planarization layer 111. The contact metal layer CM can include Al, Cu, or Ti, or combinations thereof, and can comprise a single layer or multiple layers. The contact metal layer CM can comprise multiple layers of Ti / Al / Ti.

[0105] The second planarization layer 113 can be disposed on the contact metal layer CM. The second planarization layer 113 may comprise a single layer or multiple layers containing organic or inorganic materials. As an example, the second planarization layer 113 may comprise BCB, PI, HMDSO, general-purpose commercial polymers such as PMMA or PS, polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylene polymers, vinyl alcohol polymers, or combinations thereof. The second planarization layer 113 may comprise silicon oxide (SiO2), silicon nitride (SiN2), etc.x The materials used may include silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), or combinations thereof. After forming the second planarization layer 113, chemical mechanical polishing may be performed to provide a flat top surface. As an example, the second planarization layer 113 may be omitted.

[0106] An organic light-emitting diode (OLED) comprising a pixel electrode 210, an intermediate layer 220, and a counter electrode 230 can be disposed on a second planarization layer 113. The pixel electrode 210 can be electrically connected to a contact metal layer CM through contact holes penetrating the second planarization layer 113. The contact metal layer CM can be electrically connected to a thin-film transistor (TFT) via contact holes penetrating the first planarization layer 111. The contact metal layer CM can be either a source electrode 137 or a drain electrode 138, and the OLED can be electrically connected to the thin-film transistor (TFT).

[0107] Pixel electrode 210 may be disposed on second planarization layer 113. Pixel electrode 210 may be a (semi-)transparent electrode or a reflective electrode. Pixel electrode 210 may include a reflective film comprising Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, Cu or compounds thereof, and a transparent or semi-transparent electrode layer formed above the reflective film. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and zinc aluminum oxide (AZO). Pixel electrode 210 may include a structure in which ITO / Ag / ITO may be stacked on top of each other.

[0108] A pixel defining film 180 can be disposed on a second planarization layer 113, and the pixel defining film 180 can have an opening that exposes at least a portion of the pixel electrode 210. The area exposed by the opening of the pixel defining film 180 can be defined as an emission region EA. The area surrounding the emission region EA can be a non-emission region NEA, and the non-emission region NEA can surround the emission region EA. In other words, the display region DA can include the emission region EA and the non-emission region NEA surrounding the emission region EA. The pixel defining film 180 can prevent arcing or the like at the edge of the pixel electrode 210 by increasing the distance between the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210. The pixel defining film 180 can be formed from, for example, an organic insulating material (such as polyimide, polyamide, acrylic resin, BCB, HMDSO, and phenolic resin) by spin coating or the like.

[0109] Intermediate layer 220 may be disposed on pixel electrode 210 which is at least partially exposed by pixel defining film 180. Intermediate layer 220 may include emitter layer (EML) 220b, and first functional layer 220a and / or second functional layer 220c may optionally be disposed below or above emitter layer 220b.

[0110] As an example, the intermediate layer 220 may be disposed on the pixel electrode 210, which is at least partially exposed by the pixel defining film 180. Specifically, the emitter layer 220b of the intermediate layer 220 may be disposed on the pixel electrode 210, which is at least partially exposed by the pixel defining film 180.

[0111] The first functional layer 220a may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second functional layer 220c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0112] The emitting layer 220b may include organic materials, including fluorescent or phosphorescent materials that emit red, green, blue, or white light. The emitting layer 220b may also include low-molecular-weight organic materials or polymeric organic materials.

[0113] When the emitter layer 220b comprises a low molecular weight organic material, the intermediate layer 220 may have a structure in which HTL, EML, EIL, etc., can be stacked individually or in complex structures, and may include various organic materials such as copper titanium cyanide (CuPc), N,N'-bis(1-naphthyl)-N,N'-biphenyl-benzidine (NPB), or aluminum tri-8-hydroxyquinoline (Alq3), or combinations thereof. These layers can be formed by vacuum deposition.

[0114] When the emitter layer 220b comprises a polymeric organic material, the intermediate layer 220 may have a structure including an HTL and the emitter layer 220b. The HTL may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the emitter layer 220b may comprise a polymeric material such as poly(p-phenylenevinylene) (PPV) or polyfluorene, or combinations thereof. The emitter layer 220b may be formed by screen printing, inkjet printing, or laser-induced thermal imaging (LITI), etc.

[0115] The counter electrode 230 can be disposed on the intermediate layer 220. The counter electrode 230 can be disposed on the intermediate layer 220 and can be arranged to completely cover the intermediate layer 220. The counter electrode 230 can be disposed above the display area DA and can be arranged to completely cover the display area DA. In other words, the counter electrode 230 can be formed as a single unit with the entire display panel using an aperture mask to cover the pixel P disposed in the display area DA.

[0116] The counter electrode 230 may include a conductive material having a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or alloys thereof. In other embodiments, the counter electrode 230 may further include a layer such as ITO, IZO, ZnO, or In2O3 above the (semi-)transparent layer comprising the aforementioned material.

[0117] Figure 6 This is a schematic plan view of the display device 1 according to an embodiment. Figure 6 yes Figure 2 A schematic cross-sectional view of enlarged region A.

[0118] refer to Figure 6 In addition to the non-display area NDA surrounding the display area DA, the non-display area NDA may also include a first non-display area NDA1, a second non-display area NDA2, and a curved area BA.

[0119] The first non-display area NDA1 and the second non-display area NDA2 can be defined around the curved area BA. The first non-display area NDA1 can be a region adjacent to the fourth edge E4 of the display area DA, and can be between the display area DA and the curved area BA. The second non-display area NDA2 can be a region that is not visible from the front when the curved area BA is bent, and can be a region between the curved area BA and the drive circuit 30. The curved area BA can be located between the first non-display area NDA1 and the second non-display area NDA2.

[0120] As mentioned above, with contact Figure 2 Similar to the non-display area NDA at the first edge E1 to the third edge E3 of the display area DA shown, the first non-display area NDA1 can be a non-display area NDA that is recognized by the user in the final display device or an electronic device including the display device (such as a smartphone). Since the fan-out portion 20 can be arranged in the first non-display area NDA1, the width of the first non-display area NDA1 may not be easily reduced compared to another non-display area NDA (e.g., the non-display area NDA that contacts the first edge E1 to the third edge E3 of the display area DA).

[0121] In the display device 1 according to the embodiment, the width WA1 of the first non-display area NDA1 can be reduced by dividing the fan-out portion 20 into "multiple segments". The "multiple segments" can be understood as corresponding to the first fan-out portion 21 and the second fan-out portion 22 of the fan-out portion 20, respectively. Therefore, in the embodiment, the width WA1 of the first non-display area NDA1 can be smaller than the width WA2 of the second non-display area NDA2.

[0122] like Figure 6 As shown, the fan-out portion 20 may include a first fan-out portion 21 and a second fan-out portion 22, which may be arranged in a curved region BA and spaced apart from each other by a separating region SA between the first fan-out portion 21 and the second fan-out portion 22.

[0123] The fan-out portion 20 may include a conductive line CL, and the conductive line CL may be, for example, a data line DL that transmits a data signal applied from the driving circuit 30 to the display unit 10. Figure 6 As shown, the conductive line CL may include a first conductive line CL1 and a second conductive line CL2.

[0124] The conductive line CL can be arranged to sequentially pass through the first non-display area NDA1, the curved area BA, and the second non-display area NDA2. For example... Figure 6 As shown, in the plan view, the conductive line CL can be bent at least twice. The bent portions of the conductive line CL can be arranged in the first non-display area NDA1 and the second non-display area NDA2. Since stress is concentrated in the bending area BA, the bent portions of the conductive line CL can be formed by avoiding the bending area BA, which has a high risk of breakage of the conductive line CL.

[0125] The conductive line CL can extend in the first non-display area NDA1 and the second non-display area NDA2 in a diagonal direction intersecting the first direction D1 and the second direction D2, and can extend in the curved area BA in a direction substantially parallel to the second direction D2. A portion of the conductive line CL in the curved area BA can partially extend into the first non-display area NDA1 and the second non-display area NDA2.

[0126] As an example, such as Figure 6As shown, the first fan-out portion 21 can be located on both sides of the second fan-out portion 22, with the second fan-out portion 22 between the first fan-out portions 21. Typically, the fan-out portions 20 can be provided in a symmetrical shape, and the first fan-out portions 21 can be arranged symmetrically, with the second fan-out portions 22 between the first fan-out portions 21. The second fan-out portion 22 can be provided in a symmetrical shape about an axis of symmetry SAX, and the first fan-out portions 21 can be arranged on one side and the other side of the second fan-out portion 22, respectively, with the second fan-out portions 22 between the first fan-out portions 21. For example, the first fan-out portion 21 can be arranged outside the second fan-out portion 22. In this disclosure, the first fan-out portion 21 and the second fan-out portion 22 can be divided by a separating region SA.

[0127] The first fan-out portion 21 may include a first conductive line CL1. The first conductive line CL1 may include n first-first conductive lines CL1-1 to first-nth conductive lines CL1-n. The second fan-out portion 22 may include a second conductive line CL2. The second conductive line CL2 may include m second-first conductive lines CL2-1 to second-mth conductive lines CL2-m. The number of first conductive lines CL1 may be the same as or different from the number of second conductive lines CL2.

[0128] The first conductive lines CL1 of the first fan-out portion 21 can be formed to have different lengths. The length of each of the first conductive lines CL1 can gradually decrease in the order of first-first conductive line CL1-1 to first-nth conductive line CL1-n. The length of each of the first conductive lines CL1 can be proportional to its resistance. As the length of each of the first conductive lines CL1 decreases in the order of first-first conductive line CL1-1 to first-nth conductive line CL1-n, its resistance can also decrease in the same order.

[0129] The resistance difference between conductive lines can lead to differences in resistive-capacitive (RC) delay between pixels that are electrically connected to the conductive lines. Since the resistance of the conductive lines gradually decreases in the order of the first-first conductive line CL1-1 to the first-nth conductive line CL1-n, the difference in RC delay between pixels may not be perceptible to the user.

[0130] Figure 7 This is a schematic plan view of the display device 1 according to an embodiment, and Figure 8 This is a schematic cross-sectional view of the display device 1 according to an embodiment. Specifically, Figure 8 Corresponding to along Figure 7 The cross-sectional view of display device 1 taken from line II-II'.

[0131] exist Figure 7and Figure 8 The diagram illustrates a first-n-1st conductive line CL1-n-1, a first-nth conductive line CL1-n, a second-first conductive line CL2-1, and a second-second conductive line CL2-2 that can be arranged adjacent to each other. For ease of explanation, the remaining conductive lines that can be arranged to continue the first-n-1st conductive line CL1-n-1 and the second-second conductive line CL2-2 are omitted.

[0132] The separating region SA can be formed between the first-nth conductive line CL1-n and the second-first conductive line CL2-1, which can be arranged adjacent to each other. The separating region SA can typically overlap with the curved region BA, and at least a portion of the separating region SA can extend toward the first non-display region NDA1 and the second non-display region NDA2.

[0133] refer to Figure 7 and Figure 8 As an example, the buffer layer 101, the first insulating layer 103, and the second insulating layer 105 can be disposed on the substrate 100. The third insulating layer 107 (see...) Figure 5 Additional layers and / or additional layers may be further arranged on the second insulating layer 105. However, for ease of illustration, their description is omitted.

[0134] As an embodiment, the first-n-1st conductive line CL1-n-1, the first-nth conductive line CL1-n, the second-first conductive line CL2-1, and the second-second conductive line CL2-2 can be located between the first insulating layer 103 and the second insulating layer 105. As another embodiment, various modifications can be made. For example, the first-n-1st conductive line CL1-n-1, the first-nth conductive line CL1-n, the second-first conductive line CL2-1, and the second-second conductive line CL2-2 can be located between the buffer layer 101 and the first insulating layer 103, or the first-n-1st conductive line CL1-n-1, the first-nth conductive line CL1-n, the second-first conductive line CL2-1, and the second-second conductive line CL2-2 can be located between the second insulating layer 105 and the third insulating layer 107. For example, the first-n-1st conductive line CL1-n-1 and the first-nth conductive line CL1-n can be alternately arranged on different layers, and the second-first conductive line CL2-1 and the second-second conductive line CL2-2 can also be alternately arranged on different layers.

[0135] The first-n-1st conductive line CL1-n-1 and the first-nth conductive line CL1-n arranged in the first fan-out portion 21 can be arranged to be spaced apart from each other by a first gap P1. Although Figure 7 and Figure 8The illustration shows that the first (n-1)th conductive line CL1-n-1 and the first (n)th conductive line CL1-n arranged in the first fan-out portion 21 can be arranged apart from each other by a first gap P1, but the first conductive lines CL1 arranged in the first fan-out portion 21 can also be arranged apart from each other by a first gap P1. In other words, the first conductive lines CL1 that are closest to each other can be arranged apart from each other by a first gap P1. The gap can be defined as the distance between the central axes of two adjacent lines in the first conductive lines CL1. For example, according to this disclosure, the concept of gap can be understood as the distance between central axes, rather than simply as the distance or interval between two adjacent lines. When the width of each of the first conductive lines CL1 arranged in the curved region BA can be constant, since the first conductive lines CL1 can be spaced apart from each other by a first gap P1, the interval or distance between the first conductive lines CL1 can also be constant.

[0136] The second-first conductive line CL2-1 and the second-second conductive line CL2-2 arranged in the second fan-out portion 22 can be arranged to be spaced apart from each other by a second gap P2. Although Figure 7 and Figure 8 The illustration shows that the second-first conductive line CL2-1 and the second-second conductive line CL2-2 arranged in the second fan-out portion 22 can be arranged to be spaced apart from each other by a second distance P2. However, the second conductive lines CL2 arranged in the second fan-out portion 22 can also be arranged to be spaced apart from each other by a second distance P2. In other words, the second conductive lines CL2 that are closest to each other can be arranged to be spaced apart from each other by a second distance P2.

[0137] As an example, the first conductive lines CL1 arranged in the first fan-out portion 21 can be arranged to be spaced apart by a first distance P1, and the second conductive lines CL2 arranged in the second fan-out portion 22 can be arranged to be spaced apart by a second distance P2. The first distance P1 between the first conductive lines CL1 can be smaller than the second distance P2 between the second conductive lines CL2. For example, the spacing between conductive lines arranged in the periphery of the fan-out portion can be smaller than the spacing arranged in the center of the fan-out portion.

[0138] Figure 9 This is a schematic cross-sectional view of the display device 1 according to an embodiment. Specifically, Figure 9 Corresponding to along Figure 7 The cross-sectional view of display device 1 taken by line III-III'.

[0139] refer to Figure 9The buffer layer 101, the first insulating layer 103, the second insulating layer 105, the third insulating layer 107, and the organic insulating layer 115 can be arranged on the substrate 100 of the non-display area NDA.

[0140] An opening OP in at least a portion of the exposed buffer layer 101 may be located in the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 of the non-display area NDA. Although Figure 9 The illustration shows that the opening OP can be defined in the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107. However, as another embodiment, the opening OP can be defined in the buffer layer 101, the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107. Various modifications can be made, for example, the opening OP can be defined in the buffer layer 101, the first insulating layer 103, and the second insulating layer 105.

[0141] An organic insulating layer 115 may be disposed inside the opening OP. Since inorganic films may be more susceptible to stress than organic films, a portion of the inorganic films (e.g., the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107) disposed in the bending region BA may be removed, and the organic insulating layer 115, which includes organic materials, may be filled into the opening OP to alleviate stress in the bending region BA.

[0142] refer to Figure 7 and Figure 9 The first-n-1st conductive line CL1-n-1 may include a first conductive layer 1-a disposed in the first non-display area NDA1, a second conductive layer 1-c disposed in the second non-display area NDA2, and a connecting conductive layer 1-b disposed in the curved area BA. Although Figure 7 and Figure 9 The illustration shows that the first to (n-1)th conductive line CL1-n-1 includes a first conductive layer 1-a disposed in the first non-display area NDA1, a second conductive layer 1-c disposed in the second non-display area NDA2, and a connecting conductive layer 1-b disposed in the curved area BA. However, it is understood that the first conductive line CL1 includes the first conductive layer 1-a disposed in the first non-display area NDA1, the second conductive layer 1-c disposed in the second non-display area NDA2, and the connecting conductive layer 1-b disposed in the curved area BA. Furthermore, the second conductive line CL2 may also include the same or a similar structure.

[0143] As an example, the first conductive layer 1-a and the second conductive layer 1-c can be arranged on the same layer, and the connecting conductive layer 1-b can be arranged on a different layer than the first conductive layer 1-a and the second conductive layer 1-c. For example, Figure 9As shown, the first conductive layer 1-a and the second conductive layer 1-c can be disposed on the first insulating layer 103, and the connecting conductive layer 1-b can be disposed on the organic insulating layer 115 and the third insulating layer 107. In an embodiment, the portion of the fan-out portion 20 corresponding to the curved region BA and the portion of the fan-out portion 20 corresponding to the first non-display region NDA1 and the second non-display region NDA2 can be disposed on different insulating layers.

[0144] First conductive layer 1-a, second conductive layer 1-c, and thin-film transistor (TFT) (see...) Figure 5 The gate electrode 136 (see) Figure 5 The conductive layer 1-b and the source electrode 137 (see [reference]) may be made of the same material. Figure 5 ) and drain electrode 138 (see Figure 5 () can include the same material.

[0145] The second insulating layer 105 and the third insulating layer 107 may be located between the first conductive layer 1-a, the second conductive layer 1-c, and the connecting conductive layer 1-b. The first conductive layer 1-a and the connecting conductive layer 1-b, as well as the second conductive layer 1-c and the connecting conductive layer 1-b, may be electrically connected to each other through contact holes CNTs defined in the second insulating layer 105 and the third insulating layer 107.

[0146] In another embodiment, the first conductive layer 1-a and the second conductive layer 1-c can be disposed on the second insulating layer 105, or the first conductive layer 1-a and the second conductive layer 1-c can be disposed on the third insulating layer 107. For example, when the first conductive layer 1-a and the second conductive layer 1-c are disposed on the third insulating layer 107, the first conductive layer 1-a and the second conductive layer 1-c can be disposed on the same layer as the connecting conductive layer 1-b.

[0147] As an example, at least a portion of the organic insulating layer 115 disposed in the curved region BA may be arranged to extend toward the first non-display region NDA1 and / or the second non-display region NDA2. At least a portion of the first insulating layer 103, the second insulating layer 105, and the third insulating layer 107 disposed in the first non-display region NDA1 and / or the second non-display region NDA2 may be arranged to extend toward the curved region BA.

[0148] Figure 10 This is a schematic plan view of the display device 1 according to an embodiment.

[0149] refer to Figure 10 The drive power line 40 and the common power line 45 can be arranged in the pad area of ​​the PDA. At least a portion of the drive power line 40 and the common power line 45 can be arranged to overlap with the fan-out portion 20.

[0150] At least a portion of the drive power line 40 may be arranged in the partition region SA. In other words, at least a portion of the drive power line 40 may be arranged in the partition region SA, for example, between the first fan-out portion 21 and the second fan-out portion 22.

[0151] At least a portion of the common power line 45 can be arranged in the pad area of ​​the PDA outside the fan-out portion 20. Although in Figure 10 Not shown, but the common power line 45 may have a loop shape with one side open and partially surround the display area DA.

[0152] The drive power line 40 may include, for example, with Figure 5 The source electrode 137 and drain electrode 138 of the thin-film transistor TFT are made of the same material. Figure 10 The drive power line 40 and the common power line 45 may overlap with the fan-out portion 20 in the first non-display area NDA1 and the second non-display area NDA2, and may not overlap with the fan-out portion 20 in the curved area BA.

[0153] Figure 11 This is a schematic plan view of the display device 1 according to an embodiment. Figure 11 Implementation examples and Figure 6 The difference in the embodiment is that the fan-out portion 20 further includes a third fan-out portion 23. The following description will focus on this difference. Other structures may be the same as or similar to the embodiments described above.

[0154] refer to Figure 11 According to an embodiment, the display device 1 may include a fan-out portion 20 disposed in a first non-display area NDA1, a curved area BA, and a second non-display area NDA2. The fan-out portion 20 may include a first fan-out portion 21, a second fan-out portion 22, and a third fan-out portion 23. Each first fan-out portion 21 is disposed outside the fan-out portion 20, the second fan-out portion 22 may be spaced apart from the first fan-out portion 21 in a first direction D1, and each third fan-out portion 23 is disposed between the first fan-out portion 21 and the second fan-out portion 22.

[0155] The second fan-out portion 22 can be located in the central portion of the fan-out portion 20, and the first fan-out portion 21 and the third fan-out portion 23 can be located on both sides of the second fan-out portion 22, with the second fan-out portion 22 situated between the first fan-out portion 21 and the third fan-out portion 23. The first fan-out portion 21 to the third fan-out portion 23 can be arranged symmetrically. The third fan-out portion 23 can be arranged on one side and the other side of the second fan-out portion 22, respectively, wherein the second dividing region SA2 is between the third fan-out portion 23 and the second fan-out portion 22. The first fan-out portion 21 can be arranged outside the third fan-out portion 23, wherein the first dividing region SA1 is between the first fan-out portion 21 and the third fan-out portion 23. In this disclosure, the first fan-out portion 21 to the third fan-out portion 23 can be understood as being geometrically divided by the dividing region SA.

[0156] The first fan-out portion 21 to the third fan-out portion 23 can deliver data signals applied from the drive circuit 30 located in the second non-display area NDA2 to the display unit 10.

[0157] The first fan-out portion 21 may include a first conductive line CL1. The first conductive line CL1 may include n first-first conductive lines CL1-1 to first-nth conductive lines CL1-n. The second fan-out portion 22 may include a second conductive line CL2. The second conductive line CL2 may include m second-first conductive lines CL2-1 to second-mth conductive lines CL2-m. The third fan-out portion 23 may include a third conductive line CL3. The third conductive line CL3 may include k third-first conductive lines CL3-1 to third-kth conductive lines CL3-k.

[0158] Figure 12 This is a schematic plan view of the display device 1 according to an embodiment. Figure 12 Implementation examples and Figure 11 The difference in the embodiments is that they may include a first fan-out portion and a second fan-out portion. The following description will focus on this difference. Other structures may be the same as or similar to the embodiments described above.

[0159] refer to Figure 12 The display device 1 according to an embodiment may include a first fan-out portion 20A and a second fan-out portion 20B that can be arranged in a first non-display area NDA1, a curved area BA, and a second non-display area NDA2. In an embodiment, the first fan-out portion 20A and the second fan-out portion 20B may be electrically connected to a first driving circuit 30A and a second driving circuit 30B, respectively. The first fan-out portion 20A and the second fan-out portion 20B may each include a first fan-out portion 21 to a third fan-out portion 23.

[0160] Figure 13This is a schematic plan view of the display device 1 according to an embodiment.

[0161] refer to Figure 13 The drive power line 40 and the common power line 45 can be arranged in the pad area of ​​the PDA. At least a portion of the drive power line 40 and the common power line 45 can be arranged to overlap with the fan-out portion 20. The drive power line 40 and the common power line 45 can overlap with the fan-out portion 20 in the first non-display area NDA1 and the second non-display area NDA2, and can not overlap with the fan-out portion 20 in the curved area BA.

[0162] At least a portion of the drive power line 40 may be arranged in the partition region (second partition region SA2). In other words, at least a portion of the drive power line 40 may be arranged between the second fan-out portion 22 and the third fan-out portion 23.

[0163] At least a portion of the common power line 45 can be arranged in the partitioned area (first partitioned area SA1). In other words, at least a portion of the drive power line 40 can be arranged between the first fan-out portion 21 and the third fan-out portion 23. Although in Figure 13 Not shown, but the common power line 45 may have a loop shape with one side open and partially surround the display area DA.

[0164] A fifth conductive line (not shown) may be further arranged in the pad area of ​​the PDA outside the fan-out portion 20. At least a portion of the fifth conductive line may be arranged to overlap with the fan-out portion 20. However, the fifth conductive line may not overlap with the fan-out portion 20 in the curved region BA. The fifth conductive line can deliver scan signals and / or transmit signals applied from the drive circuit 30 to the display unit 10.

[0165] A sixth conductive line (not shown) may be further arranged in a partition region (first partition region SA1). The sixth conductive line arranged in the partition region (first partition region SA1) may not overlap with the common power line 45 in the curved region BA. At least a portion of the sixth conductive line may be arranged to overlap with the fan-out portion 20. The sixth conductive line may overlap with the fan-out portions 20 in the first non-display region NDA1 and the second non-display region NDA2, and may not overlap with the fan-out portion 20 in the curved region BA. One side of the sixth conductive line may be electrically connected to a sensing electrode arranged in the display unit 10, and the other side of the sixth conductive line may be electrically connected to the driving circuit 30. As another embodiment, in the case where a touch driving circuit is included separately, the other side of the sixth conductive line may be electrically connected to the touch driving circuit.

[0166] Figure 14 This is a schematic cross-sectional view of the display device 1 according to an embodiment. Specifically, Figure 14 Corresponding to along Figure 11 The cross-sectional view of display device 1 taken by lines IV-IV' and V-V'.

[0167] refer to Figure 14 The first (n-1)th conductive line CL1-n-1 and the first (n)th conductive line CL1-n arranged in the first fan-out portion 21 can be arranged to be spaced apart from each other by a first gap P1. For ease of explanation, Figure 13 The diagram illustrates that the first (n-1)th conductive line CL1-n-1 and the first (n)th conductive line CL1-n arranged in the first fan-out portion 21 can be arranged to be separated from each other by a first gap P1. However, the first conductive lines CL1 arranged in the first fan-out portion 21 can also be arranged to be separated from each other by a first gap P1. In other words, the first conductive lines CL1 that are closest to each other can be arranged to be separated from each other by a first gap P1.

[0168] The second-first conductive line CL2-1 and the second-second conductive line CL2-2 arranged in the second fan-out portion 22 can be arranged to be spaced apart from each other by a second gap P2. For ease of explanation, Figure 13 The illustration shows that the second-first conductive line CL2-1 and the second-second conductive line CL2-2 arranged in the second fan-out portion 22 can be arranged to be spaced apart from each other by a second distance P2. However, the second conductive lines CL2 arranged in the second fan-out portion 22 can also be arranged to be spaced apart from each other by a second distance P2. In other words, the second conductive lines CL2 that are closest to each other can be arranged to be spaced apart from each other by a second distance P2.

[0169] The third-first conductive line CL3-1 and the third-second conductive line CL3-2, as well as the third-k-1st conductive line CL3-k-1 and the third-kth conductive line CL3-k, which can be arranged in the third fan-out portion 23, can be arranged to be separated from each other by a third spacing P3. For ease of explanation, Figure 14 The diagram illustrates that the third-first conductive line CL3-1, the third-second conductive line CL3-2, the third-k-1st conductive line CL3-k-1, and the third-kth conductive line CL3-k, which can be arranged in the third fan-out portion 23, can be spaced apart from each other by a third distance P3. However, the third conductive lines CL3 arranged in the third fan-out portion 23 can also be spaced apart from each other by a third distance P3. In other words, the third conductive lines CL3 that are closest to each other can be arranged to be spaced apart from each other by a third distance P3.

[0170] The first conductive lines CL1 arranged in the first fan-out portion 21 can be arranged to be spaced apart by a first gap P1, and the second conductive lines CL2 arranged in the second fan-out portion 22 can be arranged to be spaced apart by a second gap P2. The first gap P1 between the first conductive lines CL1 can be smaller than the second gap P2 between the second conductive lines CL2.

[0171] As an example, the third spacing P3 between the third conductive lines CL3 can be greater than the first spacing P1 between the first conductive lines CL1, and smaller than the second spacing P2 (P1) between the second conductive lines CL2. <P3<P2)。

[0172] In another embodiment, the third spacing P3 between the third conductive lines CL3 can be equal to the first spacing P1 between the first conductive lines CL1, and can be less than the second spacing P2 between the second conductive lines CL2 (P1 = P3). <P2)。

[0173] In another embodiment, the third spacing P3 between the third conductive lines CL3 can be greater than the first spacing P1 between the first conductive lines CL1, and can be equal to the second spacing P2 (P1) between the second conductive lines CL2. <P3=P2)。

[0174] Figure 15 This is a schematic cross-sectional view of the display device 1 according to an embodiment. Figure 15 Corresponding to along Figure 11 A cross-sectional view of display device 1 taken by line VI-VI'.

[0175] refer to Figure 11 and Figure 15 According to an embodiment, the fan-out portion 20 of the display device 1 may include a first fan-out portion 21, a second fan-out portion 22, and a third fan-out portion 23. The first fan-out portion 21 may include a first conductive line CL1, the second fan-out portion 22 may include a second conductive line CL2, and the third fan-out portion 23 may include a third conductive line CL3.

[0176] As an embodiment, the first conductive lines CL1 arranged in the first fan-out portion 21 may have different spacings from each other. The first-first conductive lines CL1-1 and the first-second conductive lines CL1-2 arranged at the outermost part of the first fan-out portion 21 of the first fan-out portion 20 may be arranged to be separated from each other by a first spacing P1, and the first-n-1st conductive lines CL1-n-1 and the first-nth conductive lines CL1-n of the first fan-out portion 21 may be arranged to be separated from each other by a second spacing P2 that may be different from the first spacing P1. The first spacing P1 may be smaller than the second spacing P2. For example, the spacing between the conductive lines arranged in the first fan-out portion 21 may increase from the outermost part of the fan-out portion 20 to the part adjacent to the third fan-out portion 23. As an embodiment, each spacing between the conductive lines arranged in the first fan-out portion 21 may gradually increase from the outermost part of the fan-out portion 20 to the part adjacent to the third fan-out portion 23. As another embodiment, the spacing may be increased at specific group intervals by grouping the conductive lines arranged in the first fan-out portion 21 into preset groups.

[0177] The third conductive lines CL3 arranged in the third fan-out portion 23 can have different spacings from each other. The third-first conductive lines CL3-1 and the third-second conductive lines CL3-2 adjacent to the first fan-out portion 21 in the third fan-out portion 23 can be arranged to be separated from each other by a third spacing P3, and the third-k-1st conductive lines CL3-k-1 and the third-kth conductive lines CL3-k adjacent to the second fan-out portion 22 in the third fan-out portion 23 can be arranged to be separated from each other by a fourth spacing P4 that may be different from the third spacing P3. The third spacing P3 may be smaller than the fourth spacing P4. For example, the spacing between the conductive lines arranged in the third fan-out portion 23 can increase from the portion adjacent to the first fan-out portion 21 to the portion adjacent to the second fan-out portion 22. As another embodiment, each spacing between the conductive lines arranged in the third fan-out portion 23 can gradually increase from the portion adjacent to the first fan-out portion 21 to the portion adjacent to the second fan-out portion 22. As another embodiment, the spacing can be increased by dividing the conductive wires arranged in the third fan-out portion 23 into preset groups at specific group intervals.

[0178] Despite Figure 15 Not shown in the figure, but the second conductive lines CL2 arranged in the second fan-out portion 22 can have different spacing from each other.

[0179] According to an embodiment, the spacing (first spacing) between conductive lines in the first fan-out portion 21 arranged outside the fan-out portion 20 can be designed to be smaller than the spacing (second spacing) between conductive lines in the second fan-out portion 22 arranged in the central portion of the fan-out portion 20, so that the resistance of the conductive lines arranged in the first fan-out portion 21 can be reduced, and the resistance deviation between the conductive lines arranged in the first fan-out portion 21 and the conductive lines arranged in the second fan-out portion 22 can be reduced.

[0180] According to an embodiment, the resistance deviation between adjacent conductive lines (where the separating region is between adjacent conductive lines) can be reduced, thereby preventing or significantly reducing the brightness deviation between adjacent pixels.

[0181] According to the embodiments of the present disclosure made as described above, a display device with reduced non-display area and improved emission uniformity between adjacent pixels can be realized.

[0182] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects in each embodiment should typically be considered as other similar features or aspects that may be used in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various modifications of form and detail may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate includes: a display area; and a non-display area comprising a first non-display area, a second non-display area, and a curved region disposed between the first non-display area and the second non-display area, wherein the first non-display area is adjacent to the display area. A display unit arranged in the display area; The driving circuitry arranged in the non-display area; and A fan-out portion is disposed in the first non-display area, the curved area, and the second non-display area, wherein... The first non-display area, the curved area, and the second non-display area are arranged between the display unit and the driving circuit, and The fan-out portion delivers the data signal applied from the drive circuit to the display unit. The fan-out portion includes: A first fan-out portion comprising a first conductive wire and disposed outside the fan-out portion; and The second fan-out portion includes a second conductive wire and is arranged in the central portion of the fan-out portion. The first conductive wires are spaced apart from each other by a first gap in the curved region, and The second conductive wires are spaced apart from each other in the curved region by a second spacing greater than the first spacing. The first conductive line and the second conductive line each include a data line.

2. The display device according to claim 1, wherein, The first fan-out portion and the second fan-out portion are spaced apart from each other in the curved region.

3. The display device according to claim 2, wherein, The first conductive line includes a first line to an nth line. The second conductive line includes the first line to the m-th line, and Among the first line to the nth line of the first conductive line and the first line to the mth line of the second conductive line, the nth line of the first conductive line and the first line of the second conductive line are arranged to be closest to each other.

4. The display device according to claim 1, wherein, The fan-out portion includes a third fan-out portion containing a third conductive line, and The third conductive wires are spaced apart from each other by a third gap in the curved region.

5. The display device according to claim 4, wherein, The third spacing is greater than or equal to the first spacing.

6. The display device according to claim 4, wherein, The third spacing is less than or equal to the second spacing.

7. The display device according to claim 4, wherein, In the plan view, the first conductive wire and the second conductive wire are bent two or more times.

8. The display device according to claim 7, wherein, The first conductive wire and the second conductive wire do not bend in the bending region.

9. The display device according to claim 1, wherein, The portions of the first and second conductive lines arranged in the curved region are arranged on different insulating films than the portions of the first and second conductive lines arranged in the first and second non-display regions.

10. The display device according to claim 9, wherein, The portion of the fan-out section corresponding to the curved area and the portion of the fan-out section corresponding to the first non-display area and the second non-display area are arranged on different insulating films.

11. The display device according to claim 10, wherein, The display unit includes: Thin-film transistors; and The light-emitting element is electrically connected to the thin-film transistor. The thin-film transistor includes a semiconductor layer, a gate electrode, and a connection electrode electrically connected to the semiconductor layer. The portion of the fan-out section corresponding to the curved region and the connecting electrode comprise the same material, and The portion of the fan-out section corresponding to the first non-display area and the second non-display area comprises the same material as the gate electrode.

12. The display device according to claim 1, further comprising an insulating layer disposed on the substrate, The insulating layer includes an opening corresponding to the curved region.

13. The display device according to claim 12, further comprising an organic insulating layer disposed in the opening of the insulating layer.

14. The display device according to claim 13, wherein, The portion of the fan-out section corresponding to the curved area is arranged on the organic insulating layer.

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