Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The semiconductor structure includes: a semiconductor substrate, on which a plurality of fins are formed; a groove located in the semiconductor substrate and separating adjacent active areas; and an isolation structure located on the semiconductor substrate and surrounding the bottom of the fin, wherein the isolation structure does not fill the groove and closes the top of the groove. The semiconductor structure and the method for forming the same described in the present application form a groove filled with air between adjacent active areas, and the groove is used to isolate adjacent active areas, thereby reducing leakage between adjacent active areas.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance and lower costs continues to increase. In order to meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, and the design of three-dimensional structures such as fin field-effect transistors (FinFETs) has become a hot topic in the semiconductor field.

[0003] However, current FinFETs still have problems such as leakage between adjacent active areas, and a more effective and reliable technical solution is needed. Summary of the invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can reduce the leakage problem between adjacent active regions of a FinFET device.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, on which a plurality of fin structures are formed, and forming a groove in the semiconductor substrate, wherein the groove separates adjacent active areas; and growing a sealing layer on the surface of the top of the groove, wherein the sealing layer seals the top of the groove.

[0006] In some embodiments of the present application, a first dielectric layer is formed on the semiconductor substrate and the fin structure, the first dielectric layer exposes a portion of the bottom surface of the fin structure, and the method for forming the semiconductor structure further includes: forming a second dielectric layer, the second dielectric layer covering the sidewalls of the trench and the surface of the fin structure exposed by the first dielectric layer; removing a portion of the second dielectric layer on the top sidewalls of the trench, a portion of the first dielectric layer on the surface of the semiconductor substrate adjacent to the top of the trench, and the second dielectric layer covering the surface of the fin structure exposed by the first dielectric layer.

[0007] In some embodiments of the present application, a method for removing a portion of the second dielectric layer on the top sidewall of the trench, a portion of the first dielectric layer on the surface of the semiconductor substrate adjacent to the top of the trench, and the second dielectric layer covering the surface of the fin structure exposed by the first dielectric layer comprises: forming a hard mask layer on the first dielectric layer and in the trench, the hard mask layer filling the trench; etching back the hard mask layer so that the top surface of the hard mask layer is lower than the top surface of the trench; etching and removing a portion of the second dielectric layer above the top surface of the hard mask layer and a portion of the first dielectric layer on the surface of the semiconductor substrate adjacent to the trench; and removing the hard mask layer.

[0008] In some embodiments of the present application, after the hard mask layer is etched back so that the top surface of the hard mask layer is lower than the top surface of the trench, the depth of the portion of the hard mask layer below the trench accounts for 10% to 20% of the depth of the trench.

[0009] In some embodiments of the present application, a method for etching and removing a portion of the second dielectric layer above the top surface of the hard mask layer and a portion of the first dielectric layer on the surface of the semiconductor substrate adjacent to the trench is isotropic etching.

[0010] In some embodiments of the present application, a closing layer is formed on the top sidewall of the trench, the surface of the semiconductor substrate adjacent to the top of the trench, and the surface of the fin structure exposed by the first dielectric layer, and the method of closing the top of the trench with the closing layer includes: epitaxially growing an epitaxial layer on the top sidewall of the trench, the surface of the semiconductor substrate adjacent to the top of the trench, and the surface of the fin structure exposed by the first dielectric layer until the epitaxial layer closes the top of the trench; and thinning the epitaxial layer to form the closing layer.

[0011] In some embodiments of the present application, the method of thinning the epitaxial layer to form the sealing layer includes: thinning the epitaxial layer using an anisotropic dry etching process; and further thinning the epitaxial layer using ashing and wet etching processes.

[0012] In some embodiments of the present application, the thickness of the sealing layer is 1 nanometer to 5 nanometers.

[0013] In some embodiments of the present application, the method for forming the semiconductor structure also includes: using an FCVD process to form an isolation material layer on the first dielectric layer and the sealing layer, wherein the isolation material layer fills the space between the plurality of fin structures and the top surface is higher than the top surface of the first dielectric layer; curing the isolation material layer and oxidizing the sealing layer.

[0014] In some embodiments of the present application, the method of curing the isolation material layer and oxidizing the epitaxial layer includes: treating the isolation material layer and oxidizing the epitaxial layer using a steam annealing process; treating the isolation material layer using a dry annealing process.

[0015] In some embodiments of the present application, the method for forming the semiconductor structure also includes: flattening the isolation material layer and the first dielectric layer to expose the top of the fin structure, wherein the fin structure includes a fin located on a semiconductor substrate and a mask layer located on the fin; performing doping ion implantation in different active areas respectively; removing the mask layer; and etching a portion of the isolation material layer and the first dielectric layer to form an isolation structure surrounding the bottom of the fin.

[0016] In some embodiments of the present application, the method for forming the groove in the semiconductor substrate includes: forming a sacrificial layer, an anti-reflection layer and a patterned photoresist layer in sequence on the surface of the first dielectric layer, the patterned photoresist layer defining the position of the groove; etching the anti-reflection layer, the sacrificial layer and the first dielectric layer using the patterned photoresist layer as a mask to form an opening in the first dielectric layer; etching the semiconductor substrate using the first dielectric layer as a mask to form the groove; and removing the sacrificial layer, the anti-reflection layer and the patterned photoresist layer.

[0017] In some embodiments of the present application, the second dielectric layer is formed by an in-situ steam generation process.

[0018] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, on which a plurality of fins are formed; a groove, located in the semiconductor substrate, separating adjacent active areas; an isolation structure, located on the semiconductor substrate and surrounding the bottom of the fin, wherein the isolation structure does not fill the groove and closes the top of the groove.

[0019] The semiconductor structure and the method for forming the same described in the present application form air-filled trenches between adjacent active regions, and the adjacent active regions are isolated by the trenches, thereby reducing leakage between the adjacent active regions. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0021] Figure 1 is a planar distribution diagram of a semiconductor structure;

[0022] Figures 2 to 5 is a schematic structural diagram of a semiconductor structure;

[0023] Figure 6 to Figure 7 Schematic diagrams of some semiconductor structures;

[0024] Figures 8 to 45 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0026] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0027] Figure 1 This is a planar distribution diagram of a semiconductor structure. Figure 1 As shown, the semiconductor structure includes a semiconductor substrate 100, and the semiconductor substrate 100 includes a plurality of active regions 110, and a plurality of fin structures 120 are formed on the plurality of active regions 110. It should be noted that: Figure 1 The planar distribution of the semiconductor structure is merely schematically illustrated to facilitate understanding of the distribution of different active regions and fin structures on the active regions described in the embodiments of the present application. Figure 1 The distribution of the active area and the fin structure is only briefly shown in the figure, and other structures are not shown. The number and size relationship of the active area and the fin structure in the figure do not represent the number and size relationship in the actual structure. Figure 1 The X direction and the Y direction are also defined in the figure for the purpose of facilitating understanding when cross-sectional views in the X direction and the Y direction are provided later.

[0028] Figures 2 to 5 Schematic diagram of a semiconductor structure. Figure 2 is the cross-sectional view in the X direction, Figure 3 It is a cross-sectional view in the Y direction. In the following text, X above a figure indicates that the figure is a cross-sectional view in the X direction, and Y above a figure indicates that the figure is a cross-sectional view in the Y direction.

[0029] refer to Figure 2 and Figure 3 As shown, the semiconductor structure includes a semiconductor substrate 200, on which a plurality of fin structures 210 are formed. An isolation structure 220 is also formed on the semiconductor substrate 200 for isolating the plurality of fin structures 210. An epitaxial doped region 230 is formed on the surface of the fin structure 210. An interlayer dielectric layer 240 is formed on the isolation structure 220 and the fin structure 210, and a contact structure 250 is formed in the interlayer dielectric layer 240, penetrating the interlayer dielectric layer 240 and electrically connected to the epitaxial doped region 230.

[0030] As the size of FinFET devices decreases, electrons may migrate along the path 20 between adjacent active regions, causing increasingly serious leakage between adjacent active regions.

[0031] In addition, reference Figure 4 As shown, when adjacent active regions are of different doping types, a depletion region 201 will be generated in the semiconductor substrate 200 and on the top of the fin structure 210 due to the presence of the PN junction. Figure 5 As shown, the depletion region 201 in the semiconductor substrate 200 may deviate toward one of the adjacent active regions and merge with the depletion region at the top of the fin structure, for example. Figure 4 The depletion region 201 in the figure is offset to the active region on the left side of the figure (the depletion region may also be offset to the active region on the other side). The offset and fusion of the depletion region 201 is an important factor leading to leakage between adjacent active regions.

[0032] In order to avoid the offset and fusion of the depletion region, the doping concentration of the active region can be increased to reduce the width of the depletion region in the semiconductor substrate (the width refers to the size of the depletion region in the horizontal direction). However, too high a doping concentration may reduce the mobility of carriers and affect device performance. In addition, the height of the fin structure and the spacing between the fin structures or the angle between the sidewalls of the fin structure and the semiconductor substrate can be increased to solve the above problem. However, this requires a high photolithography process for forming the fin structure and is not easy to implement.

[0033] Figure 6 to Figure 7 Schematic diagrams of some semiconductor structures are shown in FIG. 1. In order to solve the problem of leakage between adjacent active regions, some solutions are proposed.

[0034] refer to Figure 6 As shown, a fin structure 310 and an isolation structure 320 surrounding the bottom of the fin structure 310 are formed on a semiconductor substrate 300. In some semiconductor structures, a portion of the fin structure 310 with a height D is etched and removed to increase the size of the epitaxial doped region formed on the top surface of the fin structure 310. Reducing the height D of the removed portion of the fin structure can reduce leakage between adjacent active regions, but this will also reduce the performance of the FinFET device.

[0035] refer to Figure 7 As shown, in some other semiconductor structures, the isolation structure 420 not only surrounds the fin structure 410, but also extends between adjacent active regions of the semiconductor substrate 400 to isolate the adjacent active regions. However, in this structure, the isolation structure 420 is formed by a fluid chemical vapor deposition process and a wet annealing process. During the formation process, the portion of the isolation structure extending into the semiconductor substrate 400 will cause stress imbalance on the sidewall of the fin structure, thereby causing misalignment of the semiconductor material stacking on the sidewall of the fin structure.

[0036] In summary, there is still a need for more effective and reliable technical solutions to reduce leakage between adjacent active areas. In view of the above problems, the present application provides a semiconductor structure and a method for forming the same, which uses air-filled trenches to isolate adjacent active areas, thereby better reducing leakage between adjacent active areas.

[0037] Figures 8 to 45 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application.

[0038] refer to Figure 8 and Fig. 9 , a semiconductor substrate 500 is provided, on which a plurality of fin structures 510 are formed. The fin structures 510 include fins 511 located on the semiconductor substrate 500 and a mask layer 512 located on the fins 511 .

[0039] In some embodiments of the present application, the material of the semiconductor substrate 500 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, etc.; or (iv) a combination of the above. In addition, the semiconductor substrate 500 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 500 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0040] In some embodiments of the present application, the method of forming the fin 511 may include: growing an epitaxial layer on the semiconductor substrate 500; forming a patterned mask layer 512 on the epitaxial layer; using the patterned mask layer 512 as a mask to etch the epitaxial layer and the semiconductor substrate 500 to form the fin 511. For example, etching may be performed using a dry etching process, a wet etching process, or a combination thereof. In some embodiments of the present application, the mask layer 512 may be a thin film including silicon oxide formed using a thermal oxidation process. In other embodiments of the present application, the mask layer 512 may be a thin film including silicon nitride formed using a low pressure chemical vapor deposition process (LPCVD) or a plasma enhanced CVD (PECVD).

[0041] refer to Fig.10 and Fig.11 , a first dielectric layer 520 is formed on the semiconductor substrate 500 and the fin structure 510. The first dielectric layer 520 fills the gaps between the fin structures on the same active region.

[0042] In some embodiments of the present application, the material of the first dielectric layer 520 includes silicon oxide.

[0043] In some embodiments of the present application, a method for forming the first dielectric layer 520 includes a chemical vapor deposition process or an atomic layer deposition process.

[0044] refer to Figures 12 to 17 , a groove 530 is formed in the semiconductor substrate 500, and the groove 530 separates adjacent active areas. In some semiconductor structures, a low dielectric constant material (such as silicon oxide, etc.) is filled in the groove to isolate adjacent active areas. However, the low dielectric constant material filling process may cause stacking faults on the sidewalls of the fin structure. Therefore, in the embodiment of the present application, a sealing layer is subsequently used to seal the groove, and the groove is filled with air. The air can isolate adjacent active areas and will not cause stacking faults on the sidewalls of the fin structure.

[0045] In some embodiments of the present application, the method for forming the trench 530 in the semiconductor substrate 500 includes: referring to Fig.12 and Fig.13 A sacrificial layer 501 , an anti-reflection layer 502 and a patterned photoresist layer 503 are sequentially formed on the surface of the first dielectric layer 520 , and the patterned photoresist layer 503 defines the position of the groove 530 .

[0046] In some embodiments of the present application, the method of forming the sacrificial layer 501 includes a fluid chemical vapor deposition process (FCVD), and the method of forming the anti-reflection layer 502 and the patterned photoresist layer 503 includes a spin coating process.

[0047] In some embodiments of the present application, the method for forming the trench 530 in the semiconductor substrate 500 further includes: referring to Fig.14 and Fig.15 , using the patterned photoresist layer 503 as a mask to etch the anti-reflection layer 502, the sacrificial layer 501 and the first dielectric layer 520, to form an opening 504 in the first dielectric layer 520, Fig.15 In the embodiment, the first dielectric layer 520 also exposes a portion of the bottom surface of the fin structure 510, where the bottom refers to an end of the fin structure close to the semiconductor substrate. Exposing a portion of the bottom of the fin structure is to enable the growth of an epitaxial layer at the exposed position.

[0048] In some embodiments of the present application, a method of forming the opening 504 includes anisotropic dry etching.

[0049] In some embodiments of the present application, the method for forming the trench 530 in the semiconductor substrate 500 further includes: referring to Fig.16 and Fig.17, using the first dielectric layer 520 as a mask, etching the semiconductor substrate 500 to form the groove 530 , and removing the sacrificial layer 501 , the anti-reflection layer 502 and the patterned photoresist layer 503 .

[0050] In some embodiments of the present application, a method of forming the trench 530 includes anisotropic wet etching or anisotropic dry etching.

[0051] In some embodiments of the present application, the method of removing the sacrificial layer 501 , the anti-reflection layer 502 and the patterned photoresist layer 503 includes wet etching.

[0052] In this method, the opening 504 is first formed, and the position of the groove 530 is further defined by the opening 504, and then etching is performed along the opening 504, so as to improve the position accuracy of the groove 530. For example, after the opening 504 is formed, if it is found that the position of the opening 504 does not conform to the designed position, the position of the opening 504 can be readjusted to prevent the position of the groove 430 formed by subsequent etching from not conforming to the designed position.

[0053] In some other embodiments of the present application, the groove 530 may be formed by etching once using the patterned photoresist layer 503 as a mask, which can save process steps but requires higher photolithography accuracy.

[0054] refer to Fig.18 and Fig.19 , forming a second dielectric layer 521, the second dielectric layer 521 covers the sidewall and bottom of the trench 530 and the surface of the fin structure exposed by the first dielectric layer 520. The second dielectric layer 521 can play a role in isolating adjacent active regions.

[0055] In some embodiments of the present application, the material of the second dielectric layer 521 includes silicon oxide. The method for forming the second dielectric layer 521 includes an in-situ steam generation (ISSG) process. The ISSG process is a process in which high-temperature steam is introduced into a reaction chamber to oxidize the semiconductor material on the surface of the semiconductor substrate to form an oxide.

[0056] refer to Figures 20 to 27, remove part of the second dielectric layer 521 on the top sidewall of the trench 530, part of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the second dielectric layer 521 covering the surface of the fin structure exposed by the first dielectric layer 520. The top sidewall of the trench 530, part of the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the surface of the fin structure exposed by the first dielectric layer 250 are exposed to epitaxially grow an epitaxial layer.

[0057] In some embodiments of the present application, a method for removing a portion of the second dielectric layer 521 on the top sidewall of the trench 530, a portion of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the second dielectric layer 521 covering the surface of the fin structure exposed by the first dielectric layer 520 includes: referring to Fig. 20 and Fig.21 , a hard mask layer 540 is formed on the first dielectric layer 520 and in the trench 530 , and the hard mask layer 540 fills the trench 530 .

[0058] In some embodiments of the present application, the material of the hard mask layer 540 includes silicon-based organic matter.

[0059] In some embodiments of the present application, a method of forming the hard mask layer 540 includes spin coating.

[0060] In some embodiments of the present application, the method of removing a portion of the second dielectric layer 521 on the top sidewall of the trench 530, a portion of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the second dielectric layer 521 covering the surface of the fin structure exposed by the first dielectric layer 520 further includes: referring to Fig. 22 and Fig.23 , the hard mask layer 540 is etched back to make the top surface of the hard mask layer 540 lower than the top surface of the trench 530 .

[0061] In some embodiments of the present application, after the hard mask layer 540 is etched back so that the top surface of the hard mask layer 540 is lower than the top surface of the trench 530, the depth of the portion of the hard mask layer 540 below the trench 530 accounts for 10% to 20% of the depth of the trench. The depth of the portion of the hard mask layer 540 below the trench 530 cannot be too deep, otherwise too much of the trench 530 sidewalls will be exposed later, and the thickness of the epitaxial layer formed by epitaxy will be too thick; the depth of the portion of the hard mask layer 540 below the trench 530 cannot be too shallow, otherwise too little of the trench 530 sidewalls will be exposed later, and the epitaxial layer formed will be too thin.

[0062] In some embodiments of the present application, the method of etching back the hard mask layer 540 includes wet etching or dry etching.

[0063] In some embodiments of the present application, the method of removing a portion of the second dielectric layer 521 on the top sidewall of the trench 530, a portion of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the second dielectric layer 521 covering the surface of the fin structure exposed by the first dielectric layer 520 further includes: referring to Fig.24 and Fig.25 , the portion of the second dielectric layer 521 above the top surface of the hard mask layer 540 and the portion of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the trench 530 are etched away. The top sidewall of the trench 530, a portion of the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the surface of the fin structure exposed by the first dielectric layer 250 are exposed to epitaxially grow an epitaxial layer.

[0064] In some embodiments of the present application, the method of etching and removing the portion of the second dielectric layer 521 above the top surface of the hard mask layer 540 and the portion of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the trench 530 is isotropic etching. The isotropic etching can be dry etching or wet etching.

[0065] In some embodiments of the present application, the method of removing a portion of the second dielectric layer 521 on the top sidewall of the trench 530, a portion of the first dielectric layer 520 on the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the second dielectric layer 521 covering the surface of the fin structure exposed by the first dielectric layer 520 further includes: referring to Fig.26 and Fig. 27 , remove the hard mask layer 540. The trench 530 needs to be filled with air to isolate the active area, and no other fillings are allowed.

[0066] In some embodiments of the present application, the method of removing the hard mask layer 540 includes wet etching.

[0067] refer to Figures 28 to 33 A sealing layer 550 is grown on the top sidewall of the trench 530, the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the surface of the fin structure 510 exposed by the first dielectric layer 520, and the sealing layer 550 seals the top of the trench 530. The sealing layer 550 is used to seal the trench 530 to ensure that the trench 530 is filled with air and will not be filled with other substances in subsequent processes.

[0068] In some embodiments of the present application, a sealing layer 550 is grown on the top sidewall of the trench 530, the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the surface of the fin structure 510 exposed by the first dielectric layer 520. The method of sealing the top of the trench 530 with the sealing layer 550 includes: referring to Fig.28 and Fig.29 , epitaxially growing an epitaxial layer 551 on the top sidewall of the trench 530, the surface of the semiconductor substrate 500 adjacent to the top of the trench 530, and the surface of the fin structure 510 exposed by the first dielectric layer 520, until the epitaxial layer 551 seals the top of the trench 530; Fig.30 and Fig.33 , thinning the epitaxial layer 551 to form the sealing layer 550.

[0069] The material of the epitaxial layer 551 cannot isolate the adjacent active regions, so the epitaxial layer 551 needs to be thinned so that the epitaxial layer 551 can be completely oxidized in a subsequent process to isolate the adjacent active regions.

[0070] In some embodiments of the present application, the method of thinning the epitaxial layer 551 to form the sealing layer 550 includes: referring to Fig.30 and Fig.31 , using an anisotropic dry etching process to thin the epitaxial layer 551 until the top surface of the epitaxial layer 551 is coplanar with the top surface of the semiconductor substrate; Fig.32 and Fig.33 , and the epitaxial layer 551 is further thinned by ashing and wet etching processes. The thickness of the sealing layer 550 is an important factor in whether the sealing layer can be completely oxidized. Since wet etching is easier to control etching accuracy than dry etching, the above-mentioned dry etching plus wet etching two-step thinning can improve the thinning accuracy.

[0071] Among them, reference Fig.32 and Fig.33 , ashing and wet etching processes are used to further thin the epitaxial layer 551. First, a portion of the semiconductor substrate 500 connected to the epitaxial layer 551 is ashed to remove the epitaxial layer 551 so that the epitaxial layer 551 can be further thinned by wet etching. Then, hydrofluoric acid is used as an etching solution to etch the epitaxial layer 551. At the same time, the hydrofluoric acid can also wash away the residues produced by ashing.

[0072] In some embodiments of the present application, the thickness of the sealing layer 550 is 1 nanometer to 5 nanometers, for example, 2 nanometers, 3 nanometers, or 4 nanometers.

[0073] After the sealing layer 550 seals the top of the trench 530 , the trench 530 is filled with air. The trench 530 can isolate adjacent active areas and reduce leakage between adjacent active areas. In addition, the air in the trench 530 will not affect the sidewall of the fin structure.

[0074] In some embodiments of the present application, the method for forming a semiconductor structure further includes: referring to Fig.34 and Fig.35 , forming an isolation material layer 561 on the first dielectric layer 520 and the sealing layer 550 by using an FCVD process, wherein the isolation material layer 561 fills the space between the plurality of fin structures 510 and has a top surface higher than the top surface of the first dielectric layer 520; Fig.36 and Fig.37 , solidify the isolation material layer 561 and completely oxidize the sealing layer 550. After the sealing layer 550 is completely oxidized, the sealing layer 550 can isolate adjacent active regions.

[0075] In some embodiments of the present application, the method of curing the isolation material layer 561 and oxidizing the epitaxial layer 550 includes: treating the isolation material layer 561 with a steam annealing process to cure the isolation material layer 561 and completely oxidize the epitaxial layer 550; treating the isolation material layer 561 with a dry annealing process to further cure the isolation material layer 561. The temperature of the steam annealing process is 600 degrees Celsius to 700 degrees Celsius, and the temperature of the dry annealing process is 900 degrees Celsius to 1200 degrees Celsius.

[0076] In some embodiments of the present application, the method for forming a semiconductor structure further includes: referring to Fig.38 and Fig.39 , planarizing the isolation material layer 561 and the first dielectric layer 520 to expose the mask layer 512 on the top of the fin structure 510; Fig.40 and Fig.41 , doping ions are implanted in different active regions respectively, and a well region 570 and a well region 571 are formed in the semiconductor substrate 500 and at the bottom of the fin structure 510. According to different doping ions, the well region 570 can be a P-type well region or an N-type well region, and the well region 571 can be a P-type well region or an N-type well region. The types of the well region 570 and the well region 571 are different; Fig.42 and Fig.43 , removing the mask layer 512, wherein the method for removing the mask layer 512 comprises wet etching or dry etching; referring to Fig.44 and Fig.45, etching the isolation material layer 561 and a portion of the first dielectric layer 520 to form an isolation structure 560 (the isolation structure 560 includes the oxidized sealing layer 550) surrounding the bottom of the fin 511 (the bottom refers to the end of the fin 511 close to the semiconductor substrate 500), and the method of etching the isolation material layer 561 and the first dielectric layer 520 includes wet etching or dry etching.

[0077] The method for forming a semiconductor structure described in the present application forms a trench 530 filled with air between adjacent active areas. The trench 530 is used to isolate adjacent active areas, thereby reducing leakage between adjacent active areas without affecting the sidewalls of the fin 511 .

[0078] The embodiment of the present application also provides a semiconductor structure, referring to Fig.44 and Fig.45 The semiconductor structure includes: a semiconductor substrate 500, on which a plurality of fins 511 are formed; a trench 530, located in the semiconductor substrate 500, separating adjacent active areas; an isolation structure 560, located on the semiconductor substrate 500 and surrounding the bottom of the fin 511, wherein the isolation structure 560 does not fill the trench 530 and closes the top of the trench 530.

[0079] In some embodiments of the present application, the material of the semiconductor substrate 500 includes (i) an elemental semiconductor, such as silicon or germanium, etc.; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide, or gallium indium phosphide, etc.; or (iv) a combination of the above. In addition, the semiconductor substrate 500 may be doped (e.g., a P-type substrate or an N-type substrate). In some embodiments of the present application, the semiconductor substrate 500 may be doped with a P-type dopant (e.g., boron, indium, aluminum, or gallium) or an N-type dopant (e.g., phosphorus or arsenic).

[0080] Continue to refer Fig.44 and Fig.45 A well region 570 and a well region 571 are formed at the bottom of the semiconductor substrate 500 and the fin 511. Depending on the doping ions, the well region 570 may be a P-type well region or an N-type well region, and the well region 571 may be a P-type well region or an N-type well region, and the well region 570 and the well region 571 are of different types.

[0081] Continue to refer Fig.44 and Fig.45 A first dielectric layer 520 is formed on the semiconductor substrate 500 and the bottom surface of the fin 511. The first dielectric layer 520 can be used to isolate adjacent fins 511.

[0082] In some embodiments of the present application, the material of the first dielectric layer 520 includes silicon oxide.

[0083] Continue to refer Figure 44 to Figure 45 , a groove 530 is formed in the semiconductor substrate 500, and the groove 530 separates adjacent active areas. In some semiconductor structures, a low dielectric constant material (such as silicon oxide, etc.) is filled in the groove to isolate adjacent active areas. However, the low dielectric constant material filling process may cause stacking faults on the sidewalls of the fin structure. Therefore, in the embodiment of the present application, a sealing layer is subsequently used to seal the groove, and the groove is filled with air. The air can isolate adjacent active areas and will not cause stacking faults on the sidewalls of the fin 511.

[0084] Continue to refer Fig.44 and Fig.45 A second dielectric layer 521 is also formed in the semiconductor structure, and the second dielectric layer 521 covers the sidewalls and the bottom of the trench 530. The second dielectric layer 521 can play a role in isolating adjacent active regions.

[0085] In some embodiments of the present application, the material of the second dielectric layer 521 includes silicon oxide.

[0086] Continue to refer Fig.44 and Fig.45 In some embodiments of the present application, the material of the isolation structure 560 includes silicon oxide. The isolation structure 560 is used to isolate the fin 511 .

[0087] The semiconductor structure described in the present application forms air-filled trenches between adjacent active areas. The trenches are used to isolate adjacent active areas, thereby reducing leakage between adjacent active areas without affecting the sidewalls of the fins 511 .

[0088] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0089] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

[0090] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0091] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0092] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, on which a plurality of fin structures are formed, a first dielectric layer is formed on the semiconductor substrate and the fin structures, the first dielectric layer exposes a portion of the bottom surface of the fin structure, and a trench is formed in the semiconductor substrate, the trench separating adjacent active areas; Epitaxially growing a sealing layer on the surface of the top of the trench, wherein the sealing layer seals the top of the trench, and the trench is filled with air; forming an isolation material layer on the first dielectric layer and the sealing layer, wherein the isolation material layer fills the spaces between the plurality of fin structures and a top surface of the isolation material layer is higher than a top surface of the first dielectric layer; The insulating material layer is cured and the sealing layer is oxidized.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure also includes: forming a second dielectric layer, the second dielectric layer covering the sidewalls of the trench and the surface of the fin structure exposed by the first dielectric layer; removing part of the second dielectric layer on the sidewalls of the top of the trench, part of the first dielectric layer on the surface of the semiconductor substrate adjacent to the top of the trench, and the second dielectric layer covering the surface of the fin structure exposed by the first dielectric layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method of removing a portion of the second dielectric layer on the sidewall of the top of the trench, a portion of the first dielectric layer on the surface of the semiconductor substrate adjacent to the top of the trench, and the second dielectric layer covering the surface of the fin structure exposed by the first dielectric layer comprises: forming a hard mask layer on the first dielectric layer and in the trench, wherein the hard mask layer fills the trench; Etching back the hard mask layer so that a top surface of the hard mask layer is lower than a top surface of the trench; Etching and removing a portion of the second dielectric layer that is higher than a top surface of the hard mask layer and a portion of the first dielectric layer on a surface of the semiconductor substrate adjacent to the trench; The hard mask layer is removed.

4. The method for forming a semiconductor structure according to claim 3, wherein: After the hard mask layer is etched back so that the top surface of the hard mask layer is lower than the top surface of the trench, the depth of the portion of the hard mask layer below the trench accounts for 10% to 20% of the depth of the trench.

5. The method for forming a semiconductor structure according to claim 3, wherein: The method of etching and removing the portion of the second dielectric layer above the top surface of the hard mask layer and the portion of the first dielectric layer on the surface of the semiconductor substrate adjacent to the trench is isotropic etching.

6. The method for forming a semiconductor structure according to claim 2, wherein: A method of forming a sealing layer on the sidewall of the top of the trench, the surface of the semiconductor substrate adjacent to the top of the trench, and the surface of the fin structure exposed by the first dielectric layer, wherein the sealing layer seals the top of the trench comprises: epitaxially growing an epitaxial layer on the sidewall of the top of the trench, the surface of the semiconductor substrate adjacent to the top of the trench, and the surface of the fin structure exposed by the first dielectric layer, until the epitaxial layer seals the top of the trench; The epitaxial layer is thinned to form the sealing layer.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method of thinning the epitaxial layer to form the sealing layer comprises: Thinning the epitaxial layer using an anisotropic dry etching process; The epitaxial layer is further thinned by using ashing and wet etching processes.

8. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the sealing layer is 1 nanometer to 5 nanometers.

9. The method for forming a semiconductor structure according to claim 1, wherein: The method of curing the isolation material layer and oxidizing the sealing layer comprises: Treating the isolation material layer and oxidizing the sealing layer by a steam annealing process; The isolation material layer is treated by a dry annealing process.

10. The method for forming a semiconductor structure according to claim 1, wherein: The method further comprises: Planarizing the isolation material layer and the first dielectric layer to expose the top of the fin structure, wherein the fin structure includes a fin located on a semiconductor substrate and a mask layer located on the fin; Performing doping ion implantation in different active regions respectively; removing the mask layer; The isolation material layer and a portion of the first dielectric layer are etched to form an isolation structure surrounding the bottom of the fin.

11. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming the trench in the semiconductor substrate comprises: forming a sacrificial layer, an anti-reflection layer and a patterned photoresist layer in sequence on the surface of the first dielectric layer, wherein the patterned photoresist layer defines the position of the groove; Using the patterned photoresist layer as a mask, etching the anti-reflection layer, the sacrificial layer and the first dielectric layer to form an opening in the first dielectric layer; Using the first dielectric layer as a mask, etching the semiconductor substrate to form the trench; The sacrificial layer, the anti-reflection layer and the patterned photoresist layer are removed.

12. The method for forming a semiconductor structure according to claim 2, wherein: The second dielectric layer is formed by an in-situ steam generation process.

13. A semiconductor structure, characterized in that: include: A semiconductor substrate having a plurality of fins formed thereon; A trench, located in the semiconductor substrate, separating adjacent active regions, the trench being filled with air; An isolation structure is located on the semiconductor substrate and surrounds the bottom of the fin, wherein the isolation structure does not fill the trench and closes the top of the trench.

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