Semiconductor device and method for forming the same

Abstract

The present application provides a semiconductor device and a method for forming the same, the method comprising: providing a semiconductor substrate; removing the first barrier layer and part of the gate layer of the first gate structure, so that the top surface of the gate layer in the first region is lower than the top surface of the gate layer in the second region; forming a stress epitaxial layer in the semiconductor substrate on both sides of the second gate structure; forming a metal silicide layer on the surface of the gate layer in the first region and the surface of the stress epitaxial layer. The semiconductor device and the method for forming the same provided by the present application reduce the height of the gate layer in the first region before the grinding process, so that the height of the gate layer in the first region is lower than the height of the gate layer in the second region, thereby ensuring that the metal silicide layer in the first region will not be ground in the subsequent grinding process, thereby avoiding abnormal grinding process behavior.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Art

[0002] Generally, multiple devices are integrated on an integrated circuit at the same time, such as high voltage devices (HV devices), medium voltage devices (MV devices) and low voltage devices (LV devices), among which the gate dielectric layer thickness of high voltage devices and medium voltage devices is usually much greater than that of low voltage devices. For example, when the gate dielectric layer thickness of low voltage devices is only a few angstroms, the gate dielectric layer thickness of high voltage devices and medium voltage devices can be tens of angstroms, or even hundreds or thousands of angstroms.

[0003] The large height difference between the gate dielectric layers of high- and medium-voltage devices and low-voltage devices results in the surface of the gate layer of high- and medium-voltage devices being much higher than the surface of the gate layer of low-voltage devices when the gate layer is formed on the gate dielectric layers of high- and medium-voltage devices and low-voltage devices. When the interlayer dielectric layer and the metal gate of the low-voltage device are subsequently ground, it is easy to grind the gate layer of the medium-voltage device, causing defects in the performance of the medium-voltage device, thereby affecting the performance of the semiconductor device. Summary of the invention

[0004] The technical problem of the present application is that due to the difference in gate dielectric thickness between the medium-voltage device and the low-voltage device, the metal silicide layer in the medium-voltage device area will be ground during the subsequent grinding process, causing abnormal grinding process behavior and resulting in device damage.

[0005] To solve the above technical problems, the present application discloses a method for forming a semiconductor device, comprising: the semiconductor substrate comprises a first region, a second region and an isolation structure isolating the first region and the second region, a first gate structure is formed on the semiconductor substrate in the first region, one end of the first gate structure extends to the isolation structure, a second gate structure is formed on the semiconductor substrate in the second region, the first gate structure and the second gate structure both comprise a gate dielectric layer, a gate layer located on the gate dielectric layer and a first barrier layer located on the gate layer; the first barrier layer and part of the gate layer in the first region are removed so that the top surface of the gate layer in the first region is lower than the top surface of the gate layer in the second region; a stress epitaxial layer is formed in the semiconductor substrate on both sides of the second gate structure; and a metal silicide layer is formed on the surface of the gate layer in the first region and on the surface of the stress epitaxial layer.

[0006] In an embodiment of the present application, the process of removing the first barrier layer and part of the gate layer of the first gate structure includes: forming a photoresist layer on the second region; etching the first barrier layer and part of the gate layer of the first region so that the top surface of the gate layer of the first region is lower than the top surface of the gate layer of the second gate structure; and removing the photoresist layer.

[0007] In an embodiment of the present application, the thickness of the removed gate layer is 100 angstroms to 400 angstroms.

[0008] In an embodiment of the present application, after removing the first barrier layer and part of the gate layer in the first region, the height difference between the top surface of the gate layer in the first region and the top surface of the gate layer in the second region is 200 angstroms to 500 angstroms.

[0009] In an embodiment of the present application, the thickness of the gate dielectric layer in the first region is 100 angstroms to 300 angstroms, and the thickness of the gate dielectric layer in the second region is 10 angstroms to 100 angstroms.

[0010] In an embodiment of the present application, before forming the stressed epitaxial layer, it also includes forming offset sidewalls on both sides of the gate layer and the gate dielectric layer in the first region and on both sides of the second gate structure: a second barrier layer is deposited on the surface of the semiconductor substrate in the first region and the second region, the surface and side of the gate layer in the first region, the side of the gate dielectric layer in the first region, the surface and side of the second gate structure, and the surface of the isolation structure; the second barrier layer is etched to retain only the second barrier layer on both sides of the gate layer and the gate dielectric layer in the first region and on both sides of the second gate structure to form an offset sidewall.

[0011] In an embodiment of the present application, a material of the second barrier layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbonitride.

[0012] In an embodiment of the present application, the process of forming a stress epitaxial layer in the semiconductor substrate on both sides of the second gate structure includes: forming a first side wall on both sides of the offset side wall of the second gate structure; etching the semiconductor substrate on both sides of the first side wall to form a groove; and growing a stress epitaxial layer in the groove.

[0013] In an embodiment of the present application, the thickness of the stressed epitaxial layer is 400 angstroms to 1000 angstroms.

[0014] In an embodiment of the present application, a metal silicide layer is formed on the surface of the gate layer in the first region and the surface of the stressed epitaxial layer by using a self-aligned metal silicide process.

[0015] In an embodiment of the present application, the material of the metal silicide layer is nickel silicide.

[0016] In an embodiment of the present application, the gate dielectric layer includes at least one layer, the gate dielectric layer includes at least one layer, and the material of the gate dielectric layer includes at least one of titanium nitride, silicon nitride, silicon oxide, hafnium oxide, zinc oxide, and chromium oxide.

[0017] In an embodiment of the present application, the material of the gate layer is polysilicon.

[0018] In an embodiment of the present application, the first barrier layer includes at least one layer, and a material of the first barrier layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbonitride.

[0019] In an embodiment of the present application, after forming the metal silicide layer, it also includes: depositing a third barrier layer on the surface of the first region, the second region and the isolation structure; forming an interlayer dielectric layer on the surface of the third barrier layer; exposing the gate layer of the second gate structure; removing the gate layer of the second gate structure, and forming a metal gate at a corresponding position of the gate layer of the second gate structure.

[0020] In an embodiment of the present application, a material of the third barrier layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbonitride.

[0021] In an embodiment of the present application, the material of the interlayer dielectric layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbon nitride oxide.

[0022] In an embodiment of the present application, the material of the metal gate includes at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.

[0023] The present application also provides a semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate comprising a first region, a second region and an isolation structure isolating the first region and the second region; a first gate dielectric layer, located on the semiconductor substrate in the first region; a second gate dielectric layer, located on the semiconductor substrate in the second region; a first gate layer, located on the first gate dielectric layer, and one end of the first gate dielectric layer and the first gate layer extends to the isolation structure, and a metal silicide layer is formed on the surface of the first gate layer; a metal gate, located on the second gate dielectric layer; a third barrier layer, covering the first region and the second region, and exposing the surface of the metal gate, the top surface of the third barrier layer on the surface of the metal silicide layer is lower than the surface of the metal gate; an interlayer dielectric layer, covering the first region and the second region, and being flush with the top surface of the metal gate.

[0024] In an embodiment of the present application, the material of the first region gate layer includes polysilicon.

[0025] In an embodiment of the present application, the material of the metal gate includes at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.

[0026] Compared with the prior art, the technical solution of this application has at least the following beneficial effects:

[0027] The semiconductor device and the method for forming the same provided by the present application reduce the height of the gate layer in the first region before the grinding process so that the height of the gate layer in the first region is lower than the height of the gate layer in the second region, thereby avoiding contact with the metal silicide layer on the top of the gate layer in the first region during the subsequent grinding process, which would affect the grinding process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor device;

[0030] Figure 2 for Figure 1 The cross-section is cut along the AA position and viewed from the B direction;

[0031] Figure 3-Figure 13 The schematic cross-sectional views corresponding to the steps of the semiconductor device forming method of the present application are shown in FIG. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0034] In the prior art, there is a problem that the difference in gate dielectric layer thickness between the medium-voltage device area and the low-voltage device area causes the structure of the medium-voltage device area to be damaged during the grinding process, resulting in defects in the performance of the medium-voltage device. The cause of the above situation is analyzed in combination with a semiconductor device structure.

[0035] like Figure 1 As shown in FIG. 1 , it is a three-dimensional diagram of an existing semiconductor device structure. It should be noted that: Figure 1 The emphasis is on the positional relationship between the various structures, and the drawing is not strictly based on the size ratio of the device structure.

[0036] The semiconductor device includes a semiconductor substrate 10, the semiconductor substrate 10 includes a first region 11, a second region 12 and an isolation structure 13, the isolation structure 13 isolating the first region 11 from the second region 12. The first region 11 may be a medium voltage device region, the second region 12 may be a low voltage device region, and the medium voltage device and the low voltage device refer to the relative high and low working voltages of the semiconductor components. The working voltage of the medium voltage device is greater than the working voltage of the low voltage device.

[0037] The isolation structure 13 is a deep trench isolation structure with a high aspect ratio. The material filled in the isolation structure 13 ( Figure 1 A first gate structure 14a is formed on the semiconductor substrate of the first region 11, one end of the first gate structure 14a extends to the isolation structure 13, and a second gate structure 14b is formed on the semiconductor substrate of the second region 12.

[0038] For easier understanding of the first gate structure 14a extending onto the isolation structure 13, please refer to Figure 2 . Figure 2for Figure 1 The cross-sectional view is cut along the AA position and viewed from the B direction. It should be noted that the AA position is exactly the position where the first gate structure 14a extends to the isolation structure 13 and the second gate structure 14b is still located on the semiconductor substrate 10. Figure 1 The cross-sectional view taken along the AA position shows that the first gate structure 14a is located on the isolation structure 13, and the second gate structure 14b is located on the semiconductor substrate 10. Figure 1 and Figure 2 As shown, the first gate structure 14a includes a gate dielectric layer 14a1, a gate layer 14a2 located on the gate dielectric layer 14a1, and a barrier layer 14a3 located on the gate layer 14a2. Similarly, the second gate structure 14b includes a gate dielectric layer 14b1, a gate layer 14b2 located on the gate dielectric layer 14b1, and a barrier layer 14b3 located on the gate layer 14b2.

[0039] In some embodiments, the thickness of the gate dielectric layer 14a1 in the first region is much greater than the thickness of the gate dielectric layer 14b1 formed on the surface of the semiconductor substrate in the second region 12. For example, when the thickness of the gate dielectric layer 14b1 is on the order of several angstroms, the thickness of the gate dielectric layer 14a1 can be from tens of angstroms to hundreds of angstroms. Therefore, after the gate layer 14a2 and the gate layer 14b2 are formed in the first region 11 and the second region 12, respectively, the surface of the gate layer 14a2 in the first region 11 will also be much higher than the surface of the gate layer 14b2 in the second region 12.

[0040] When the interlayer dielectric layer is polished in the subsequent process to expose the gate layer 14b2 on the second region 12, the metal silicide on the top of the gate layer 14a2 will be polished, resulting in abnormal chemical mechanical polishing behavior and device failure.

[0041] Based on this, the present application provides a semiconductor device and a method for forming the same, which lowers the height of the gate layer in the first region before the interlayer dielectric layer grinding process, so that the top surface of the gate layer in the first region is lower than the top surface of the gate structure in the second region, thereby avoiding grinding of the metal silicide on the top surface of the gate layer in the first region during the subsequent grinding process.

[0042] The technical solution of the present application is described in detail below in conjunction with the embodiments and drawings. The drawings of the following embodiments of the present application all show cross-sectional views of the gate of the first region extending to the isolation structure, which are not drawn strictly in proportion and are only schematically represented. In addition, in addition to the special limitation on the thickness of the removed gate layer, the thickness of other structures in the technical solution of the present application is selected according to the process and is not limited here.

[0043] The present application provides a method for forming a semiconductor device, comprising:

[0044] Step S1, providing a semiconductor substrate, wherein the semiconductor substrate includes a first region, a second region, and an isolation structure isolating the first region and the second region, a first gate structure is formed on the semiconductor substrate in the first region, one end of the first gate structure extends to the isolation structure, a second gate structure is formed on the semiconductor substrate in the second region, and the first gate structure and the second gate structure both include a gate dielectric layer, a gate layer located on the gate dielectric layer, and a first blocking layer located on the gate layer.

[0045] Step S2, removing the first barrier layer and part of the gate layer in the first region, so that the top surface of the gate layer in the first region is lower than the top surface of the gate layer in the second region.

[0046] Step S3, forming a stressed epitaxial layer in the semiconductor substrate on both sides of the second gate structure.

[0047] Step S4: forming a metal silicide layer on a surface of the gate layer in the first region and a surface of the stressed epitaxial layer.

[0048] Please refer to Figure 3 Step S1, providing a semiconductor substrate 100, the semiconductor substrate 100 can be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes a multilayer structure composed of the material layers or silicon on insulator (SOI), stacked silicon on insulator (SSOI), etc. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon or silicon on insulator.

[0049] The semiconductor substrate 100 includes a first region 110, a second region 120, and an isolation structure 130 isolating the first region 110 from the second region 120. The first region 110 and the second region 120 may both include N-type or P-type doping ions. The first region 110 may be a medium voltage device region, and the second region 120 may be a low voltage device region.

[0050] In some embodiments of the present application, the isolation structure 130 may include an insulating dielectric layer 130a and an oxide layer 130b located between the insulating dielectric layer 130a and the semiconductor substrate. The material of the oxide layer 130b is, for example, a silicon oxide layer, which may be formed by a thermal oxidation process. The material of the insulating dielectric layer 130a may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the insulating dielectric layer 130a is silicon oxide, and the process for forming the insulating dielectric layer 130a may be a chemical vapor deposition process or a physical vapor deposition process. Optionally, the chemical vapor deposition process may be, for example, a high aspect ratio (HARP) deposition process. Of course, the isolation structure 130 may also be any other known trench isolation structure. The method for forming the isolation structure 130 may also be any method for manufacturing a trench isolation structure, which is not limited in the present application.

[0051] A gate structure 140a is formed on the semiconductor substrate of the first region 110, one end of the gate structure 140a extends to the isolation structure 130, and the gate structure 140a includes a gate dielectric layer 140a1, a gate layer 140a2 located on the gate dielectric layer 140a1, and a first barrier layer 140a3 located on the gate layer 140a2. Similarly, a gate structure 140b is formed on the semiconductor substrate of the second region 120, and the gate structure 140b includes a gate dielectric layer 140b1, a gate layer 140b2 located on the gate dielectric layer 140b1, and a first barrier layer 140b3 located on the gate layer 140b2.

[0052] The thickness of the gate dielectric layer in the first region is 100 angstroms to 300 angstroms, and the thickness of the gate dielectric layer in the second region is 10 angstroms to 100 angstroms.

[0053] The gate layer may be made of polysilicon (poly). The gate dielectric layer 140a1 and the gate dielectric layer 140b1 may be one layer or multiple layers, for example, may include a nitride layer and / or an oxide layer, wherein the nitride layer may include at least one of titanium nitride and silicon nitride, and the oxide layer may include at least one of silicon oxide, hafnium oxide, zinc oxide, and chromium oxide.

[0054] The first barrier layer 140a3 and the first barrier layer 140b3 may include one or more layers, such as an oxide layer, a nitride layer, or an oxide layer / nitride layer / oxide layer three-layer structure, etc., depending on the previous process technology, wherein the oxide layer may be silicon dioxide and the nitride layer may be silicon nitride.

[0055] It should be noted that in some embodiments, other film layers (not shown in the figure) are formed between the isolation structure 130 and the gate structure 140a, and between the semiconductor substrate of the second region 120 and the gate structure 140b. The material of the other film layers depends on the previous manufacturing process, for example, it may be silicon oxide.

[0056] Please refer to Figure 4a and Figure 4b , step S2, removing the first barrier layer 140a3 and part of the gate layer 140a2 in the first region, so that the top surface of the gate layer 140a2 in the first region is lower than the top surface of the gate layer 140b2 in the second region. The thickness of the removed gate layer 140a2 is designed according to the actual operation situation, as long as it is ensured that the metal silicide on the gate layer 140a2 in the first region 110 will not be touched during subsequent grinding. For example, the thickness of the removed gate layer 140a2 can be 100 angstroms to 400 angstroms, specifically 100 angstroms, 200 angstroms, 300 angstroms or 400 angstroms. After removing the first barrier layer 140a3 and part of the gate layer 140a2 in the first region 110, the height difference between the top surface of the gate layer 140a2 in the first region 110 and the top surface of the gate layer 140b2 in the second region 120 is 200 angstroms to 500 angstroms.

[0057] In some embodiments of the present application, the process of removing the first barrier layer 140a3 and a portion of the gate layer 140a2 of the first gate structure 140a may specifically include:

[0058] A photoresist layer 150 is formed on the second region 120. Figure 4a As shown;

[0059] The first barrier layer 140a3 and a portion of the gate layer 140a2 of the first gate structure 140a are etched to make the top surface 140a2 of the gate layer of the first gate structure 140a lower than the top surface of the gate layer 140b2 of the second region 120. Figure 4b shown.

[0060] Specifically, the first barrier layer 140a3 and the gate layer 140a2 of the first region 110 may be etched by dry etching, and the type of etching gas may be selected according to the material to be etched. If the first barrier layer 140a3 is a three-layer structure of silicon oxide / silicon nitride / silicon oxide, the etching gas for dry etching silicon oxide may include CF4 or CHF3, and the etching gas for dry etching silicon nitride may include SF6 / O2 or CF4 / O2. When etching the gate layer 140a2, if the material of the gate layer 140a2 is polysilicon, the etching gas may include Cl2.

[0061] After the etching is completed, the photoresist layer 150 is removed. In some embodiments of the present application, the process of removing the photoresist layer 150 is an ashing process. Therefore, when the photoresist layer 150 is removed, a thin natural oxide layer 160 is formed on the surface of the gate layer 140a2 of the first gate structure 140a. Figure 5 shown.

[0062] Step S3 is performed to form a stress epitaxial layer in the semiconductor substrate on both sides of the second gate structure. In some embodiments, before forming the stress epitaxial layer, offset sidewalls are formed on both sides of the gate layer 140a1 and the gate dielectric layer 140a2 of the first region 110 and on both sides of the second gate structure 140b. Figure 6a A second barrier layer 170 is deposited on the surfaces of the semiconductor substrate in the first region 110 and the second region 120, the surface and side surfaces of the gate layer 140a2 in the first region, the side surfaces of the gate dielectric layer in the first region, the surface and side surfaces of the second gate structure 140b, and the surface of the isolation structure 130. The second barrier layer 170 may be grown by chemical vapor deposition or a furnace tube process. The second barrier layer 170 may include a nitride layer, such as silicon nitride.

[0063] Then, the surface of the isolation structure 130, the surface of the gate layer 140a2 in the first region (if the oxide layer 160 formed when removing the photoresist layer 150 in the above process still exists, it is on the surface of the oxide layer 160), the surface of the second gate structure 140b, and the second barrier layer 170 on the surface of the semiconductor substrate in the first region 110 and the second region 120 are removed, and offset sidewalls are formed on both sides of the gate layer 140a1 and the gate dielectric layer 140a2 in the first region and on both sides of the second gate structure 140b, such as Figure 6b That is, only the second barrier layer 170 located at the two sidewall portions of the gate layer 140a1 and the gate dielectric layer 140a2 and the two sidewall portions of the second gate structure 140b is retained to form the offset spacer.

[0064] When removing the second barrier layer 170 , an anisotropic dry etching method may be selected, and the etching gas may include chlorine gas, carbon fluoride, and the like.

[0065] Please combine Figure 7a and Figure 7b As shown, a stressed epitaxial layer 200 , such as a silicon germanium epitaxial layer, is formed in the semiconductor substrate on both sides of the second gate structure 140 b .

[0066] Please refer to Figure 7a, firstly, a first sidewall is formed on both sides of the offset sidewall of the second gate structure 140b (that is, the second barrier layer 170 on both sides of the second gate structure 140b). The first sidewall structure of the embodiment of the present application is an ON (Oxide Nitride) structure. The formation process of the ON structure may be to sequentially deposit an oxide layer 180 and a nitride layer 190 on the second region 120 by chemical vapor deposition, wherein the oxide layer 180 and the nitride layer 190 may be, for example, silicon oxide and silicon nitride. Then, the nitride layer 190 and the oxide layer 180 on the semiconductor surface of the second region 120 and the surface of the gate structure 140b are sequentially etched by anisotropic dry etching, leaving only the nitride layer 190 and the oxide layer 180 on both sides of the gate structure 140b in the second region 120, to form the first sidewall of the ON structure.

[0067] Please refer to Figure 7b , then the semiconductor substrate on both sides of the first sidewall is etched to form a groove, for example, dry etching can be used, and a stress epitaxial layer 200 is grown in the groove. The stress epitaxial layer 200 is, for example, a silicon germanium epitaxial layer. The shape of the silicon germanium epitaxial layer can be a sigma-like shape, which has the best effect on improving semiconductor performance. Of course, other shapes of silicon germanium epitaxial layers can also be selected according to specific process technology. The thickness of the stress epitaxial layer 200 can be 400 angstroms to 1000 angstroms.

[0068] After forming the silicon germanium epitaxial layer, the source and drain can be formed by ion implantation, which will not be described in detail here.

[0069] Please refer to Figure 8a and Figure 8b In step S4, a metal silicide layer 220 is formed on the surface of the gate layer 140a2 in the first region 110 and the surface of the stressed epitaxial layer 200. The metal silicide layer 220 is formed by adopting a self-aligned metal silicide process.

[0070] Please refer to Figure 8a After the SAB etching process, the second sidewall 210 is formed on both sides of the offset sidewall of the first region 110 and the first sidewall of the second region 120. At the same time, after the SAB etching process, the oxide layer 160 on the surface of the gate layer 140a2 on the first region 110 is removed, exposing the surface of the gate layer 140a, in preparation for the subsequent formation of metal silicide.

[0071] Please refer to Figure 8b , a metal, such as nickel, is deposited on the surface of the gate layer 140a2 and the stress epitaxial layer 200, so that the polysilicon on the surface of the gate layer 140a2 and the stress epitaxial layer 200 reacts with the deposited metal to form a metal silicide layer, such as nickel silicide. Since there is a barrier layer on the surface of the gate layer 140b2, a metal silicide layer cannot be formed.

[0072] After the metal silicide layer 220 is formed, subsequent process steps may be performed. For example, the following conventional steps may be included:

[0073] A third barrier layer 230 is deposited on the surface of the first region 110, the second region 120 and the isolation structure 130. The third barrier layer 230 may be at least one of a nitride layer, silicon oxide, silicon oxynitride and silicon carbonitride, such as silicon nitride. Fig. 9 shown.

[0074] Reference Fig.10a To Attachment Fig.10b An interlayer dielectric layer 240 is deposited on the surface of the third barrier layer 230 , and the surface of the interlayer dielectric layer 240 is substantially level with the top surface of the gate structure 140 b 2 in the second region 120 .

[0075] Please refer to Fig.10a As shown, a dielectric material layer 240a is deposited on the surface of the third barrier layer 230, and the dielectric material layer 240a completely covers the first region 110 and the second region 120, and the top surface of the entire dielectric material layer 240a is higher than the top surfaces of the first gate structure and the second gate structure. In this embodiment, the material of the dielectric material layer 240a includes at least one of silicon nitride, silicon oxide, silicon oxynitride, and silicon oxycarbonitride, for example, silicon oxide, and the process for forming the dielectric material layer 240a can be a chemical vapor deposition process or a physical vapor deposition process, such as a plasma vapor deposition process.

[0076] Reference Fig.10b As shown, the dielectric material layer 240a is planarized to completely expose the third barrier layer 230 on the surface of the second gate structure 140b, and the dielectric material layer 240a is converted into an interlayer dielectric layer 240, and the surface of the interlayer dielectric layer 240 is basically level with the top surface of the third barrier layer 230 on the surface of the second gate structure 140b.

[0077] Since the surface of the second barrier layer 230 of the first region 110 is lower than the top surface of the third barrier layer 230 of the second gate structure 140b, when the process of planarizing the dielectric material layer 240a is stopped, the metal silicide layer 220 of the first region will not be etched, and the planarization process is, for example, a chemical mechanical polishing process (CMP). After the interlayer dielectric layer 240 is formed, the surfaces of the interlayer dielectric layer 240 of the first region and the second region are substantially horizontal, and the top surface of the third barrier layer 230 on the surface of the second gate structure 140b is substantially horizontal with the surface of the interlayer dielectric layer 240. The "substantially horizontal" described in the embodiments of the present application means that it is completely horizontal or that although it is expected to be completely horizontal, due to process operation and control issues, the two relative planes are substantially on the same horizontal plane, and the surface height difference is within the maximum error range allowed by the process.

[0078] Please refer to the attached Fig.11 As shown, the gate layer 140b2 of the second gate structure 140b is exposed. The third barrier layer 230 and the first barrier layer 140b3 on the gate layer 140b2 need to be removed in sequence, and the removal process is, for example, a dry etching process, and the plasma used in the dry etching process includes CF4.

[0079] Please refer to the attached Fig.12 and 13 As shown, the gate layer 140b2 of the second gate structure 140b is removed, and a metal gate 250 is formed at a corresponding position of the gate layer 140b2 of the second gate structure 140b. The process of removing the gate layer 140b2 of the second gate structure 140b is, for example, a dry etching process. The process of forming the metal gate is, for example, chemical vapor deposition or physical vapor deposition, and a metal gate material is deposited on the surface of the gate dielectric layer 140b1. The metal gate material is also deposited on the entire surface of the interlayer dielectric layer 240. Therefore, a planarization process such as a CMP process is subsequently used to grind the metal gate material until there is no metal gate material on the interlayer dielectric layer 240 in the first region, and the surface of the metal gate material on the surface of the gate dielectric layer 140b1 is substantially level with the surface of the interlayer dielectric layer 240, so as to form a metal gate 250. The metal gate material includes at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN. The metal gate material described in the embodiment of the present application is, for example, metal aluminum.

[0080] The method for forming a semiconductor device provided in the present application etches the gate layer of the first region before the grinding process so that the top of the gate layer of the first region is lower than the top of the gate layer of the second region, thereby avoiding grinding of the metal silicide layer on the gate layer of the first region in the subsequent CMP process, resulting in abnormal mechanical behavior and damage to the device structure.

[0081] The present application also provides a semiconductor device. Fig.13 The structure is basically the same, only the device name is slightly different from the above, but the actual structure is the same.

[0082] Please continue to refer to Fig.13 , the semiconductor device comprises: a semiconductor substrate 100, the semiconductor substrate 100 comprising a first region 110, a second region 120 and an isolation structure 130 isolating the first region 110 and the second region 120;

[0083] A first gate dielectric layer 140a1, located on the semiconductor substrate in the first region 110;

[0084] A second gate dielectric layer 140b1, located on the semiconductor substrate in the second region 120;

[0085] A first gate layer 140a2 is located on the first gate dielectric layer 140a1, and one end of the first gate dielectric layer 140a1 and the first gate layer 140a2 extends to the isolation structure 130, and a metal silicide layer 220 is formed on the surface of the first gate layer 140a2;

[0086] A metal gate 250, located on the second gate dielectric layer 140b1;

[0087] A third barrier layer 230 covers the first region 110 and the second region 120 and exposes the surface of the metal gate 250 , wherein the top surface of the third barrier layer 230 on the surface of the metal silicide layer 220 is lower than the surface of the metal gate 250 ;

[0088] The interlayer dielectric layer 240 covers the first region 110 and the second region 120 and is flush with the top surface of the metal gate 250 .

[0089] In an embodiment of the present application, the material of the first gate layer 140a2 includes polysilicon. The material of the metal gate 250 includes at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.

[0090] In summary, after reading this detailed disclosure, it will be apparent to those skilled in the art that the foregoing detailed disclosure may be presented only by way of example and may not be limiting. Although not explicitly stated herein, it will be appreciated by those skilled in the art that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are intended to be proposed by this disclosure and are within the spirit and scope of the exemplary embodiments of this disclosure.

[0091] In addition, certain terms in this application have been used to describe embodiments of the present disclosure. For example, "one embodiment", "embodiment" and / or "some embodiments" mean that a particular feature, structure or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present disclosure. Therefore, it can be emphasized and should be understood that two or more references to "embodiment" or "one embodiment" or "alternative embodiment" in various parts of this specification do not necessarily refer to the same embodiment. In addition, specific features, structures or characteristics may be appropriately combined in one or more embodiments of the present disclosure.

[0092] It should be understood that in the foregoing description of the embodiments of the present disclosure, in order to help understand a feature and for the purpose of simplifying the present disclosure, the present application sometimes combines various features in a single embodiment, drawing or its description. Alternatively, the present application disperses various features in multiple embodiments of the present application. However, this does not mean that the combination of these features is necessary. It is entirely possible for those skilled in the art to extract some of the features and understand them as separate embodiments when reading the present application. In other words, the embodiments in the present application can also be understood as the integration of multiple secondary embodiments. This is also true when the content of each secondary embodiment is less than all the features of a single aforementioned disclosed embodiment.

[0093] In some embodiments, the numbers expressing the quantity or properties of certain embodiments of the present application used to describe and claim protection should be understood as being modified in some cases by the terms "about", "approximately" or "substantially". For example, unless otherwise stated, "about", "approximately" or "substantially" may represent a ±20% variation of the value described. Therefore, in some embodiments, the numerical parameters listed in the written description and the attached claims are approximate values, which may vary depending on the desired properties that a particular embodiment attempts to obtain. In some embodiments, the numerical parameters should be interpreted according to the number of reported significant figures and by applying ordinary rounding techniques. Although some embodiments of the present application are described, the numerical ranges and parameters listed in a wide range are approximate, but the numerical values ​​that are as accurate as possible are listed in the specific examples.

[0094] Each patent, patent application, patent application publication, and other materials, such as articles, books, specifications, publications, documents, articles, etc., cited herein may be incorporated herein by reference in its entirety for all purposes, except for any prosecution document history related thereto, any equivalent that may be inconsistent or conflicting with this document, or any equivalent prosecution document history that may have a limiting effect on the broadest scope of the claims now or later associated with this document. For example, if there is any inconsistency or conflict between the description, definition, and / or use of a term associated with any of the incorporated materials and the term, description, definition, and / or use associated with this document, the term in this document shall control.

[0095] Finally, it should be understood that the embodiments of the application disclosed herein are explanations of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Therefore, the embodiments disclosed in the present application are merely examples and not limitations. Those skilled in the art can adopt alternative configurations according to the embodiments in the present application to implement the application in the present application. Therefore, the embodiments of the present application are not limited to which embodiments have been accurately described in the application.

Claims

1. A method for forming a semiconductor device, characterized in that: include: A semiconductor substrate is provided, the semiconductor substrate comprising a first region, a second region, and an isolation structure isolating the first region from the second region, a first gate structure is formed on the semiconductor substrate in the first region, one end of the first gate structure extends to the isolation structure, a second gate structure is formed on the semiconductor substrate in the second region, the first gate structure and the second gate structure both comprise a gate dielectric layer, a gate layer located on the gate dielectric layer, and a first barrier layer located on the gate layer, the first region is a medium-voltage device region, the second region is a low-voltage device region, the thickness of the gate dielectric layer in the first gate structure is greater than the thickness of the gate dielectric layer in the second gate structure, and the surface of the gate layer in the first gate structure is higher than the surface of the gate layer in the second gate structure; removing the first barrier layer and part of the gate layer in the first region, so that the top surface of the gate layer in the first region is lower than the top surface of the gate layer in the second region; forming a stressed epitaxial layer in the semiconductor substrate on both sides of the second gate structure; A metal silicide layer is formed on a surface of the gate layer in the first region and a surface of the stressed epitaxial layer.

2. The method for forming a semiconductor device according to claim 1, wherein: The process of removing the first barrier layer and a portion of the gate layer of the first gate structure includes: forming a photoresist layer on the second region; Etching the first barrier layer and a portion of the gate layer in the first region so that a top surface of the gate layer in the first region is lower than a top surface of the gate layer of the second gate structure; The photoresist layer is removed.

3. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the gate layer removed is 100 angstroms to 400 angstroms.

4. The method for forming a semiconductor device according to claim 1, wherein: After the first barrier layer and part of the gate layer in the first region are removed, the height difference between the top surface of the gate layer in the first region and the top surface of the gate layer in the second region is 200 angstroms to 500 angstroms.

5. The method for forming a semiconductor device according to claim 1, wherein: The thickness of the gate dielectric layer in the first region is greater than 100 angstroms and less than or equal to 300 angstroms, and the thickness of the gate dielectric layer in the second region is 10 angstroms to 100 angstroms.

6. The method for forming a semiconductor device according to claim 1, wherein: Before forming the stress epitaxial layer, the method further includes forming offset sidewalls on both sides of the gate layer and the gate dielectric layer in the first region and on both sides of the second gate structure: Depositing a second barrier layer on the surface of the semiconductor substrate in the first region and the second region, the surface and side of the gate layer in the first region, the side of the gate dielectric layer in the first region, the surface and side of the second gate structure, and the surface of the isolation structure; The second barrier layer is etched to retain only the second barrier layer on both sides of the gate layer and the gate dielectric layer in the first region and on both sides of the second gate structure to form an offset sidewall.

7. The method for forming a semiconductor device according to claim 6, wherein: The material of the second barrier layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbonitride.

8. The method for forming a semiconductor device according to claim 6, wherein: The process of forming a stressed epitaxial layer in the semiconductor substrate on both sides of the second gate structure includes: Forming a first spacer on both sides of the offset spacer of the second gate structure; Etching the semiconductor substrate on both sides of the first sidewall to form a groove; A stressed epitaxial layer is grown in the recess.

9. The method for forming a semiconductor device according to claim 8, wherein: The thickness of the stress epitaxial layer is 400 angstroms to 1000 angstroms.

10. The method for forming a semiconductor device according to claim 1, wherein: A metal silicide layer is formed on the surface of the gate layer in the first region and the surface of the stress epitaxial layer by using a self-aligned metal silicide process.

11. The method for forming a semiconductor device according to claim 1, wherein: The material of the metal silicide layer includes nickel silicide.

12. The method for forming a semiconductor device according to claim 1, wherein: The gate dielectric layer includes at least one layer, and the material of the gate dielectric layer includes at least one of titanium nitride, silicon nitride, silicon oxide, hafnium oxide, zinc oxide, and chromium oxide.

13. The method for forming a semiconductor device according to claim 1, wherein: The material of the gate layer includes polysilicon.

14. The method for forming a semiconductor device according to claim 1, wherein: The first barrier layer includes at least one layer, and a material of the first barrier layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbonitride.

15. The method for forming a semiconductor device according to claim 1, wherein: After forming the metal silicide layer, the method further comprises: Depositing a third barrier layer on the surfaces of the first region, the second region and the isolation structure; forming an interlayer dielectric layer on a surface of the third barrier layer; exposing the gate layer of the second gate structure; The gate layer of the second gate structure is removed, and a metal gate is formed at a corresponding position of the gate layer of the second gate structure.

16. The method for forming a semiconductor device according to claim 15, wherein: The material of the third barrier layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride and silicon carbonitride.

17. The method for forming a semiconductor device according to claim 15, wherein: The material of the interlayer dielectric layer includes at least one of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbon nitride oxide.

18. The method for forming a semiconductor device according to claim 15, wherein: The material of the metal gate includes at least one of W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and TaSiN.

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