Semiconductor device and method for forming the same

Abstract

A semiconductor device and a method for forming the same. The semiconductor device includes a well region located in a substrate. A source region and a drain region are arranged in the substrate on opposite sides of the well region. A gate electrode is arranged above the well region, and the gate electrode has a bottom surface arranged below the topmost surface of the substrate and extending between the source region and the drain region. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source region, the drain region, and the trench isolation structure. The gate electrode structure has a center portion and a corner portion. The center portion has a first thickness, and the corner portion has a second thickness greater than the first thickness.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device and a method for forming the same. Background Art

[0002] Many electronic devices contain numerous metal oxide semiconductor field-effect transistors (MOSFETs). A MOSFET includes a gate disposed between a source and a drain. MOSFETs can be classified as high voltage (HV), medium voltage (MV), or low voltage (LV) devices, depending on the magnitude of the voltage applied to the gate to turn on the MOSFET. The structural design parameters of each MOSFET in an electronic device vary depending on the desired electrical properties. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device, comprising: a well region located in a substrate; a source region and a drain region arranged in the substrate on opposite sides of the well region; a gate electrode arranged above the well region, the gate electrode comprising a bottom surface arranged below the topmost surface of the substrate and extending between the source region and the drain region; a trench isolation structure surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure separating the gate electrode from the well region, the source region, the drain region and the trench isolation structure, wherein the gate dielectric structure comprises a central portion having a first thickness and a corner portion having a second thickness, and wherein the second thickness is greater than the first thickness.

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a well region located in a substrate; a source region and a drain region arranged in the substrate on opposite sides of the well region; a gate electrode arranged in the substrate and directly between the source region and the drain region; a trench isolation structure continuously surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure arranged on the outer sidewall and bottom surface of the gate electrode, wherein the gate dielectric structure comprises a central portion having a first thickness, an inner corner portion having a second thickness greater than the first thickness, and an outer corner portion having a third thickness greater than the second thickness, and wherein the first thickness, the second thickness and the third thickness are measured along the same direction from the bottommost surface of the gate dielectric structure.

[0005] An embodiment of the present invention provides a method, comprising: forming a trench isolation structure to surround a well region of a substrate; removing a portion of the substrate to form a recess in the substrate, wherein the outer sidewalls of the recess are defined by the trench isolation structure; forming a first gate dielectric layer above the surface of the recess in the substrate; forming a second gate dielectric layer above the first gate dielectric layer; performing a removal process to remove central portions of the first gate dielectric layer and the second gate dielectric layer, wherein after the removal process, a portion of the first gate dielectric layer and a portion of the second gate dielectric layer remain on the trench isolation structure; forming a third gate dielectric layer above the surface of the recess in the substrate and above the second gate dielectric layer; and forming a gate electrode above the third gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B Cross-sectional views of some embodiments of a recessed metal oxide semiconductor field effect transistor (MOSFET) are shown, which includes a gate dielectric structure having corner portions that are thicker than a central portion.

[0008] Figure 2A and Figure 2B Shown separately Figure 1A and Figure 1B Cross-sectional views of some alternative embodiments of recessed MOSFETs.

[0009] Figure 3 Cross-sectional views of some embodiments of a recessed MOSFET having a gate electrode surrounded by a gate dielectric structure and extending between source / drain regions are shown.

[0010] Figure 4 A top view of a recessed MOSFET is shown, which includes a gate dielectric structure having corner portions that are thicker than a central portion.

[0011] Figure 5A and Figure 5B A cross-sectional view of some embodiments from another perspective of a recessed MOSFET including a gate dielectric structure having corner portions that are thicker than a center portion is shown.

[0012] Figure 6Cross-sectional views of some embodiments of two recessed MOSFETs disposed on and within a substrate and including a gate dielectric structure having corner portions that are thicker than a center portion are shown.

[0013] Figure 7 A graph of current versus gate voltage is shown when applied to a recessed MOSFET including a gate dielectric structure having corner portions that are thicker than a center portion.

[0014] FIG. 8A to FIG. 8C , FIG. 9A to FIG. 9C as well as FIG. 10A to FIG. 10C Various views of some alternative embodiments of recessed MOSFETs are shown that include a gate dielectric structure having corner portions that are thicker than a center portion.

[0015] Fig.11A and FIG. 11B to FIG. 27A and Fig.27B Various views of some embodiments of a method of forming a recessed MOSFET including a gate dielectric structure having corner portions that are thicker than a center portion are shown.

[0016] Fig.28 Shown with Fig.11A and FIG. 11B to FIG. 27A and Fig.27B The method shown in is a flowchart of some embodiments of the method. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided themes. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted likewise accordingly.

[0019] A metal oxide semiconductor field effect transistor (MOSFET) includes a gate electrode disposed between a source region and a drain region on a substrate. In addition, a gate dielectric layer may be disposed between the gate electrode and the substrate. In medium voltage (MV) devices, the gate dielectric layer is thicker than in low voltage (LV) devices to withstand higher voltages without breakdown. However, the thicker gate dielectric layer may increase the overall height of the MV device compared to LV devices. Therefore, some MV devices may utilize a recessed MOSFET, in which the gate dielectric layer and the gate electrode are recessed below the topmost surface of the substrate in a lateral direction and are directly located between the source region and the drain region.

[0020] Although recessed MOSFETs reduce the height of MV devices, the reliability of recessed MOSFETs may be affected. For example, as the gate voltage applied to the gate electrode increases, the increase in current through the recessed MOSFET may not have a substantially constant slope as the voltage increases. In some cases, the inconsistent behavior of current versus voltage is due to the gate dielectric layer being thinner at the lower corner of the gate electrode near the recessed substrate, resulting in different threshold voltages at different regions of the gate electrode.

[0021] Various embodiments of the present disclosure relate to forming a gate dielectric structure having an outer portion of a thicker corner surrounding a gate electrode in a recessed MOSFET to improve the predictability, controllability, and reliability of the overall recessed MOSFET. In such embodiments, the thicker corner of the gate dielectric structure may be arranged at an area of ​​the gate dielectric structure that directly contacts the trench isolation structure and is arranged at the corner of the source region and the drain region. The trench isolation structure may continuously surround the recessed MOSFET, and the gate electrode may extend from a first side of the trench isolation structure to a second side of the trench isolation structure. In some embodiments, to increase the thickness of the corner of the gate dielectric structure, a second gate dielectric layer above the first gate dielectric layer is formed in a recessed portion of the substrate. Then, the center portion of the first gate dielectric layer and the second gate dielectric layer is removed by photolithography and removal processes, so that the remaining portion of the first gate dielectric layer and the second gate dielectric layer directly overlies the trench isolation structure. In some embodiments, a third dielectric layer is then formed above the second dielectric layer and the substrate. Therefore, a majority of the gate dielectric structure has a first thickness of the third dielectric layer, while a corner portion of the gate dielectric structure has a second thickness equivalent to the sum of the thicknesses of the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer. The corner portion of the gate dielectric structure can prevent an undesired current from flowing in the substrate below the corner portion. As the thickness of the corner portion of the overlying trench isolation structure of the gate dielectric structure increases, the reliability of the recessed MOSFET is improved.

[0022] Figure 1A A cross-sectional view 100A of some embodiments of an integrated chip including a recessed metal oxide semiconductor field effect transistor (MOSFET) having a gate dielectric structure with thicker corner portions is shown.

[0023] Figure 1A The cross-sectional view 100A can be taken from the yz plane of the recessed MOSFET, while the source region and the drain region of the recessed MOSFET can be seen in the xz plane perpendicular to the yz plane (see Figure 3 ). Figure 1A The cross-sectional view 100A of FIG. 1 includes a substrate 101. In some embodiments, the substrate 101 may be or include a semiconductor material (e.g., silicon, germanium, etc.), may be a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In some embodiments, the substrate 101 includes a well region 102. The well region 102 may have a higher doping concentration and / or a different doping type than the substrate 101. For example, in some embodiments, the substrate 101 may be undoped, and the well region 102 may have a first doping type (e.g., p-type) or a second doping type (e.g., n-type).

[0024] In some embodiments, the trench isolation structure 104 is disposed within the substrate 101 and surrounds the well region 102 and / or an area of ​​the substrate 101. In some embodiments, the trench isolation structure 104 is a shallow trench isolation (STI) structure such that the trench isolation structure 104 extends into the substrate 101 to a depth between the front side and the back side of the substrate 101. In other embodiments, the trench isolation structure 104 can be a full or deep trench isolation structure such that the trench isolation structure 104 extends completely or almost completely through the thickness of the substrate 101. In some embodiments, the trench isolation structure 104 includes a dielectric material such as silicon dioxide and prevents signals (e.g., current, voltage) of the recessed MOSFET from interfering with other devices on the substrate 101 outside the area of ​​the well region 102 surrounded by the trench isolation structure 104.

[0025] In some embodiments, the gate electrode 108 is disposed in the substrate 101. In some embodiments, the gate electrode 108 extends from a first side of the trench isolation structure 104 to a second side of the trench isolation structure 104 in the y direction. In some embodiments, a spacer structure 110 may be disposed above the substrate 101. In some embodiments, the spacer structure 110 is mainly used during the formation of the gate electrode 108 and / or other features of the recessed MOSFET. In some embodiments, an interconnect structure 112 is disposed above the substrate 101. In some embodiments, the interconnect structure 112 includes a contact via 116 and an interconnect wire 118 in the interconnect dielectric structure 114. The interconnect structure 112 may provide a conductive path between the gate electrode 108 of the integrated chip and other devices.

[0026] In some embodiments, the gate electrode 108 has a topmost surface 108t that is approximately flat with the topmost surface 101t of the substrate 101. Therefore, the bottommost surface 108b of the gate electrode 108 is disposed below the topmost surface 101t of the substrate 101. Since the gate electrode 108 is recessed below the substrate 101, the overall height of the recessed MOSFET can be reduced.

[0027] In some embodiments, the gate dielectric structure 106 is disposed on the outer surface and the lower surface of the gate electrode 108. The gate dielectric structure 106 may include: a central portion 106a covering the bottommost surface 108b of the gate electrode 108; and a corner portion 106b surrounding the central portion 106a and disposed on the lower surface and the outer sidewall of the gate electrode 108. In some embodiments, the corner portion 106b of the gate dielectric structure 106 directly contacts the trench isolation structure 104 and a portion of the well region 102 of the substrate 101. In some embodiments, the corner portion 106b of the gate dielectric structure 106 further includes an inner corner portion 106c and an outer corner portion 106d. In such embodiments, the inner corner portion 106c may couple the central portion 106a of the gate dielectric structure 106 to the outer corner portion 106d.

[0028] In some embodiments, the central portion 106a of the gate dielectric structure 106 has a first thickness t1; the inner corner portion 106c of the gate dielectric structure 106 has a second thickness t2 that is greater than the first thickness t1; and the outer corner portion 106d of the gate dielectric structure 106 has a third thickness t3 that is approximately equal to or greater than the second thickness t2. In such embodiments, the first thickness t1, the second thickness t2, and the third thickness t3 are all measured in the z-direction and measured from the bottommost surface of the gate dielectric structure 106. In some embodiments, the corner portion 106b of the gate dielectric structure 106 may include three gate dielectric layers, while the central portion 106a of the gate dielectric structure 106 may include one gate dielectric layer. In some embodiments, the gate dielectric layers constituting the gate dielectric structure 106 include the same or similar material (e.g., oxide), and thus, in the cross-sectional view 100A, it may be difficult to distinguish the individual gate dielectric layers of the gate dielectric structure 106. In some embodiments, the corner portion 106 b has a greater thickness than the central portion 106 a of the gate dielectric structure 106 to ensure that the gate dielectric structure 106 of the recessed MOSFET has a sufficiently thick corner portion 106 b to reduce undesired current flow in the substrate 101 , thereby improving the predictability and reliability of the recessed MOSFET.

[0029] Figure 1B Show Figure 1A A cross-sectional view 100B of an alternative embodiment of the cross-sectional view 100A is shown, in which the layers of the gate electrode structure are depicted.

[0030] Figure 1BThe gate dielectric structure 106 includes a first gate dielectric layer 120, a second gate dielectric layer 122 disposed above the first gate dielectric layer 120, and a third gate dielectric layer 124. In some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 include the same or similar materials, and thus Figure 1B , the interfaces between the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 are shown by dashed lines. In some embodiments, the second gate dielectric layer 122 includes a high temperature oxide material. In some embodiments, the corner portion 106b of the gate dielectric structure 106 includes the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124, while the center portion 106a of the gate dielectric structure 106 includes the third gate dielectric layer 124, but does not include the first gate dielectric layer 122 and the second gate dielectric layer 124. Therefore, in some embodiments, the first thickness t1 is equal to the thickness of the third gate dielectric layer 124. In some embodiments, the addition of the first gate dielectric layer 122 and the second gate dielectric layer 124 increases the thickness of the gate dielectric structure 106 at the corner portion 106b of the gate dielectric structure 106.

[0031] In some embodiments, the sum of the thicknesses of the first gate dielectric layer 120 and the second gate dielectric layer 122 is equal to the difference between the first thickness t1 and the second thickness t2. In some embodiments, the ratio of the difference between the first thickness t1 and the second thickness t2 to the first thickness t1 is, for example, in a range between approximately 1.5 and approximately 3. In some embodiments, the ratio of the difference between the first thickness t1 and the second thickness t2 to the third thickness t3 is, for example, in a range between approximately 0.25 and approximately 0.33. In some embodiments, the ratio between the first thickness t1 and the third thickness t3 is, for example, in a range between approximately 0.125 and approximately 0.18. In some embodiments, the ratio between the second thickness t2 and the third thickness t3 is, for example, in a range between approximately 0.5 and approximately 1.

[0032] In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 of the corner portion 106b of the gate dielectric structure 106 extend from the trench isolation structure 104 to directly above the well region 102 to a first distance d1. In some embodiments, the first distance d1 may be in a range of, for example, between approximately 0.1 microns and approximately 0.3 microns. In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 of the corner portion 106b of the gate dielectric structure 106 extend above the trench isolation structure 104 to a second distance d2. In some embodiments, the ratio between the first distance d1 and the second distance d2 is in a range of, for example, between approximately 0.5 and approximately 2. In some embodiments, the third distance d3 is measured between the outermost sidewalls of the gate dielectric structure 106, and the fourth distance d4 separates the opposing first gate dielectric layers 120. In some embodiments, the ratio between the first distance d1 and the fourth distance d4 is in a range of, for example, between approximately 0.01 and approximately 0.2. In some embodiments, a ratio between the fourth distance d4 and the third distance d3 is in a range between approximately 0.9 and approximately 0.99, for example.

[0033] Figure 2A A cross-sectional view 200A is shown of some other embodiments of a recessed MOSFET including a gate dielectric structure having corner portions that are thicker than a center portion.

[0034] In some embodiments, the gate electrode 108 has a bottommost surface 108b disposed below the topmost surface 101t of the substrate 101, and has a topmost surface 108t disposed above the topmost surface 101t of the substrate 101. In some such embodiments, the recessed MOSFET still has an overall reduced height because the gate electrode 108 has a bottommost surface 108b disposed below the topmost surface 101t of the substrate 101. In some embodiments, the spacer structure 110 is disposed on the topmost surface 101t of the substrate 101 and / or the gate dielectric structure 106, and directly contacts the outermost sidewalls of the gate electrode 108. Furthermore, in some embodiments, a silicide layer 202 may be disposed over the gate electrode 108 to improve the performance of the contact between the contact via 116 and the gate electrode 108.

[0035] In some embodiments, due to the corner portion 106b of the gate dielectric structure 106, the gate electrode 108 includes a lower portion 108L that is disposed directly on the central portion 106a of the gate dielectric structure 106 and has an outer sidewall surrounded by the inner corner portion 106c of the gate dielectric structure 106. In addition, in some embodiments, the gate electrode 108 includes an upper portion 108U that is disposed above the lower portion 108L, directly on the inner corner portion 106c of the gate dielectric structure 106 and has an outer sidewall surrounded by the outer corner portion 106d of the gate dielectric structure 106. In some embodiments, the upper portion 108U of the gate electrode 108 is wider than the lower portion 108L of the gate electrode 108. In some embodiments, the lower portion 108L of the gate electrode 108 may have a width measured in the y-direction and in a range of, for example, between approximately 0.1 micrometers and approximately 100 micrometers. Furthermore, in some embodiments, the upper portion 108U of the gate electrode 108 is thicker than the lower portion 108L of the gate electrode 108. In some other embodiments, the upper portion 108U of the gate electrode 108 may be thinner or approximately equal in thickness to the lower portion 108L of the gate electrode 108.

[0036] In some embodiments, the gate electrode 108 may include, for example, polysilicon, aluminum, cobalt, ruthenium, or some other suitable conductive material. In addition, in some embodiments, the gate dielectric structure 106 may include, for example, silicon oxynitride, silicon dioxide, hafnium oxide, or some other suitable dielectric material. In some embodiments, the first thickness t1 of the gate dielectric structure 106 may be, for example, in a range between approximately 100 angstroms and approximately 300 angstroms. In some embodiments, the second thickness t2 of the gate dielectric structure 106 may be, for example, in a range between approximately 300 angstroms and approximately 500 angstroms. In some embodiments, the third thickness t3 of the gate dielectric structure 106 may be, for example, in a range between approximately 0.08 microns and approximately 2 microns. It should be understood that other values ​​of the first thickness t1, the second thickness t2, and the third thickness t3 are also within the scope of the present disclosure.

[0037] Figure 2B Show Figure 2A A cross-sectional view 200B of an alternative embodiment of the cross-sectional view 200A is shown, in which the layers of the gate electrode structure are depicted.

[0038] like Figure 2B As shown in the cross-sectional view 200B of FIG. 1 , in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 of the gate dielectric structure 106 may be distinguishable from each other. In some embodiments, the gate electrode 108 directly contacts only the third gate dielectric layer 124 of the gate dielectric structure 106.

[0039] Figure 3 A cross-sectional view 300 of some embodiments of a recessed MOSFET from the xz plane is shown.

[0040] In some embodiments, the xz plane is substantially perpendicular to Figure 1A and Figure 2A In some embodiments, the recessed MOSFET includes a source / drain region 302 disposed in a region of the substrate 101 defined by the trench isolation structure 104. In some embodiments, the source / drain region 302 may have a doping type opposite to that of the well region 102. In some embodiments, the source / drain region 302 is surrounded by a lightly doped region 304, wherein the lightly doped region 304 has the same doping type as the source / drain region 302 but a lower doping concentration.

[0041] In some embodiments, in the cross-sectional view 300, the gate electrode 108 extends between the source / drain regions 302 in the x-direction and is also recessed in the substrate 101. In some embodiments, the interconnect structure 112 has a contact via 116 coupled to the source / drain regions 302 and the gate electrode 108. In some embodiments, the source / drain regions 302 are disposed directly between the gate electrode 108 and the trench isolation structure 104 in the x-direction. In some embodiments, the spacer structure 110 is disposed on the substrate 101 and directly contacts the outer sidewalls of the gate electrode 108. In other embodiments, the gate electrode 108 has a topmost surface 108t that is substantially coplanar with the topmost surface 101t of the substrate 101, and thus the spacer structure 110 does not directly contact the gate electrode 108.

[0042] In some embodiments, the corner portion (106b) of the gate dielectric structure 106 is not visible from the cross-sectional view 300 on the xz plane. In some embodiments, the gate dielectric structure 106 surrounds the bottom surface and outer sidewalls of the gate electrode 108 from the xz plane to prevent the gate electrode 108 from contacting the well region 102, the lightly doped region 304 and / or the source / drain region 302. In some embodiments, the gate dielectric structure 106 has a first thickness t1 from the xz plane, and thus the gate dielectric structure 106 directly disposed between the source / drain region 302 may include a gate dielectric layer having the first thickness t1. In some such embodiments, the gate dielectric structure 106 includes a third gate dielectric layer 124 from the xz plane, and the first gate dielectric layer and the second gate dielectric layer ( Figure 2AThe gate dielectric structure 106 has a substantially uniform first thickness t1 surrounding the gate electrode 108 between the source / drain regions 302, so that the same "ON" gate voltage can be used to simultaneously "turn on" the entire channel region under the gate electrode 108 to allow mobile charge carriers to move between the source / drain regions 302.

[0043] Figure 4 A top view 400 of some embodiments of a recessed MOSFET transistor including a gate dielectric structure with thicker corner portions is shown.

[0044] In some embodiments, Figure 2A The cross-sectional line AA' may correspond to Figure 4 The cross-sectional line AA', and Figure 3 The cross-sectional line BB' may correspond to Figure 4 Cross-section line BB'.

[0045] Figure 4 The top view 400 shows that in some embodiments, the outer corner portion 106d of the gate dielectric structure 106 directly overlies the trench isolation structure 104. In addition, the inner corner portion 106c of the gate dielectric structure 106 is arranged below the gate electrode 108 and is not visible from the top view 400. Therefore, for ease of understanding, Figure 4 106c is shown by dashed lines in FIG. 106. In some embodiments, the inner corner portion 106c is disposed directly between the outer portions of the source / drain regions 302. In some embodiments, any line extending through the source / drain regions 302 along the x-direction does not also extend through the outer corner portion 106d of the gate dielectric structure 106. In some other embodiments, the inner corner portion 106c is not disposed directly between the outer portions of the source / drain regions 302, and thus any line extending through the source / drain regions 302 along the x-direction does not also extend through the inner corner portion 106c of the gate dielectric structure 106.

[0046] Figure 5A A cross-sectional view 500A illustrates some embodiments of a recessed MOSFET transistor including a gate dielectric structure with thicker corner portions extending between isolation structures on the xz plane. In some embodiments, the cross-sectional view 500A includes a gate dielectric structure corresponding to a gate dielectric structure having a plurality of gate dielectric layers extending between isolation structures on the xz plane. Figure 4 Cross-sectional line CC'. Cross-sectional line CC'.

[0047] Figure 4 The cross-sectional line CC' of FIG. 1 extends through the corner portion 106b of the gate dielectric structure 106. Therefore, in some embodiments, Figure 5AThe cross-sectional view 500A shows the corner portion 106b extending between opposite sides of the trench isolation structure 104. In other words, from some perspectives, the gate dielectric structure 106 continuously has the second thickness t2 as it extends between the trench isolation structures 104 in the x-direction.

[0048] Figure 5B Show Figure 5A A cross-sectional view 500B of an alternative embodiment of the cross-sectional view 500A is shown, in which the layers of the gate electrode structure are depicted.

[0049] like Figure 5B As shown in the cross-sectional view 500B, in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 of the gate dielectric structure 106 may be distinguishable from each other and extend between opposite sides of the trench isolation structure 104 in the x-direction.

[0050] Figure 6 A cross-sectional diagram 600 of some embodiments of a first recessed MOSFET disposed next to a second recessed MOSFET on the yz plane is shown.

[0051] In some embodiments, the integrated chip includes a first recessed MOSFET 602 disposed next to a second recessed MOSFET 604. In some embodiments, the first recessed MOSFET 602 may be an n-type MOSFET, wherein when the first recessed MOSFET 602 is “on”, the mobile charge carriers are electrons. In such embodiments, the first recessed MOSFET 602 may have a first well region 102a that is p-type. In some embodiments, the second recessed MOSFET 604 may be a p-type MOSFET, wherein when the second recessed MOSFET 604 is “on”, the mobile charge carriers are holes. In such embodiments, the second recessed MOSFET 604 may have a second well region 102b that is n-type.

[0052] In some embodiments, the first recessed MOSFET 602 and the second recessed MOSFET 604 include a gate dielectric structure 106 having a corner portion 106 b having a greater thickness than a center portion 106 a. In some embodiments, the interconnect structure 112 further includes an interconnect via 620 and a bonding pad 622. Other integrated chips and / or semiconductor devices can be coupled to the first recessed MOSFET 602 and / or the second recessed MOSFET 604 through the bonding pad 622.

[0053] Figure 7A graph 700 showing some embodiments of current versus gate voltage when applied to a recessed MOSFET having a gate dielectric structure with thicker corner portions than the center portion, such as for example Figures 1A to 6 As shown in .

[0054] Graph 700 shows exemplary data points 702 of the absolute value of the current in a recessed MOSFET as a function of the current applied to the gate electrode ( Figure 3 In some embodiments, when the gate voltage is equal to the transition voltage 704 and the first transition current 708 travels through the recessed MOSFET, current begins to flow through the recessed MOSFET. In some embodiments, as the gate voltage increases from the transition voltage 704, the current can increase at a substantially constant rate until the current reaches a saturation current 712 at the threshold voltage 706, where the channel region is at the gate electrode ( Figure 3 108) below and the source / drain region ( Figure 3 In some embodiments, due to the gate dielectric structure ( Figure 2A The corner part of 106) ( Figure 2A 106b), so the entire recessed MOSFET (for example, in Figure 2A The cross-sectional view 200A and Figure 3 The threshold voltage 706 of the first transition current 708 (at the cross-sectional view 300 of FIG. 1 ) is substantially the same, and thus the slope 710 of the exemplary data point 702 is actually substantially constant between the first transition current 708 and the saturation current 712. Compared to a case where the slope 710 varies between the first transition current 708 and the saturation current 712, a recess MOSFET having a substantially constant slope 710 is more reliable.

[0055] FIG. 8A to FIG. 8C Various views 800A to 800C illustrate some alternative embodiments of recessed MOSFETs having a gate dielectric structure including corner portions that are thicker than a center portion.

[0056] like Fig. 8A As shown in the top view 800A of FIG. 8 , in some embodiments, the corner portion 106 b of the gate dielectric structure 106 does not extend continuously between the outermost portions of the gate dielectric structure 106 in the x-direction.

[0057] Figure 8B The cross-sectional view 800B shows the Fig. 8A In some embodiments, Fig. 8A The cross-sectional line AA' corresponds to Figure 8BIn other words, in some embodiments, Figure 8B The cross-sectional view 800B corresponds to Fig. 8A The cross-sectional line AA' of the top view 800A. In addition, Fig. 8A The top view 800A corresponds to Figure 8B The cross-sectional line AA'.

[0058] like Figure 8B As shown in the cross-sectional view 800B, Fig. 8A The cross-sectional line AA′ of FIG. 1 extends through the corner portion 106 b of the gate dielectric structure 106 . Therefore, in some embodiments, Figure 8B The cross-sectional view 800B of FIG. 8 includes a gate dielectric structure 106 having a corner portion 106 b that surrounds a center portion 106 a and is thicker than the center portion 106 a .

[0059] Figure 8C The cross-sectional view 800C shows the Fig. 8A In some embodiments, Fig. 8A The cross-sectional line CC' corresponds to Figure 8C In other words, in some embodiments, Figure 8C The cross-sectional view 800C corresponds to Fig. 8A In addition, Fig. 8A The top view 800A corresponds to Figure 8C Cross-sectional line CC'.

[0060] In some embodiments, the corner portion 106b having the second thickness t2 extends completely between opposite sides of the trench isolation structure 104. However, in some embodiments, the corner portion 106b may not directly overlie the trench isolation structure 104 or may only partially overlie the trench isolation structure 104. In some other embodiments, the corner portion 106b may not directly overlie the trench isolation structure 104 or may only partially overlie the trench isolation structure 104. Figure 8C In the cross-sectional view 800C, from the xz-plane, the trench isolation structure 104 is continuously underlying the entire gate dielectric structure 106 .

[0061] In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 are disposed directly between the third gate dielectric layer 124 and the well region 102. Furthermore, in some embodiments, the third gate dielectric layer 124 surrounds the outermost sidewalls of the first gate dielectric layer 120 and the second gate dielectric layer 122 perpendicular to the x-direction as viewed in the xz plane. In some such embodiments, the third gate dielectric layer 124 separates the first gate dielectric layer 120 and the second gate dielectric layer 122 from the trench isolation structure 104.

[0062] FIG. 9A to FIG. 9CVarious views 900A to 900C show some other alternative embodiments of recessed MOSFETs having a gate dielectric structure including corner portions that are thicker than a center portion.

[0063] like Fig. 9A As shown in the top view 900A of FIG. 1 , in some embodiments, a plurality of corner portions 106 b are disposed above the trench isolation structure 104. In some such embodiments, a line extending in the x-direction may intersect the plurality of corner portions 106 b.

[0064] In some embodiments, Fig. 9A The cross-sectional line AA' corresponds to Fig. 9B In other words, in some embodiments, Fig. 9B The cross-sectional view 900B corresponds to Fig. 9A The cross-sectional line AA' of the top view 900A. In addition, Fig. 9A The top view 900A corresponds to Fig. 9B The cross-sectional line AA'.

[0065] like Fig. 9B As shown in the cross-sectional view 900B, Fig. 9A The cross-sectional line AA' of FIG. 1 extends through the corner portion 106b of the gate dielectric structure 106 in the y-direction. Therefore, in some embodiments, Fig. 9B The cross-sectional view 900B includes a gate dielectric structure 106 having corner portions 106 b that surround a central portion 106 a and are thicker than the central portion 106 a.

[0066] Fig. 9C The cross-sectional view 900C shows the Fig. 9A In some embodiments, Fig. 9A The cross-sectional line CC' corresponds to Fig. 9C In other words, in some embodiments, Fig. 9C The cross-sectional view 900C corresponds to Fig. 9A The cross-sectional line CC' of the top view 900A. In addition, Fig. 9A The top view 900A corresponds to Fig. 9C Cross-sectional line CC'.

[0067] like Fig. 9C As shown in the cross-sectional view 900C of FIG. 1 , in some embodiments, a plurality of corner portions 106 b of the gate dielectric structure 106 are arranged between opposite sides of the trench isolation structure 104 in the x-direction. In some embodiments, the third gate dielectric layer 124 continuously extends between the corner portions 106 b.

[0068] FIG. 10A to FIG. 10C Various views 1000A to 1000C show some other alternative embodiments of recessed MOSFETs having a gate dielectric structure including corner portions that are thicker than a center portion.

[0069] like Fig. 10A As shown in the top view 1000A of FIG. 1 , in some embodiments, the corner portion 106b of the gate dielectric structure 106 includes an additional inner corner portion 106e, wherein the inner corner portion 106c is between the outer corner portion 106d and the additional inner corner portion 106e. In some embodiments, the additional inner corner portion 106e is directly disposed between the source / drain regions 302, while in other embodiments, the additional inner corner portion 106e is not directly disposed between the source / drain regions 302. In addition, in some embodiments, Fig. 10A From the top view 1000A of , the additional inner corner portion 106e is arranged behind the gate electrode 108 and is therefore shown by a dashed line.

[0070] In some embodiments, Fig. 10A The cross-sectional line AA' corresponds to Fig. 10B In other words, in some embodiments, Fig. 10B The cross-sectional view 1000B corresponds to Fig. 10A The cross-sectional line AA' of the top view 1000A. In addition, Fig. 10A The top view 1000A corresponds to Fig. 10B The cross-sectional line AA'.

[0071] like Fig. 10B As shown in the cross-sectional view 1000B, Fig. 10A The cross-sectional line AA' of FIG. 1 extends through the corner portion 106b of the gate dielectric structure 106 in the y-direction. Therefore, in some embodiments, Fig. 10BThe cross-sectional view 1000B of 1000B includes a gate dielectric structure 106 having a corner portion 106b, which surrounds a central portion 106a and is thicker than the central portion 106a. In addition, in some embodiments, the gate dielectric structure 106 includes an additional inner corner portion 106e, which is thicker than the central portion 106a and the inner corner portion 106c of the gate dielectric structure 106. In some such embodiments, the additional inner corner portion 106e may include a thicker portion 122a of the second gate dielectric layer 122. In some such embodiments, the additional inner corner portion 106e of the gate dielectric structure 106 may be arranged directly above the well region 102, rather than directly above the trench isolation structure 104. In some other embodiments, the additional inner corner portion 106e may directly overlie the trench isolation structure 104. In some embodiments, the additional inner corner portion 106 e is thicker than the inner corner portion 106 c , which further reduces undesired current flow in the well region 102 of the substrate 101 .

[0072] Fig. 10C The cross-sectional view 1000C shows the Fig. 10A In some embodiments, Fig. 10A The cross-sectional line CC' corresponds to Fig. 10C In other words, in some embodiments, Fig. 10C The cross-sectional view 1000C corresponds to Fig. 10A The cross-sectional line CC' of the top view 1000A. In addition, Fig. 10A The top view 1000A corresponds to Fig. 10C Cross-sectional line CC'.

[0073] like Fig. 10C As shown in the cross-sectional view 1000C of FIG. 1000B , in some embodiments, the corner portion 106 b includes a first gate dielectric layer 120, a second gate dielectric layer 122, and a third gate dielectric layer 124 extending continuously between opposite sides of the trench isolation structure 104 as viewed from the xz plane. In some such embodiments, Fig. 10A The cross-sectional line CC' does not intersect the additional inner corner portion 106e, and thus the additional inner corner portion ( Fig. 10A 106e) does not exist in Fig. 10C In the cross-sectional view 1000C.

[0074] Fig.11A and FIG. 11B to FIG. 27A and Fig.27BVarious views 1100A and 1100B to 2700A and 2700B illustrate some embodiments of a method of forming a recessed MOSFET having a gate dielectric structure having thicker corner portions than a center portion. Fig.11A and FIG. 11B to FIG. 27A and Fig.27B , but it should be understood that Fig.11A and FIG. 11B to FIG. 27A and Fig.27B The structure disclosed in is not limited to this method, but instead can stand alone as a structure independent of the method.

[0075] like Fig.11A As shown in cross-sectional view 1100A of , a substrate 101 is provided. In various embodiments, the substrate 101 may include any type of semiconductor body (e.g., silicon / CMOS bulk, SiGe, SOI, etc.) and any other type of semiconductor material, the semiconductor body being, for example, a semiconductor wafer or one or more dies on a wafer. In some embodiments, a trench isolation structure 104 may be formed in the substrate 101. The trench isolation structure 104 may be formed by selectively etching the substrate 101 to form a trench defined by the sidewalls of the substrate 101. Subsequently, the trench is filled with one or more dielectric materials, such as silicon dioxide, thereby forming the trench isolation structure 104. In some embodiments, the trench isolation structure 104 continuously surrounds a region of the substrate 101. In some embodiments, the cross-sectional view 1100A represents the trench isolation structure 104 from the perspective of the xz plane and from the yz plane.

[0076] Fig. 11B It is shown that it can correspond to Fig.11A 1100B of some embodiments. In some embodiments, Fig. 11B The cross-sectional line AA' corresponds to Fig.11A 1100A is a cross-sectional view of the substrate 101. The top view 1100B is in the xy plane. In some embodiments, the trench isolation structure 104 is a continuously connected ring structure in the substrate 101.

[0077] In the following FIG. 12A to FIG. 27B In the figure, the "A" diagram represents a step in the method of forming a recessed MOSFET from a cross-sectional view on the yz plane, the "B" diagram represents a step in the method of forming a recessed MOSFET from a cross-sectional view on the xz plane; and the "C" diagram represents a step in the method of forming a recessed MOSFET from a top view on the xy plane. For example, Fig. 12A The cross-sectional view 1200A is in the yz plane, Fig. 12B The cross-sectional view 1200B is in the xz plane, and Fig. 12C The top view 1200C is in the xy plane. In addition, Fig. 12A, Fig. 12B as well as Fig. 12C The same step of the method is shown from different planes / viewing angles.

[0078] like Fig. 12A As shown in the cross-sectional view 1200A of , the recess 1202 is formed by photolithography and subsequent etching of the substrate 101 between the trench isolation structures 104. In some embodiments, the inner portion of the trench isolation structure 104 is removed, and thus the recess 1202 has an outer sidewall defined by the trench isolation structure 104. In some embodiments, the depth of the recess 1202 is in a range of, for example, approximately 0.08 microns to approximately 2 microns. In addition, in some embodiments, an ion implantation process is performed on the substrate 101 to form a well region 102 between the trench isolation structures 104. In some embodiments, the well region 102 also extends below the trench isolation structure 104 and / or exceeds the outer sidewalls of the trench isolation structure 104. In some embodiments, the well region 102 has a first doping type (e.g., n-type) or a second doping type (e.g., p-type).

[0079] like Fig. 12B As shown in the cross-sectional view 1200B of FIG. 1 , in some embodiments, the recess 1202 does not extend into the trench isolation structure 104. Therefore, from the perspective of the xz plane, the recess 1202 has an outer sidewall defined by the substrate 101. In addition, in some embodiments, the recess 1202 is relatively thin in the x direction. Fig. 12A It is narrower in the y direction.

[0080] like Fig. 12C As shown in the top view 1200C of FIG. 1200A , in some embodiments, the recess 1202 extends between the trench isolation structures 104 in the y-direction. From the top view 1200C, the outer sidewalls of the recess 1202 are defined using dashed lines. In some embodiments, Fig. 12A The cross-sectional view 1200A corresponds to Fig. 12C The cross-sectional line AA', and Fig. 12B The cross-sectional view 1200B corresponds to Fig. 12C Cross-section line BB'.

[0081] like Fig.13AAs shown in the cross-sectional view 1300A of , the first gate dielectric layer 120 is deposited on the surface of the recess 1202. In some embodiments, the first gate dielectric layer 120 may include, for example, silicon dioxide, silicon oxynitride, hafnium oxide, or some other suitable dielectric material. In some embodiments, the first gate dielectric layer 120 is formed by means of a thermal oxidation process. In other embodiments, the first gate dielectric layer 120 may be formed by means of a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.). In some embodiments, the first gate dielectric layer 120 is formed on the upper surface of the trench isolation structure 104, while in other embodiments, the first gate dielectric layer 120 is not formed on the upper surface of the trench isolation structure 104. In some embodiments, the first gate dielectric layer 120 has a fourth thickness t4 that is substantially uniform on the surface of the recess 1202. In some embodiments, the fourth thickness t4 is in a range between, for example, approximately 100 angstroms and approximately 200 angstroms.

[0082] like Fig. 13B As shown in the cross-sectional view 1300B of FIG. 1300B , in some embodiments, the first gate dielectric layer 120 can also be seen from the xz plane. In some embodiments, the first gate dielectric layer 120 is also formed over a portion of the topmost surface 101t of the substrate 101.

[0083] like Fig.14A A cross-sectional view 1400A and Fig. 14B As shown in the cross-sectional view 1400B of FIG. 1400B , in some embodiments, the lightly doped region 304 is formed directly between the trench isolation structure 104 and the recess 1202 along the x-direction. Therefore, in some embodiments, Fig.14A The cross-sectional view 1400A is not Fig.13A and Fig.14A In some embodiments, the lightly doped region 304 is formed using photolithography and ion implantation processes, such that the lightly doped region 304 is disposed directly between the trench isolation structure 104 and the recess 1202 and also has a different doping type from the well region 102 .

[0084] In some other embodiments, the lightly doped region 304 and / or the well region 102 are formed before the first gate dielectric layer 120 is formed in the recess 1202. Therefore, it should be understood that FIG. 11A to FIG. 14B The order of the steps of the methods shown in FIG. 5 may be varied.

[0085] like Fig.15A A cross-sectional view 1500A and Fig. 15BAs shown in the cross-sectional view 1500B of , the second gate dielectric layer 122 is formed directly on the first gate dielectric layer 120. In some embodiments, the second gate dielectric layer 122 includes the same material as the first gate dielectric layer 120. In some other embodiments, the second gate dielectric layer 122 may include a different material from the first gate dielectric layer 120. In some embodiments, the second gate dielectric layer 122 may be formed by means of chemical vapor deposition (CVD) or by means of some other suitable deposition process (e.g., PVD, ALD, etc.). In addition, in some embodiments, the second gate dielectric layer 122 may include a high temperature oxide. For example, in some embodiments, the second gate dielectric layer 122 may include silicon dioxide formed at a high temperature. In some such embodiments, the reactants to form the high temperature silicon dioxide may include dichlorosilane and nitrous oxide, and may react in a chamber set to a temperature in a range between, for example, approximately 800 degrees Celsius and approximately 1000 degrees Celsius. In some other embodiments, the high temperature oxide may include silicon oxynitride.

[0086] In some embodiments, the second gate dielectric layer 122 has a fifth thickness t5 that is substantially uniform over the first gate dielectric layer 120. In some embodiments, the fifth thickness t5 is in a range between, for example, approximately 100 angstroms and approximately 200 angstroms.

[0087] like Fig.16A A cross-sectional view 1600A and Fig. 16B As shown in the cross-sectional view 1600B of FIG. 1600B , in some embodiments, the first mask structure 1602 is formed directly over a portion of the first gate dielectric layer 120 and a portion of the second gate dielectric layer 122 that directly contacts and / or directly overlies the trench isolation structure 104. Therefore, in some embodiments, the first mask structure 1602 can be seen on the yz plane. Fig.16A 1600A, but not visible in the xz plane. Fig. 16B 1600B. In some other embodiments, the first mask structure 1602 may cover the trench isolation structure 104 from the xz plane and is therefore visible from the xz plane. In some embodiments, the first mask structure 1602 also directly overlies a portion of the well region 102 that is in direct contact with the first gate dielectric layer 120. In some embodiments, the first mask structure 1602 directly overlies a portion of the well region 102 by a first distance d1 measured in the y direction. In some embodiments, the first distance d1 is in a range between, for example, approximately 0.1 microns and approximately 0.3 microns.

[0088] In some embodiments, the first mask structure 1602 may be formed using a photolithography and removal (eg, etching) process. In some embodiments, the first mask structure 1602 includes a photoresist material or a hard mask material. In some embodiments, the first mask structure 1602 also directly covers the Fig.16A In some other embodiments, the first mask structure 1602 may also be formed over the entire trench isolation structure 104, and thus in some embodiments, the first mask structure 1602 may exist Fig. 16B The cross-sectional view 1600B is directly above the trench isolation structure 104.

[0089] like Fig. 16C As shown in the top view 1600C of FIG. 1600 , in some embodiments, the first mask structure 1602 resembles two rectangles. In some embodiments, Fig.16A The cross-sectional view 1600A corresponds to Fig. 16C The cross-sectional line AA', and Fig. 16B The cross-sectional view 1600B corresponds to Fig. 16C In some other embodiments, from Fig. 16C From the top view 1600C, the first mask structure 1602 can also completely cover the trench isolation structure 104 to protect the trench isolation structure 104 from subsequent removal processes.

[0090] In some other embodiments, from the top view 1600C, the first mask structure 1602 has different designs to implement different gate electrode structure designs, such as FIG. 8A to FIG. 8C , FIG. 9A to FIG. 9C and / or FIG. 10A to FIG. 10C For example, in some other embodiments, the design shown in Fig. 16C In some such other embodiments, the alternative first mask structure 1602a is used to replace the first mask structure 1602. In such other embodiments, the alternative first mask structure 1602a shown by the dashed line is narrower than the recess 1202 in the x-direction. In some such other embodiments, the alternative first mask structure 1602a can be used to form FIG. 8A to FIG. 8C The embodiment shown in .

[0091] like Fig.17A A cross-sectional view 1700A and Fig. 17B As shown in the cross-sectional view 1700B of FIG. 1700B , in some embodiments, a removal process is performed to remove a portion of the first gate dielectric layer 120 and a portion of the second gate dielectric layer 122 that are not directly below the first mask structure 1602. Therefore, in some embodiments, Fig.17A and Fig. 17BThe removal process removes the central portion of the first gate dielectric layer 120 and the second gate dielectric layer 122, so that the remaining portions of the first gate dielectric layer 120 and the second gate dielectric layer 122 directly contact the trench isolation structure 104 along the yz plane. In some embodiments, Fig.17A and Fig. 17B The removal process may include a dry etching process performed substantially in the z-direction. Fig.17A and Fig. 17B After the removal process, the recess 1202 includes some lower surfaces and outer sidewalls defined by the substrate 101 and / or regions of the substrate 101 (eg, the well region 102 and the lightly doped region 304 ).

[0092] In some embodiments, the trench isolation structure 104 is Fig.17A and Fig. 17B In some other embodiments, the first mask structure 1602 covers the entire trench isolation structure 104, and thus the first mask structure 1602 prevents the use of Fig.17A and Fig. 17B The trench isolation structure is removed by a removal process.

[0093] like Fig. 17C As shown in the top view 1700C of FIG. 1700A , in some embodiments, the first gate dielectric layer and the second gate dielectric layer ( Fig.17A 120, 122) do not exist because the first gate dielectric layer and the second gate dielectric layer ( Fig.17A 120, 122) behind the first mask structure 1602. In some embodiments, Fig.17A The cross-sectional view 1700A corresponds to Fig. 17C The cross-sectional line AA', and Fig. 17B The cross-sectional view 1700B corresponds to Fig. 17C Cross-section line BB'.

[0094] like Fig.18A The cross-sectional view 1800A and Fig.18B As shown in the cross-sectional view 1800B, in some embodiments, the first mask structure ( Fig.16A1602) and forming a third gate dielectric layer 124 over the surface of the recess 1202 and over the second gate dielectric layer 122. In some embodiments, the third gate dielectric layer 124 may include the same material as the first gate dielectric layer 120 and / or the second gate dielectric layer 122, while in some other embodiments, the third gate dielectric layer 124 may include a different material from the first gate dielectric layer 120 and / or the second gate dielectric layer 122. In some embodiments, the third gate dielectric layer 124 may be formed by chemical vapor deposition (CVD) or by some other suitable deposition process (e.g., PVD, ALD, etc.). In some embodiments, the third gate dielectric layer 124 has a substantially uniform first thickness t1 over the first gate dielectric layer 120. In some embodiments, the first thickness t1 is in a range of, for example, approximately 100 angstroms and approximately 300 angstroms.

[0095] like Fig. 18C As shown in the top view 1800C of FIG. 1800A , in some embodiments, the second gate dielectric layer 122 is shown by a dotted line to illustrate that the second gate dielectric layer 122 is only arranged under certain portions of the third gate dielectric layer 124. In some embodiments, Fig.18A The cross-sectional view 1800A corresponds to Fig. 18C The cross-sectional line AA', and Fig.18B The cross-sectional view 1800B corresponds to Fig. 18C Cross-section line BB'.

[0096] like Fig.19A The cross-sectional view 1900A and Fig.19B As shown in the cross-sectional view 1900B of FIG. 1900B, in some embodiments, a gate electrode material 1902 is then formed over the third gate dielectric layer 124 and fills the recess in the substrate 101 ( Fig.18A and Fig.18B 1202). In some embodiments, the gate electrode material 1902 may be formed by a deposition process (e.g., CVD, PVD, ALD, sputtering, electroplating, etc.). In some embodiments, the gate electrode material 1902 may include polysilicon, aluminum, cobalt, ruthenium, or some other suitable conductive material.

[0097] like Fig. 20A Cross-sectional view 2000A and Fig. 20B As shown in the cross-sectional view 2000B of FIG. 2000B , in some embodiments, the gate electrode material ( Fig.19A1902) to form a gate electrode 108 having a substantially flat topmost surface 108t. Since the topmost surface 108t of the gate electrode 108 is substantially flat, the subsequently deposited layers above the gate electrode 108 may also have a substantially flat upper surface. In some embodiments, the gate electrode material ( Fig.19A The topmost surface 108t of the gate electrode 108 is planarized (e.g., CMP) so that the topmost surface 108t of the gate electrode 108 is substantially planar with the topmost surface 101t of the substrate 101. In some other embodiments, the topmost surface 108t of the gate electrode 108 may be subjected to a planarization process (e.g., CMP) and a removal process (e.g., etching) so that the topmost surface 108t of the gate electrode 108 is arranged above the topmost surface 101t of the substrate 101. In some other embodiments (not shown), the work function layer may be formed in the recess ( Fig.18A 1202) and above or below the gate electrode 108 to further adjust the threshold voltage of the recessed MOSFET.

[0098] Furthermore, in some embodiments, Fig. 20A and Fig. 20B A planarization process (e.g., CMP) and / or some other removal process (e.g., etching) may remove any portion of the first gate dielectric layer 120, the second gate dielectric layer 122, and / or the third gate dielectric layer 124 disposed above the topmost surface 101t of the substrate 101. Fig. 20A and Fig. 20B After the planarization process and / or removal process, the first gate dielectric layer 120, the second gate dielectric layer 122 and the third gate dielectric layer 124 form a gate dielectric structure 106 surrounding the gate electrode 108. Fig. 20A From the cross-sectional view 2000A of FIG. 2 , the gate dielectric structure 106 includes a central portion 106a, which includes only the third gate dielectric layer 124 and has a first thickness t1. In some embodiments, the first thickness t1 is measured from the bottommost surface 106L of the gate dielectric structure 106 to the first middle surface 106f of the gate dielectric structure 106, wherein the first middle surface 106f is between the bottommost surface 106L and the topmost surface 106t of the gate dielectric structure 106. In some embodiments, the first thickness t1 is measured from the bottommost surface 106L of the gate dielectric structure 106 to the first middle surface 106f of the gate dielectric structure 106. Fig. 20B From the cross-sectional view 2000B, the gate dielectric structure 106 only includes the third gate dielectric layer 124 and thus has a first thickness t1.

[0099] In addition, the gate dielectric structure 106 includes a corner portion 106b surrounding the central portion 106a and directly overlying the trench isolation structure 104. The corner portion 106b of the gate dielectric structure 106 has a second thickness t2, which is equal to the sum of the thicknesses (t4, t5, t1) of the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124. In some embodiments, the second thickness t2 is measured between the bottommost surface 106L of the gate dielectric structure 106 and the second middle surface 106s of the gate dielectric structure 106, wherein the second middle surface 106s of the gate dielectric structure 106 is between the first middle surface 106f and the topmost surface 106t of the gate dielectric structure 106. In some embodiments, the corner portion 106b also has a third thickness t3, which can be defined as the height of the gate dielectric structure 106 and measured in the z-direction from the bottommost surface 106L to the topmost surface 106t of the gate dielectric structure 106. The first thickness t1, the second thickness t2, and the third thickness t3 are all measured in the same z-direction. The second thickness t2 is greater than the first thickness t1 to ensure that the ratio of current to gate voltage is substantially constant to improve the reliability of the recessed MOSFET. In some embodiments, the second thickness t2 is at least three times the first thickness t1 because in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 can each be at least 100 angstroms thick.

[0100] like Fig. 20C As shown in the top view 2000C of FIG. 1 , in some embodiments, the first gate dielectric layer 120, the second gate dielectric layer 122, and the third gate dielectric layer 124 are visible. In some embodiments, the first gate dielectric layer 120 and the second gate dielectric layer 122 directly overlie the trench isolation structure 104. In some embodiments, the first gate dielectric layer 120 and / or the second gate dielectric layer 122 also directly overlie and contact a portion of the well region ( Fig. 20A 102). In some embodiments, Fig. 20A The cross-sectional view 2000A corresponds to Fig. 20C The cross-sectional line AA', and Fig. 20B The cross-sectional view 2000B corresponds to Fig. 20C Cross-section line BB'.

[0101] like Fig.21A A cross-sectional view 2100A, Fig. 21B A cross-sectional view 2100B and Fig. 21CAs shown in the top view 2100C of FIG. 1 , a hard mask layer 2102 may be formed over the gate electrode 108. In some embodiments, the hard mask layer 2102 may also directly overlie some or all of the gate dielectric structure 106. In some embodiments, the hard mask layer 2102 includes a hard mask material, such as silicon nitride, silicon carbide, or some other suitable hard mask material. In some embodiments, the hard mask layer 2102 is first deposited over the substrate 101 by means of a deposition process (e.g., CVD, PVD, ALD, etc.), and then patterned by means of a photolithography process and a removal (e.g., etching) process.

[0102] In addition, in some embodiments, the spacer structure 110 can be formed on the outer sidewalls of the hard mask layer 2102. In some embodiments, the spacer structure 110 is formed by depositing a spacer layer over the hard mask layer 2102 and the substrate 101; then a dry etching process can be performed to remove a substantially horizontal portion of the spacer layer to form the spacer structure 110. In some embodiments, the spacer structure 110 can include, for example, silicon dioxide, silicon nitride, some other suitable dielectric material, or a combination of the foregoing. In some embodiments, the spacer structure 110 has a substantially curved outer sidewall. In addition, in some embodiments, the spacer structure 110 and the hard mask layer 2102 can together completely and directly overlie the gate electrode 108 and the gate dielectric structure 106.

[0103] In some other embodiments, the hard mask layer 2102 may be formed before performing the removal process of the gate electrode 108. For example, in some embodiments, the gate electrode material ( Fig.19A 1902) may first undergo a planarization process (e.g., CMP), and then a hard mask layer 2102 may be formed over the planarized gate electrode material. Then, in some embodiments, an etching process according to the hard mask layer 2102 may be performed to remove an outer portion of the planarized gate electrode, thereby forming the gate electrode 108. In such other embodiments, the gate electrode 108 may have a topmost surface 108t disposed above the topmost surface 101t of the substrate 101.

[0104] like Fig.22A A cross-sectional view 2200A and Fig. 22BAs shown in the cross-sectional view 2200B of FIG. 2200B , in some embodiments, the source / drain region 302 may be formed laterally between the spacer structure 110 and the trench isolation structure 104. In some embodiments, the source / drain region 302 is formed by doping a portion of the lightly doped region 304 by ion implantation. The source / drain region 302 may have the same doping type as the lightly doped region 304, but at a higher doping concentration. The source / drain region 302 may be formed by a self-aligned process, in which the hard mask layer 2102 and the spacer structure 110 act as a mask during the ion implantation process. The source / drain region 302 is formed from Fig.22A This is not visible in the cross-sectional view 2200A of , because there is no space between the spacer structure and the trench isolation structure 104 for forming the source / drain region 302 .

[0105] like Fig.23A A cross-sectional view 2300A and Fig. 23B As shown in the cross-sectional view 2300B of FIG. 2300B, in some embodiments, a first interconnect dielectric layer 114a is formed over the substrate 101 and the hard mask layer 2102. In some embodiments, the first interconnect dielectric layer 114a is formed by a deposition process (e.g., PVD, CVD, ALD, etc.), and may include, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or the like.

[0106] like Fig.24A A cross-sectional view of 2400A and Fig. 24B As shown in the cross-sectional view 2400B of FIG. 2400B , in some embodiments, a planarization process (e.g., CMP) may be performed to remove a portion of the first interconnect dielectric layer 114a disposed above the hard mask layer 2102. In some embodiments, the planarization process (e.g., CMP) may also remove the upper portion of the spacer structure 110 and the hard mask layer 2102, so that the spacer structure 110 may have a substantially flat upper surface. In some other embodiments, Fig.24A and Fig. 24B The planarization process (eg, CMP) does not remove portions of the spacer structure 110 and / or portions of the hard mask layer 2102 .

[0107] like Fig.25A Cross-sectional view 2500A, Fig.25B A cross-sectional view 2500B and Fig.25CAs shown in top view 2500C of FIG. 1 , in some embodiments, the hard mask layer ( Fig.24A 2102). In some embodiments, the spacer structure 110 is not removed. In some embodiments, the hard mask layer ( Fig.24A 2102), and the gate electrode 108, the gate dielectric structure 106 and the trench isolation structure 104 can be substantially resistant to removal by wet etching or dry etching.

[0108] In some embodiments (not shown), before removing the hard mask layer ( Fig.24A After 2102), a gate replacement process may optionally be performed. In such embodiments, the gate electrode 108 may be selectively removed from the gate dielectric structure 106 and a different gate electrode material may be formed within the gate dielectric structure 106. In some such embodiments, the gate electrode 108 may be selectively removed from the gate dielectric structure 106 and a different gate electrode material may be formed within the gate dielectric structure 106. FIG. 19A to FIG. 19B and FIG. 20A to FIG. 20C The gate electrode 108 in the embodiment may be referred to as a "dummy gate electrode", and then the dummy gate electrode is removed and the FIG. 25A to FIG. 25C The gate electrode 108 is replaced by the gate electrode 108. For example, in some embodiments, a gate replacement process can be used to reduce damage to the gate electrode 108 during various processing steps.

[0109] like Fig.26A A cross-sectional view 2600A, Fig.26B A cross-sectional view 2600B and Fig.26C As shown in top view 2600C of FIG. 1 , in some embodiments, a silicide layer 202 is formed on the gate electrode 108. In some embodiments, the silicide layer 202 is formed when the gate electrode 108 includes polysilicon. In some such embodiments, the silicide layer 202 may include, for example, cobalt silicide, titanium silicide, nickel silicide, or some other suitable metal silicide material. In some embodiments, the silicide layer 202 is formed by depositing a transition metal layer covering the gate electrode 108, and then heating the transition metal layer to react with the polysilicon of the gate electrode 108. In some embodiments, the silicide layer 202 helps to form a conductive feature formed above the gate electrode 108 to couple to the gate electrode 108.

[0110] like Fig.27A A cross-sectional view of 2700A and Fig.27BAs shown in the cross-sectional view 2700B of FIG. 2700B , in some embodiments, the interconnect structure 112 is formed above the gate electrode 108 and the source / drain region 302 so that the recessed MOSFET can be coupled to more devices (e.g., a memory device, another transistor, an image sensor, etc.) arranged above the substrate 101. In some embodiments, the interconnect structure 112 includes a contact via 116, an interconnect wire 118, and an interconnect via 620 arranged in the first interconnect dielectric layer 114a, the second interconnect dielectric layer 114b, the third interconnect dielectric layer 114c, and / or the fourth interconnect dielectric layer 114d. In some embodiments, the first interconnect dielectric layer 114a, the second interconnect dielectric layer 114b, the third interconnect dielectric layer 114c and / or the fourth interconnect dielectric layer 114d may include, for example, nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k oxides (e.g., carbon-doped oxides, SiCOH), or the like. In addition, in some embodiments, the contact vias 116, the interconnect wires 118, and the interconnect vias 620 may each include, for example, copper, tungsten, aluminum, titanium, tantalum, or some other suitable conductive material. In some embodiments, the interconnect structure 112 may be formed by various steps, including a deposition process (e.g., PVD, CVD, ALD, sputtering, etc.), a removal process (e.g., wet etching, dry etching, CMP, etc.), and / or a patterning process (e.g., photolithography / etching).

[0111] Fig.28 A flow chart illustrating some embodiments of a method 2800 of forming a gate dielectric structure having corner portions thicker than a center portion in a recessed MOSFET.

[0112] Although method 2800 is shown and described below as a series of actions or events, it should be understood that the order shown of such actions or events should not be interpreted in a limiting sense. For example, in addition to the actions or events shown and / or described herein, some actions may occur in different orders and / or simultaneously with other actions or events. In addition, not all of the actions shown may be required to implement one or more aspects or embodiments of the description herein. In addition, one or more of the actions depicted herein may be performed with one or more separate actions and / or stages.

[0113] At act 2802, a trench isolation structure is formed to surround a well region of a substrate. Fig.11A A cross-sectional view 1100A corresponding to some embodiments of act 2802 is shown.

[0114] At act 2804, a portion of the substrate is removed to form a recess in the substrate, wherein outer sidewalls of the recess are defined by the trench isolation structure. Fig. 12A A cross-sectional view 1200A is shown corresponding to some embodiments of act 2804 .

[0115] At act 2806 , a first gate dielectric layer is formed over a surface of the recess in the substrate. Fig.14A A cross-sectional view 1400A is shown corresponding to some embodiments of act 2806 .

[0116] At act 2808, a second gate dielectric layer is formed over the first gate dielectric layer. Fig.15A A cross-sectional view 1500A is shown corresponding to some embodiments of act 2808 .

[0117] At act 2810, a removal process is performed to remove central portions of the first gate dielectric layer and the second gate dielectric layer. Fig.17A A cross-sectional view 1700A corresponding to some embodiments of act 2810 is shown.

[0118] At act 2812, a third gate dielectric layer is formed over a surface of the recess in the substrate and over the second gate dielectric layer. Fig.18A A cross-sectional view 1800A is shown corresponding to some embodiments of act 2812 .

[0119] At act 2814, a gate electrode is formed over the third gate dielectric layer. Fig. 20A A cross-sectional view 2000A is shown corresponding to some embodiments of act 2814 .

[0120] Therefore, the present disclosure is directed to a method of increasing the thickness of a gate dielectric structure at a corner portion of the gate dielectric structure in a recessed MOSFET to improve the reliability of the recessed MOSFET.

[0121] Therefore, in some embodiments, the present disclosure relates to a semiconductor device, comprising: a well region located in a substrate; a source region and a drain region arranged in the substrate on opposite sides of the well region; a gate electrode arranged above the well region, the gate electrode comprising a bottom surface arranged below the topmost surface of the substrate and extending between the source region and the drain region; a trench isolation structure surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure separating the gate electrode from the well region, the source region, the drain region and the trench isolation structure, wherein the gate dielectric structure comprises a central portion having a first thickness and a corner portion having a second thickness, and wherein the second thickness is greater than the first thickness.

[0122] In some embodiments, the gate electrode extends from the source region to the drain region in a first direction, wherein the gate electrode extends from a first side of the trench isolation structure to a second side of the trench isolation structure in a second direction perpendicular to the first direction, and wherein the corner portion of the gate dielectric structure is arranged directly above the first side and the second side of the trench isolation structure and contacts the first side and the second side of the trench isolation structure. In some embodiments, the second thickness is at least three times the first thickness. In some embodiments, the first thickness of the center portion of the gate dielectric structure is measured between a bottommost surface and a first middle surface of the gate dielectric structure, wherein the second thickness of the corner portion of the gate dielectric structure is measured between the bottommost surface and a second middle surface of the gate dielectric structure, wherein the first middle surface is between the second middle surface and the bottommost surface of the gate dielectric structure, and wherein the second middle surface is below the topmost surface of the gate dielectric structure. In some embodiments, the corner portion of the gate dielectric structure has a third thickness measured in the same direction as the first thickness and the second thickness, and wherein the third thickness is greater than the first thickness and the second thickness. In some embodiments, the gate electrode extends from the source region to the drain region in a first direction, and wherein any line extending through the source and drain regions in the first direction does not extend through the corner portion of the gate dielectric structure. In some embodiments, a lower portion of the gate electrode disposed over the center portion of the gate dielectric structure is narrower than an upper portion of the gate electrode disposed over the corner portion of the gate dielectric structure. In some embodiments, the corner portion of the gate dielectric structure includes a first region directly overlying the trench isolation structure and a second region directly overlying and contacting the well region, wherein the first region is thinner than the second region.

[0123] In other embodiments, the present disclosure relates to a semiconductor device, comprising: a well region located in a substrate; a source region and a drain region arranged in the substrate on opposite sides of the well region; a gate electrode arranged in the substrate and directly between the source region and the drain region; a trench isolation structure continuously surrounding the source region, the drain region and the gate electrode; and a gate dielectric structure arranged on the outer sidewalls and bottom surface of the gate electrode, wherein the gate dielectric structure comprises a central portion having a first thickness, an inner corner portion having a second thickness greater than the first thickness, and an outer corner portion having a third thickness greater than the second thickness, and wherein the first thickness, the second thickness, and the third thickness are measured in the same direction from the bottommost surface of the gate dielectric structure.

[0124] In some embodiments, the inner corner portion couples the center portion to the outer corner portion, wherein the outer corner portion overlies the trench isolation structure and the center portion extends between opposite sides of the trench isolation structure. In some embodiments, the inner corner portion of the gate dielectric structure overlies and directly contacts the trench isolation structure and the well region. In some embodiments, the gate electrode includes an upper portion having a first width and a lower portion having a second width, the second width being less than the first width, wherein an outer sidewall of the upper portion contacts the outer corner portion of the gate dielectric structure, and wherein an outer sidewall of the lower portion contacts the inner corner portion of the gate dielectric structure. In some embodiments, the gate dielectric structure includes three dielectric layers. In some embodiments, the inner corner portion and the outer corner portion of the gate dielectric structure include the three dielectric layers, and wherein the center portion of the gate dielectric structure includes one of the three dielectric layers. In some embodiments, the one of the three dielectric layers is the topmost layer of the inner corner portion of the gate dielectric structure.

[0125] In yet other embodiments, the present disclosure relates to a method comprising: forming a trench isolation structure to surround a well region of a substrate; removing a portion of the substrate to form a recess in the substrate, wherein an outer sidewall of the recess is defined by the trench isolation structure; forming a first gate dielectric layer above a surface of the recess in the substrate; forming a second gate dielectric layer above the first gate dielectric layer; performing a removal process to remove a central portion of the first gate dielectric layer and the second gate dielectric layer, wherein after the removal process, a portion of the first gate dielectric layer and a portion of the second gate dielectric layer remain on the trench isolation structure; forming a third gate dielectric layer above the surface of the recess in the substrate and above the second gate dielectric layer; and forming a gate electrode above the third gate dielectric layer.

[0126] In some embodiments, the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer include the same material. In some embodiments, after the removal process, the first gate dielectric layer contacts a portion of the well region. In some embodiments, the method further includes: performing a planarization process on the gate electrode and the first gate dielectric layer, the second gate dielectric layer, and / or the third gate dielectric layer, wherein after the planarization process, the gate electrode, the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer, and the substrate have substantially coplanar upper surfaces. In some embodiments, the method further includes: before the removal process, forming a mask structure over an outer portion of the first gate dielectric layer and the second gate dielectric layer, wherein the mask structure does not directly overlie the central portion of the first gate dielectric layer and the second gate dielectric layer.

[0127] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a well region, located in the substrate; a source region and a drain region disposed in the substrate on opposite sides of the well region; a gate electrode disposed above the well region, the gate electrode comprising a bottom surface disposed below a topmost surface of the substrate and extending between the source region and the drain region; A trench isolation structure surrounding the source region, the drain region and the gate electrode; as well as a gate dielectric structure, separating the gate electrode from the well region, the source region, the drain region and the trench isolation structure, The gate dielectric structure includes a center portion having a first thickness and a corner portion having a second thickness, wherein the second thickness is greater than the first thickness, and wherein the second thickness is at least three times the first thickness.

2. The semiconductor device according to claim 1, wherein the gate electrode extends from the source region to the drain region in a first direction, wherein the gate electrode extends from a first side of the trench isolation structure to a second side of the trench isolation structure in a second direction perpendicular to the first direction, and wherein the corner portion of the gate dielectric structure is arranged directly above the first side and the second side of the trench isolation structure and contacts the first side and the second side of the trench isolation structure.

3. The semiconductor device of claim 1 , wherein the first thickness of the center portion of the gate dielectric structure is measured between a bottommost surface and a first middle surface of the gate dielectric structure, wherein the second thickness of the corner portion of the gate dielectric structure is measured between the bottommost surface and a second middle surface of the gate dielectric structure, wherein the first middle surface is between the second middle surface and the bottommost surface of the gate dielectric structure, and wherein the second middle surface is below a topmost surface of the gate dielectric structure. 4 . The semiconductor device of claim 1 , wherein the corner portion of the gate dielectric structure has a third thickness measured in the same direction as the first thickness and the second thickness, and wherein the third thickness is greater than the first thickness and the second thickness.

5. The semiconductor device of claim 1 , wherein the gate electrode extends from the source region to the drain region in a first direction, and wherein any line extending through the source and drain regions in the first direction does not extend through the corner portion of the gate dielectric structure. 6 . The semiconductor device of claim 1 , wherein a lower portion of the gate electrode disposed over the center portion of the gate dielectric structure is narrower than an upper portion of the gate electrode disposed over the corner portion of the gate dielectric structure. 7 . The semiconductor device according to claim 1 , wherein the corner portion of the gate dielectric structure comprises a first region directly overlying the isolation structure and a second region directly overlying and contacting the well region, wherein the first region is thinner than the second region.

8. A semiconductor device comprising: a well region, located in the substrate; a source region and a drain region disposed in the substrate on opposite sides of the well region; a gate electrode disposed in the substrate and directly between the source region and the drain region; A trench isolation structure continuously surrounds the source region, the drain region and the gate electrode; as well as a gate dielectric structure disposed on the outer sidewalls and bottom surface of the gate electrode, wherein the gate dielectric structure comprises: a central portion having a first thickness; an inner corner portion having a second thickness, the second thickness being greater than the first thickness; and an outer corner portion having a third thickness, the third thickness being greater than the second thickness, and The first thickness, the second thickness, and the third thickness are measured along the same direction from a bottommost surface of the gate dielectric structure, and the second thickness is at least three times the first thickness.

9. The semiconductor device of claim 8, wherein the inner corner portion couples the central portion to the outer corner portion, wherein the outer corner portion overlies the trench isolation structure, and the central portion extends between opposite sides of the trench isolation structure. 10 . The semiconductor device of claim 8 , wherein the inner corner portion of the gate dielectric structure overlies and directly contacts the trench isolation structure and the well region.

11. The semiconductor device of claim 8, wherein the gate electrode comprises an upper portion having a first width and a lower portion having a second width, the second width being smaller than the first width, wherein an outer sidewall of the upper portion contacts the outer corner portion of the gate dielectric structure, and wherein an outer sidewall of the lower portion contacts the inner corner portion of the gate dielectric structure. 12 . The semiconductor device of claim 8 , wherein the gate dielectric structure comprises three dielectric layers. 13 . The semiconductor device of claim 12 , wherein the inner corner portion and the outer corner portion of the gate dielectric structure include the three dielectric layers, and wherein the central portion of the gate dielectric structure includes one of the three dielectric layers. 14 . The semiconductor device of claim 13 , wherein the one of the three dielectric layers is a topmost layer of the inner corner portion of the gate dielectric structure.

15. A method for forming a semiconductor device, comprising: forming a trench isolation structure to surround a well region of the substrate; removing a portion of the substrate to form a recess in the substrate, wherein an outer sidewall of the recess is defined by the trench isolation structure; forming a first gate dielectric layer over a surface of the recess in the substrate; forming a second gate dielectric layer over the first gate dielectric layer; performing a removal process to remove central portions of the first gate dielectric layer and the second gate dielectric layer, wherein after the removal process, a portion of the first gate dielectric layer and a portion of the second gate dielectric layer remain on the trench isolation structure; forming a third gate dielectric layer over the surface of the recess in the substrate and over the second gate dielectric layer; forming a gate electrode over the third gate dielectric layer; as well as performing a planarization process on the gate electrode and the first gate dielectric layer, the second gate dielectric layer and / or the third gate dielectric layer, wherein after the planarization process, the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer form a gate dielectric structure surrounding the gate electrode, The gate dielectric structure includes a center portion having a first thickness and a corner portion having a second thickness, wherein the second thickness is greater than the first thickness, and wherein the second thickness is at least three times the first thickness. 16 . The method for forming a semiconductor device according to claim 15 , wherein the first gate dielectric layer, the second gate dielectric layer, and the third gate dielectric layer comprise a same material. 17 . The method for forming a semiconductor device according to claim 15 , wherein after the removal process, the first gate dielectric layer contacts a portion of the well region.

18. The method for forming a semiconductor device according to claim 15, After the planarization process, the gate electrode, the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the substrate have substantially coplanar upper surfaces.

19. The method for forming a semiconductor device according to claim 15, further comprising: Prior to the removal process, a mask structure is formed over outer portions of the first gate dielectric layer and the second gate dielectric layer, wherein the mask structure does not directly overlie the central portions of the first gate dielectric layer and the second gate dielectric layer.

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