Display device and method of manufacturing the same

Abstract

The present invention relates to a display device and a manufacturing method thereof. The display device includes a substrate including a first region and a second region; a first active layer located on the first region and including a first channel region, a first source region on one side of the first channel region, a first drain region on the other side of the first channel region, and a first extension region extending in a direction from the first source region to the second region; a first gate electrode located above the first active layer and overlapping the first channel region; a driving voltage line located on the first active layer, overlapping the first source region, and extending along the first extension region; a first connection electrode located on the first drain region; and a pixel electrode located above the first gate electrode and connected to the first connection electrode.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0070461, filed with the Korean Intellectual Property Office on June 10, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some embodiments of this disclosure relate to display devices and methods of manufacturing thereof that can improve process efficiency and ensure design space. Background Technology

[0004] Among display devices, organic light-emitting diode (OLED) displays offer wide viewing angles, excellent contrast ratios, and fast response times. Therefore, OLED displays have become a focus of attention as the next generation of display devices.

[0005] Typically, in organic light-emitting display devices, thin-film transistors and organic light-emitting devices are formed on a substrate, and the organic light-emitting devices operate by emitting light autonomously. These organic light-emitting display devices are used as display units in small products such as mobile phones or as display units in large products such as televisions (TVs).

[0006] Such a display device includes a thin-film transistor (TFT) for driving and a capacitor. Here, the TFT may include an active layer comprising a channel region, a source region, and a drain region, and a gate electrode electrically insulated from the active layer by a gate insulating layer.

[0007] However, in display devices and manufacturing methods according to the prior art, multiple masking processes may be required, which reduces process efficiency, and design space may become insufficient because multiple configurations are provided. Summary of the Invention

[0008] Some embodiments of this disclosure include display devices and methods of manufacturing the same that can improve process efficiency and ensure design space. However, these are merely examples, and the scope of this disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows, and will be apparent in part from the description, or may be learned by practicing the embodiments presented in this disclosure.

[0010] According to one or more embodiments, a display device includes: a substrate including a first region in which first pixel circuitry is located and a second region in which second pixel circuitry is located; a first active layer located on the first region and including a first channel region, a first source region on a first side of the first channel region, a first drain region on a second side of the first channel region, and a first extension region extending in a direction from the first source region to the second region; a first gate electrode located above the first active layer and overlapping the first channel region; a driving voltage line located on the first active layer, overlapping the first source region, and extending along the first extension region; a first connection electrode located on the first drain region; and a pixel electrode located above the first gate electrode and connected to the first connection electrode.

[0011] The display device may further include: a second active layer located on the first region and including a second channel region, a second source region on a first side of the second channel region, a second drain region on a second side of the second channel region, and a second extension region extending in a direction from the second source region to the second region; a second gate electrode located above the second active layer and overlapping the second channel region; a data line located on the second active layer, overlapping the second source region, and extending along the second extension region; a second connection electrode located on the second drain region; and a bridging electrode electrically connecting the second connection electrode to the first gate electrode.

[0012] The display device may further include: a third active layer located on the second region, and including a third channel region, a third source region on a first side of the third channel region, a third drain region on a second side of the third channel region, and a third extension region extending in a direction from the third source region to the first region and integral with the first extension region; and a third gate electrode located above the third active layer and overlapping the third channel region, wherein a driving voltage line extends from the first extension region to the third extension region and overlaps with the third source region.

[0013] The display device may further include: a fourth active layer located on the second region, and including a fourth channel region, a fourth source region on a first side of the fourth channel region, a fourth drain region on a second side of the fourth channel region, and a fourth extension region extending in a direction from the fourth source region to the first region and integral with the second extension region; and a fourth gate electrode located above the fourth active layer and overlapping the fourth channel region, wherein a data line extends from the second extension region to the fourth extension region and overlaps with the fourth source region.

[0014] The display device may further include: a gate insulating layer in the region overlapping with the first gate electrode between the first active layer and the first gate electrode, and in the region overlapping with the second gate electrode between the second active layer and the second gate electrode.

[0015] The bridging electrode may include the same material as the pixel electrode and have the same stacked structure as the pixel electrode.

[0016] The driving voltage line, data line, first connection electrode, and second connection electrode may include the same material and have the same stacked structure.

[0017] The first active layer and the second active layer may include oxide semiconductors.

[0018] The display device may further include a bottom metal layer (BML) having an isolated shape and located below the first active layer.

[0019] BML can be electrically connected to the pixel electrode through contact holes.

[0020] The display device may further include: a counter electrode located on the pixel electrode, and an intermediate layer located between the pixel electrode and the counter electrode and including an emission layer.

[0021] According to one or more embodiments, a method of manufacturing a display device includes: a first masking process, forming a first conductive layer on a substrate including a first region and a second region, and patterning the first conductive layer into a bottom metal layer (BML) having an isolated shape; a second masking process, sequentially forming a semiconductor layer and a second conductive layer on the result of the first masking process, patterning the semiconductor layer into a first active layer and a second active layer in the first region, and patterning the second conductive layer into a driving voltage line, a data line, a first connection electrode, and a second connection electrode; and a third masking process, sequentially forming a first insulating layer and a third conductive layer on the result of the second masking process, and patterning the first insulating layer into a... The third conductive layer is patterned into a first gate electrode and a second gate electrode; and a fourth masking process is performed to form a second insulating layer on the result of the third masking process and to form a plurality of contact holes in the second insulating layer, wherein the first active layer in the first region includes a first channel region, a first source region on a first side of the first channel region, a first drain region on a second side of the first channel region, and a first extension region extending in the direction from the first source region to the second region, and wherein the second active layer in the first region includes a second channel region, a second source region on a first side of the second channel region, a second drain region on a second side of the second channel region, and a second extension region extending in the direction from the second source region to the second region.

[0022] The second masking process may include: patterning a semiconductor layer in the second region into a third active layer and a fourth active layer, and patterning a second conductive layer into a driving voltage line, a data line, a third connection electrode, and a fourth connection electrode. The third masking process includes: patterning a third conductive layer in the second region into a third gate electrode and a fourth gate electrode. The third active layer in the second region includes a third channel region, a third source region on a first side of the third channel region, a third drain region on a second side of the third channel region, and a third extension region extending in the direction from the third source region to the first region and integral with the first extension region. The fourth active layer in the second region includes a fourth channel region, a fourth source region on a first side of the fourth channel region, a fourth drain region on a second side of the fourth channel region, and a fourth extension region extending in the direction from the fourth source region to the first region and integral with the second extension region. The driving voltage line extends from the first extension region to the third extension region and overlaps with the third source region. The data line extends from the second extension region to the fourth extension region and overlaps with the fourth source region.

[0023] The second mask in the second mask process may include a halftone mask, which includes a fully transmissive area, a semi-transmissive area, and a non-transmissive area.

[0024] The second masking process may include: forming a first photosensitive layer on a second conductive layer and patterning the first photosensitive layer using a second mask to form a first photosensitive layer pattern, wherein the second mask is located above the second conductive layer, and in the first photosensitive layer pattern, the first photosensitive layer is not located in an uncoated area overlapping with the fully transmissive area of ​​the second mask, the first photosensitive layer is located in a semi-coated area overlapping with the semi-transmissive area of ​​the second mask and has a thickness less than the initial thickness, and the first photosensitive layer is located in a fully coated area overlapping with the non-transmissive area of ​​the second mask and has the initial thickness.

[0025] The second mask process may further include: removing the semiconductor layer and the second conductive layer located in the uncoated area; ashing the entire surface of the first photosensitive layer pattern to remove the thickness of the first photosensitive layer located in the semi-coated area; and removing the second conductive layer located in the semi-coated area by using selective etching.

[0026] The method further includes: a fifth mask process, forming a fourth conductive layer on the result of the fourth mask process, and patterning the fourth conductive layer into pixel electrodes and bridging electrodes, wherein the bridging electrodes electrically connect the second connection electrode to the first gate electrode.

[0027] The fourth masking process may include: forming a first contact hole in the second insulating layer for exposing a portion of the first gate electrode, forming a second contact hole for exposing a portion of the first connection electrode, and forming a third contact hole for exposing a portion of the second connection electrode.

[0028] The fourth mask process may further include forming a fourth contact hole in the second insulating layer for exposing a portion of the BML, wherein the BML is connected to the pixel electrode through the fourth contact hole.

[0029] The method further includes: a sixth masking process, forming a pixel-defining layer on the result of the fifth masking process, and patterning the pixel-defining layer into emitting and non-emitting regions.

[0030] From the detailed description of this disclosure used to implement the following disclosure, claims and drawings, aspects different from those described above will become apparent.

[0031] These general and specific aspects can be realized by using systems, methods, computer programs, or any combination of systems, methods, and computer programs. Attached Figure Description

[0032] The above and other aspects of some embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0033] Figure 1 This is a schematic diagram illustrating the configuration of a portion of a display device according to some embodiments;

[0034] Figure 2 The schematic map shows what is included. Figure 1 Equivalent circuit diagram of pixel circuits in a display device;

[0035] Figure 3 It is a schematic map showing the arrangement in Figure 1 A layout diagram showing the positions of thin-film transistors and capacitors in the pixel circuit of a display device;

[0036] Figure 4 It is along Figure 3 A cross-sectional view of the display device taken by lines P1 and P2 and lines P4 to P7;

[0037] Figure 5 It is along Figure 3 Cross-sectional views of the display device taken from lines P1 and P2, as well as lines P3, P6, and P7;

[0038] Figure 6 The schematic map shows what is included. Figure 1 A cross-sectional view of the connection structure of the bottom metal layer (BML) in a display device;

[0039] Figure 7 It is a schematic map showing the manufacturing process. Figure 1 A flowchart of a method for displaying a device; and

[0040] Figures 8 to 17It is a schematic map showing the manufacturing process. Figure 1 A cross-sectional view of a part of the method for displaying a device. Detailed Implementation

[0041] The features of the inventive concept and the methods for carrying out the inventive concept can be more readily understood by referring to the detailed description of the embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be embodied in various different forms and should not be construed as limited to the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art aspects and features of the inventive concept. Therefore, processes, elements, and techniques unnecessary for those skilled in the art to fully understand the aspects and features of the inventive concept are not described.

[0042] Unless otherwise stated, the same reference numerals, characters, or combinations thereof refer to the same elements throughout the drawings and written description, and therefore their description will not be repeated. Furthermore, portions irrelevant to the description of the embodiments may be omitted to make the description clear. In the drawings, the relative dimensions of elements, layers, and areas may be exaggerated for clarity. Additionally, the use of crosshairs and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for the specific material of the elements, material properties, dimensions, scale, commonalities between the illustrated elements, and / or any other characteristics, properties, or characteristics of the elements.

[0043] Various embodiments are described herein with reference to cross-sectional views as schematic illustrations of examples and / or intermediate structures. Therefore, variations in the shape of the illustrations as a result of, for example, manufacturing techniques and / or tolerances can be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of this disclosure. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes specifically illustrated, but should include deviations in shape due to, for example, manufacturing processes.

[0044] For example, an injection zone illustrated as rectangular will typically have rounded or curved features at its edges and / or a gradient of injection concentration, rather than a binary change from an injection zone to a non-injection zone. Similarly, a buried zone formed by injection can result in some injection in the area between the buried zone and the surface through which the injection occurs. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to depict the actual shape of the areas of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of this disclosure.

[0045] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0046] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, the first element, first component, first area, first layer, or first part described below may be referred to as a second element, second component, second area, second layer, or second part without departing from the spirit and scope of this disclosure.

[0047] For ease of explanation, spatially relative terms such as “below,” “under,” “down,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature as illustrated in the accompanying drawings and another element(s). It will be understood that, in addition to the orientations depicted in the drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be oriented in other ways (e.g., rotated 90 degrees or oriented in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “above” a second part, this indicates that the first part is arranged above or below the second part, and not limited to the upper side of the second part based on the direction of gravity.

[0048] Furthermore, in this specification, the terms "in a plane" or "plan view" mean the target portion viewed from above, and the term "in a cross section" means the cross section formed by vertically cutting the target portion viewed from the side.

[0049] It will be understood that when an element, layer, area, or component is referred to as being "formed on," "on," "connected to," or "coupled to" another element, layer, area, or component, the element, layer, area, or component may be directly formed on, on, connected to, or coupled to the other element, layer, area, or component, or indirectly formed on, on, connected to, or coupled to the other element, layer, area, or component, such that one or more intermediate elements, layers, areas, or components may be present. However, "directly connected / directly coupled" refers to a component being directly connected to or coupled to another component without any intermediate components. Similarly, other expressions describing relationships between components, such as "between" and "directly between," or "adjacent to" and "directly adjacent to," can be interpreted similarly. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may be present.

[0050] For the purposes of this disclosure, expressions such as “at least one of…” modify the entire list of elements when following a list of elements and do not modify any individual element in the list. For example, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of two or more of only X, only Y, only Z, X, Y, and Z, such as XYZ, XYY, YZ, and ZZ or any variations thereof. Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the listed items. For example, expressions such as “A and / or B” can include A, B, or A and B.

[0051] In this example, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction, and / or the third direction.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly indicates otherwise. It will be further understood that, when used in this specification, the terms “comprising,” “having,” and “including” specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the items listed herein.

[0053] As used herein, the terms “substantially,” “about,” “approximately,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for the inherent bias of measured or calculated values ​​that would be generally accepted by those skilled in the art. As used herein, when considering the measurement in discussion and the errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), “about” or “approximately” includes the stated value and means within an acceptable deviation of the specific value as determined by those skilled in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to “one or more embodiments of this disclosure.”

[0054] When one or more embodiments can be implemented differently, a particular process sequence may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description.

[0055] The electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of these devices can be implemented on a flexible printed circuit film, a tape-on-a-package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0056] Furthermore, the various components of these devices can be processes or threads running on one or more processors within one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which can be implemented using standard memory devices such as random access memory (RAM) within the computing device. The computer program instructions can also be stored in other non-transitory computer-readable media such as, for example, CD-ROMs or flash drives. Moreover, those skilled in the art will recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of this disclosure.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and / or the context of this specification, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0058] Figure 1 This is a schematic diagram illustrating the configuration of a portion of a display device according to some embodiments.

[0059] The display device according to some embodiments may have a light-emitting display area and a non-light-emitting non-display area. It will be understood that substrate 100 (see...) Figure 3 This includes both display and non-display areas.

[0060] In the following description, organic light-emitting display devices will be used as examples of display devices according to some embodiments. However, the display devices according to this disclosure are not limited thereto. In other embodiments, examples of display devices according to this disclosure may include display devices such as inorganic light-emitting display devices or quantum dot light-emitting display devices. For example, the emitting layer of the display element included in the display device may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0061] like Figure 1 As shown, the display device according to some embodiments may include a controller 10, a data driver 20, and a scan driver 30.

[0062] The data driver 20 provides data signals to the pixels, and the scan driver 30 provides scan signals to the pixels. In the display area, pixels can be located at the points where the data line DL, connected to the data driver 20 and extending in the y-axis direction, and the scan line SL, connected to the scan driver 30 and extending in the x-axis direction, intersect each other. Furthermore, pixel circuitry can be located within each pixel.

[0063] In this context, a "pixel" can refer to a sub-pixel that emits different colors. Each pixel within a pixel can include a display element and can emit, for example, red, green, blue, or white light. Each pixel can include pixel circuitry connected to scan lines SL and data lines DL, and an organic light-emitting diode (OLED) as the display element connected to the pixel circuitry (see [link to OLED]). Figure 2 ).

[0064] In the following text, the area of ​​the first pixel containing the first pixel circuit and the light-emitting diode connected to the first pixel circuit can be referred to as "first area PX1". The area of ​​the second pixel adjacent to the first pixel, containing the second pixel circuit and the light-emitting diode connected to the second pixel circuit, can be referred to as "second area PX2". Figure 1 The middle diagram shows region PX1 and region PX2.

[0065] Figure 2 The schematic map shows what is included. Figure 1 The equivalent circuit diagram of the pixel circuit in the display device.

[0066] The pixel circuit PC may include capacitors and multiple thin-film transistors. In some embodiments, such as Figure 2 As shown, the pixel circuit PC may include a first thin-film transistor (TFT1), a second thin-film transistor (TFT2), and a capacitor Cst. In this case, the first TFT1 may be a driving thin-film transistor (TFT), and the second TFT2 may be a switching TFT. The second TFT2 may be connected to a scan line SL and a data line DL, and may be configured to transmit a data signal DLm input via the data line DL to the first TFT1 according to a scan signal SLn input via the scan line SL.

[0067] The capacitor Cst can be electrically connected to the second thin-film transistor TFT2 and the driving voltage line PL, and can store a voltage corresponding to the difference between the first voltage ELVDD applied to the driving voltage line PL and the second voltage applied to the second thin-film transistor TFT2.

[0068] The first thin-film transistor TFT1 can be connected to the driving voltage line PL and the capacitor Cst, and can control the driving current I flowing from the driving voltage line PL to the organic light-emitting diode OLED in response to the value of the voltage stored in the capacitor Cst. oled The counter electrode (e.g., cathode) of an organic light-emitting diode (OLED) can be connected to a line to which a common voltage ELVSS is applied. An OLED can emit light with a voltage equal to or greater than the driving current I. oled The image is displayed using light of corresponding brightness.

[0069] in addition, Figure 2 The figure illustrates P-type thin-film transistors TFT1 and TFT2, but other embodiments are not limited thereto. For example, some or all of the multiple thin-film transistors in the pixel circuit PC may be N-type or P-type thin-film transistors. That is, the multiple thin-film transistors may include an undoped channel region and source and drain regions doped on both sides of the channel region. The impurities may vary depending on the type of thin-film transistor and may include N-type or P-type impurities.

[0070] also, Figure 2 The illustration shows a pixel circuit PC comprising two thin-film transistors TFT1 and TFT2 and a capacitor Cst, but other embodiments are not limited to this. The number of thin-film transistors and the number of capacitors can be varied depending on the design of the pixel circuit PC. For example, the pixel circuit PC may include three or more thin-film transistors and / or two or more capacitors. In the example, the pixel circuit PC may include seven thin-film transistors and one capacitor. However, for ease of illustration, the following description will depict a pixel circuit PC comprising two thin-film transistors and one capacitor.

[0071] Figure 3 It is a schematic map showing the arrangement in Figure 1 A layout diagram showing the positions of thin-film transistors TFT1 and TFT2 and capacitor Cst in the pixel circuit PC of a display device. Figure 4 It is along Figure 3 The cross-sectional view of the display device taken by lines P1 and P2 and lines P4 to P7, and Figure 5 It is along Figure 3 The cross-sectional views of the display device are taken from lines P1 and P2, as well as lines P3, P6 and P7.

[0072] For convenience, Figure 3 The bottom metal layer (BML) 300 is omitted. That is to say, although in Figure 3 Not shown, but the BML 300 and the connection structure accompanying the BML 300 can overlap with other configurations. Furthermore, it will be understood that... Figure 3The shaded area represents the region covered by pixel-defined layer 110, and Figure 3 The unshaded portion represents the area in which the pixel electrode 210 is exposed through the opening in the pixel defining layer 110.

[0073] like Figure 3 As shown, a display device according to some embodiments may include a substrate 100 containing multiple regions, and thin-film transistors TFT1 and TFT2 having a multilayer structure, capacitor Cst, driving voltage line PL, data line DL, display element 200, pixel defining layer 110, etc. may be located on the substrate 100.

[0074] Substrate 100 may comprise glass, metal, ceramic, or flexible or bendable materials. When substrate 100 is flexible or bendable, it may comprise polymer resins such as polyethersulfone (PES), polyacrylate, polyetherimide, polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). Substrate 100 may have a single-layer or multi-layer structure comprising the materials described above. When substrate 100 has a multi-layer structure, various modifications are possible, in which substrate 100 comprises two layers comprising polymer resins and a barrier layer between the two layers comprising an inorganic material (such as silicon oxide, silicon nitride, or silicon oxynitride).

[0075] Reference Figure 4 and Figure 5 A buffer layer 101 may be located on the substrate 100. The buffer layer 101 may comprise inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure. Furthermore, the buffer layer 101 may extend to both the display area and the non-display area. The buffer layer 101 may be configured to increase or improve the smoothness of the top surface of the substrate 100, or to reduce, minimize, or prevent impurities or moisture from penetrating from the outside of the substrate 100 into the active layer.

[0076] On the other hand, in some embodiments, the BML 300, as the lower metal layer, may be located on the substrate 100. The BML 300, having an isolated shape, may be located below the first active layer 121-1 of the first thin-film transistor TFT1. In this case, the buffer layer 101 may be located on the substrate 100 and simultaneously cover the BML 300. The BML 300 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu). The BML 300 may have a single-layer structure or a multi-layer structure comprising the above-described materials.

[0077] Furthermore, BML 300 can be connected to pixel electrode 210 via a contact hole for exposing a portion of BML 300 from the bottom surface of pixel electrode 210, and will refer to Figure 6 Provide a detailed description.

[0078] The pixel circuit PC may be located on the buffer layer 101 in the display area on the substrate 100. The pixel circuit PC may include a first thin-film transistor TFT1, a second thin-film transistor TFT2, a capacitor Cst, a driving voltage line PL, and a data line DL. The display element 200 being electrically connected to the pixel circuit PC is understood to mean that the pixel electrode 210 included in the display element 200 is electrically connected to the first thin-film transistor TFT1.

[0079] The display device according to some embodiments may include a first thin-film transistor TFT1 as a driving TFT and a second thin-film transistor TFT2 as a switching TFT in a first region PX1.

[0080] The first thin-film transistor TFT1 may include a first active layer 121-1 and a first gate electrode 123-1. In this case, the first active layer 121-1 may include a first channel region C1, a first source region S1 on one side of the first channel region C1, a first drain region D1 on the other side of the first channel region C1, and a first extension region E1 extending in the direction from the first source region S1 to the second region PX2. The first gate electrode 123-1 may be located above the first active layer 121-1 and may overlap with the first channel region C1. Furthermore, the first drain region D1 may be connected to the pixel electrode 210 of the display element 200.

[0081] On the other hand, one end 125-1 of the driving voltage line PL can be located on the first active layer 121-1, can overlap with the first source region S1, and can extend along the first extension region E1 of the first active layer 121-1. The first connection electrode 127-1 can be located on the first active layer 121-1 and can overlap with the first drain region D1. That is, one end 125-1 of the driving voltage line PL can be located on the source electrode of the first thin-film transistor TFT1, and the first connection electrode 127-1 can be located on the drain electrode of the first thin-film transistor TFT1.

[0082] The second thin-film transistor TFT2 may include a second active layer 121-2 and a second gate electrode 123-2. In this case, the second active layer 121-2 may include a second channel region C2, a second source region S2 on one side of the second channel region C2, a second drain region D2 on the other side of the second channel region C2, and a second extension region E2 extending in the direction from the second source region S2 to the second region PX2. The second gate electrode 123-2 may be located above the second active layer 121-2 and may overlap with the second channel region C2. One end 125-2 of the data line DL may be located on the second active layer 121-2, may overlap with the second source region S2, and may extend along the second extension region E2 of the second active layer 121-2. The second connection electrode 127-2 may be located on the second drain region D2 of the second active layer 121-2. In other words, one end 125-2 of the data line DL can be located on the source electrode of the second thin film transistor TFT2, and the second connection electrode 127-2 can be located on the drain electrode of the second thin film transistor TFT2.

[0083] The first thin-film transistor TFT1 and the second thin-film transistor TFT2 can be electrically connected to each other. For this purpose, the display device may further include a bridging electrode 215 for electrically connecting the second connection electrode 127-2 of the second thin-film transistor TFT2 to the first gate electrode 123-1 of the first thin-film transistor TFT1. In this case, the bridging electrode 215 may include the same material as the pixel electrode 210 and may have the same stacked structure as the pixel electrode 210. That is, when forming the pixel electrode 210, the bridging electrode 215 can be formed in a single process step using the same material as the pixel electrode 210.

[0084] Furthermore, the display device according to some embodiments may further include a third thin-film transistor TFT3 located in the second region PX2, which serves as a driving TFT and has the same structure as the first thin-film transistor TFT1, and a fourth thin-film transistor TFT4 serving as a switching TFT and having the same structure as the second thin-film transistor TFT2.

[0085] The third thin-film transistor TFT3 may include a third active layer, a third gate electrode, a third connection electrode, and one end of a driving voltage line PL. The third active layer may include a third channel region, a third source region on one side of the third channel region, a third drain region on the other side of the third channel region, and a third extension region extending in the direction from the third source region to the first region PX1, wherein the third extension region is integral with the first extension region E1. That is, the first active layer 121-1 of the first thin-film transistor TFT1 in the first region PX1 and the third active layer of the third thin-film transistor TFT3 in the second region PX2 can extend from one end of the first active layer 121-1 to one end of the third active layer, and can be integrally formed with each other.

[0086] Furthermore, the driving voltage line PL can extend from the first extension region E1 of the first active layer 121-1 of the first thin-film transistor TFT1 in the first region PX1 to the third extension region of the third active layer of the third thin-film transistor TFT3 in the second region PX2. The driving voltage line PL can overlap with the third source region. That is, the driving voltage line PL can extend from one end in the first region PX1 to one end in the second region PX2, and can be integrally formed.

[0087] The fourth thin-film transistor TFT4 may include a fourth active layer, a fourth gate electrode, a fourth connection electrode, and one end of the data line DL. The fourth active layer may include a fourth channel region, a fourth source region on one side of the fourth channel region, a fourth drain region on the other side of the fourth channel region, and a fourth extension region extending from the fourth source region to the first region PX1 and integral with the second extension region E2. That is, the second active layer 121-2 of the second thin-film transistor TFT2 in the first region PX1 and the fourth active layer of the fourth thin-film transistor TFT4 in the second region PX2 can extend from one end of the second active layer 121-2 to one end of the fourth active layer.

[0088] Furthermore, the data line DL can extend from the second extension region E2 of the second active layer 121-2 of the second thin-film transistor TFT2 in the first region PX1 to the fourth extension region of the fourth active layer of the fourth thin-film transistor TFT4 in the second region PX2. The data line DL can overlap with the fourth source region. That is, the data line DL can extend from one end in the first region PX1 to one end in the second region PX2, and can be integrally formed.

[0089] like Figure 3 As shown, the elements in the second region PX2 may be the same as those in the first region PX1 and have the same reference numerals. For the sake of brevity, their descriptions will not be repeated.

[0090] As described above, in a display device according to some embodiments, the active layers of the driving TFTs in each of the first region PX1 and the second region PX2 can be integrally formed, and the active layers of the switching TFTs in each of the first region PX1 and the second region PX2 can be integrally formed, and the driving voltage line PL and data line DL on the active layers can be integrally formed with each other in the first region PX1 and the second region PX2. Therefore, the active layer and driving voltage line PL or the active layer and data line DL can be formed by applying only one mask process. Thus, process efficiency can be improved. However, by only patterning the conductive layer on the active layer and by exposing a portion of the active layer, the electrodes in the source region and the electrodes in the drain region may be separated from each other. For this purpose, a selective etching process can be used, and its detailed description will be provided later.

[0091] Furthermore, the first active layer 121-1 and the second active layer 121-2 may comprise oxide semiconductors such as indium gallium zinc oxide (IGZO). However, other embodiments are not limited thereto, and the first active layer 121-1 and the second active layer 121-2 may comprise amorphous silicon, polycrystalline silicon, or organic semiconductor materials.

[0092] Gate electrodes 123-1 and 123-2 may comprise various conductive materials including Mo, Al, Cu, and Ti, and may have various stacked structures. For example, gate electrodes 123-1 and 123-2 may comprise Mo layers and Al layers, or may have a multilayer structure of Mo / Al / Mo.

[0093] In the example, the drive voltage line PL, the data line DL, and the connecting electrodes 127-1 and 127-2 can be located on the same layer. That is, the drive voltage line PL, the data line DL, and the connecting electrodes 127-1 and 127-2 can include the same material, can have the same layered structure, and can be formed concurrently or substantially simultaneously in a single process. Figures 3 to 6 As shown, one end 125-1 of the driving voltage line PL can be located on the first source region S1, which serves as the source electrode of the first thin-film transistor TFT1; one end 125-2 of the data line DL can be located on the second source region S2, which serves as the source electrode of the second thin-film transistor TFT2; the first connection electrode 127-1 can be located on the first drain region D1, which serves as the drain electrode of the first thin-film transistor TFT1; and the second connection electrode 127-2 can be located on the second drain region D2, which serves as the drain electrode of the second thin-film transistor TFT2. Therefore, in the plan view, one end 125-1 of the driving voltage line PL and one end 125-2 of the data line DL do not occupy separate areas and can overlap with either the first thin-film transistor TFT1 or the second thin-film transistor TFT2, thereby ensuring a wider design space.

[0094] Therefore, the driving voltage line PL, the data line DL, and the connecting electrodes 127-1 and 127-2 can include various conductive materials such as Mo, Al, Cu, and Ti, and can have various layered structures. For example, the driving voltage line PL, the data line DL, and the connecting electrodes 127-1 and 127-2 can include Ti layers and Al layers, or can have a Ti / Al / Ti multilayer structure.

[0095] Furthermore, to ensure the insulating properties between the active layers 121-1 and 121-2 and the gate electrodes 123-1 and 123-2, gate insulating layers 103, comprising inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride, can be located between the active layers 121-1 and 121-2 and the gate electrodes 123-1 and 123-2, respectively. Additionally, a first interlayer insulating layer 105, having a certain dielectric constant, can be located above the gate electrodes 123-1 and 123-2. The first interlayer insulating layer 105 can be an insulating layer comprising silicon oxide, silicon nitride, and / or silicon oxynitride. The drive voltage line PL, data line DL, and connection electrodes 127-1 and 127-2 can be located below the first interlayer insulating layer 105. In this way, the insulating layer comprising inorganic materials can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This can be applied to embodiments and examples of modifications thereof described later.

[0096] In some embodiments, the gate insulating layer 103 may be located between the active layers 121-1 and 121-2 and the gate electrodes 123-1 and 123-2, respectively, in the region where the gate insulating layer 103 overlaps with the gate electrodes 123-1 and 123-2. That is, the gate insulating layer 103 may be located only in the same region as the region where the gate electrodes 123-1 and 123-2 are located, and may be etched in one or more regions other than the region where the gate electrodes 123-1 and 123-2 are located. Therefore, the gate insulating layer 103 and the gate electrodes 123-1 and 123-2 can be etched once and can be formed using only one mask process. This improves process efficiency.

[0097] A capacitor Cst can have an upper electrode CE1 and a lower electrode CE2. With an interlayer insulating layer between the upper electrode CE1 and the lower electrode CE2, the upper electrode CE1 and the lower electrode CE2 can overlap each other to achieve capacitance. In this case, the interlayer insulating layer can serve as the dielectric layer of the capacitor Cst.

[0098] In some embodiments, the upper electrode CE1 of capacitor Cst may be located on the same layer as the gate electrodes 123-1 and 123-2 of the first thin-film transistor TFT1 and the second thin-film transistor TFT2. That is, the upper electrode CE1 may comprise the same material as the gate electrodes 123-1 and 123-2, and may have the same stacked structure as the gate electrodes 123-1 and 123-2. In this case, like the gate electrodes 123-1 and 123-2, the gate insulating layer 103 may be located below the upper electrode CE1, and may overlap the upper electrode CE1 with a substantially the same area as the upper electrode CE1, and the gate insulating layer 103 may serve as a dielectric layer.

[0099] Furthermore, the lower electrode CE2 of capacitor Cst can be located on the same layer as the connection electrodes 127-1 and 127-2 of the first thin-film transistor TFT1 and the second thin-film transistor TFT2. That is, the lower electrode CE2 can include the same material as the connection electrodes 127-1 and 127-2, and can have the same stacked structure as the connection electrodes 127-1 and 127-2. In this case, the lower electrode CE2 of capacitor Cst can be integrally formed with the second connection electrode 127-2 on the second drain region D2 of the second thin-film transistor TFT2.

[0100] Furthermore, the lower electrode CE2 of capacitor Cst can be located on the same layer as the connecting electrodes 127-1 and 127-2, the driving voltage line PL, and the data line DL. That is, when the lower electrode CE2 of capacitor Cst, the connecting electrodes 127-1 and 127-2, the driving voltage line PL, and the data line DL are located on the same layer, they can comprise the same material and have the same stacked structure. In this case, the first active layer 121-1 or the second active layer 121-2 can be located below the lower electrode CE2 and can overlap with the lower electrode CE2 with a substantially the same area.

[0101] The planarization layer 109 may be located on the first thin-film transistor TFT1 and the second thin-film transistor TFT2. When an organic light-emitting device, as an example of a display element 200, is located above the first thin-film transistor TFT1 and the second thin-film transistor TFT2, the planarization layer 109 typically planarizes the upper portion of the protective layer 107 used to cover the first thin-film transistor TFT1 and the second thin-film transistor TFT2. The planarization layer 109 may include organic materials such as benzocyclobutene (BCB) or hexamethyldisiloxane (HMDSO). Figures 4 to 5 In this embodiment, the planarization layer 109 has a single-layer structure, but in other embodiments it may have a multi-layer structure, and various modifications are possible.

[0102] In the display area of ​​the substrate 100, the display element 200 may be located on the planarization layer 109. The display element 200 may be an organic light-emitting device, which includes a pixel electrode 210, a counter electrode 230, and an intermediate layer 220 between the pixel electrode 210 and the counter electrode 230 and includes an emission layer.

[0103] like Figure 4 and Figure 5 As shown, the pixel electrode 210 can contact the first connection electrode 127-1 of the first thin-film transistor TFT1 through an opening formed in the planarization layer 109, thereby being electrically connected to the first thin-film transistor TFT1. The pixel electrode 210 can be a (semi-)transparent electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr and their compounds, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 may have an ITO / Ag / ITO stacked structure.

[0104] Pixel defining layer 110 may be located on planarization layer 109. Pixel defining layer 110 may have an opening corresponding to each sub-pixel in the sub-pixel, thereby defining an emitting region and a non-emitting region. In this case, the opening may be formed such that at least a portion of the center of pixel electrode 210 can be exposed. Furthermore, pixel defining layer 110 may increase the distance between the edge of pixel electrode 210 and the counter electrode 230 on pixel electrode 210, thereby preventing arcing at the edge of pixel electrode 210. Pixel defining layer 110 may comprise an organic material such as polyimide or HMDSO.

[0105] The intermediate layer 220 of the display element 200 may include a low molecular weight material or a polymer material.

[0106] When the intermediate layer 220 comprises a low molecular weight material, the intermediate layer 220 can have a structure in which the hole injection layer (HIL), hole transport layer (HTL), emission layer (EML), electron transport layer (ETL), and electron injection layer (EIL) are stacked into a single or complex structure, and can comprise various organic materials such as copper phthalocyanine (CuPc), N,N'-bis(1-naphthyl)-N,N'-diphenyl-benzidine (NPB), and tri-8-hydroxyquinoline aluminum (Alq3). These layers can be formed by methods such as vacuum deposition.

[0107] When the intermediate layer 220 comprises a polymer material, it may have a structure including an HTL and an EML. In this case, the HTL may comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may comprise polymer materials of polyphenylacetylene and polyfluorene types. The intermediate layer 220 may be formed by methods such as screen printing, inkjet printing, or laser-induced thermal imaging (LITI). The intermediate layer 220 is not limited to the examples described above, but may have various structures. Furthermore, the intermediate layer 220 may comprise a layer integrally formed in the plurality of pixel electrodes 210, or may comprise a layer patterned to correspond to each of the plurality of pixel electrodes 210 (overlapping with each of the plurality of pixel electrodes 210 when viewed from a direction perpendicular to the substrate 100).

[0108] The counter electrode 230 of the display element 200 may be located on top of the display area. In one example, the counter electrode 230 may include an integral layer to cover the entire surface of the display area and may be located on top of the display area. That is, the counter electrode 230 may be integrally formed in multiple display elements 200 to correspond to multiple pixel electrodes 210. In this case, the counter electrode 230 may cover the display area and may extend to a portion of the non-display area outside the display area. In another example, the counter electrode 230 may include a layer patterned to correspond to each of the multiple pixel electrodes 210 (e.g., overlapping each of the pixel electrodes 210 when viewed from a direction perpendicular to the substrate 100) and may be located on top of the display area.

[0109] The counter electrode 230 can be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 230 can be a transparent electrode or a reflective electrode, and can include a thin metal layer having a low work function, including lithium (Li), calcium (Ca), LiF / Ca, LiF / Al, Ag, Mg, and compounds thereof. Furthermore, in addition to the thin metal layer, the counter electrode 230 can further include a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In2O3.

[0110] Furthermore, in other embodiments, the display device may further include an encapsulation layer configured to cover the display element 200, thereby protecting the display element 200. The encapsulation layer can reduce or prevent the possibility of damage to the display element 200 due to external moisture or oxygen. The encapsulation layer may cover the display area and may extend to at least a portion of the non-display area. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.

[0111] Figure 6 The schematic map shows what is included. Figure 1 A cross-sectional view of the BML connection structure in the display device.

[0112] like Figure 6 As shown, BML 300 can be spaced apart from the lower portion of the first active layer 121-1 of the first thin-film transistor TFT 1. BML 300 can be connected to the pixel electrode 210 through contact holes for exposing a portion of BML 300 from the bottom surface of the pixel electrode 210. Therefore, a constant voltage or signal can be applied to BML 300, thereby reducing or preventing damage to the pixel circuit PC due to electrostatic discharge, and thus improving the reliability of the first thin-film transistor TFT 1.

[0113] Figure 7 It is a schematic map showing the manufacturing process. Figure 1 A flowchart of a method for displaying a device.

[0114] like Figure 7 As shown, a method for manufacturing a display device according to some embodiments may include first to sixth mask processes S10, S20, S30, S40, S50, and S60. That is, a process of sequentially applying six masks can be performed to manufacture a display device.

[0115] In the following text, reference will be made to Figures 8 to 17 Each mask process in the mask process is described in detail, and redundant content that includes the above descriptions will be omitted.

[0116] For example, referencing Figure 8 The first mask process S10 will be described with reference to... Figures 9 to 12 The second mask process S20 will be described with reference to Figure 13 The third mask process S30 will be described with reference to Figure 14 The fourth mask process S40 will be described with reference to Figure 15 The fifth mask process S50 will be described with reference to... Figure 16 The sixth mask process S60 is described, and references will be made to... Figure 17 The operation of the intermediate layer 220 and the counter electrode 230 forming the display element 200 is described.

[0117] Figures 8 to 17 This is a cross-sectional view of the display device taken along the first region PX1. However, the method of manufacturing the display device according to some embodiments can be performed concurrently or substantially simultaneously in multiple regions (e.g., in regions PX1 and PX2). For example, a material layer can be formed on the entire surface of the substrate 100 comprising multiple regions, and the formed material layer can be patterned simultaneously in each of the regions.

[0118] On the other hand, in some embodiments, the first to sixth masks used in the first to sixth mask processes S10, S20, S30, S40, S50, and S60 may mean a mask assembly comprising a frame having one or more openings (opening areas) and a mask in which one or more openings are formed along a pattern. Furthermore, if appropriate (e.g., in the second mask process S20), a halftone mask may be applied.

[0119] Figure 8 This is a process diagram illustrating the result of the first mask process S10.

[0120] The first masking process S10 may include forming a first conductive layer on a substrate 100 and patterning the first conductive layer on the substrate 100 into a BML 300 having an isolated shape. The area patterned in the BML 300 may be the area where a thin-film transistor is located in a subsequent process. Furthermore, as... Figure 8 As shown, BML300 can be patterned on substrate 100, and buffer layer 101 can be formed on the formed BML 300.

[0121] Figures 9 to 12 This is a process diagram illustrating the second mask process S20.

[0122] The second mask process S20 may include: sequentially forming a semiconductor layer 121m and a second conductive layer 125m on the result of the first mask process S10; patterning the semiconductor layer 121m into a first active layer 121-1 and a second active layer 121-2 and patterning the second conductive layer 125m into a driving voltage line PL, a data line DL, a first connecting electrode 127-1 and a second connecting electrode 127-2.

[0123] In some embodiments, the second mask used in the second masking process S20 may be a halftone mask capable of forming a photosensitive layer with a step difference for each region. The halftone mask may include a fully transmissive region, a partially transmissive region, and a non-transmissive region. A fully transmissive region may be a region in which all light incident on the halftone mask is transmitted, a partially transmissive region may be a region in which only a portion of the light incident on the halftone mask is transmitted, and a non-transmissive region may be a region in which all light incident on the halftone mask is blocked. When a photosensitive layer of uniform thickness is formed on the entire surface of the substrate 100 using a halftone mask, if the halftone mask is arranged on the upper portion of the photosensitive layer to overlap with the photosensitive layer, the region overlapping the fully transmissive region of the halftone mask may be an uncoated region A3 in which the entire photosensitive layer is removed, the region overlapping the partially transmissive region of the halftone mask may be a partially coated region A2 in which only a portion of the photosensitive layer is removed, and the region overlapping the non-transmissive region of the halftone mask may be a fully coated region A1 in which the photosensitive layer is not removed.

[0124] For example, a halftone mask can be formed in a certain pattern on a transparent substrate such as a quartz substrate. In this case, the nontransmissive area can be patterned on the quartz substrate using a material such as Cr or CrO2, and the transmittance of the illuminated light can be adjusted by using at least one material selected from the group consisting of Cr, Si, Mo, tantalum (Ta) and Al to adjust the ratio or thickness of the constituent parts.

[0125] For example, patterning the semiconductor layer 121m and the second conductive layer 125m in the second mask process S20 may include: forming a first photosensitive layer 400 on the second conductive layer 125m; forming a first photosensitive layer pattern by patterning the first photosensitive layer 400 using a second mask; removing the semiconductor layer 121m and the second conductive layer 125m located in the uncoated region A3 of the first photosensitive layer pattern; graying the entire surface of the first photosensitive layer pattern to remove the thickness of the first photosensitive layer 400 located in the semi-coated region A2 of the first photosensitive layer pattern; removing the second conductive layer 125m located in the semi-coated region A2 of the first photosensitive layer pattern using selective etching; and removing the first photosensitive layer 400 from the entire surface of the first photosensitive layer pattern.

[0126] In this case, the first photosensitive layer 400 may include a material (photoresist) that causes a chemical change when light is irradiated onto the first photosensitive layer 400. For example, the first photosensitive layer 400 may include a negative photoresist such as a diazide, methacrylate, or cinnamate, and / or may include a positive photoresist such as polymethyl methacrylate, naphthoquinone diazide, or polybutene 1-sulfone. However, the first photosensitive layer 400 is not limited to the examples described above.

[0127] like Figure 9 As shown, in the first photosensitive layer pattern, when the second mask is located on the second conductive layer 125m, all light irradiated on the fully transmissive area can pass through the uncoated area A3 overlapping the fully transmissive area of ​​the second mask, allowing the entire first photosensitive layer 400 to be removed, and thus forming an opening for exposing the second conductive layer 125m. Furthermore, a portion of the light irradiated on the semi-transmissive area can pass through the semi-coated area A2 overlapping the semi-transmissive area of ​​the second mask, allowing a first photosensitive layer 400 with a thickness less than its initial thickness to be formed. Additionally, all light irradiated on the non-transmissive area can be blocked in the fully coated area A1 overlapping the non-transmissive area of ​​the second mask, allowing the first photosensitive layer 400 to be retained, and a first photosensitive layer 400 with its initial thickness to be formed.

[0128] Subsequently, as Figure 10 As shown, portions of the semiconductor layer 121m and the second conductive layer 125m located in the uncoated area A3 of the first photosensitive layer pattern can be removed. Dry etching or wet etching processes using photoresist can be applied to such a removal process. However, any patterning process can be used in other embodiments. This can also be applied to other patterning processes in methods of manufacturing display devices.

[0129] Subsequently, as Figure 11 As shown, an ashing process can be performed to remove a portion of the first photosensitive layer 400 located in the semi-coated region A2 of the first photosensitive layer pattern from the entire surface of the first photosensitive layer pattern. (Refer to...) Figure 11 After the ashing process is performed, a portion of the first photosensitive layer 400 can be retained in the fully coated region A1, and all portions of the first photosensitive layer 400 can be removed from the partially coated region A2. Therefore, the second conductive layer 125m located in the partially coated region A2 can be exposed.

[0130] For example, in the ashing process, oxygen can be supplied and radio frequency or microwaves can be applied to generate plasma. The ions or free radicals in the plasma can chemically react with the photoresist, and these ions can collide with the photosensitive layer (photoresist), allowing the photosensitive layer to be removed. However, other embodiments are not limited to this.

[0131] Subsequently, as Figure 12As shown, the second conductive layer 125m located in the semi-coated region A2 exposed by the ashing process can be removed by using a selective etching process. In this case, the selective etching process can be a dry etching process or a wet etching process using photoresist, etc., but the process is not limited to these. As in processes using materials that satisfy a predetermined etch rate relative to the second conductive layer 125m and the semiconductor layer 121m, the selective etching process can include any etching process for enhancing the selectivity of the layer to be etched.

[0132] When the active layers 121-1 and 121-2, the driving voltage line PL, the data line DL, and the connecting electrodes 127-1 and 127-2 are patterned through the process described above, the first photosensitive layer 400 can be removed from the entire surface of the first photosensitive layer pattern. The process for removing the first photosensitive layer 400 can use a stripping process or a peeling process, but the process is not limited to these.

[0133] Although not in Figure 12 As shown, however, when the lower electrode CE2 of capacitor Cst is located on the same layer as the driving voltage line PL, data line DL, and connecting electrodes 127-1 and 127-2, the lower electrode CE2 can be formed together with the driving voltage line PL, data line DL, and connecting electrodes 127-1 and 127-2 in the second mask process S20. Like the driving voltage line PL, data line DL, and connecting electrodes 127-1 and 127-2, an active layer having an area substantially the same as the area of ​​the lower electrode CE2 can be located at the lower portion of the lower electrode CE2.

[0134] Figure 13 This is a process diagram illustrating the result of the third mask process S30.

[0135] The third mask process S30 may include: sequentially forming a first insulating layer and a third conductive layer on the result of the second mask process S20; using the third mask to pattern the first insulating layer into a gate insulating layer 103; and patterning the third conductive layer into gate electrodes 123-1 and 123-2.

[0136] For example, the third masking process S30 may include: sequentially forming a first insulating layer and a third conductive layer on the entire surface resulting from the second masking process S20; forming a second photosensitive layer pattern using the second mask after the second photosensitive layer is formed on the third conductive layer; and removing the first insulating layer and the third conductive layer in areas other than those where the gate insulating layer 103 and gate electrodes 123-1 and 123-2 are located by performing an etching process. In this case, the etching processes on the gate insulating layer 103 and gate electrodes 123-1 and 123-2 may not be performed separately, but rather a single etching process may be performed to etch the gate insulating layer 103 and the gate electrodes 123-1 and 123-2 in parallel or substantially simultaneously. Therefore, portions of the first insulating layer in areas where the gate electrodes 123-1 and 123-2 are not located can be etched and removed. The gate insulating layer 103 may be located substantially only in areas overlapping with the gate electrodes 123-1 and 123-2.

[0137] In some embodiments, when the upper electrode CE1 of capacitor Cst is located on the same layer as the gate electrodes 123-1 and 123-2, the upper electrode CE1 can be formed together with the gate electrodes 123-1 and 123-2 in the third mask process S30, and like the gate electrodes 123-1 and 123-2, a gate insulating layer 103 having an area substantially the same as the area of ​​the upper electrode CE1 can be located at the lower portion of the upper electrode CE1.

[0138] Figure 14 This is a process diagram illustrating the result of the fourth mask process S40.

[0139] The fourth mask process S40 may include: forming a second insulating layer on the result of the third mask process S30; and forming a plurality of contact holes on the second insulating layer by using the fourth mask.

[0140] For example, in the fourth masking process S40, a second insulating layer can be formed on the result of the third masking process S30, and a photosensitive layer pattern can be formed on the second insulating layer. This allows the second insulating layer to be exposed only at locations where multiple contact holes are formed by using the fourth mask, and contact holes can be formed in areas of the second insulating layer in which the second insulating layer is exposed. Furthermore, an additional layer (e.g., an insulating layer, a protective layer, or a planarization layer) can be located on the upper or lower portion of the second insulating layer. In this case, the contact holes formed in the second insulating layer can extend into the additional layer.

[0141] In this case, the multiple contact holes may include a first contact hole for exposing a portion of the first gate electrode 123-1, a second contact hole for exposing a portion of the first connection electrode 127-1, a third contact hole for exposing a portion of the second connection electrode 127-2, and a fourth contact hole for exposing a portion of the BML 300.

[0142] Figure 15 This is a process diagram showing the result of the fifth mask process S50.

[0143] The fifth mask process S50 may include: forming a fourth conductive layer on the result of the fourth mask process S40; and patterning the fourth conductive layer into pixel electrode 210 and bridging electrode 215.

[0144] For example, in the fifth mask process S50, the photosensitive layer pattern can be formed on the result of the fourth mask process S40 such that the top surface of the result of the fourth mask process S40 can be exposed only in the areas where the pixel electrode 210 and the bridging electrode 215 are to be formed by using the fifth mask, and electrode material can be arranged in the exposed areas so that the pixel electrode 210 and the bridging electrode 215 can be formed.

[0145] Pixel electrode 210 can be connected to first connection electrode 127-1 through a second contact hole formed in the fourth mask process S40, and bridging electrode 215 can be connected to first gate electrode 123-1 and second connection electrode 127-2 through the first contact hole and third contact hole formed in the fourth mask process S40. Therefore, first thin-film transistor TFT1 and pixel electrode 210 can be electrically connected to each other, and first thin-film transistor TFT1 and second thin-film transistor TFT2 can be electrically connected to each other through bridging electrode 215.

[0146] In the fifth mask process S50, the electrode material can even be arranged in the fourth contact hole. In this case, the BML 300 can be connected to the pixel electrode 210 through the fourth contact hole.

[0147] Figure 16 This is a process diagram showing the result of the sixth mask process S60.

[0148] The sixth mask process S60 may include: forming a pixel defining layer on the result of the fifth mask process S50; and patterning the pixel defining layer into a pixel defining layer 110 for defining emission regions and non-emission regions.

[0149] For example, in the sixth mask process S60, the photosensitive layer pattern can be formed on the result of the fifth mask process S50 such that the photosensitive layer can be located only in the area where the opening of the pixel defining layer 110 is to be formed by using the sixth mask, and the pixel defining layer material can be arranged in the area other than the area where the photosensitive layer is located, so that a pixel defining layer 110 with an opening for exposing a portion of the pixel electrode 210 can be formed.

[0150] like Figure 17As shown, after the sixth mask process S60, the intermediate layer 220 and the counter electrode 230 of the display element 200 can be formed.

[0151] As described above, according to some embodiments, process efficiency can be improved and the display device and its manufacturing method within the design space can be realized. The scope of this disclosure is not limited to the described aspects.

[0152] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended for limiting purposes. Descriptions of features or aspects within the embodiments should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made in one or more embodiments without departing from the spirit and scope defined by the appended claims, and functional equivalents of the appended claims should be included within the spirit and scope defined by the appended claims.

Claims

1. A display device, comprising: A substrate, comprising a first region in which a first pixel circuit is located and a second region in which a second pixel circuit is located; A first active layer is located on the first region and includes a first channel region, a first source region on a first side of the first channel region, a first drain region on a second side of the first channel region, and a first extension region extending in the direction from the first source region to the second region. The first gate electrode is located above the first active layer and overlaps with the first channel region; A gate insulating layer is located between the first active layer and the first gate electrode in the region overlapping with the first gate electrode; The driving voltage line is located directly on the first active layer, overlaps with the first source region, is located on the same layer as the gate insulating layer, and extends along the first extension region; The first connecting electrode is located on the first drain region; as well as A pixel electrode is located above the first gate electrode and is connected to the first connection electrode.

2. The display device according to claim 1, further comprising: The second active layer is located on the first region and includes a second channel region, a second source region on a first side of the second channel region, a second drain region on a second side of the second channel region, and a second extension region extending in the direction from the second source region to the second region. The second gate electrode is located above the second active layer and overlaps with the second channel region; The data line is located on the second active layer, overlaps with the second source region, and extends along the second extension region; The second connecting electrode is located on the second drain region; as well as A bridging electrode is used to electrically connect the second connecting electrode to the first gate electrode.

3. The display device according to claim 2, further comprising: The third active layer is located on the second region and includes a third channel region, a third source region on a first side of the third channel region, a third drain region on a second side of the third channel region, and a third extension region that extends in the direction from the third source region to the first region and is integral with the first extension region. as well as The third gate electrode is located above the third active layer and overlaps with the third channel region. The driving voltage line extends from the first extension region to the third extension region and overlaps with the third source region.

4. The display device according to claim 3, further comprising: The fourth active layer is located on the second region and includes a fourth channel region, a fourth source region on a first side of the fourth channel region, a fourth drain region on a second side of the fourth channel region, and a fourth extension region that extends in the direction from the fourth source region to the first region and is integral with the second extension region. as well as The fourth gate electrode is located above the fourth active layer and overlaps with the fourth channel region. The data line extends from the second extension area to the fourth extension area and overlaps with the fourth source area.

5. The display device according to claim 2, wherein The gate insulating layer is located between the second active layer and the second gate electrode in the region overlapping with the second gate electrode.

6. The display device according to claim 2, wherein, The bridging electrode comprises the same material as the pixel electrode and has the same stacked structure as the pixel electrode.

7. The display device according to claim 2, wherein, The driving voltage line, the data line, the first connection electrode, and the second connection electrode are made of the same material and have the same stacked structure.

8. The display device according to claim 2, wherein, The first active layer and the second active layer comprise oxide semiconductors.

9. The display device according to claim 1, further comprising: The bottom metal layer has an isolated shape and is located below the first active layer.

10. The display device according to claim 9, wherein, The bottom metal layer is electrically connected to the pixel electrode through a contact hole.

11. The display device according to claim 10, further comprising: Counter electrode, located on the pixel electrode; as well as An intermediate layer is located between the pixel electrode and the counter electrode and includes an emission layer.

12. A method of manufacturing a display device, the method comprising: The first mask process forms a first conductive layer on a substrate including a first region and a second region, and patterns the first conductive layer into a bottom metal layer with an isolated shape. The second mask process sequentially forms a semiconductor layer and a second conductive layer on the result of the first mask process. In the first region, the semiconductor layer is patterned into a first active layer and a second active layer, and the second conductive layer is patterned into a driving voltage line, a data line, a first connection electrode, and a second connection electrode. A third masking process sequentially forms a first insulating layer and a third conductive layer on the result of the second masking process, while patterning the first insulating layer and the third conductive layer, such that in the first region the first insulating layer is patterned into a gate insulating layer and the third conductive layer is patterned into a first gate electrode and a second gate electrode. as well as The fourth masking process involves forming a second insulating layer on the result of the third masking process, and forming a plurality of contact holes in the second insulating layer. The first active layer in the first region includes a first channel region, a first source region on a first side of the first channel region, a first drain region on a second side of the first channel region, and a first extension region extending in the direction from the first source region to the second region. The second active layer in the first region includes a second channel region, a second source region on a first side of the second channel region, a second drain region on a second side of the second channel region, and a second extension region extending in the direction from the second source region to the second region.

13. The method according to claim 12, wherein, The second mask process includes: In the second region, the semiconductor layer is patterned into a third active layer and a fourth active layer, and The second conductive layer is patterned into the driving voltage line, the data line, the third connection electrode, and the fourth connection electrode. The third mask process includes patterning the third conductive layer into a third gate electrode and a fourth gate electrode in the second region. The third active layer in the second region includes a third channel region, a third source region on a first side of the third channel region, a third drain region on a second side of the third channel region, and a third extension region extending in the direction from the third source region to the first region and integral with the first extension region. The fourth active layer in the second region includes a fourth channel region, a fourth source region on a first side of the fourth channel region, a fourth drain region on a second side of the fourth channel region, and a fourth extension region extending in the direction from the fourth source region to the first region and integral with the second extension region. The driving voltage line extends from the first extension region to the third extension region and overlaps with the third source region. The data line extends from the second extension area to the fourth extension area and overlaps with the fourth source area.

14. The method according to claim 12, wherein, The second mask in the second mask process includes a halftone mask, which includes a fully transmissive area, a semi-transmissive area, and a non-transmissive area.

15. The method according to claim 14, wherein, The second mask process includes: A first photosensitive layer is formed on the second conductive layer, and the first photosensitive layer is patterned using the second mask to form a first photosensitive layer pattern. Wherein, the second mask is located above the second conductive layer, and in the first photosensitive layer pattern, the first photosensitive layer is not located in the uncoated area overlapping the fully transmissive area of ​​the second mask, the first photosensitive layer is located in the semi-coated area overlapping the semi-transmissive area of ​​the second mask and has a thickness less than the initial thickness, and the first photosensitive layer is located in the fully coated area overlapping the non-transmissive area of ​​the second mask and has the initial thickness.

16. The method according to claim 15, wherein, The second mask process further includes: Remove the semiconductor layer and the second conductive layer located in the uncoated area; The entire surface of the first photosensitive layer pattern is grayed out, removing the thickness of the first photosensitive layer located in the semi-coated area; and The second conductive layer located in the semi-coated area is removed by selective etching.

17. The method of claim 12, further comprising: The fifth masking process involves forming a fourth conductive layer on the result of the fourth masking process, and patterning the fourth conductive layer into pixel electrodes and bridging electrodes. The bridging electrode electrically connects the second connecting electrode to the first gate electrode.

18. The method according to claim 17, wherein, The fourth mask process includes: In the second insulating layer, a first contact hole is formed for exposing a portion of the first gate electrode, a second contact hole is formed for exposing a portion of the first connection electrode, and a third contact hole is formed for exposing a portion of the second connection electrode.

19. The method according to claim 18, wherein, The fourth mask process further includes: A fourth contact hole is formed in the second insulating layer to expose a portion of the bottom metal layer, and The bottom metal layer is connected to the pixel electrode through the fourth contact hole.

20. The method of claim 19, further comprising: The sixth masking process forms a pixel-defining layer on the result of the fifth masking process, and patterns the pixel-defining layer into emitting and non-emitting regions.

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