A multi-channel super junction IGBT device

Abstract

The present invention proposes a multi-channel super junction IGBT device, including a metallized collector, a P-substrate, a first N-type epitaxial layer located above the P-substrate, and a second N-epitaxial layer located above the first N-type epitaxial layer; the second N-epitaxial layer includes at least a first virtual MOS cell unit and a MOS cell unit, and the first virtual MOS cell unit includes a groove formed by reactive ion etching, a thermally grown gate oxide layer arranged inside the groove, and heavily doped polysilicon deposited in the gate oxide layer. The device structure disclosed in the present invention breaks the cell size limit of the PN column pitch of the traditional super junction IGBT device, and can increase or decrease the top MOS cell and the virtual MOS cell according to the application requirements of the device to adjust the gate input capacitance of the super junction IGBT device, prevent current oscillation when the device is turned on, and improve the device's anti-EMI capability. At the same time, it also has the characteristics of adjusting the saturated output current density, forward conduction voltage drop, and short circuit time tolerance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a multi-channel super junction IGBT device. Background Art

[0002] A conventional super junction IGBT (Insulated Gate Bipolar Transistor) device structure in the prior art is as follows: Figure 1 As shown, it includes a metallized collector 1, a P-type substrate 2, a first N-type epitaxial layer 3 located above the P-type substrate 2, a P column 4 formed in the first N-type epitaxial layer by a deep trench etching backfilling process, a second N-epitaxial layer 5 located above the first N-type epitaxial layer 3 and the P column 4, and there is only one MOS cell 50 in the second N-type epitaxial layer 5. The MOS cell 50 includes a groove 6 formed by etching, a thermally grown gate oxide layer 7, deposited heavily doped polysilicon 8, and a P-type body region 9 formed by a self-alignment process. The P-type body region 9 is provided with partially independent N+ source regions 10, deposited borophosphosilicate glass 11, and a metallized emitter 12 on the upper surface.

[0003] Super junction IGBT devices are new power semiconductor devices that add repeated PN columns to the epitaxial layer based on the traditional IGBT device structure. The formation of PN columns has similar effects on the optimization of device parameters such as withstand voltage and forward conduction voltage drop as super junction MOS devices. The introduction of PN columns makes super junction IGBT devices have a better forward withstand voltage than Pbody-N - In addition to the longitudinal electric field of the Epi junction, the mutual depletion of the PN column generates a transverse electric field, which modulates the triangular electric field distribution of the traditional IGBT device into a rectangular distribution, greatly improving the voltage resistance of the super junction IGBT device. Under the premise of ensuring a certain breakdown voltage of the device, the concentration of the N-Epi layer can be significantly increased, thereby significantly reducing the forward conduction voltage drop, helping the super junction IGBT device to significantly reduce the conduction loss when used. Under the same current specifications, the area of ​​the super junction IGBT device can be greatly reduced, reducing the chip cost.

[0004] The formation of superjunction structure in superjunction IGBT device follows the process of superjunction MOS. There are two main manufacturing methods: one is to form superjunction structure through multiple epitaxial injections; the other is to complete it through deep trench etching and filling. Currently, both manufacturing methods are widely used and divided into different generations of products according to the width (pitch) of PN column. For example, the pitch of Infineon C3 process is 16μm, the pitch of C6 and P6 process is 12μm, and the pitch of C7 and P7 process is 5.5μm. There is only one MOS cell structure in each pitch.

[0005] The excellent electrical performance of super junction IGBT devices makes the chip area smaller and the current density higher. Smaller chip area leads to smaller gate input capacitance. When super junction IGBT devices are used to replace traditional IGBT devices, the strong driving current of the driver chip will cause the super junction IGBT device to easily form current oscillation when turned on, causing EMI problems and even causing the device to burn out. Therefore, super junction IGBT devices cannot directly replace traditional IGBT devices when applied. It is necessary to adjust the peripheral circuit or replace the driver chip with a smaller driving current, which indirectly increases the system cost and complexity of the application solution provider. At the same time, improving the current density of IGBT devices is also a key direction for the development of IGBT technology. Summary of the invention

[0006] In view of this, the technical problem to be solved by the present invention is to provide a multi-channel super junction IGBT device, which can adjust the gate input capacitance of the super junction IGBT device without changing the device process complexity and affecting the device breakdown voltage, prevent current oscillation when the device is turned on, enhance the device's anti-EMI capability, and directly replace the traditional IGBT device when applied. It also has the characteristics of adjusting the saturated output current density, forward conduction voltage drop, and short-circuit time tolerance.

[0007] The technical scheme of the present invention is: a multi-channel super junction IGBT device, comprising: a metallized collector, a P-substrate, a first N-type epitaxial layer located above the P-substrate, and a second N-epitaxial layer located above the first N-type epitaxial layer; a P column is formed in the first N-type epitaxial layer by multiple epitaxial implantations or deep trench etching backfilling processes, and the second N-epitaxial layer comprises at least two first virtual MOS cell units and a MOS cell unit, wherein the first virtual MOS cell unit has the same structure as the MOS cell unit, and the first virtual MOS cell unit comprises a groove formed by reactive ion etching, a thermally grown gate oxide layer arranged inside the groove, and heavily doped polysilicon deposited in the gate oxide layer, a P-type body region formed by a self-aligned process, borophosphosilicate glass deposited above the P-type body region, and an emitter with a metallized upper surface located above the borophosphosilicate glass;

[0008] The second N epitaxial layer may further include a second virtual MOS cell unit, the second virtual MOS cell unit and the MOS cell unit have the same structure, and the P-type body region of the second virtual MOS cell unit does not have an emitter potential;

[0009] A plurality of mutually independent source regions are arranged in the P-type body region of the MOS cell unit.

[0010] Preferably, in the second N epitaxial layer, the number and ratio of the first virtual MOS cell unit, the second virtual MOS cell unit and the MOS cell unit are adjusted according to application requirements, wherein there is at least one MOS cell unit and all of them may be MOS cell units.

[0011] Preferably, the resistivity of the second N epitaxial layer is greater than that of the first N epitaxial layer, and the resistivity of the second N epitaxial layer is in the range of 4-40Ω·cm.

[0012] Preferably, the second N epitaxial layer has a thickness in the range of 4-40 μm.

[0013] Preferably, the P column is formed by deep trench etching and silicon backfilling process or by multiple epitaxy and ion implantation and high temperature annealing.

[0014] Preferably, the P column does not contact the P-type body region and the trench.

[0015] Preferably, the upper layer of the metallized collector is formed into a field stop layer by epitaxy, and the resistivity of the field stop layer is smaller than that of the first N-type epitaxial layer. The thickness of the field stop layer is 10-40 μm.

[0016] Preferably, the solution of the present invention is applicable to a P-channel multi-channel super junction IGBT device.

[0017] Preferably, the semiconductor material in the IGBT device may be bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0018] The beneficial effect of the present invention is that a multi-channel super junction IGBT device can adjust the gate input capacitance of the super junction IGBT device by adjusting the number of the first virtual MOS cell unit, the MOS cell unit and the second virtual MOS cell unit of the top structure of the device, and has the advantages of adjusting the saturated output current density, the forward conduction voltage drop, the short circuit time tolerance and the like of the device. Increasing the first virtual MOS cell unit can increase the gate input capacitance, prevent the current oscillation when the device is turned on, and improve the device's anti-EMI capability. Increasing the third virtual MOS cell unit can form an electron accumulation region under the P-type body region when the device is forward-conducted, modulate the carrier concentration distribution inside the device to be closer to a PIN diode, form a carrier injection enhancement effect, reduce the forward conduction voltage drop of the device, and reduce the conduction loss of the device. According to simulation data, increasing the first virtual MOS cell unit can increase the gate input capacitance of the super junction IGBT device by multiples. Adding two second virtual MOS cell units can reduce the forward conduction voltage drop by more than 10%. In addition, the increase of the first virtual MOS cell unit and the second virtual MOS cell unit does not affect the breakdown voltage and short circuit tolerance characteristics of the device. The MOS cell unit provides the base current of the parasitic PNP transistor to the super junction IGBT device. Increasing the MOS cell unit can increase the electron hole density of the first N-type epitaxial layer, thereby increasing the saturated output current density of the device, while reducing the forward conduction voltage drop and reducing conduction loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic structural diagram of a conventional super junction IGBT device embodiment of the prior art;

[0020] Figure 2 It is a schematic structural diagram of a multi-channel super junction IGBT device according to the first embodiment of the present invention;

[0021] Figure 3 is a schematic structural diagram of a multi-channel super junction IGBT device according to a second embodiment of the present invention;

[0022] Figure 4 is a schematic structural diagram of a multi-channel super junction IGBT device according to a third embodiment of the present invention;

[0023] Figure 5 is a schematic structural diagram of a multi-channel super junction IGBT device according to a fourth embodiment of the present invention;

[0024] FIG6 is a manufacturing flow chart of key steps of the first embodiment of the present invention; DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be fully described in a specific way in combination with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work fall within the protection scope of the present invention. The principles and features of the present invention are described below in combination with the drawings. The examples are only used for the present invention at that time, and are not used to limit the scope of the present invention.

[0026] It should be understood that the terms such as "having", "including" and "comprising" used in the present invention do not specify the existence or addition of one or more other elements or their combinations. At the same time, in order to clearly illustrate the specific embodiments of the present invention, the schematic diagrams listed in the drawings of the specification magnify the thickness of the layers and regions described in the present invention, and the sizes of the listed figures do not represent the actual sizes; the drawings of the specification are schematic and should not limit the scope of the present invention. The embodiments listed in the specification should not be limited to the specific shapes of the regions shown in the drawings of the specification, but include the obtained shapes such as deviations caused by preparation.

[0027] like Figure 2 As shown, a multi-channel super junction IGBT device provided by the first embodiment of the present invention includes a metallized collector 1, a P-substrate 2, a first N-type epitaxial layer 3 located above the P-substrate 2, and a second N-epitaxial layer 5 located above the first N-type epitaxial layer 3; a P column 4 is formed in the first N-type epitaxial layer 3 by multiple epitaxial implantations or deep trench etching backfilling processes, and the second N-epitaxial layer 5 includes at least two first virtual MOS cell units 51 and a MOS cell unit 50, wherein the first virtual MOS cell unit (5 1) having the same structure as the MOS cell unit (50), the first virtual MOS cell unit (51) comprising a groove (6) formed by reactive ion etching, a thermally grown gate oxide layer (7) arranged inside the groove (6) and heavily doped polysilicon (8) deposited inside the gate oxide layer (7), a P-type body region (9) formed by a self-alignment process, a deposited borophosphosilicate glass (11) located above the P-type body region (9), and an emitter (12) with a metallized upper surface located above the borophosphosilicate glass (11);

[0028] The second N epitaxial layer 5 may further include a second virtual MOS cell unit 52, the second virtual MOS cell unit 52, the first virtual MOS cell unit 51 and the MOS cell unit 50 have the same structure, and the P-type body region 9 of the second virtual MOS cell unit 52 is not connected to the potential of the emitter 12;

[0029] A plurality of mutually independent source regions 10 are disposed in the P-type body region 9 of the MOS cell unit 50 .

[0030] Furthermore, the number and ratio of the second virtual MOS cell unit 52 , the first virtual MOS cell unit 51 and the MOS cell unit 50 in the second N epitaxial layer 5 are adjusted according to application requirements, wherein there is at least one MOS cell unit 50 and all of them may be MOS cell units 50 .

[0031] Furthermore, the resistivity of the second N epitaxial layer 5 is greater than that of the first N epitaxial layer 3 , and the resistivity of the second N epitaxial layer 5 is in the range of 4-40Ω·cm.

[0032] Furthermore, the thickness of the second N epitaxial layer 5 is in the range of 4-40 μm.

[0033] A further feature is that the P column 4 is formed by deep trench etching and silicon backfilling process, multiple epitaxy or ion implantation and high temperature annealing.

[0034] Furthermore, the P column 4 is not in contact with the P-type body region 9 and the trench 6 .

[0035] Furthermore, the upper layer of the metallized collector 1 is formed into a field stop layer by epitaxy, and the resistivity of the field stop layer is less than the resistivity of the first N-type epitaxial layer 3 . The thickness of the field stop layer is 10-40 μm.

[0036] Furthermore, the solution of the present invention is applicable to a P-channel multi-channel super junction IGBT device.

[0037] Furthermore, the semiconductor material in the IGBT device may be bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

[0038] The first advantage of the present invention is that the number of virtual MOS cells 51 and MOS cells 50 is increased, which is not limited by the process pitch used by the device. The super junction withstand voltage part of the super junction IGBT device is separated from the top MOS part, and each can be designed independently without being affected.

[0039] The second advantage of the present invention is that adding the first virtual MOS cell unit 51 does not change the main process flow of the super junction IGBT device, and the solution is highly operable.

[0040] The third advantage of the present invention is that the number of first virtual MOS cell units 51 can be flexibly increased according to application requirements. This solution can monotonically increase the gate input capacitance of the super junction IGBT device, thereby avoiding the current oscillation and EMI problems of the super junction IGBT device. At the same time, the breakdown voltage and short circuit tolerance of the device will not degrade. In addition to increasing the virtual MOS cells, the MOS cell unit 50 can also be increased, which can significantly improve the saturated output current density of the device, enhance the conductivity modulation state effect, and reduce the forward conduction voltage drop of the device.

[0041] Figure 3 It is a schematic diagram of the structure of a multi-channel super junction IGBT device of the present invention, wherein the emitter contact hole is not opened in the second virtual MOS cell unit 52, so that the potential of the P-type body region 9 is floating, which is conducive to the formation of an electron accumulation layer below the P-type body region 9 when the device is forward-conducted, thereby reducing the forward conduction voltage drop;

[0042] Figure 4 Schematic diagram of a multi-channel super junction IGBT device structure of the present invention, corresponding to the first embodiment, wherein the super junction part can be formed by multi-layer epitaxy and multiple ion implantation, the principle is the same as Figure 2 Embodiment 1.

[0043] Figure 5 Schematic diagram of a multi-channel super junction IGBT device structure of the present invention, corresponding to the second embodiment, wherein the super junction part can be formed by multi-layer epitaxy and multiple ion implantation, the principle is the same as Figure 3 Embodiment 2.

[0044] FIG6 is a manufacturing flow chart of the key steps of the first embodiment of the present invention. Figure 6-1 It is an epitaxial wafer used in Wafer start, including a high-resistance P-type substrate 2 and a first N-type epitaxial layer 3; Figure 6-2 The P column 3 is formed by deep trench reactive ion etching and silicon backfilling process to form a super junction structure of a super junction IGBT device; Figure 6-3 The second N-type epitaxial layer 5 is formed by high-temperature epitaxy. The key is that the resistivity of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer, so as to avoid the walk-out phenomenon during the test process. Figure 6-4 A hard mask is used to form a trench 6 by reactive ion etching, and a carrier storage layer is implanted; Figure 6-5 The gate oxide layer 7 is thermally grown by dry oxidation; Figure 6-6 Depositing in-situ doped polysilicon and etching to form a gate 8; Figure 6-7 The P-type body region 9 is formed by self-alignment, using ion implantation and high temperature well driving; Figure 6-8 The emitter region 10 is formed by photolithography implantation, and the implantation area of ​​the emitter region distinguishes the dummy MOS cell 51 from the MOS cell 50; Figure 6-9The process is to deposit borophosphosilicate glass 11, reflow at high temperature, perform contact hole photolithography and etching, and etch away 3000-5000A thick silicon. Whether the contact hole is opened or not distinguishes between virtual cells 51 and 52. Then, a metal layer is deposited to form an emitter 12. After that, the wafer is flipped over to thin the device, P-type ions are injected to form an ohmic contact, and a Ti / NiV / Ag metal layer is deposited to form a collector 1, and finally a structure such as Figure 2 The first embodiment of the present invention is shown.

[0045] Figure 6 describes the key steps of manufacturing an N-channel super junction IGBT device, and the solution of the present invention is also applicable to a P-channel super junction IGBT device. The semiconductor material may be bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

Claims

1. A multi-channel super junction IGBT device, characterized in that: The invention comprises a metallized collector (1), a P-substrate (2), a first N-type epitaxial layer (3) located above the P-substrate (2), and a second N-epitaxial layer (5) located above the first N-type epitaxial layer (3); a P column (4) is formed in the first N-type epitaxial layer (3) by multiple epitaxial implantations or deep trench etching backfilling processes; the second N-epitaxial layer (5) comprises at least two first virtual MOS cell units (51) and a MOS cell unit (50); the first virtual MOS cell unit (51) and the MOS cell unit (50) have the same structure; the first virtual MOS cell unit (51) comprises a groove (6) formed by reactive ion etching, a thermally grown gate oxide layer (7) arranged inside the groove (6) and heavily doped polysilicon (8) deposited in the gate oxide layer (7); a P-type body region (9) formed by a self-alignment process and a P-type gate region (9) located inside the P- A borophosphosilicate glass (11) deposited above the body region (9) and an emitter (12) with an upper surface metallized and located above the borophosphosilicate glass (11); The second N epitaxial layer (5) includes a second virtual MOS cell unit (52); the second virtual MOS cell unit (52), the first virtual MOS cell unit (51) and the MOS cell unit (50) have the same structure; the P-type body region (9) of the second virtual MOS cell unit (52) does not have a potential connected to the emitter (12); and the P-type body region (9) of the MOS cell unit (50) is provided with a plurality of mutually independent source regions (10); The resistivity of the second N epitaxial layer (5) is greater than that of the first N epitaxial layer (3), and the resistivity of the second N epitaxial layer (5) is in the range of 4-40Ω•cm; The thickness of the second N epitaxial layer (5) is in the range of 4-40µm.

2. A multi-channel super junction IGBT device according to claim 1, characterized in that: The number and ratio of the first virtual MOS cell unit (51), the second virtual MOS cell unit (52) and the MOS cell unit (50) in the second N epitaxial layer (5) are adjusted according to application requirements, wherein there is at least one MOS cell unit (50).

3. The multi-channel super junction IGBT device according to claim 1, characterized in that: The P column (4) is formed by deep trench etching and silicon backfilling process or by multiple epitaxy and ion implantation and high temperature annealing.

4. The multi-channel super junction IGBT device according to claim 1, characterized in that: The P column (4) is not in contact with the P-type body region (9) and the trench (6).

5. The multi-channel super junction IGBT device according to claim 1, characterized in that: The upper layer of the metallized collector (1) forms a field stop layer through epitaxy, and its resistivity is lower than the resistivity of the first N-type epitaxial layer (3). The thickness of the field stop layer is 10-40 μm.

6. A multi-channel super junction IGBT device according to any one of claims 1 to 5, characterized in that: The IGBT device is suitable for a P-channel multi-channel super junction IGBT device.

7. A multi-channel super junction IGBT device according to any one of claims 1 to 5, characterized in that: The semiconductor material in the IGBT device is bulk silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium.

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