Power management integrated circuit and operating method thereof

Abstract

A power management integrated circuit (PMIC) and its operation method are provided. The PMIC includes: a DC-DC converter configured to provide output power to a load; a controller configured to control the switching of the DC-DC converter; and a sensing circuit including a capacitor element and configured to detect the output current flowing through a node between the DC-DC converter and the load.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0069838, filed on June 9, 2020, and Korean Patent Application No. 10-2021-0054635, filed on April 27, 2021, the entire subject matter of which is incorporated herein by reference. Technical Field

[0002] The inventive concept generally relates to power management integrated circuits (PMICs), and more specifically, to PMICs including detection circuits having capacitive elements capable of extending the operating bandwidth of the PMIC. Background Technology

[0003] Power control interfaces (PMICs) have become essential components in numerous consumer products, such as smartphones and tablet PCs. These products (many of which are mobile devices or battery-powered devices) require efficient power management. That is, minimizing power consumption and improving power efficiency are crucial aspects of PMICs in mobile devices. Switching regulators (e.g., pulse-width modulation (PWM) DC-DC converters) that can provide power with high drive voltage and excellent power efficiency have been widely used in PMICs because they typically offer a stable output voltage. However, unfortunately, DC-DC converters have limited operating bandwidth. Summary of the Invention

[0004] In response to this limitation and to address other related issues, embodiments of the inventive concept provide a PMIC including a detection circuit with a capacitive element that provides additional zeros and poles, thereby extending the operating bandwidth.

[0005] According to one aspect of the inventive concept, a PMIC is provided, the PMIC comprising: a DC-DC converter configured to provide output power to a load; a controller configured to control the switching of the DC-DC converter; and a sensing circuit including a capacitive element and configured to detect the output current flowing through a node between the DC-DC converter and the load.

[0006] According to one aspect of the inventive concept, a PMIC is provided, the PMIC comprising: a DC-DC converter configured to provide output power to a load; a controller configured to control the switching of the DC-DC converter; a sensing circuit including a capacitor array and configured to detect the output current flowing through a node between the DC-DC converter and the load; and a frequency-to-digital converter configured to adjust the total capacitance of the capacitor array.

[0007] According to one aspect of the inventive concept, a method for operating a PMIC is provided. The method includes: detecting a change in output current at a node between the PMIC and a load; and supplying an output voltage corresponding to the output current to the node based on added zeros and poles associated with a capacitive element included in a sensing circuit. Attached Figure Description

[0008] The advantages of the inventive concept, as well as its generation and use, can be clearly understood by considering the following specific embodiments and accompanying drawings, in which:

[0009] Figure 1 This is a block diagram illustrating an electronic device including a PMIC according to an embodiment of the inventive concept;

[0010] Figure 2 , Figure 7 , Figure 9 and Figure 10 These are block diagrams illustrating different embodiments of the PMIC according to the inventive concept;

[0011] Figure 3A , Figure 3B and Figure 3C This is a corresponding circuit diagram illustrating a DC-DC converter according to an embodiment of the inventive concept;

[0012] Figure 4 This is a circuit diagram illustrating a detection circuit according to an embodiment of the inventive concept;

[0013] Figure 5A and Figure 5B This is a graph showing the relationship between amplitude and frequency of a PMIC according to an embodiment of the inventive concept, as well as the relationship between amplitude and phase and frequency.

[0014] Figure 6 This is a flowchart illustrating a method of operating a PMIC according to an embodiment of the inventive concept;

[0015] Figure 8 This is a circuit diagram illustrating a capacitor array according to an embodiment of the inventive concept;

[0016] Figure 11A and Figure 11B This is a flowchart illustrating a method of operating a PMIC according to an embodiment of the inventive concept; and

[0017] Figure 12 This is a graph showing the amplitude of the capacitive element as a function of frequency for various adjustment modes according to embodiments of the inventive concept. Detailed Implementation

[0018] Throughout the written description and accompanying drawings, the same reference numerals and labels are used to denote the same or similar elements, components, and features. In the following, embodiments of the inventive concept will be described in some additional detail with reference to the accompanying drawings.

[0019] Figure 1 This is a block diagram illustrating an electronic device 1000 including a power management integrated circuit (PMIC) 1100 according to an embodiment of the inventive concept.

[0020] Reference Figure 1 The electronic device 1000 may include a PMIC 1100, an application processor (AP) 1200, an input device 1300, a display 1400, a memory 1500, and a battery 1600. In this regard, electronic device 1000 may be any of the following: vehicle, smartphone, personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player, ultra-mobile PC (UMPC), workstation, portable computer, webtablet, tablet computer, cordless phone, mobile phone, e-book, portable game console, navigation device, black box, digital camera, digital multimedia broadcast (DMB) player, 3D television, smart television, digital audio recorder, digital audio player, digital image recorder, digital image player, digital video recorder, digital video player, storage device constituting a data center, device capable of transmitting (e.g., sending and / or receiving) information via a wireless environment, various electronic devices constituting a home network, various electronic devices constituting a computer network, various electronic devices constituting a telematics network, radio frequency identification (RFID) device, or various components constituting a computing system. In some embodiments, electronic device 1000 may be a wearable device (such as an electronic bracelet or electronic necklace).

[0021] Electronic device 1000 may include at least one PMIC 1100. PMIC 1100 may receive power from battery 1600 and may generally regulate, limit, supply and / or manage the power within electronic device 1000 (hereinafter, individually or collectively, “manage power”). That is, PMIC 1100 may manage the power associated with AP 1200, input device 1300, display 1400 and / or memory 1500.

[0022] Therefore, in some embodiments, the electronic device 1000 may use a single PMIC 1100 to manage power related to the AP 1200, input device 1300, display 1400, and / or memory 1500, and in other embodiments, the electronic device 1000 may use multiple PMICs 1100 to manage power related to the AP 1200, input device 1300, display 1400, and / or memory 1500.

[0023] AP 1200 can control the overall operation of electronic device 1000. For example, AP 1200 can display data stored in memory 1500 using display 1400 based on input signals generated by input device 1300. Here, input device 1300 can be implemented as a pointing device, touchpad, computer mouse, keypad, keyboard, etc.

[0024] Of particular note regarding embodiments of the inventive concept is that the PMIC 1100 can operate with an extended operating bandwidth and relaxed phase margin by ensuring additional zeros and poles. Furthermore, the PMIC 1100 can operate with improved frequency response characteristics by adjusting the zeros and poles with respect to a specific operating frequency.

[0025] Figure 2 This is a block diagram illustrating an embodiment of the PMIC 10 according to the inventive concept. Figure 2 The PMIC 10 can be understood as the previous one regarding Figure 1 An example of the PMIC 1100 described.

[0026] Reference Figure 1 and Figure 2 The PMIC 10 can supply power and / or clock signals to the electronic device 1000. In this regard, the PMIC 10 can receive power from an external source, convert and / or regulate (e.g., rectify) the received power to generate a stable voltage and / or current (hereinafter, "voltage / current"), and then distribute and control the generated voltage / current. Here, the PMIC 10 can be implemented as a single semiconductor chip or a group of semiconductor chips.

[0027] exist Figure 2 In the illustrated example, PMIC 10 may include a controller 100, a DC-DC converter 200, a sensing circuit 300, and a load 400, wherein the sensing circuit 300 includes a capacitor element 310.

[0028] The controller 100 can be used to control the overall operation of the PMIC 10, or at least control the intelligent components of the PMIC 10 (such as the DC-DC converter 200 and the sensing circuit 300). That is, the controller 100 can provide various functional controls consistent with the nature and purpose of the electronic device 1000. For example, in some embodiments, the AP 1200 can be used to generate various control signals for controlling the intelligent components of the PMIC 10.

[0029] In some embodiments, controller 100 can control the operation of PMIC 10 by adjusting the switching (or switching) time (or switching cycle) of DC-DC converter 200 to appropriately generate output power (e.g., voltage / current) supplied to load 400. That is, controller 100 can receive a control signal indicating a change in the output power to be supplied to load 400 as a result of voltage detection operations performed by sensing circuit 300. For example, controller 100 can adjust the switching time of DC-DC converter 200 in response to fluctuations in output power. Although not explicitly stated... Figure 2 As shown, however, the controller 100 may provide operating frequencies for driving the PMIC 10 to other components or devices.

[0030] In some embodiments, the controller 100 may be implemented as a central processing unit (CPU), an arithmetic logic unit (ALU) that performs arithmetic and logical operations (such as bit shifting), a digital signal processor (DSP), a microprocessor, an application-specific integrated circuit (ASIC), control logic, etc. In some embodiments, the controller 100 may include a state machine containing logic gates or a combination of a processor and a memory storing instructions executable by the processor.

[0031] The DC-DC converter 200 can convert direct current (DC) power with a first level into DC power with a second (different) level. In some embodiments, the DC-DC converter 200 can use a switching element to interrupt the input DC power received from an external source and can be configured to generate output DC power by adjusting the switching cycle. In some embodiments, the external source providing the input DC power can be a battery 1600.

[0032] In some embodiments, output DC power can be provided to a load 400 included in the PMIC 10.

[0033] The output DC power can be used differently as a voltage / current having a level that can change in response to a control signal provided by the sensing circuit 300. That is, in some embodiments, the first DC power and the second DC power can have different levels, different frequencies, and / or different phases. However, in other embodiments, the AC input power can be provided by an external source, and the DC power can be supplied to the DC-DC converter 200 through appropriate AC-DC conversion (e.g., by using an AC-DC converter).

[0034] As described above, a switching regulator can be used as a type of DC-DC converter 200. The switching regulator generates DC power by adjusting the switching cycle of the switching elements. For example, the switching regulator can use a ramp signal to generate a pulse width modulation (PWM) signal and generate a desired output voltage by raising and / or lowering (hereinafter referred to as "raising / lowering") the input voltage in response to the PWM signal.

[0035] In some embodiments, the DC-DC converter 200 may include a buck converter that generates power at a level lower than the input power, a boost converter that generates power at a level higher than the input power, and / or a buck-boost converter that generates power at a level higher or lower than the input power. However, the inventive concept is not limited thereto, and various types of DC-DC conversion can be performed by the DC-DC converter 200.

[0036] In some embodiments, the sensing circuit 300 can detect the output power supplied to the load 400. That is, the sensing circuit 300 can monitor the output power supplied to the load 400 (e.g., output voltage / current, output power, output frequency, output phase, etc.) at a first node N1 to provide the controller 100 with information about voltage changes (e.g., voltage drops and / or voltage rises) related to the output power. In some embodiments, this information can be transmitted from the sensing circuit 300 to the controller 100 in the form of a "voltage change signal".

[0037] In response to a voltage change signal, the controller 100 (or some other component in the electronic device 1000) can operate (e.g., perform one or more functions) to stabilize the output power according to the detected voltage change. These one or more functions can be implemented in hardware and / or software. In some embodiments, the sensing circuit 300 can also be connected to ground (GND) at the second node N2 as a measurement reference. With this configuration, the sensing circuit 300 can operate to monitor the state of the output power within a defined operating bandwidth.

[0038] Under certain conditions, the magnitude and variation of the output power (e.g., output current) provided by the DC-DC converter may increase. A sudden change in output current may cause the output voltage to drop below a minimum threshold. If the output voltage drops below the minimum threshold, it may not be supplied to the load, and a malfunction of the electronic device containing the DC-DC converter may occur. Here, as conventionally provided, the operating bandwidth of the DC-DC converter 200 may be limited by its structural (or compositional) characteristics. Furthermore, the DC-DC converter 200 may experience switching losses, thus presenting practical limitations on extending the operating bandwidth of a PMIC containing the DC-DC converter 200.

[0039] However, according to embodiments of the inventive concept, the sensing circuit 300 may include a capacitor element 310. In this context, a “capacitor element” can be understood as an element in an AC circuit where the phase of the current leads (or precedes) the phase of the voltage. The capacitor element 310 may be configured differently. For example, the capacitor element 310 may include one or more discrete capacitors. In this document, the term “discrete” refers to a physically identifiable element, in contrast to distributed, parasitic, or inherent elements.

[0040] In some embodiments, the capacitor element 310 may be a variable capacitor. In some embodiments, the capacitor element 310 may be a capacitor array comprising two or more capacitors. However, the inventive concept is not limited thereto, and the capacitor element 310 may be implemented as a combination of passive and / or active elements capable of influencing (or changing) capacitance. Thus, in some embodiments, the capacitor element 310 may represent one or more passive and / or active elements providing capacitive reactance greater than inductive reactance.

[0041] As described above, in some embodiments, the setup and connections of the sensing circuit 300 within the PMIC 10 can be understood as implementing a negative feedback path associated with the controller 100. Therefore, in some embodiments, the capacitor element 310 can be understood as an additional capacitor element added to the negative feedback path of the sensing circuit 300. In this regard, by adding the capacitor element 310 to the negative feedback path of the sensing circuit 300, embodiments of the inventive concept generate additional zeros and poles associated with the operation of the sensing circuit 300. These added zeros and poles can effectively increase the operating bandwidth (and phase margin) of the DC-DC converter 200 and the PMIC 10. For example, the DC-DC converter 200 has an operating bandwidth and phase margin at least partially determined by the capacitor element 310 of the sensing circuit 300.

[0042] Therefore, the added capacitor element 310 can be used to adjust the total capacitance of the negative feedback path. Here, the total capacitance can be determined based on the permissible operating frequency or permissible operating bandwidth of the PMIC 10. Furthermore, the total capacitance, including capacitor element 310, can be adjusted so that optimal pole and zero arrangements can be provided under the control of the electronic device 1000.

[0043] In the preceding description, load 400 can be understood as any element or component that consumes electrical energy and is managed by PMIC 10. In this regard, load 400 can be modeled as the total resistance required for the operation of electronic device 1000. Therefore, load 400 is supplied with voltage / current managed by PMIC 10.

[0044] In some of the illustrated embodiments of the inventive concept, load 400 is described as being included within PMIC 10, but this is merely an example for ease of description. Load 400 can be understood as a model of an electrical energy sink associated with various intellectual property blocks that variably require voltage / current during operation of electronic device 1000.

[0045] Of particular note is that embodiments of the inventive concept (e.g., PMIC 10) completely address the operating bandwidth limitations associated with the DC-DC converter 200 by providing a capacitor element 310 to the sensing circuit 300. Therefore, embodiments of the inventive concept can extend the operating bandwidth and phase margin for better stabilization of the electronic device 1000 including the PMIC 10. As an additional benefit, because embodiments of the inventive concept can adjust the zero-point and pole arrangement by adjusting the capacitance of the capacitor element 310, the transient response state can be quickly stabilized and the frequency response characteristics can be improved.

[0046] Figure 3A This is a circuit diagram illustrating a DC-DC converter 210 according to an embodiment of the inventive concept. Figure 3A The DC-DC converter 210 is Figure 2 An example of a DC-DC converter 200, which can be used to perform the functions described above.

[0047] Reference Figure 2 and Figure 3A The DC-DC converter 210 can be implemented as a buck converter capable of generating an output power level lower than the input power. For example, the DC-DC converter 210 may include a P-type metal-oxide-semiconductor field-effect transistor (MOSFET). a N-type MOSFET MN a Inductor L a Converter resistor R Paand converter capacitor C Oa .

[0048] The DC-DC converter 210 can be supplied with a P-type MOSFET control signal PD from the controller 100. a and / or N-type MOSFET control signal ND a Furthermore, it can convert the source voltage VDD into a DC voltage with a different level. In some embodiments, the DC-DC converter 210 can generate a DC voltage with a level lower than that of the source voltage VDD. The DC-DC converter 210 can generate an output voltage V Oa As an output, the output voltage can be provided to the first node N1.

[0049] In some embodiments, the source voltage VDD can be generated from the P-type MOSFET MP. a One end (e.g., the source) is applied, and a third node N3 can be formed in the P-type MOSFET MP. a At the other end (e.g., the drain), and the P-type MOSFET control signal PD a It can be supplied to P-type MOSFET MP a The gate of the N-type MOSFET MN. In some embodiments, the third node N3 may be formed in the N-type MOSFET MN. a At one end (e.g., the drain), the ground power supply GND can be obtained from the N-type MOSFET MN. a The other end (e.g., the source) is applied, and the N-type MOSFET control signal ND is applied. a It can be supplied to N-type MOSFET MN a The gate of the DC-DC converter. In some embodiments, the DC-DC converter 210 can be controlled by a P-type MOSFET control signal PD. a and N-type MOSFET control signal ND a To control the P-type MOSFET MP a and N-type MOSFET MN a This converts the source voltage VDD into voltages with different levels.

[0050] P-type MOSFET MP a and N-type MOSFET MN a The third node N3 can be shared. For example, a P-type MOSFET MP a Drain terminal and N-type MOSFET MN a The drain terminals can be connected to each other by sharing a third node N3 as a contact element. Here, the third node N3 can also be connected to the first wire LX. a .

[0051] In some embodiments, a P-type MOSFET MP a and N-type MOSFET MN a The converted voltage can be obtained through the first line LX a Provided. Through the first-line LX a The provided conversion voltage can be obtained through inductor L a When it drops to the intermediate voltage V O l a Connect to line LX a Inductor L a With converter resistor R Pa The potential between them can be V O l a Output voltage V Oa It can be at the intermediate voltage V O l a Through the converter resistor R Pa It is generated at that time. Converter capacitor C Oa It can be charged (or stored) with the output voltage V Oa The corresponding charge, or the release related to the output voltage V Oa The corresponding charge.

[0052] Controller 100 can output a P-type MOSFET control signal PD a This makes the P-type MOSFET MP a In response to a voltage change signal provided by the sensing circuit 300, the N-type MOSFET MN a The conduction period is longer. Therefore, the converter capacitor C is reduced. Oa It can be recharged and has an output voltage V. Oa The required level can be raised again. Similarly, when the system's required current decreases instantaneously, the N-type MOSFET MN... a Can be compared to P-type MOSFET MP a The conduction time is longer.

[0053] Figure 3B This is a circuit diagram illustrating a DC-DC converter 220 according to an embodiment of the inventive concept. Again, Figure 3B The DC-DC converter 220 shown can perform the previously mentioned... Figure 2 The functions described in the DC-DC converter 200. However, with Figure 3A Compared to the DC-DC converter 210, Figure 3B The DC-DC converter 220 can be implemented to generate an output voltage V with a level higher than the input power. Ob A boost converter type DC-DC converter.

[0054] Reference Figure 2 and Figure 3B The DC-DC converter 220 may include an inductor L b N-type MOSFET MN b P-type MOSFET MP b Converter resistor R Pb and converter capacitor C Ob .

[0055] The DC-DC converter 220 can be provided with a P-type MOSFET control signal PD by the controller 100. b and / or N-type MOSFET control signal ND b Furthermore, it can convert the source voltage VDD into a DC voltage with a different level. In some embodiments, the DC-DC converter 220 can generate a DC voltage with a level higher than the source voltage VDD. The DC-DC converter 220 can generate an output voltage V Ob As output. Output voltage V Ob It can be provided to the first node N1.

[0056] In some embodiments, the source voltage VDD can be obtained from the inductor L b One end is applied, and a fourth node N4 can be formed in the inductor L. b At the other end. In some embodiments, the fourth node N4 can be formed on the N-type MOSFET MN. b At one end (e.g., the drain), the ground power supply GND can be obtained from the N-type MOSFET MN. b The other end (e.g., the source) is applied, and the N-type MOSFET control signal ND is applied. b It can be supplied to N-type MOSFET MN b The gate of the DC-DC converter. In some embodiments, the DC-DC converter 220 can be controlled by an N-type MOSFET based on the control signal ND. b Control N-type MOSFET MN b This converts the source voltage VDD into voltages with different levels.

[0057] Inductor L b and N-type MOSFET MN b The fourth node N4 can be shared. For example, inductor L b One end and N-type MOSFET MN b The drain terminals can be connected to each other by sharing a fourth node N4 as a contact element. Here, the fourth node N4 can also be connected to the first wire LX. b .

[0058] In some embodiments, by inductor L b and N-type MOSFET MN b The converted voltage can be obtained through the first line LX b Provided. Through the first-line LX b The supplied current can also be used as a "sensing current". sen First-line LX b It can be connected to a P-type MOSFET MP b The voltage potential at the fourth node N4 can be obtained through the P-type MOSFET MP. b When it drops to the intermediate voltage V O l b Connect to line LX b Inductor L b With converter resistor R Pb The voltage between them can be V O l b Output voltage V Ob It can be at the intermediate voltage V O l b Through the converter resistor R Pb It is generated at that time. Here, the converter capacitor C Ob It can be charged (or stored) with the output voltage V Ob The corresponding charge or release and output voltage V Ob The corresponding charge.

[0059] P-type MOSFET MP b One end (e.g., the drain) can be connected to the fourth node N4, and the P-type MOSFET MP b The other end (e.g., the source) can be connected to the converter resistor R. Pb Additionally, the P-type MOSFET control signal PD b It can be supplied to P-type MOSFET MP b The gate of the P-type MOSFET. P-type MOSFET control signal PD b It can be provided from controller 100.

[0060] Figure 3C This is a circuit diagram illustrating a DC-DC converter 230 according to an embodiment of the inventive concept.

[0061] Here again, Figure 3C The DC-DC converter 230 can perform the previously mentioned... Figure 2 The functions described in the DC-DC converter 200. However, with Figure 3A 210 step-down DC-DC converter and Figure 3B Compared to the boost converter type DC-DC converter 220, Figure 3C The DC-DC converter 230 can be implemented as a buck-boost converter type DC-DC converter capable of increasing or decreasing the level of the output voltage relative to the input voltage.

[0062] DC-DC converter 230 may include a first P-type MOSFET MP1 c First N-type MOSFET MN1 c Inductor L c Second P-type MOSFET MP2 c Second N-type MOSFET MN2 c Converter resistor R Pc and converter capacitor C Oc .

[0063] DC-DC converter 230 can be provided with a first P-type MOSFET control signal PD1 from controller 100. c and / or the first N-type MOSFET control signal ND1 c Furthermore, the DC-DC converter 230 can convert the source voltage VDD into DC voltages with different levels. In some embodiments, the DC-DC converter 230 can generate a DC voltage with a level greater than or less than the source voltage VDD. The DC-DC converter 230 can generate an output voltage V Oc As output. Output voltage V Oc It can be provided at the first node N1.

[0064] In some embodiments, the source voltage VDD can be generated from the first P-type MOSFET MP1. c With one end (e.g., the source) applied, a fifth node N5 can be formed in the first P-type MOSFET MP1. c At the other end (e.g., the drain), and the first P-type MOSFET control signal PD1 c It can be supplied to the first P-type MOSFET MP1 c The gate of the first N-type MOSFET MN1. In some embodiments, the fifth node N5 may be formed in the first N-type MOSFET MN1. c At one end (e.g., the drain), the ground power supply GND can be obtained from the first N-type MOSFET MN1. c The other end (e.g., the source) is applied, and the first N-type MOSFET control signal ND1 is applied. c It can be supplied to the first N-type MOSFET MN1 c The gate of the DC-DC converter. In some embodiments, the DC-DC converter 230 can be controlled based on the first P-type MOSFET control signal PD1. c and the first N-type MOSFET control signal ND1c Control of the first P-type MOSFET MP1 c and the first N-type MOSFET MN1 c This converts the source voltage VDD into voltages with different levels. The fifth node N5 can also be connected to the inductor L. c The current flows through inductor L c The current can be called the detection current l sen The first P-type MOSFET MP1 c and the first N-type MOSFET MN1 c The fifth node N5 can be shared. For example, the first P-type MOSFET MP1 c The drain terminal and the first N-type MOSFET MN1 c The drain terminals can be connected to each other by sharing the fifth node N5 as a contact element.

[0065] In some embodiments, the first P-type MOSFET MP1 c and the first N-type MOSFET MN1 c The converted voltage can pass through inductor L c And then it reaches the sixth node N6. The sixth node can be connected to the second N-type MOSFET MN2. c Second P-type MOSFET MP2 c For example, the second P-type MOSFET MP2 c The drain terminal and the second N-type MOSFET MN2 c The drain terminals can be connected to each other by sharing a sixth node N6 as a contact. Second N-type MOSFET MN2 c The source terminal can be connected to ground power supply GND, and the second N-type MOSFET control signal ND2. c It can be supplied to the second N-type MOSFET MN2 c The gate terminal, and the second P-type MOSFET MP2 c The source terminal can be connected to the converter resistor R. Pc The second P-type MOSFET control signal PD2 c It can be supplied to the second P-type MOSFET MP2 c The gate terminal. The voltage represented at the sixth node N6 can be changed as a voltage through the second P-type MOSFET MP2. c The intermediate voltage V of the result O l c And the output voltage V Oc It can be used as an intermediate voltage V O l cThrough the converter resistor R Pc The result is generated. Converter capacitor C Oc It can be charged with an output voltage V Oc The corresponding charge or release and output voltage V Oc The corresponding charge.

[0066] Figure 4 This is a circuit diagram illustrating a sensing circuit 301 according to an embodiment of the inventive concept. Here, Figure 4 The sensing circuit 301 is Figure 2 An example of the sensing circuit 300, which can perform the functions previously described.

[0067] Reference Figure 4 The sensing circuit 301 may include an amplifier A1, resistive elements (e.g., first resistors to fourth resistors) RF1, RF2, RF3 and RF4, and a capacitor element 311.

[0068] Amplifier A1 can be implemented as an operational amplifier, but is not limited to this. A first resistor RF1 can be connected to the seventh node N7 between the positive input terminal of amplifier A1 and the ground power supply GND, and a second resistor RF2 can be connected to each of the seventh node N7 and the first node N1. A third resistor RF3 can be connected to the eighth node N8, which is located between the negative input terminal and the output terminal of amplifier A1, and a fourth resistor RF4 can be connected between the eighth node N8 and the second node N2.

[0069] In some embodiments, the ratio of the resistance value of the first resistor RF1 to the resistance value of the second resistor RF2 may be the same as the ratio of the resistance values ​​of the third resistor RF3 and the fourth resistor RF4. However, the inventive concept is not limited thereto, and the resistance values ​​of the resistive elements RF1, RF2, RF3, and RF4 may be varied according to the transfer function or electrical characteristics required by the PMIC 10. For example, the resistance value of the third resistor RF3 may be the same as the resistance value of the first resistor RF1, and the resistance value of the fourth resistor RF4 may be the same as the resistance value of the second resistor RF2.

[0070] In some embodiments, capacitor element 311 may be connected between the eighth node N8 (which is the negative input terminal of the amplifier) ​​and the ground power supply GND. The ground power supply GND to which capacitor element 311 is connected may be different from or the same as the ground power supply GND to which the first resistor RF1 is connected.

[0071] Consistent with the description of capacitor element 310 above, capacitor element 311 may include at least one capacitor. Capacitor element 311 can be understood as an element in an AC circuit where the phase of the current leads the phase of the voltage. In some embodiments, capacitor element 311 may be a variable capacitor, or may include a capacitor array comprising two or more capacitors. However, the inventive concept is not limited thereto, and capacitor element 311 may be implemented as any reasonable combination of passive and / or active elements capable of changing capacitance. However, in Figure 4 For ease of description, capacitor element 311 is described as a single capacitor CF2.

[0072] In some embodiments, one end of capacitor CF2 can be connected to the eighth node N8, and the third resistor RF3, which is connected to the negative input terminal of the amplifier, is connected to the eighth node N8. Additionally, the other end of capacitor CF2 can be connected to ground (GND).

[0073] The addition of capacitor element 311 generates additional zeros and poles in sensing circuit 300. When the resistance value of the first resistor RF1 is the same as the resistance value of the third resistor RF3, capacitor element 311 can additionally generate zeros, as described in Equation 1 below.

[0074]

[0075] When the resistance value of the first resistor RF1 is the same as the resistance value of the third resistor RF3, the capacitor element 311 can additionally generate a pole, as described in Equation 2 below. In Equation 1, RF1 can represent the resistance value of the first resistor RF1, and CF2 can represent the resistance value of the third resistor RF3.

[0076]

[0077] Here, A represents the open-loop gain of amplifier A1, and ω3dB can represent the 3dB pole of amplifier A1.

[0078] The zeros and poles generated by the additional capacitor element 311 can be adjusted by the total capacitance of the first resistor RF1, the second resistor RF2, and the capacitor element 311 (e.g., capacitor CF2).

[0079] Reference Figure 3A , Figure 3B and Figure 3C When the current consumed by the load 400 increases instantaneously, the output voltage V is connected. Oa V Ob or V Oc The converter capacitor C supplied to the first node N1 Oa C Ob Or COc It can provide the required current instantly, and the converter capacitor C Oa C Ob Or C Oc The voltage can be reduced to the voltage corresponding to the discharge current. The reduced output voltage V Oa V Ob or V Oc It can be detected by sensing circuit 300.

[0080] Therefore, when the operating environment of the PMIC changes (e.g., additional current consumption), the magnitude and variation of the output power provided by the DC-DC converter will increase. Under certain conditions, this change in output power can become significant, potentially causing a malfunction in the function of providing output power to the load 400 or electronic devices. Therefore, the PMIC is designed to suppress significant changes in output power.

[0081] A common method to suppress significant changes in output power is to increase the size of the converter capacitor Co; however, this requires a significant amount of physical space and increases the manufacturing cost of the PMIC. Furthermore, when a DC-DC converter using switching elements is included in the PMIC design, the operating bandwidth may be limited.

[0082] Conversely, the PMIC according to the embodiment of the inventive concept extends the operating bandwidth and phase margin, while stabilizing the output voltage by adding capacitors to ensure additional poles and zeros. As a result, the frequency response characteristics can be improved because the zeros and poles can be adjusted by detecting the operating frequency of the PMIC according to the embodiment of the inventive concept. Furthermore, the PMIC according to the embodiment of the inventive concept ensures fast frequency response characteristics by selecting the adjustment mode of the capacitors according to changes in the operating frequency.

[0083] Figure 5A and Figure 5B This is a graph showing the relationship between the amplitude and phase of a PMIC and its frequency according to some embodiments of the inventive concept.

[0084] Figure 5A and Figure 5B This is shown as a Bode plot. Figure 5A In this diagram, the horizontal axis indicates frequency, and the vertical axis indicates signal amplitude in decibels (dB). Figure 5B In this system, the horizontal axis indicates the frequency, and the vertical axis indicates the phase of the signal in degrees.

[0085] Reference Figure 2 , Figure 4 and Figure 5AThe amplitude of a conventional response is indicated by a dashed line, while the amplitude of a response provided by an embodiment of the inventive concept is indicated by a solid line. (See also...) Figure 5A The dashed line in the diagram represents the operating bandwidth of a conventional DC-DC converter, which is the first frequency fc1.

[0086] However, in some embodiments, the operating bandwidth can be increased when zeros and poles are added with or due to the addition of capacitor element 310 (311). Therefore, in some embodiments, referring to Figure 5A The solid line in the figure, due to the poles and zeros added about or due to capacitor element 310 (311), allows a second frequency fc2 that is higher than the first frequency fc1 to be obtained as an improved operating frequency.

[0087] The zero-point break frequency fza, which is the frequency at which the amplitude fluctuation trend changes, is described in Equation 3 below, where ω Z It can represent zero point.

[0088] fza=ω Z / (2π) (3)

[0089] As the inflection point frequency at which the amplitude fluctuation trend changes, the extreme inflection point frequency fpa is described by Equation 4, which follows immediately below, where ω P It can represent an extreme point.

[0090] fpa=ω P / (2π) (4)

[0091] Reference Figure 5A The solid line in the diagram represents the amplitude decreasing gradually at a specific slope (e.g., -20 dB / dec) because the PMIC according to the embodiment of the inventive concept includes additional zeros and poles. This amplitude can be maintained parallel to the frequency axis at the zero-inflection frequency fza corresponding to the additional zero. Furthermore, the amplitude can be gradually decreased again from the pole-inflection frequency fpa corresponding to the additional pole. According to Equation 2, since it is understood that the pole-inflection frequency fpa has two poles wp1 and wp2, the slope of the amplitude decrease can be twice the slope (e.g., -20 dB / dec) before the zero-inflection frequency fza (e.g., -20 dB / dec) (e.g., -40 dB / dec).

[0092] Reference Figure 2 , Figure 4 and Figure 5B The phase of a conventional response is shown as a dashed line, while the phase of an embodiment according to the inventive concept is shown as a solid line. (See also...) Figure 5BThe dashed line in the diagram represents the phase margin of a conventional DC-DC converter, which can be as large as the first phase PM1. As the operating bandwidth increases, the phase margin can be reduced.

[0093] However, in some embodiments, the phase margin can be increased when the zeros and poles are relative to or due to the addition of capacitor element 310 (311). See also... Figure 5B The solid line, due to the effects of the additional poles and zeros, shows that even at frequencies greater than the zero-inflection frequency fza, the phase can increase compared to the normal response (dashed line), and can decrease from the interval between the first frequency fc1 and the pole-inflection frequency fpa. Therefore, since the second phase PM2 at the second frequency fc2 may not be significantly higher than the first phase PM1, the phase margin can be extended (i.e., phase enhancement can be achieved).

[0094] While ensuring improved operating frequency and phase margin, the PMIC according to the embodiments of the inventive concept can also ensure fast response characteristics and improved overall system stability.

[0095] Figure 6 This is a flowchart illustrating, in one example, a method for operating a PMIC according to an embodiment of the inventive concept.

[0096] Reference Figure 2 , Figure 3A and Figure 6 In the exemplary method, the load current of load 400 is changed (S110). In this regard, the load current may be the current required for proper operation of the electronic device 1000. Assuming PMIC 10 is connected to load 400 at the first node N1, the voltage / current required for proper operation of load 400 may vary due to processing speed, environment, and required performance level.

[0097] As a result of the change in load current, the converter capacitor C in the DC-DC converter 210... Oa The voltage is changed (S120). In some embodiments, as the required current of the load 400 changes, the converter capacitor C... Oa It can provide the current required for a load of 400.

[0098] Therefore, the change in output current can be detected by the sensing circuit 300 (S130). In some embodiments, the current transmitted through the first node N1 can be controlled by the converter capacitor C according to the change in the required current of the load 400. Oa Change.

[0099] The output voltage can then be supplied based on the zeros and poles added with or due to the capacitor element 310 (S140). In some embodiments, the sensing circuit 300 can include the added zeros and poles by including the capacitor element 310, and therefore, the operating bandwidth of the PMIC 10 can be extended. The sensing circuit 300 can provide the detection result to the controller 100. The controller 100 can control the DC-DC converter 200 based on the extended operating bandwidth to supply an output voltage V with fast transient response stability. Oa The DC-DC converter 200 can provide an output voltage V at the first node N1. Oa .

[0100] Then, the converter capacitor C can be restored. Oa The voltage (S150). For example, when the converter capacitor C Oa When supplying current to the load, the converter capacitor C Oa It can be charged, and when the converter capacitor C Oa When storing charge, the converter capacitor C Oa It can be discharged.

[0101] Figure 7 This is a block diagram illustrating a PMIC 20 according to an embodiment of the inventive concept. Here, Figure 7 PMIC20 can be understood as Figure 2 Modifications to PMIC 10.

[0102] Reference Figure 7 (and with) Figure 2 Compared to other embodiments, PMIC 20 includes a controller 102, a DC-DC converter 202, a sensing circuit 302, a capacitor array 312 included in the sensing circuit 302, a load 402, and a frequency-to-digital converter (FDC) 502.

[0103] The operating frequency fs can be changed to reduce effects such as electromagnetic interference (EMI) on PMIC 20. The frequency response characteristics can be improved by adjusting the total capacitance of capacitor array 312 based on the operating frequency fs of PMIC 20.

[0104] Therefore, FDC 502 can be used to convert the operating frequency fs provided by controller 102 into digital code output (DCO), and capacitor array 312 can adjust the total capacitance by adjusting the switch in response to DCO.

[0105] The zeros and poles can depend on the operating frequency. In some embodiments, as the operating frequency increases, the zeros and poles can shift to a relatively high frequency band. In response to the increase in operating frequency, FDC 502 can reduce the total capacitance of capacitor array 312. For example, FDC can provide DCO as a digital signal for adjusting the combination of multiple capacitors to reduce the capacitance of the variable capacitor or to reduce the total capacitance of capacitor array 312. In some embodiments, as the operating frequency fs decreases, the zeros and poles can shift to a low frequency band, and FDC can generate DCO as a digital signal for adjusting the combination of multiple capacitors to increase the capacitance of the variable capacitor or to increase the total capacitance of capacitor array 312.

[0106] Figure 8 This is a circuit diagram showing a capacitor array 314 that can be used in some embodiments of the inventive concept.

[0107] Reference Figure 8 The capacitor array 314 may include multiple capacitors C2 connected in parallel. One end of each of the multiple capacitors C2 may be connected to node x(N). x Furthermore, the other end of each of the multiple capacitors C2 can be connected in series to a switch, and the switching on / off state is controlled by the DCO.

[0108] In some embodiments, the capacitor array 314 may have a total capacitance regulated based on the DCO. For example, according to the DCO, some of the plurality of capacitors C2 may be closed or enabled (e.g., by closing a connected switch), and other capacitors of the plurality of capacitors C2 may be opened or disabled (e.g., by opening a connected switch).

[0109] As a result of appropriately combining multiple capacitors C2, a desired equivalent capacitance CF2 can be generated. That is, a capacitor CF2 having a capacitance value corresponding to the combined capacitance value of the multiple capacitors C2 can be generated. In some embodiments, the capacitor array 314 may be referred to as the multiple capacitors C2, or generally as the capacitor CF2.

[0110] Figure 9 This is a circuit diagram illustrating an embodiment of the PMIC 30 according to the inventive concept.

[0111] Reference Figure 9 (and with) Figure 2 and Figure 7 (Compared to the embodiments shown in the figure), PMIC 30 may include a controller (CTRL) 103, a DC-DC converter 203, a sensing circuit 303 including a capacitor array 313, a load 403, and an FDC 503. Figure 9 The DC-DC converter 203 can be Figure 3A DC-DC converter 210 Figure 3B DC-DC converter 220 and Figure 3C One of the converters in a DC-DC converter series. Figure 9 The sensing circuit 303 can be Figure 2 Example embodiment of the sensing circuit 300.

[0112] The first resistor RF1 can be connected to the seventh node N7 between the positive input terminal of amplifier A1 and the ground power supply GND, and the second resistor RF2 can be connected between the seventh node N7 and the first node N1. The third resistor RF3 can be connected to the eighth node N8, which is between the negative input terminal of amplifier A1 and the output terminal of the amplifier, and the fourth resistor RF4 can be connected between the eighth node N8 and the second node N2.

[0113] One end of capacitor array 313 can be connected to the eighth node N8 between the third resistor RF3 and the fourth resistor RF4, with the fourth resistor RF4 connected to the negative input terminal of amplifier A1. The other end of capacitor array 313 can be connected to ground power supply GND.

[0114] The FDC 503 is a circuit that converts frequency into digital code. The FDC 503 can be configured to include, but is not limited to, switched capacitors, current sources, low-pass filters, and analog-to-digital converters (ADCs). The FDC 503 can generate digital code using an output voltage that acts as an analog signal, increasing non-linearly with frequency.

[0115] In some embodiments, the FDC can detect a detection current l, which is the current flowing through the first line LX. sen The total capacitance of capacitor array 313 is adjusted by the magnitude of the capacitance. In some embodiments, the FDC can adjust the zeros and poles of PMIC 30 by adjusting the capacitance of capacitor array 313 based on the operating frequency fs of controller 103. In some embodiments, the FDC can respond to the detected current l sen The total capacitance of capacitor array 313 is adjusted according to the frequency. Figure 9 In the reference numerals PD, ND, MN, V O l respectively with Figure 3A Reference numeral PD shown a ND a MN a V O l a similar.

[0116] Figure 10 This is a circuit diagram illustrating an embodiment of the PMIC 40 according to the inventive concept.

[0117] Reference Figure 10 (and with) Figure 2 ,mark Figure 7 and Figure 9 (Compared to the embodiments shown in the figure), PMIC 40 may include controller 104, DC-DC converter 204, sensing circuit 304, capacitor array 314 included in sensing circuit 304, load 404 and current digital converter (CDC) 504. Figure 10 The DC-DC converter 204 can be Figure 3A DC-DC converter 210 Figure 3B DC-DC converter 220 and Figure 3C One of the converters in the DC-DC converter 230, and Figure 10 The sensing circuit 304 can be Figure 4 The sensing circuit 301.

[0118] Figure 10 The DC-DC converter 204 shown can perform the previously mentioned... Figure 2 The functions described in the DC-DC converter 200, and with Figure 3A 210 step-down DC-DC converter and Figure 3B Compared to the boost converter type DC-DC converter 220, it can be a linear regulator type DC-DC converter. In this sense, a linear regulator is understood to increase or decrease the output voltage relative to the input voltage.

[0119] The linear regulator type DC-DC converter 204 may include an amplifier A2, a P-type MOSFET MP, and a converter resistor R. P The reference voltage VREF provided by controller 104 can be applied to the negative input terminal of amplifier A2, and the feedback signal FB (e.g., voltage change signal) output by sensing circuit 304 can be provided to the positive input terminal of amplifier A2. The output of amplifier A2 can be provided as amplifier output voltage VG to the gate terminal of P-type MOSFET MP. The source voltage VDD can be supplied to one end of P-type MOSFET MP (e.g., the source), and the other end of P-type MOSFET MP (e.g., the drain) can be connected to converter resistor R. P The node of the drain of the P-type MOSFET MP and the converter resistor R P The current can be called the detection current l sen And detect current l sen It can be provided to CDC 504.

[0120] The sensing circuit 304 may include an amplifier A1, first resistors RF1 to RF4, a first feedback resistor R1, and a second feedback resistor R2. Here, with... Figure 4 Compared to the sensing circuit 301, the sensing circuit 304 further includes a first feedback resistor R1 and a second feedback resistor R2 for adjusting the output voltage, but the inventive concept is not limited thereto.

[0121] First resistor RF1 and second resistor RF2 can be connected to the positive input terminal of amplifier A1. First resistor RF1 can be connected to ground (GND), and second resistor RF2 can be connected to the node that provides the output voltage Vo to load 404. Third resistor RF3 and fourth resistor RF4 can be connected to the negative input terminal of amplifier A1. Third resistor RF3 can be connected to the output terminal of amplifier A1, and fourth resistor RF4 can be connected to the node that provides ground (GND) to load 404. One end of first feedback resistor R1 can be connected to the output terminal of amplifier A1, and the other end of first feedback resistor R1 can be connected to second feedback resistor R2. The other end of second feedback resistor R2 can be connected to ground (GND). Feedback signal FB can be generated from the node between first feedback resistor R1 and second feedback resistor R2, and feedback signal FB can be provided to DC-DC converter 204.

[0122] In some embodiments, one end of capacitor array 314 may be connected to the ninth node N9 between the third resistor RF3 and the fourth resistor RF4, the third resistor RF3 and the fourth resistor RF4 are connected to the negative input terminal of amplifier A1, and the other end of capacitor array 314 may be connected to ground power supply GND.

[0123] A CDC (Digital Current Detector) is a circuit that converts current into a digital code. The CDC 504 can be configured to include a low-pass filter and an analog-to-digital converter (ADC), but is not limited to these. It senses the current. sen A low-pass filter is used to generate and detect the current l. sen The detection voltage is linearly proportional. As the detection voltage increases, the CDC 504 can perform analog-to-digital conversion on the output voltage, which is an analog signal, to generate a digital code.

[0124] CDC can detect the current l as the current flowing through inductor L. sen The total capacitance of the capacitor array 314 can be adjusted by measuring the size of the current. Based on the inventive concept, the CDC can adjust the total capacitance of the capacitor array 314 by measuring the current. sen Adjust the capacitance of capacitor array 314 to adjust the zero and pole of PMIC 40.

[0125] Figure 11A and Figure 11B This is a flowchart illustrating a method of operating the PMIC 20 according to an embodiment of the inventive concept. Execution Figure 11A and Figure 11B The method of PMIC can be Figure 9 PMIC 30 or Figure 10 PMIC 40.

[0126] Reference Figure 8 , Figure 10 and Figure 11A The change in the operating frequency fs of the PMIC 30 is detected (S210). Here, the change in the operating frequency fs can be detected when the controller 103 provides the operating frequency fs used to drive the PMIC 30 to the FDC 503.

[0127] Then, FDC 503 adjusts the total capacitance of capacitor array 312 (S220). Here, FDC 503 can generate a DCO that can adjust the total capacitance by adjusting the switches of capacitor array 312 (e.g., thereby switching or enabling / disabling the capacitors in capacitor array 312). For example, as the operating frequency fs increases, FDC can provide a digital signal that adjusts a combination of multiple capacitors to reduce the total capacitance of capacitor array 312, and as the operating frequency fs decreases, FDC can generate a digital signal that adjusts a combination of multiple capacitors to increase the total capacitance of capacitor array 312.

[0128] Reference Figure 8 , Figure 10 and 11B The change in the output current of the DC-DC converter 203 is detected (S310). Here, the detection current l flowing through the inductor L included in the DC-DC converter 203 and connected to the third node N3 can be detected. sen The change.

[0129] Then, the current-to-digital converter 504 adjusts the total capacitance of the capacitor array 314 (S320). Here, the CDC 504 can adjust the capacitance based on the detected current l. sen The switching of capacitor array 314 is adjusted to generate a DCO that can adjust the total capacitance. For example, with the detection current l sen As the CDC increases, it can provide the DCO as a digital signal to the capacitor array 314. This digital signal adjusts the combination of multiple capacitors to reduce the total capacitance of the capacitor array 314; as the detection current increases... sen To reduce the capacitance, the CDC can provide a DCO as a digital signal to the capacitor array 314, which adjusts the combination of multiple capacitors to increase the total capacitance of the capacitor array 314. The CDC can then adjust the capacitance based on the detected current l. senAdjust the capacitance of capacitor array 314 to adjust the zero and pole of PMIC30.

[0130] Figure 12 It is shown that... Figure 2 The graphs shown in the embodiment depict the amplitude (e.g., the capacitance of the capacitor element 310) versus frequency for each adjustment mode.

[0131] Capacitor element ( Figure 2 The capacitor element 310 can select an adjustment mode for adjusting the capacitor based on changes in the operating frequency fs. In some embodiments, the capacitor element 310 can select any one of the following adjustment modes: a first adjustment mode for linearly responding to changes in the operating frequency fs, a second adjustment mode for exponentially responding to changes in the operating frequency fs, and a third adjustment mode for logarithmically responding to changes in the operating frequency fs. The capacitor element 310 can ensure a fast response rate by selecting the adjustment mode.

[0132] Although the inventive concept has been specifically shown and described with reference to particular embodiments thereof, it will be understood that various changes in form and function may be made without departing from the spirit and scope of the appended claims.

Claims

1. A power management integrated circuit, the power management integrated circuit comprising: A DC-DC converter is configured to provide output power to a load; The controller is configured to control the switching of the DC-to-DC converter; as well as The sensing circuit includes a capacitive element and is configured to detect the output current flowing through the node between the DC-to-DC converter and the load. The sensing circuit also includes an operational amplifier and at least one resistor, with a capacitor connected between the negative input terminal of the operational amplifier and ground. The capacitor element provides one or more additional zeros and one or more poles.

2. The power management integrated circuit according to claim 1, wherein, A first resistor connected to ground and a second resistor connected to the node are connected to the positive input terminal of the operational amplifier, and The third resistor, connected to the output terminal of the operational amplifier, and the fourth resistor, connected to ground, are connected to the negative input terminal.

3. The power management integrated circuit according to claim 2, wherein, The ratio of the resistance values ​​of the first resistor to the resistance values ​​of the second resistor is the same as the ratio of the resistance values ​​of the third resistor to the resistance values ​​of the fourth resistor.

4. The power management integrated circuit according to claim 1, wherein, DC-DC converters include buck converters.

5. The power management integrated circuit according to claim 1, wherein, DC-DC converters include boost converters.

6. The power management integrated circuit according to claim 1, wherein, DC-DC converters include buck-boost converters.

7. The power management integrated circuit according to claim 1, wherein, DC-DC converters include linear regulators.

8. The power management integrated circuit according to any one of claims 1 to 7, wherein, A DC-to-DC converter has an operating bandwidth and phase margin that are at least partially determined by the capacitive elements of the sensing circuit.

9. A power management integrated circuit, the power management integrated circuit comprising: A DC-DC converter is configured to provide output power to a load; The controller is configured to control the switching of the DC-to-DC converter; Sensing circuitry, including a capacitor array and configured to detect the output current flowing through a node between a DC-to-DC converter and a load; and The frequency-to-digital converter is configured to adjust the total capacitance of the capacitor array. The sensing circuit also includes an operational amplifier and at least one resistor, and a capacitor array is connected between the negative input terminal of the operational amplifier and ground. The capacitor array provides one or more additional zeros and one or more poles.

10. The power management integrated circuit according to claim 9, wherein, The frequency-to-digital converter regulates the total capacitance by switching the capacitor elements in the capacitor array in response to the operating frequency received from the controller.

11. The power management integrated circuit according to claim 9, wherein, DC-DC converters include inductors, and A frequency-to-digital converter converts the inductor current flowing through an inductor into digital code.

12. The power management integrated circuit according to claim 9, wherein, A first resistor connected to ground and a second resistor connected to the node are connected to the positive input terminal of the operational amplifier, and The third resistor, connected to the output terminal of the operational amplifier, and the fourth resistor, connected to ground, are connected to the negative input terminal of the operational amplifier.

13. The power management integrated circuit according to claim 12, wherein, The ratio of the resistance values ​​of the first resistor to the resistance values ​​of the second resistor is the same as the ratio of the resistance values ​​of the third resistor to the resistance values ​​of the fourth resistor.

14. A method of operating a power management integrated circuit, the method comprising: Detect changes in the output current at the node between the power management integrated circuit and the load; as well as Based on the added zeros and poles associated with the capacitive elements included in the sensing circuit, an output voltage corresponding to the output current is supplied to the node. The sensing circuit also includes an operational amplifier and at least one resistor, and a capacitor is connected between the negative input terminal of the operational amplifier and ground.

15. The method of claim 14, further comprising: The capacitance of the capacitor element is adjusted in response to the operating frequency of the power management integrated circuit.

16. The method of claim 14, further comprising: Measure the inductor current flowing through the inductor in the power management integrated circuit; as well as The capacitance of the capacitor element is adjusted in response to the frequency of the inductor current.

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