Packaging substrate, electronic device package, and method of manufacturing the same

Abstract

This disclosure provides an encapsulation substrate and a method for manufacturing the same. The encapsulation substrate includes a substrate, an electronic component, and conductive traces. The electronic component is disposed in the substrate. The electronic component includes conductive traces and a magnetic layer. The conductive traces include alignment mark segments and connection segments, and the magnetic layer partially covers the conductive traces. The magnetic layer includes an alignment window and a recess. The alignment window is disposed in an upper surface of the magnetic layer and exposes a first upper surface of the alignment mark segments. The recess is disposed in the upper surface of the magnetic layer and exposes a second upper surface of the connection segments. The conductive traces are located in the recesses and are electrically connected to the second upper surface of the connection segments of the conductive traces.

Description

Technical Field

[0001] This disclosure relates to a packaging substrate and a method of manufacturing the same, and more specifically to a packaging substrate having embedded electronic components and a method of manufacturing the same. Background Technology

[0002] With multifunctionality and high performance becoming typical requirements for consumer electronics and communication products such as smartphones, electronic device packages are expected to possess excellent electrical characteristics, low power consumption, and a large number of I / O ports. To achieve multifunctionality and high performance, electronic device packages are equipped with more active and passive components. However, these active and passive components increase the overall thickness of the electronic device package. Therefore, there is a need to develop a thin, multifunctional, high-performance, and low-power packaging substrate to meet the compactness requirements of consumer electronics and communication products. Summary of the Invention

[0003] One aspect of this disclosure relates to a packaging substrate. In some embodiments, the packaging substrate includes a substrate, an electronic component, and a first conductive trace. The substrate includes a first surface and a second surface opposite to the first surface. The electronic component is disposed in the substrate. The electronic component includes a conductive wire and a magnetic layer, the conductive wire including alignment mark segments and connection segments, the magnetic layer partially covering the conductive wire. The magnetic layer includes an upper surface adjacent to the first surface and a lower surface adjacent to the second surface. The magnetic layer includes a first alignment window and a first recess, the first alignment window being disposed in the upper surface of the magnetic layer and exposing the first upper surface of the alignment mark segments, the first recess being disposed in the upper surface of the magnetic layer and exposing the second upper surface of the connection segments. The first conductive trace is located in the first recess and is electrically connected to the second upper surface of the connection segment of the conductive wire.

[0004] Another aspect of this disclosure relates to a method of manufacturing a packaging substrate. In some embodiments, the method includes the following operations: providing an electronic component. The electronic component includes a magnetic layer and conductive lines at least partially covered by the magnetic layer. Partially removing the magnetic layer from an upper surface to form an alignment window, the alignment window partially exposing a first upper surface of the conductive lines as an alignment mark. Recessing the magnetic layer from the upper surface by referring to the alignment mark to form a recess that partially exposes a second upper surface of the conductive lines. Placing the electronic component in a cavity of the substrate by referring to the alignment mark. A dielectric layer is formed in the cavity and the recess. Through-holes are formed in the dielectric layer in the recess to expose the conductive lines. Conductive traces are formed on the conductive lines exposed through the through-holes in the dielectric layer.

[0005] Another aspect of this disclosure relates to a method for manufacturing a semiconductor device package. In some embodiments, the method includes the following operations: providing the aforementioned package substrate; forming a redistribution layer (RDL) on a first surface of the substrate; forming a semiconductor die on the RDL; encapsulating the semiconductor die; and forming a plurality of electrical connectors on a second surface of the substrate. Attached Figure Description

[0006] When with attachment Figure 1 When reading the following detailed description, various aspects of some embodiments of this disclosure can be readily understood from it. Various structures may not be drawn to scale, and the dimensions of various structures may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a schematic top view of a packaging substrate according to some embodiments of the present disclosure.

[0008] Figure 1A It is along Figure 1 A cross-sectional view of the packaging substrate taken from line 1A-1A'.

[0009] Figure 1B It is along Figure 1 A cross-sectional view of the packaging substrate taken from line 1B-1B'.

[0010] Figure 1C It is along Figure 1 A cross-sectional view of the packaging substrate taken from line 1C-1C'.

[0011] Figure 2A , Figure 2A1 , Figure 2A2 , Figure 2B , Figure 2B1 , Figure 2B2 , Figure 2C , Figure 2C1 , Figure 2D , Figure 2E and Figure 2F Operations for manufacturing a packaging substrate according to some embodiments of the present disclosure are illustrated.

[0012] Figure 3 This is a schematic perspective view of an electronic component according to some embodiments of the present disclosure.

[0013] Figure 3A This is a schematic cross-sectional view of an electronic component according to some embodiments of the present disclosure.

[0014] Figure 4 This is a schematic top view of an electronic component according to some embodiments of the present disclosure.

[0015] Figure 5 This is a schematic top view of an electronic component according to some embodiments of the present disclosure.

[0016] Figure 5A This is a schematic cross-sectional view of a packaging substrate according to some embodiments of the present disclosure.

[0017] Figure 6 This is a schematic top view of an electronic component according to some embodiments of the present disclosure.

[0018] Figure 6A This is a schematic cross-sectional view of a packaging substrate according to some embodiments of the present disclosure.

[0019] Figure 7 This is a schematic cross-sectional view of a packaging substrate according to some embodiments of the present disclosure.

[0020] Figure 8 This is a schematic cross-sectional view of a packaging substrate according to some embodiments of the present disclosure.

[0021] Figure 9 Operations for manufacturing an electronic device package according to some embodiments of the present disclosure are illustrated.

[0022] Figure 10 Operations for manufacturing an electronic device package according to some embodiments of the present disclosure are illustrated. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to explain certain aspects of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed or arranged in direct contact, and may also include embodiments in which additional features are formed and arranged between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] For ease of description, spatial relative terms such as “below,” “under,” “above,” “on top,” “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” and “side” may be used herein to describe the relationship between one element or feature as shown in the accompanying drawings and one or more other elements or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be an intermediate element present.

[0025] Figure 1 This is a schematic top view of the packaging substrate 1 according to some embodiments of the present disclosure. Figure 1A It is along Figure 1 A cross-sectional view of the packaging substrate 1 taken by line 1A-1A'. Figure 1B It is along Figure 1 A cross-sectional view of the packaging substrate 1 taken by line 1B-1B', and Figure 1C It is along Figure 1 A cross-sectional view of the packaging substrate 1 taken along line 1C-1C'. To highlight the features of the packaging substrate 1, in... Figure 1 Some components, such as dielectric layers and conductive traces, are not shown in the drawing. Figure 1 , Figure 1A , Figure 1B and Figure 1CAs shown, the encapsulation substrate 1 includes a substrate 10, an electronic component 20, and a first conductive trace 31. The substrate 10 includes a first surface 101 and a second surface 102 opposite to the first surface 101. The substrate 10 may include an encapsulation substrate having a circuit system therein. For example, the substrate 10 may include a core substrate, a coreless substrate, or other types of substrate. The substrate 10 may include a support portion 10S defining one or more cavities 10C for accommodating the electronic component 20. In some embodiments, the cavities 10C may, but are not limited to, penetrate the substrate 10. In some embodiments, the material of the support portion 10S is relatively robust. For example, the material of the support portion 10S may include polypropylene (PP) or other suitable dielectric or insulating materials. The substrate 10 may include a plurality of conductive structures 10T, such as conductive vias, extending from the first surface 101 of the substrate 10 to the second surface 102 to electrically connect the electronic component and / or semiconductor die disposed on the first surface 101 and the second surface 102. For example, the conductive structure 10T may include copper or other suitable conductive materials. In some embodiments, the cross-sectional shape of the conductive structure 10T may include, but is not limited to, an X-shape or an hourglass shape. In some other embodiments, the cross-sectional shape of the conductive structure 10T may include a rectangle, a trapezoid, or other suitable shape.

[0026] An electronic component 20 is disposed in a substrate 10. In some embodiments, the electronic component 20 is disposed in a cavity 10C of the substrate 10. The thickness of the electronic component 20 may be less than or equal to the thickness of the substrate 10, such that mounting the electronic component 20 does not increase the overall thickness of the encapsulation substrate 1. The electronic component 20 includes a magnetic layer 22 and one or more conductive lines 24. For example, the electronic component 20 may include a passive component such as an inductor. The magnetic layer 22 includes an upper surface 22U adjacent to the first surface 101 and a lower surface 22L adjacent to the second surface 102. The magnetic layer 22 may include ferrite or other suitable magnetic materials. For example, the material of the magnetic layer 22 may include a compound containing iron oxide and other components, such as magnesium (Mg), aluminum (Al), barium (Ba), manganese (Mn), copper (Cu), nickel (Ni), or cobalt (Co). In some embodiments, the magnetic layer 22 is an opaque magnetic material that is opaque to light. The conductive lines 24 may include metal wires such as copper wires. In some embodiments, the ends of the conductive wire 24 may, but are not limited to, slightly protrude from the magnetic layer 22. In some other embodiments, the ends of the conductive wire 24 may be substantially coplanar with or covered by the magnetic layer 22.

[0027] The conductive line 24 may include an alignment mark segment 241 and a connecting segment 242. In some embodiments, the alignment mark segment 241 and the connecting segment 242 may be connected to each other. In some embodiments, the first upper surface 241U of the alignment mark segment 241 and the second upper surface 242U of the connecting segment 242 may be lower than the upper surface of the conductive line 24, and the first upper surface 241U of the alignment mark segment 241 may even be lower than the second upper surface 242U of the connecting segment 242. In some embodiments, both the alignment mark segment 241 and the connecting segment 242 have a non-circular cross-sectional shape. For example, both the first upper surface 241U of the alignment mark segment 241 and the second upper surface 242U of the connecting segment 242 have substantially flat surfaces.

[0028] Magnetic layer 22 partially covers conductive line 24. Magnetic layer 22 includes a first alignment window 22W1 disposed in the upper surface 22U of magnetic layer 22 and exposing the first upper surface 241U of alignment mark segment 241, making the first upper surface 241U of connection segment 242 visible and acting as an alignment mark. Magnetic layer 22 further includes a first recess 22R1 disposed in the upper surface 22U of magnetic layer 22 and exposing the second upper surface 242U of connection segment 242.

[0029] The first conductive trace 31 is disposed in the first recess 22R1 and electrically connected to the second upper surface 242U of the connection section 242 of the conductive line 24. The non-circular cross-sectional shape of the connection section 242 can enhance the adhesion between the conductive line 24 and the first conductive trace 31. In some embodiments, the conductive line 24 can be configured as a coil of an inductor. In some embodiments, the electronic component 20 can include multiple conductive lines 24, and the electronic component 20 can include multiple inductors embedded in the magnetic layer 22. In some embodiments, such as Figure 1 and Figure 1A As shown, the first alignment window 22W1 includes a slot that continuously traverses the plurality of conductive lines 24 and exposes the first upper surface 241U of the alignment mark segment 241 of the plurality of conductive lines 24. The first recess 22R1 is formed after the alignment mark segment 241 is formed, and therefore the alignment mark segment 241 can be used as an alignment mark, allowing precise control of the position of the first recess 22R1 to expose the connection segment 242.

[0030] In some embodiments, such as Figure 1B As shown, some conductive structures in the conductive structure 10T can be electrically connected to the first conductive trace 31. In some other embodiments, some conductive structures in the conductive structure 10T can be electrically disconnected from the first conductive trace 31.

[0031] The encapsulation substrate 1 may further include a first dielectric layer 40 disposed between the magnetic layer 22 and the first conductive trace 31. The first dielectric layer 40 may comprise a transparent dielectric material that is transparent to light or a translucent dielectric material that is translucent to light. For example, the first dielectric layer 40 may comprise a thermoplastic material, such as acrylonitrile butadiene styrene (ABS). The first dielectric layer 40 may be further disposed in the cavity 10C and between the edge 20E of the electronic component 20 and the support portion 10S of the substrate 10. In some embodiments, the first dielectric layer 40 is configured to secure the electronic component 20 in the cavity 10C. In some embodiments, the first dielectric layer 40 may at least partially cover the upper surface 22U of the magnetic layer 22, and the first dielectric layer 40 may expose the lower surface 22L of the magnetic layer 22. In some embodiments, the lower surface 22L may be higher than the second surface 102 of the substrate 10, substantially coplanar with the second surface, or lower than the second surface. A first dielectric layer 40 may be partially disposed in a first recess 22R1 and includes a through-hole 40P in the first recess 22R1, the through-hole exposing a second upper surface 242U of a connection segment 242 of the conductive line 24. A first conductive trace 31 may be disposed on the first dielectric layer 40 and fill the through-hole 40P and the first recess 22R1 to electrically connect the connection segment 242 of the conductive line 24. The first conductive trace 31 may further extend to the support portion 10S.

[0032] In some embodiments, such as Figure 1B As shown, the first dielectric layer 40 may further include protrusions 40X inserted into the magnetic layer 22 between adjacent conductive lines 24. The protrusions 40X can divide the electronic component 20 into two or more inductor regions, and the dimensions of the width, length, and depth of the protrusions 40X can be modified to adjust the inductance of the electronic component 20.

[0033] In some embodiments of this disclosure, the electronic component 20 is at least partially embedded in the cavity 10C of the substrate 10, and thus the overall thickness of the encapsulation substrate 1 can be reduced. The first alignment window 22W1 of the opaque magnetic layer 22 exposes the alignment mark segment 241 and makes the conductive line 24 visible. Therefore, the first recess 22R1 of the magnetic layer 22 can be accurately formed using the visible alignment mark segment 241 as the alignment mark. Thus, the first conductive trace 31 formed in the first recess 22R1 can be accurately aligned with the conductive line 24. Compared to a circular profile, the non-circular second upper surface 242U of the connecting segment 242 can enhance the adhesion between the first conductive trace 31 and the conductive line 24, and thus improve the connection reliability between the first conductive trace 31 and the conductive line 24.

[0034] Figure 2A , Figure 2A1 , Figure 2A2, Figure 2B , Figure 2B1 , Figure 2B2 , Figure 2C , Figure 2C1 , Figure 2D , Figure 2E and Figure 2F Operations for manufacturing a packaging substrate according to some embodiments of the present disclosure are illustrated, wherein Figure 2A , Figure 2B and Figure 2C It is drawn in top view, and Figure 2A1 , Figure 2A2 , Figure 2B1 , Figure 2B2 , Figure 2C1 , Figure 2D , Figure 2E and Figure 2F It was drawn in a cross-sectional view. Figure 2A A top view of the electronic components is depicted. Figure 2A1 It is along Figure 2A The cross-sectional view taken by lines 2A1-2A1', and Figure 2A2 It is along Figure 2A A cross-sectional view taken by line 2A2-2A2'. (Reference) Figure 2A , Figure 2A1 and Figure 2A2 An electronic component 20 is provided. The electronic component 20 includes a magnetic layer 22 and conductive wires 24 at least partially covered by the magnetic layer 22. In some embodiments, the conductive wires 24 are straight conductors arranged in parallel and extending along a first direction D1. In some other embodiments, the conductive wires 24 may be curved conductors, looped conductors, winding conductors, etc. In some embodiments, both ends of each conductive wire 24 may protrude from a corresponding edge 20E of the electronic component 20. Alternatively, both ends of each conductive wire 24 may be substantially coplanar with the corresponding edge 20E of the electronic component 20.

[0035] Figure 2B A top view of the electronic components is depicted. Figure 2B1 It is along Figure 2B The cross-sectional view taken by line 2B1-2B1', and Figure 2B2 It is along Figure 2B A cross-sectional view taken from line 2B2-2B2'. (Reference) Figure 2B , Figure 2B1 and Figure 2B2The magnetic layer 22 and the conductive wire 24 are recessed to form one or more alignment windows 22W1 that partially expose a portion of the conductive wire 24. In some embodiments, the magnetic layer 22 and the conductive wire 24 are recessed along a second direction D2 intersecting the first direction D1, such that the alignment windows 22W1 can expose a portion of each conductive wire 24 even if the conductive wire 24 covered by the magnetic layer 22 is not visible. In some embodiments, the first direction D1 is substantially perpendicular to the second direction D2. In some embodiments, the alignment windows 22W1 are formed mechanically, for example by a gear cutter. The gear cutter can remove a portion of the magnetic layer 22 and the conductive wire 24 along the second direction D2, such that the alignment windows 22W1 can be a continuous groove or trench traversing the conductive wire 24. Figure 2B As shown, the minimum width W1 of the alignment window 22W1 along the second direction D2 is wider than the width W2 of the conductive line 24 along the second direction D2. The alignment window 22W1 may include a substantially vertical sidewall profile or a sloping sidewall profile. After the magnetic layer 22 and the conductive line 24 are recessed, each conductive line 24 includes an alignment mark segment 241 exposed through the alignment window 22W1. In some embodiments, the first upper surface 241U of the alignment mark segment 241 includes a substantially flat surface.

[0036] Figure 2C A top view of the electronic components is depicted, and Figure 2C1 It is along Figure 2C A cross-sectional view taken from line 2C1-2C1'. (Reference) Figure 2C and Figure 2C1 The magnetic layer 22 is recessed from the upper surface 22U by referencing alignment marks to form a first recess 22R1 that partially exposes the second upper surface 242U of the conductive wire 24. In some embodiments, the first recess 22R1 may be formed, but is not limited to, optically, for example by laser drilling. The first recess 22R1 may include, but is not limited to, a sloped sidewall profile. The first recess 22R1 of the magnetic layer 22 may include a plurality of holes that are separated from each other and respectively expose the second upper surface 242U of the connection segment 242 of the conductive wire 24.

[0037] like Figure 2DAs shown, an electronic component 20 is disposed in a cavity 10C of a substrate 10. In some embodiments, adhesive tape 38 is adhered to a second surface 102 of the substrate 10 to seal the cavity 10C, and the electronic component 20 is disposed in the cavity 10C and secured with the adhesive tape 38. Since the second segment 242 of the conductive line 24 can be viewed through the alignment window 22W1, the alignment mark segment 241 of the conductive line 24 exposed through the alignment window 22W1 can be used as an alignment mark to accurately align the electronic component 20. In some embodiments, before the electronic component 20 is disposed in the cavity 10C of the substrate 10, the magnetic layer 22 is recessed from the upper surface 22U to form a first recess 22R1. In some other embodiments, after the electronic component 20 is disposed in the cavity 10C of the substrate 10, the magnetic layer 22 is recessed from the upper surface 22U to form the first recess 22R1.

[0038] like Figure 2E As shown, a first dielectric layer 40 is formed in the cavity 10C, the alignment window 22W1, and the first recess 22R1. In some embodiments, the first dielectric layer 40 may be flowable, and the fluid of the first dielectric layer 40 may fill the cavity 10C and be located between the edge 20E of the electronic component 20 and the support portion 10S of the substrate 10. The first dielectric layer 40 may further cover the first surface 101 of the substrate 10. The first dielectric layer 40 may be thermosetting and / or optically cured to solidify.

[0039] like Figure 2F As shown, a through-hole 40P is formed in the first dielectric layer 40 within the first recess 22R1 to expose the connection segment 242 of the conductive line 24. In some embodiments, the through-hole 40P may be formed, but is not limited to, optically, for example, by laser drilling. The through-hole 40P may include, but is not limited to, a sloping sidewall profile. The position of the through-hole 40P can be accurately aligned using the alignment mark segment 241 of the conductive line 24 exposed through the alignment window 22W1. In some embodiments, the tape 38 may contain an indirect material used as a sacrificial layer and will be removed after the formation of the first dielectric layer 40. Examples of indirect materials used as tape 38 may include, but are not limited to, a dielectric film coated with adhesive. Alternatively, tape 38 may contain a direct material that will be retained after the formation of the first dielectric layer 40. The adhesion of the direct material may depend on temperature. For example, the adhesion of the direct material increases with increasing temperature. Examples of direct materials used as tape 38 may include, but are not limited to, Ajinomoto additive layer (ABF) and resin. Conductive traces 31 are formed on the connection section 242 of the conductive line 24 exposed by the through-hole 40P of the first dielectric layer 40, so as to form a conductive trace 31. Figure 1 , Figure 1A , Figure 1B and Figure 1C The packaging substrate 1 shown.

[0040] The packaging substrate and manufacturing method disclosed herein are not limited to the embodiments described above, and can be implemented according to other embodiments. For the sake of simplicity and ease of comparison between the various embodiments of this disclosure, similar components in the following embodiments are labeled with the same reference numerals and may not be described repeatedly.

[0041] Figure 3 This is a schematic perspective view of an electronic component 20 according to some embodiments of the present disclosure, and Figure 3A This is a schematic cross-sectional view of an electronic component 20 according to some embodiments of the present disclosure. Figure 3 and Figure 3A As shown, with Figure 2B Compared to the electronic component 20 shown, the two ends of each conductive line 24 are substantially coplanar with the corresponding edge 20E of the electronic component 20.

[0042] Figure 4 This is a schematic top view of an electronic component 20 according to some embodiments of the present disclosure. Figure 4 As shown, the first alignment window 22W1 may partially overlap with the first recess 22R1. For example, the first alignment window 22W1 includes a groove that continuously traverses the plurality of conductive lines 24, and the first recess 22R1 includes a plurality of holes that are separated from each other and partially overlap with the first alignment window 22W1.

[0043] Figure 5 This is a schematic top view of an electronic component 20 according to some embodiments of the present disclosure, and Figure 5A This is a schematic cross-sectional view of the packaging substrate 2 according to some embodiments of the present disclosure. Figure 5 and Figure 5A As shown, the first alignment window 22W1 of the magnetic layer 22 includes a plurality of holes, which are separated from each other and expose the first upper surface 241U of the alignment mark segment 241 of the conductive line 24. The first recess 22R1 of the magnetic layer 22 may include a plurality of holes, which are separated from each other and expose the second upper surface 242U of the second segment 242 of the conductive line 24.

[0044] The minimum width W1 of the first alignment window 22W1 along the first direction D1 or the second direction D2 is wider than the width W2 of the conductive line 24 in the second direction D2. The minimum width W3 of the first recess 22R1 along the first direction D1 or the second direction D2 is wider than the width W2 of the conductive line 24 in the second direction D2. The shapes of the first alignment window 22W1 and / or the first recess 22R1 may each include a circle, a rectangle, or other shapes. In some embodiments, the first alignment window 22W1 is formed mechanically, for example, by drilling. In some embodiments, the first upper surface 241U of the alignment mark segment 241 of the conductive line 24 after the formation of the first alignment window 22W1 may include, for example, the following: Figure 5A The concave surface is shown. In some other embodiments, the first upper surface 241U of the alignment mark segment 241 of the conductive line 24 after the formation of the first alignment window 22W1 may include a notched surface. In some embodiments, the first recess 22R1 may be formed, but is not limited to, optically, for example by laser drilling. The first recess 22R1 may include, but is not limited to, an inclined sidewall profile. The first alignment window 22W1 and the first recess 22R1 may be separate from each other.

[0045] Figure 6 This is a schematic top view of an electronic component 20 according to some embodiments of the present disclosure, and Figure 6A This is a schematic cross-sectional view of the packaging substrate 3 according to some embodiments of the present disclosure. Figure 6 and Figure 6A As shown, with Figure 5 and Figure 5A Compared to the packaging substrate 2, the first alignment window 22W1 partially overlaps with the first recess 22R1. In some other embodiments, the first alignment window 22W1 may completely overlap with the first recess 22R1. For example, the first alignment window 22W1 may be slightly larger than the first recess 22R1, and the first alignment window 22W1 may completely surround the first recess 22R1.

[0046] Figure 7 This is a schematic cross-sectional view of the packaging substrate 4 according to some embodiments of the present disclosure. Figure 7 As shown, with Figure 1 , Figure 1A , Figure 1B and Figure 1CCompared to the encapsulation substrate 1, the magnetic layer 22 may further include a second recess 22R2, which is disposed in the lower surface 22L of the magnetic layer 22 and exposes the lower surface 242L of the connection segment 242. The encapsulation substrate 4 may further include a second conductive trace 32, which is located in the second recess 22R2 and electrically connected to the lower surface 242L of the connection segment 242 of the conductive line 24. In some embodiments, the magnetic layer 22 may further include a second alignment window 22W2, which is disposed in the lower surface 22L of the magnetic layer 22 and exposes the lower surface 241L of the alignment mark segment 241. In some embodiments, the encapsulation substrate 4 may further include a second dielectric layer 42 disposed between the magnetic layer 22 and the second conductive trace 32. In some embodiments, the second recess 22R2 may be aligned with the first recess 22R1. In some embodiments, the second alignment window 22W2 may be aligned with the first alignment window 22W1. In some other embodiments, the second alignment window 22W2 may not be aligned with the first alignment window 22W1.

[0047] In some embodiments, some conductive structures in the conductive structure 10T may be electrically connected to the second conductive trace 32. In some other embodiments, some conductive structures in the conductive structure 10T may be electrically disconnected from the second conductive trace 32.

[0048] Figure 8 This is a schematic cross-sectional view of the packaging substrate 5 according to some embodiments of the present disclosure. Figure 8 As shown, with Figure 7 Compared to the packaging substrate 4, the second recess 22R2 is not aligned with the first recess 22R1.

[0049] Figure 9 Operations for manufacturing an electronic device package 100 according to some embodiments of the present disclosure are illustrated. For example... Figure 9 As shown, a packaging substrate is provided. (Selection) Figure 7The package substrate 4 shown is an example, but not limited to it. Any other package substrate described above can be selected. A first redistribution layer (RDL) 50 may be formed on the first surface 101 of the substrate 10. The first RDL 50 may include one or more insulating layers 52 and one or more conductive layers 54 stacked on top of each other. In some embodiments, a buffer layer 44 may be formed on the first surface 101 of the substrate 10 prior to the formation of the first RDL 50. The buffer layer 44 may increase the adhesion between the first RDL 50 and the package substrate 4 and mitigate warpage issues. One or more first semiconductor dies 60 may be disposed on the first RDL 50 and electrically connected to the first RDL. In some embodiments, the first semiconductor dies 60 may be electrically connected to the first RDL 50 in a flip-chip manner, wherein conductive bumps 62, such as solder bumps, face the first RDL 50, and an underfill 64 may be formed between the first semiconductor die 60 and the first RDL 50. The first semiconductor die 60 may comprise any type of active die, passive die, or combination thereof. The first semiconductor die 60 can be electrically connected to the electronic component 20 and the conductive structure 10T via the first RDL 50. An encapsulation layer 66 can be formed to encapsulate the first semiconductor die 60. The encapsulation layer 66 may contain molding material and may partially or completely encapsulate the first semiconductor die 60.

[0050] In some embodiments, a plurality of electrical connectors 80, such as solder balls, may be formed on the second surface 102. A second RDL 70 may be formed on the second surface 102 of the substrate 10 prior to the formation of the plurality of electrical connectors. The second RDL 70 may include one or more insulating layers 72 and one or more conductive layers 74 stacked on top of each other. In some embodiments, a passivation layer 76, such as a solder mask, may be formed on the second RDL 70 to partially expose the bonding pads of the second RDL 70, and the electrical connectors 80 are connected to the exposed bonding pads. In some embodiments, a second semiconductor die 82 may be disposed on the second RDL 70 and electrically connected to the second RDL. In some embodiments, the second semiconductor die 80 may be electrically connected to the second RDL 70 in a flip-chip manner using conductive bumps 84, such as solder bumps. The second semiconductor die 82 may comprise any type of active die, passive die, or combination thereof. In some embodiments, the second semiconductor die 82 and the electrical connectors 80 are disposed at substantially the same horizontal height. The second semiconductor die 82 can be thinner than the electrical connector 80, allowing the electrical connector 80 to be further connected to external electronic components such as printed circuit boards (PCBs).

[0051] Figure 10 Operations for manufacturing an electronic device package 200 according to some embodiments of the present disclosure are illustrated. For example... Figure 10 As shown, with Figure 9Compared to the electronic device package 100, the tape 38 is made of a direct material and remains on the second surface 102 of the substrate 10, and is disposed between the substrate 10 and the second dielectric layer 42. The tape 38 may be recessed such that the second dielectric layer 42 and the second conductive trace 32 can penetrate the tape 38.

[0052] In some embodiments of this disclosure, the packaging substrate includes electronic components embedded in cavities within the substrate, thus reducing the overall thickness of the packaging substrate. Alignment windows of the opaque magnetic layer expose and make the conductive lines visible. Therefore, recesses in the magnetic layer can be accurately formed using visible alignment mark segments as alignment markers. Consequently, conductive traces formed in the recesses can be accurately aligned with the conductive lines.

[0053] As used herein, unless the context clearly indicates otherwise, the singular terms “a / an” and “the” may include plural referents.

[0054] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and explain small variations. When used in conjunction with an event or situation, the terms may refer to instances where the event or situation occurred precisely or instances where the event or situation was close to occurring. For example, when used in conjunction with a numerical value, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the numerical values ​​may be considered “substantially” the same or equal. For example, "essentially parallel" can refer to an angle variation range of less than or equal to ±10° relative to 0°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. Similarly, "essentially perpendicular" can refer to an angle variation range of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0055] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​that are explicitly specified as the limits of the range, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0056] While this disclosure has been described and illustrated with reference to specific embodiments thereof, such depictions and illustrations are not intended to limit the disclosure. Those skilled in the art will understand that various changes and substitutions may be made without departing from the spirit and scope of the disclosure as defined by the claims. Illustrations may not necessarily be drawn to scale. There may be differences between artistic representations and actual installations in this disclosure due to manufacturing processes and tolerances. Other embodiments of this disclosure may exist that are not specifically shown. The specification and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein are described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or rearranged to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless expressly indicated herein, the order and grouping of operations are not a limitation of this disclosure.

Claims

1. A packaging substrate comprising: A substrate, the substrate comprising a first surface and a second surface opposite to the first surface; Electronic components, disposed in the substrate, the electronic components comprising: Conductive lines, the conductive lines including alignment mark segments and connection segments; and A magnetic layer partially covering the conductive wire, the magnetic layer comprising an upper surface adjacent to the first surface and a lower surface adjacent to the second surface, wherein the magnetic layer includes a first alignment window and a first recess, the first alignment window being disposed in the upper surface of the magnetic layer and exposing a first upper surface of the alignment mark segment, and the first recess being disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection segment; and A first conductive trace is located in the first recess and is electrically connected to the second upper surface of the connection segment of the conductive line.

2. The packaging substrate according to claim 1, further comprising a first dielectric layer disposed between the magnetic layer and the first conductive trace.

3. The packaging substrate of claim 2, wherein the first dielectric layer is disposed in the first recess of the magnetic layer and partially surrounds the first conductive trace.

4. The packaging substrate of claim 2, wherein the substrate includes a support portion defining a cavity, and the electronic component is disposed in the cavity.

5. The packaging substrate of claim 4, wherein the first dielectric layer is further disposed between the edge of the electronic component and the support portion of the substrate.

6. The packaging substrate of claim 1, wherein the electronic component comprises a plurality of conductive lines, and the first alignment window of the magnetic layer comprises a groove that continuously traverses the plurality of conductive lines and exposes the first upper surface of the alignment mark segment of the plurality of conductive lines.

7. The packaging substrate of claim 6, wherein the first alignment window of the magnetic layer includes a plurality of holes, the plurality of holes being separated from each other and respectively exposing the first upper surface of the alignment mark segment of the plurality of conductive lines.

8. The packaging substrate of claim 1, wherein the minimum width of the first alignment window is wider than the width of the conductive line.

9. The packaging substrate of claim 1, wherein the first upper surface of the alignment mark segment comprises a substantially flat surface, a concave surface, or a notched surface.

10. The packaging substrate of claim 1, wherein the second upper surface of the connection segment comprises a substantially flat surface.

11. The packaging substrate of claim 1, wherein the first upper surface of the alignment mark segment is lower than the second upper surface of the connection segment.

12. The packaging substrate of claim 1, wherein the first alignment window partially overlaps with the first recess.

13. The packaging substrate of claim 1, wherein the magnetic layer further includes a second recess disposed in the lower surface of the magnetic layer and exposing the lower surface of the connection segment.

14. The packaging substrate of claim 13, wherein the second recess is aligned with the first recess.

15. The packaging substrate of claim 13, wherein the magnetic layer further includes a second alignment window disposed in the lower surface of the magnetic layer and exposing the lower surface of the alignment mark segment.

16. The packaging substrate of claim 13, further comprising a second conductive trace located in the second recess and electrically connected to the lower surface of the connection segment of the conductive trace.

17. The packaging substrate of claim 16, further comprising a second dielectric layer disposed between the magnetic layer and the second conductive trace.

18. A method for manufacturing a packaging substrate, the method comprising: An electronic component is provided, the electronic component including a magnetic layer and conductive lines at least partially covered by the magnetic layer; The magnetic layer is partially removed from the upper surface to form an alignment window, which partially exposes the first upper surface of the conductive wire, which acts as an alignment mark. By referring to the alignment mark, the magnetic layer is recessed from the upper surface to form a recess on the second upper surface that partially exposes the conductive wire; The electronic components are placed in the cavity of the substrate by referring to the alignment marks; A dielectric layer is formed in the cavity and the recess; A perforation is formed in the dielectric layer within the recess to expose the conductive wire; as well as Conductive traces are formed on the conductive lines exposed through the perforations in the dielectric layer.

19. The method of claim 18, wherein the alignment window is formed by a gear cutter or a drill, and the recess is formed by laser drilling or by a drill, and the perforation is formed by laser drilling.

20. A method for manufacturing an electronic device package, the method comprising: Provide the packaging substrate of claim 1; A redistribution layer RDL is formed on the first surface of the substrate; A semiconductor die is formed on the RDL; Encapsulating the semiconductor die; as well as A plurality of electrical connectors are formed on the second surface of the substrate.

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