Ferroelectric-based transistors

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to ferroelectric-based transistors and methods of manufacturing the same. The ferroelectric-based transistor comprises: a semiconductor-on-insulator substrate comprising a semiconductor material, a buried insulator layer below the semiconductor material, and a substrate material below a semiconductor channel material; a ferroelectric capacitor below the buried insulator layer and comprising a bottom electrode, a top electrode, and a ferroelectric material between the bottom electrode and the top electrode; a gate stack above the semiconductor material; a first terminal contact connected to the bottom electrode of the ferroelectric capacitor; and a second terminal contact connected to the top electrode of the ferroelectric capacitor.

Description

Technical Field

[0001] The present disclosure relates to semiconductor structures and, more particularly, to ferroelectric based transistors and methods of fabrication. Background Art

[0002] The ferroelectric field effect transistor (FeFET) gate stack structure is characterized by ferroelectric (FE) material integration, in which a buffer interface layer is grown between the ferroelectric material layer and the Si substrate. Compared with the ferroelectric material, the buffer interface layer has an intrinsically lower dielectric constant, thereby changing the gate stack field distribution toward an increased field at the buffer interface layer and a reduced field across the ferroelectric material. Therefore, the FeFET operating range is shifted toward higher write conditions and is accompanied by severe charge injection and trapping in the ferroelectric material layer, resulting in limited durability of the memory. Durability and write conditions are key challenges for FeFETs to achieve universal memory characteristics.

[0003] The FeFET memory window (MW) is defined as the period between erase and program I d -V g Read V T The memory window size is a result of the direct relationship between the memory window and the thickness of the ferroelectric material layer derived based on the FeFET gate stack (MW ~ 2E c *d F ). Therefore, considering the constant E c In the case of FeFETs, this relationship resembles a fundamental physical limit on the maximum achievable memory window, preventing FeFETs from being used as multi-bit storage memories and limiting gate stack scalability beyond the thickness range where the memory window is optimal.

[0004] In addition, the FeFET readout operation is performed by sweeping the gate voltage (V g ). Since the ferroelectric material layer integrated into the FeFET gate stack is subjected to the same readout voltage, the ferroelectric material thickness and V g Under certain conditions in the range, the read operation can result in changing the state of the ferroelectric material. For FeFETs based on the scaled thickness of the ferroelectric material layer, the read disturb becomes more challenging.

[0005] Common FRAM type memories are characterized by the integration of ferroelectric capacitors in the back end of line (BEOL), where the ferroelectric capacitors are connected to the drain terminals of the front end of line (FEOL) logic devices. The integration of ferroelectric capacitors in the BEOL limits the maximum practical capacitor size and thus the remnant polarization P that can be obtained. r . Maximizing P rThe value becomes critical for high sense currents so the design aspects of the sense amplifier can be relaxed.

[0006] Low write operation of FeFETs is achieved by utilizing a relatively high dielectric constant buffer interface layer to reduce the voltage across the buffer interface layer, thereby facilitating an increased voltage across the ferroelectric material FeFET. In turn, this leads to improved durability characteristics of the FeFET. However, the durability and write voltage improvements are still far from meeting the specifications for the main application domain (e.g., embedded memory) and may limit FeFETs to niche applications.

[0007] Attempts to expand the FeFET memory window by increasing the ferroelectric layer thickness are challenging due to the degradation of the ferroelectric properties resulting from the deviation from the stable orthorhombic phase as the thickness of the ferroelectric increases during deposition due to premature film crystallization. The ferroelectric properties are more pronounced for scaled film thickness, and therefore, attempts to increase the ferroelectric layer thickness result in an increase in the fraction of the stable non-ferroelectric phase within the film. This results in a reduced P r value, and therefore limits the maximum achievable memory window for a certain increase in ferroelectric material layer thickness.

[0008] Furthermore, write / read disturb becomes a challenge for FeFETs with integration into array structures, which leads to the consideration of special read / write schemes to avoid changing the memory state of unselected devices in the array. However, this will increase the complexity of array operation. Summary of the invention

[0009] In one aspect of the present disclosure, a structure includes: a ferroelectric capacitor located beneath a buried insulator material in a semiconductor-on-insulator (SOI) technology; a field effect transistor (FET) isolated from the ferroelectric capacitor by at least the buried insulator material; and different contacts to a bottom electrode and a top electrode of the ferroelectric capacitor and to the FET, wherein write and read operations are decoupled between the ferroelectric capacitor and the FET independent of an interface layer in a gate stack of the FET.

[0010] In one aspect of the present disclosure, a structure includes: a ferroelectric capacitor beneath a buried insulator material of a semiconductor-on-insulator (SOI) technology; a field effect transistor (FET) isolated from the ferroelectric capacitor by at least the buried insulator material; and different contacts to a bottom electrode and a top electrode of the ferroelectric capacitor and the FET, wherein write and read operations are decoupled between the ferroelectric capacitor and the FET independently of an interface layer of a gate stack of the FET.

[0011] In one aspect of the present disclosure, a structure includes: a substrate material; a buried oxide layer located on the substrate material; a semiconductor material located on the buried oxide layer, the semiconductor material representing a channel region of a field effect transistor (FET); a ferroelectric capacitor integrated with the substrate material and located below the buried oxide layer, the ferroelectric capacitor including a top electrode in contact with the buried oxide layer, a bottom electrode in contact with the substrate material, and a ferroelectric material located between the top electrode and the bottom electrode; a through-hole contact extending through the buried oxide layer and contacting the top electrode; a contact electrically connected to the bottom electrode; a source contact electrically connected to a source region of the FET; a drain contact electrically connected to a drain region of the FET; and a gate contact electrically connected to a gate electrode of the FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure is described in the following detailed description by way of non-limiting examples of exemplary embodiments of the present disclosure and with reference to the several accompanying drawings.

[0013] Figure 1 A planar capacitor beneath a buried insulator layer and a corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0014] Figure 2 Trench isolation regions and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0015] Figure 3 A gate stack and corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0016] Figure 4 Contacts to the gate stack and source / drain regions and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0017] Figure 5 A device including, among other features, two contact terminals and a corresponding manufacturing process according to aspects of the present disclosure are shown.

[0018] Figure 6 A device including, among other features, three contact terminals and a corresponding manufacturing process according to aspects of the present disclosure are shown.

[0019] Figure 7 Another device including, among other features, three contact terminals and a corresponding manufacturing process according to aspects of the present disclosure are shown.

[0020] Figure 8-10 A device including, among other features, four contact terminals and a corresponding manufacturing process according to aspects of the present disclosure are shown.

[0021] Figure 11-13 Devices utilizing, among other features, one or more deep trench metal-ferroelectric-metal (MFM) capacitors and corresponding fabrication processes are shown in accordance with aspects of the present disclosure.

[0022] Fig.14 and 15 A device having three contact terminals and a MFMFIS stacked gate configuration and a corresponding fabrication process are shown, among other features, according to aspects of the present disclosure.

[0023] Fig.16 A device having four contact terminals and a tailored gate structure and a corresponding manufacturing process according to aspects of the present disclosure, among other features, are shown.

[0024] Figure 17-19 Devices featuring, among other features, capacitors including multiple layers of ferroelectric material and corresponding fabrication processes in accordance with aspects of the present disclosure are shown.

[0025] Fig. 20 and 21 Flowcharts depicting various manufacturing processes are shown according to aspects of the present disclosure. DETAILED DESCRIPTION

[0026] The present disclosure relates to semiconductor structures, and more particularly, to ferroelectric-based transistors and methods of fabrication. More particularly, the present disclosure provides ferroelectric-based field effect transistors (FeFETs) for fully depleted silicon-on-insulator (FD-SOI) technology. Advantageously, the ferroelectric-based transistors provide improved reliability due to the use of a metal-ferroelectric-metal (MFM) stack, while also providing improved flexibility by decoupling the size of the MFM stack from the gate stack.

[0027] To overcome the above challenges, the devices described herein are compatible with standard FD-SOI manufacturing schemes. In these schemes, a substrate (e.g., Si) region located below a buried oxide (BOX) is utilized to provide integration with ferroelectric materials suitable for FRAM (or other memory) and FeFET-based technologies. For example, in an embodiment, a ferroelectric-based transistor can be implemented in different devices, such as FeFET memory cells, eDRAM, and eFRAM, by a buried ferroelectric capacitor structure located below the buried oxide (BOX) of the FD-SOI and a laminated stack of ferroelectric materials for the gate stack. With respect to the latter feature, the FD-SOI FeFET gate stack may have different gate stack configurations (e.g., metal-ferroelectric-insulator-semiconductor (MFIS), metal-ferroelectric-metal-insulator-semiconductor (MFMIS), metal ferroelectric-metal-insulator-ferroelectric-insulator-semiconductor (MFMFIS)), wherein the gate stack has a designed area ratio.

[0028] In a more specific embodiment, the MFM planar capacitor is integrated into the region below the BOX of SOI technology, where the ferroelectric material remnant polarization controls the surface potential of the semiconductor channel on top of the BOX. This in turn determines the V associated with the main FD-SOIFET device. T The integrated ferroelectric material may be any type of material having a reversible dipole switching response under the influence of an applied electric field and characterized by a remanent polarization of the ferroelectric material in the absence of an applied electric field. Examples of such ferroelectric materials include binary oxide-based high-k dielectric materials (e.g., HfO2, ZrO2) with possible extrinsic dopant elements (e.g., Si, Al, etc.) to stabilize the ferroelectric material orthorhombic phase.

[0029] In a more specific embodiment, antiferroelectric (AFE) materials can be utilized based on designed top and bottom metal electrodes to provide a hysteresis loop in which the remnant polarization can be used to shift similar to a memory state. The top and bottom electrodes of the ferroelectric capacitor are contacted to write the memory state and control the dipole orientation independently of the FD-SOI FET device. In this way, it is possible to decouple the write and read operations between the capacitor and the FET independently of the interface layer. In one variation, the source terminal is connected to the top electrode of the ferroelectric material capacitor; and the bottom electrode is connected to the drain or substrate terminal. Therefore, the overall durability of the FD-SOI-based memory is determined by the durability capability of the MFM capacitor.

[0030] In a further variation of the device, the MFM capacitor is integrated with the ferroelectric material integration in the gate stack of the FD-SOI FET, which provides a dual ferroelectric material layer integration. The ferroelectric material layer integrated into the FD-SOI gate stack can take the form of MFMIS, MFIS and MFS stacking configurations. In these implementations, the two ferroelectric material layers located on top and below the BOX control the Si surface potential, resulting in increased control of the channel and effectively increased FD-SOI FeFET memory window size.

[0031] In addition to the MFM capacitor integration below the BOX region, other variants include multiple (triple) ferroelectric material integration in the form of MFMFIS gate stack configuration. MFMIS and MFMFIS gate stack configurations can also have tuned thickness and area ratios of the two capacitors (FE and FE / IL). Direct ferroelectric material layer thickness variation and lamination-based ferroelectric material stacks for the bottom and top of FD-SOI FETs are also device variations.

[0032] In operation, the ferroelectric materials located below and on top of the BOX are independently written to provide possible multi-bit data storage. The writing scheme is adjusted to control the substrate of the individual ferroelectric material layers to achieve tuned V corresponding to multi-levels. T The corresponding V is achieved by measuring the drain current of the FD-SOI FET device and mapping it to a multi-bit binary state. T Shifted readout. Additionally, the writing / reading of the memory state is decoupled to provide minimal disturbance on the ferroelectric state, e.g., the ferroelectric state is written independently of the FD-SOI gate stack by applying a write pulse to the ferroelectric capacitor. In this configuration, device readout is achieved by sweeping the gate voltage of the normal dielectric stack and measuring the source-drain current.

[0033] The ferroelectric-based transistors of the present disclosure can be manufactured in a variety of ways using a variety of different tools. However, typically, methods and tools are used to form structures with dimensions in the micrometer and nanometer scales. Methods, i.e., techniques, for manufacturing the ferroelectric-based transistors of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structure is constructed on a wafer and implemented as a film of material patterned by a photolithography process on top of the wafer. In particular, the manufacture of ferroelectric-based transistors uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by photolithographic imaging, and (iii) selectively etching the film to the mask.

[0034] Figure 1A planar capacitor located below a buried insulator layer and a corresponding manufacturing process are shown in accordance with aspects of the present disclosure, among other features. More specifically, structure 10 includes a substrate 12. Substrate 12 can be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP and other III / V or II / VI compound semiconductors. Planar capacitor 14 is fabricated on substrate 12. In an embodiment, planar capacitor 14 includes a stack (e.g., a metal-ferroelectric-metal (MFM) capacitor) consisting of a bottom electrode 14a, a ferroelectric material 14b, and a top electrode 14c.

[0035] The bottom electrode 14a and the top electrode 14c are highly conductive materials grown by various techniques such as deposition or sputtering of a metal layer. For example, the top electrode 14c and the bottom electrode 14a can be titanium nitride. In other embodiments, due to the difference in the work function of the selected metal, the electrode materials can be the same or different metal materials to achieve the built-in potential. The top electrode 14c can be deposited by low temperature deposition techniques; however, high temperature deposition techniques can also be used.

[0036] The ferroelectric material 14b may be any type of material that has a reversible dipole switching response under the influence of an applied electric field (e.g., voltage) and is further characterized by a remanent polarization of the ferroelectric material in the absence of an applied electric field. The remanent polarization of the ferroelectric material 14b may control the surface potential of a semiconductor channel, such as the semiconductor material 20 located on top of the insulator layer 16. This in turn determines the V associated with the FD-SOI FET device. T Shifted to reflect the memory state stored in the capacitor 14. Examples of ferroelectric material 14b include binary oxide-based high-k dielectric materials (e.g., HfO2, ZrO2) with optional non-intrinsic doping elements (e.g., Si, Al, etc.) to stabilize the orthorhombic phase of the ferroelectric material. The ferroelectric material 14b can be grown by various techniques, in which optional dopant elements can be introduced to stabilize a certain crystalline phase. The thickness of the two electrodes 14a, 14c and the interlayer thickness of the ferroelectric material 14b can be varied to match the target operating specifications.

[0037] After depositing the top electrode 14c, a dedicated anneal is provided to crystallize the ferroelectric material 14b before the oxide layer growth (e.g., insulator layer 16) or at a later stage of device integration. This dedicated anneal is designed to match the optimal crystallization annealing range of the ferroelectric material 14b specific to the integration. In addition, non-dedicated annealing steps inherent to the integration flow (e.g., source and drain dopant activation) are considered as methods for crystallizing the ferroelectric material 14b.

[0038] After forming capacitor 14, insulator layer 16 is deposited on top of top electrode 14c to isolate material 14a, 14b, 14c of capacitor 14 from the channel region of the device. In an embodiment, insulator layer 16 can be any suitable material, including silicon oxide, sapphire, other suitable insulating materials and / or combinations thereof. Exemplary insulator layer 16 is a buried oxide layer (BOX). Insulator layer 16 is formed by any suitable process, such as isolation by oxygen implantation (SIMOX), oxidation, deposition and / or other suitable processes.

[0039] Still reference Figure 1 , an optional via contact 18 is formed through the insulator layer 16, which contacts the top electrode 14c of the capacitor 14. In an embodiment, as an example, the contact 18 will be used to control and write the memory state. However, it will be understood by those of ordinary skill in the art that the top electrode is preferably controlled by a source contact through the insulator layer 16, as further described herein. For example, although the via contact 18 is not the default due to charge screening of ferroelectric polarization, it is still possible to include, for example, Figure 4 The option of via contacts 18 for readout is shown. Therefore, in a preferred embodiment, writing is preferably performed through the source contact. Furthermore, in case both the source terminal and the drain terminal contact the metal-ferroelectric-metal (MFM), the device then operates as a FRAM and not as a FeFET, see for example Figure 7 .

[0040] The contact 18 can be formed by conventional photolithography, etching and deposition methods known to those skilled in the art. For example, the resist formed on the insulator layer 16 is exposed to energy (light) to form a pattern (opening). An etching process with selective chemistry (e.g., reactive ion etching (RIE)) will be used to form a groove that reaches the top electrode 14c through the opening of the resist. After removing the resist by a conventional oxygen ashing process or other known strippers, the conductive material can be deposited by any conventional deposition process (e.g., CVD process). Any residual material on the surface of the insulator layer 16 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0041] Semiconductor material 20 is deposited on insulator layer 16, effectively forming SOI technology. Semiconductor material 20 will be the active channel region of a device such as a FET, and may be composed of any suitable single crystalline material with a preferred crystallographic orientation (e.g., (100), (110), (111) or (001) crystallographic orientation). In addition, in embodiments, semiconductor material 20 may be composed of the same or different material as substrate 12. Semiconductor material 20 may be fabricated using wafer bonding techniques or other suitable methods, such as channel layer growth, in which epitaxial material is grown in an active channel over insulator layer 16. The thickness of the channel region (e.g., semiconductor material 20) and insulator layer 16 may be varied to match the target performance specifications for the device.

[0042] Figure 2 A trench isolation region 22 and a corresponding manufacturing process are shown, among other features. In an embodiment, the trench isolation region 22 is formed by conventional photolithography, etching, and deposition processes, as described herein. The trench isolation region 22 may be a shallow trench isolation structure that defines a channel region 23 of the device, for example, composed of semiconductor material 20. Specifically, the combination of the trench isolation region 22 and the insulator layer 16 will effectively isolate the channel region 23 of the device.

[0043] Figure 2 It is further shown that the semiconductor material 20, the insulator layer 16, and the capacitor materials 14a, 14b, 14c are removed outside of the channel region 23. That is, through a selective etching process, these materials are removed to expose the surface of the semiconductor material 20. In this embodiment, the exposure of the semiconductor material 20 will allow a contact terminal to apply a voltage to the bottom electrode 14a.

[0044] Figure 3 The deposition and patterning of the gate stack material to form the gate stack 25 of the FD-SOI FET device is shown. The FD-SOI FET device can be manufactured based on a gate first or gate last integration scheme, where in the gate last scheme, a dummy gate is utilized when the source-drain dopant activation annealing precedes the actual gate deposition. On the other hand, as Figure 3 and Figure 4 As shown, for example, the gate-first approach is characterized by the actual gate stack deposition, followed by self-aligned source-drain ion implantation, and subsequent implant activation annealing. After the gate material is deposited, photolithography and etching processes are performed to pattern these materials into the gate stack 25.

[0045] More specifically, the gate stack deposition is characterized by growing an optional interfacial layer 26 on top of the semiconductor material 20. The interfacial layer 26 is any type of dielectric material in which there can be a selective tradeoff between the material bandgap parameter and the dielectric constant. The interfacial layer 26 can be grown by various techniques (e.g., thermal growth or deposition) to achieve an interfacial layer thickness that matches the target operating specification. A gate dielectric material layer 28 is deposited on the interfacial layer 26. In an embodiment, the gate dielectric material 28 can be a high-k gate dielectric material, such as HfO2 Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and a combination of multiple layers thereof, which is characterized by its thickness and dielectric constant generally being in a range higher than the dielectric material 26. The high-k dielectric material 28 can be optimized to exhibit ferroelectric properties under the influence of an applied electric field. The interface-free growth method of this layer is also a possible alternative to omitting the dielectric material 26.

[0046] Still refer to Figure 3 , a metal layer 30, such as a gate electrode, is deposited on the dielectric material 28. The metal layer 30 will act as a metal gate for the high-k dielectric layer and similarly act as a capping metal for the target ferroelectric material. The properties (e.g., type, thickness, work function) of the metal layer 30 can be adjusted to correspond to the target device properties of an n-type or p-type based FD-SOI FET device. Examples of work function materials for p-channel FETs include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. Examples of work function materials for n-channel FETs include TiN, TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC. The work function material can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) including sputtering, atomic layer deposition (ALD), or other suitable methods.

[0047] In an embodiment, the metal layer 30 can induce stress on the thin film of high-k dielectric material 28 so that the stabilization of a particular ferroelectric material crystalline phase is energetically favorable. The metal layer 30 can also extend to act as a bottom electrode for subsequent layers of deposited ferroelectric material. In this regard, due to the tuning of the capacitor area ratio within the stack structure, the area of ​​the metal layer 30 can be controlled to achieve certain performance advantages. The metal layer 30 also acts as a floating metal gate, where charge tunneling through the interface and storage in the floating gate can be used to enable the bottom of the FD-SOI stack to exhibit memory characteristics.

[0048] In an optional embodiment, a ferroelectric material 32 may be used in the gate stack 25. The thickness and type of the two ferroelectric materials 32 may be varied to fit within a specific flow thermal budget and target device performance in subsequent process steps. A top gate electrode 34 may be deposited as a capping layer for the ferroelectric material 32. The top gate electrode 34 may be composed of a metal capping material on top of the ferroelectric material 32 followed by a highly conductive Si material, wherein the high conductivity is achieved by non-intrinsic Si doping with a high doping concentration corresponding to an n-type or p-type highly conductive layer. The properties of the top gate electrode 34 in terms of thickness, dopant concentration, and dopant type may be adjusted to match its utilization for a p-type or n-type based FD-SOI FET device.

[0049] With respect to the deposited gate stack material, the gate stack etch is adjusted to structure the active gate region 25, while the region of the source-drain is etched to the Si substrate for a possible source-drain implantation step. The number and order of the etching steps can be adjusted to etch the bottom and top of the stack separately or in a single step related to the target stack configuration of the final device. Similarly, with respect to the gate stack etch, the order of the source-drain ion implantation 36 and the implant activation step can be controlled. The source ion implantation 36 will contact the contact 18.

[0050] exist Figure 4 , sidewall spacers 38 are formed on the gate stack 25. In an embodiment, the sidewall spacers 38 are nitride materials deposited by a blanket deposition process, such as CVD, followed by an anisotropic etching process, thereby leaving material on the sidewalls of the gate stack 25. Contact terminals 40a, 40b, 40c, 40d are formed to contact the drain and source regions 36, the exposed substrate 12, and the gate stack 25 (e.g., the gate electrode 34). The contact terminals 40a, 40b, 40c, 40d are formed by conventional photolithography, etching, and deposition methods so that no additional explanation is required for a complete understanding of the present disclosure.

[0051] In an embodiment, contact terminal 40b will be used to apply a voltage to top electrode 14c (through contact 18); while contact terminal 40c will be used to apply a voltage to bottom electrode 14a (through substrate 12). In this way, contact terminals 40b, 40c will be used to write data into the memory by switching ferroelectric material 14b, for example, switching the dipole of ferroelectric material 14b, as described in more detail below. Contact terminal 40b will also apply a voltage to the channel region of gate stack 25.

[0052] Figure 5A device 10a is shown that includes two contact terminals 40b, 40d. In this device 10a, the contact terminal 40b provides an applied voltage to both the source region and the top electrode 14c of the capacitor 14. Thus, the field is written across the buried oxide 16, the S / D as the top contact, and the substrate 12 as the bottom metal electrode (MFM contact); although as an option already noted herein, the via contact 18 can still be used for readout. The remaining features are the same as those of reference 1. Figure 1-4 The characteristics described are the same.

[0053] Figure 6 A device 10b is shown including three contact terminals 40b, 40d, 40e and a contact 18b, wherein the contact 18b extends from the contact terminal 40e to the bottom electrode 14a of the capacitor 14. Figure 4 In contrast to the voltage applied through the substrate 12 shown, the contact terminal 40e applies the voltage directly to the bottom electrode 14a. A shallow trench isolation 22a is also provided. The remaining features are the same as those of reference Figure 1-4 The characteristics described are the same.

[0054] Figure 7 A device 10c is shown that includes three contact terminals 40a, 40b, 40d and a contact 18c. The gate stack 25 can be an FD-SOI FeFET based on the MFIS stack structure and is mainly used to operate as a FRAM device. In the device 10c, the contact 18c is located on the drain side of the device and extends through the semiconductor material 20 to the bottom electrode 14a of the capacitor 14. In this way, the source side contact terminal 40b can provide the applied voltage to the top electrode 14c, and the drain side contact terminal 40a can provide the applied voltage to the bottom electrode 14a. In addition, in this configuration, the read current between the source and the drain becomes proportional to the polarization charge of the switched buried MFM, where the writing of the MFM is performed through the via contacts 18, 18c. The remaining features are the same as those of reference Figure 1-4 The characteristics described are the same.

[0055] Figure 8-10 A device with four terminals, such as a FeFET memory, is shown, which has write and read operations. As shown in each of these devices 10d, 10e, 10f, the bottom electrode 14a of the capacitor 14 is connected to the contact 18 (e.g., through a via contact) through the source contact terminal 40b, and the bottom electrode 14a is contacted via the substrate contact terminal 40c. In addition to the capacitor 14, Figure 8 The gate stack 25a includes a single ferroelectric stack (eg, MFM stack) 42 (with respect to Figure 4 The alternative devices described are similar); and devices 10e, 10f include dual ferroelectric stacks 42a, 42b. In this way, (i) Figure 8 The device 10d is a MFMIS stacked configuration with a designed MFM to MIS area ratio, (ii) Fig. 9 The device 10e is a MFMFIS-based structure with a designed area ratio for dual ferroelectric stack integration, and (iii) Fig.10 The device 10e is a MFMFIS structure having dual ferroelectric integration, a designed area ratio, and further including an electrode contact 40f connected to the bottom MFM stack 42b and an electrode contact 40d connected to the top MFM stack 42a.

[0056] As in other embodiments having ferroelectric materials for capacitors and gate stacks, for example, in Fig.10 In the device 10e, the polarization of the ferroelectric material 14b of the capacitor 14 can be adjusted so as to change the back bias operating point by the polarization field. Advantageously, in normal operation, there is no need to apply a back bias voltage, which provides an additional reduction in power consumption. In addition, the back bias of the ferroelectric material can be adjusted by programming or erasing operations on the back gate. And, the top word line will control the ferroelectric material and readout of the gate stack; while the back gate word line will control the ferroelectric material 14b of the capacitor 14. Therefore, as with other embodiments, there is independent switching of different ferroelectric materials.

[0057] Figure 11-13 Devices utilizing one or more deep trench MFM capacitors 14' are shown, such as FeFET memories. In these embodiments, the deep trench MFM capacitor 14' is characterized by a high aspect ratio deep etch profile inside the Si substrate / oxide to provide an intrinsic high remanent polarization for the ferroelectric capacitor. The substrate of the ferroelectric material 14b is controlled by pulses at the two electrode terminals of the capacitor. The ferroelectric memory state is read out by reversing the ferroelectric dipole state and measuring the corresponding switching current. In another variation of the device, multiple deep trenches of the ferroelectric capacitor are connected in a parallel configuration to provide a maximized ferroelectric remanent polarization.

[0058] More specifically, Fig.11 and Fig.12 The devices 10g, 10h shown in FIG. 1 respectively show a single deep trench MFM capacitor 14' integrated in the region below the insulator layer 16 (BOX); and Fig.13 A structure 10i utilizing a plurality of deep trench MFM capacitors 14', 14'a is shown. Similar to what has been described, the deep trench capacitors 14', 14'a include a bottom electrode 14a, a ferroelectric material 14b, and a top electrode 14c. An insulator layer 16a is also provided within the deep trenches to fill the remaining area, which may be deposited in the same deposition process as the insulator layer 16.

[0059] exist Figure 11-13 In each of the embodiments of FIG. 1 , the top electrode 14 c of the capacitor 14 ′ is connected to the source terminal 40 b of the FD-SOI FET using the contact 18 (eg, through an oxide via). Fig.13 As shown, the drain terminal (eg, contact 18') may be used to contact the additional MFM capacitor 14'a. Fig.13 In the structure 10i of FIG. 1 , the additional capacitor 14'a will extend the lifetime of the device operation by allowing switching between different available capacitors 14', 14'a. In the devices 10g and 10i, the bottom electrode 14a of the capacitor 14' can be contacted via the substrate terminal 40c; while in FIG. 1 , the bottom electrode 14a of the capacitor 14' can be contacted via the substrate terminal 40c; Fig.12 In the embodiment of the present invention, the bottom electrode 14a of the capacitor 14' may be connected via the drain terminal 18'. As previously described, memory state readout is achieved by switching the capacitor dipole state and measuring the source-drain current.

[0060] Fig.14 and 15 A device having three terminals to operate primarily as a FRAM device with write and read operations is shown. In an embodiment, device 10j includes an MFMIS stack configuration 25b with a designed MFM to MIS area ratio (e.g., a single ferroelectric layer integration); while device 10k includes an MFMIS stack configuration 25c with a designed area ratio for dual ferroelectric stack integration (e.g., a layered ferroelectric layer stack integration). In addition, as shown in each of these devices 10j, 10k, an additional buried insulator layer 16b (e.g., an oxide material) is introduced under the capacitor 14 to isolate the capacitor 14 from the substrate 12. As a result, the capacitor is completely isolated from both the substrate 12 and the semiconductor material 20 (e.g., the channel region).

[0061] In these implementations, the top electrode 14c and the bottom electrode 14a of the capacitor 14 are connected to the contacts 18, 18' using the source and drain terminals 40a, 40b, respectively. In these devices 10j, 10k, memory state readout is achieved by sweeping the gate voltage and measuring the source to drain current while a bias voltage is applied to the drain terminal contact 40a. That is, the read current between the source and the drain becomes proportional to the polarization charge of the switched buried MFM, for example, the write MFM is accomplished through the via contacts 18, 18'. From I d -V g Characteristics of the extracted V T Similar to the state stored in the ferroelectric layer. In addition, the reversible dipole switching provides a sense current for reading out the memory state similar to FRAM or DRAM memory.

[0062] In addition, still refer to Fig.14 and15 , the area ratio of the capacitors of the gate structures 25b, 25c can be tuned to achieve a stack voltage distribution to facilitate ferroelectric switching and enable device operation at lower write voltages. The ferroelectric layers in the gate stacks 25b, 25c can be switched by applying a write pulse to the gate terminal 40d while the source terminal 40b and the drain terminal 40a are biased to a reference voltage. In addition, the thickness and type of ferroelectric material in the capacitor 14 and the gate stacks 25b, 25c can be tuned to match the target performance specifications. In addition, the integration of multiple ferroelectric layers enables operation in different modes between multi-level and extended endurance modes of FD-SOI FeFETs with large memory windows (MW).

[0063] Fig.16 A device 101 having four terminals and a designed gate structure 25d is shown, which can also be operated primarily as a FRAM device. More specifically, Fig.16 The device 101 shows a MFMFIS structure including a dual ferroelectric integration with a designed area ratio. In this configuration, the electrodes 48 of the bottom capacitor 25d' are individually connected through contacts 40g to independently control the switching of each layer in the double layer stack 25d. In operation, memory state readout is achieved by applying a voltage to the bottom electrode 14a and measuring the source to drain current with a bias voltage applied to the drain terminal. d -V g Characteristics of the extracted V T Similar to the states stored in the ferroelectric layer.

[0064] Figure 17-19 Devices 10m, 10n, 10o, such as FeFET memories, are shown with capacitors 14" comprising multiple layers of ferroelectric material (e.g., MFIFM stacked capacitor integration) beneath a buried insulator layer 16. More specifically, Fig.17 Device 10m represents a MIS FD-SOI FET with high-k dielectric integration, where the internal metal is replaced by a thin insulating layer 14d (e.g., 0.5nm to 1.0nm) of, for example, Al2O3 or SiO2. In this configuration, write operations can be accomplished through terminals 40c and source / drain terminals 40a / 40b. Fig.18 The device 10n represents a MFIS stacked structure with ferroelectric material integration, and Fig.19 The device 10o shows a dual ferroelectric layer gate stack integration with MFMFIS configuration and designed area ratio. Therefore, the devices 10m, 10n, 10o may have a single or multiple ferroelectric stack in the gate stack.

[0065] Multilayered ferroelectric materials provide the ability to enhance ferroelectric film granularity, which reduces ferroelectric variability, thereby enabling reliable multi-level primitive operation. For example, devices 10m, 10n, 10o provide multi-bit memory storage, where ferroelectric write operations are tuned to provide controlled V corresponding to different bit storages. T The shift, different bit storage is due to the large memory window (MW) associated with the multi-layer structure device.

[0066] Multilayer ferroelectric materials are realized by integration of an MFIFM stack structure in which the states of the top and bottom ferroelectric layers 14b, 14b' can be switched optionally using a common intermediate electrode 14d. Furthermore, in each of these devices 10m, 10n, 10o, the top and bottom electrodes are connected by via contacts, while the bottom electrode is contacted by a substrate contact terminal 40c. This provides the possibility of writing the state of each independent ferroelectric layer individually, thus obtaining a V corresponding to multi-bit storage. T Associated control of the shift. Furthermore, in this configuration, in the absence of a floating electrode, the write operation will pass through the entire stack.

[0067] Furthermore, as described above, the gate stacks shown in devices 10m, 10n, 10o can be structured in a range between normal dielectrics and single or dual ferroelectric material integration. The area ratios and thicknesses of the integrated layers in the stack can be tuned to achieve target performance specifications. In a multi-bit mode of operation, the columnar interruption of grain growth allows a higher number of grains, which enables multi-level switching when changing the write pulse amplitude between the substrate terminal contact 40c and the source / drain contacts (e.g., contacts 40b, 40a).

[0068] Applied pulses with similar polarity to the top and bottom electrodes result in dipole orientations that are opposite in direction and thus correspond to a reduced internal field and have no effect on the channel surface potential. On the other hand, applied pulses with opposite polarity result in a maximized V corresponding to a larger memory window (MW). T In addition, asymmetric pulse amplitudes and gradually increasing pulse amplitudes are possible options for achieving multi-level storage. Figure 17-19 In the embodiment of the present invention, writing to the buried MFM capacitor is accomplished by burying the oxide, and as will be appreciated by those skilled in the art, the source and drain contacts may be omitted in the case of a FeFET, and may be used in the case of a FRAM device.

[0069] Now it should be understood that Figure 4-10Each device shown in , can contact both the top electrode 14c and the bottom electrode 14a of the capacitor 14 to achieve low voltage operation, as well as to achieve a high endurance FeFET. The top electrode 14c of the capacitor 14 is primarily contacted through the source terminal (e.g., the contact terminal 40b of the FD-SOI FET). Therefore, the source terminal of the FD-SOI FET has a dual operation function, which defaults to a current source during readout and additionally serves as a write terminal for the memory state. On the other hand, the bottom electrode 14a of the capacitor 14 can be contacted using a different mechanism, wherein the top electrode 14c of the capacitor 14 is contacted through the source terminal (e.g., the contact terminal 40b of the FD-SOI FET). Figure 4 The substrate contact 40c shown in FIG. 4 is provided with additional through-hole terminals (e.g., Figure 6 ), or by drain via contact (e.g. Figure 7 In addition, in any of these embodiments, as with respect to Figures 1 to 4 As described, having an integrated MFM capacitor within the gate stack 25 is an option.

[0070] Read and write operations

[0071] Figure 4-19 The device provides read and write operations. Generally, in operation, the bottom electrode and the top electrode of the MFM capacitor are contacted to control and write the memory state. The write voltage is expected to be lower than that of a standard FeFET, which is controlled by E c *d F OK, where E c and d F are the coercive field and thickness of the ferroelectric material, respectively. The characteristic of the device is that the write voltage is independent of the buffer interface layer 26 located between the ferroelectric material layer and the semiconductor material 20. The write voltage for the device becomes directly proportional to the ferroelectric material thickness scaling, thereby adapting to the possibility of scaling the ferroelectric material layer thickness for implementing memory operations with lower write voltages. In another variation, the ferroelectric material layer is designed by materials engineering for a reduced coercive field and / or a reduced field required for saturated polarization switching to achieve low voltage switching ferroelectric material capacitors.

[0072] More specifically, here is a description of the write and read operations:

[0073] Write Operation:

[0074] The memory state of the FD-SOI FeFET is achieved by a pulse applied to the MFM capacitor 14 between the two electrode terminals 14a, 14c of the capacitor 14 and corresponding to a programming (PG) or erasing (ER) operation. In this regard, the other terminals of the FD-SOI FeFET device are in a floating condition. The PG pulse is expected to have a positive amplitude that causes dipole switching and an associated FE positive remanent polarization. Similarly, the ER pulse has an opposite polarity and is expected to switch the dipole in the opposite direction, resulting in a negative remanent polarization.

[0075] Similarly, the ferroelectric material layer in the gate stack 25 can be switched by applying a write pulse to the gate terminal and referencing the other device terminals. Thus, the device terminals (e.g., source, drain, and body) are biased to a reference voltage, such as 0V; and a PG / ER pulse with positive / negative amplitude is applied to the gate terminal. The PG / ER pulse amplitude, shape, and duration are adjusted to match the best operating specifications for the FE integration layer.

[0076] Read operation:

[0077] By scanning the gate terminal voltage (V g ) and measure the current between the source and drain terminals (I d ) to realize the memory status readout. d -V g Characteristics and device V T The shift becomes dependent on the memory state stored on each of the FE integration layers. Figure 4 and 6 The substrate terminal of the device is biased to a reference voltage, and a certain bias voltage can be used to control the operating memory window of the device. Figure 7 In the device 10c, the substrate body terminal is omitted and readout is considered to use the floating substrate terminal.

[0078] Flowchart showing the additive manufacturing process

[0079] Fig. 20 and 21 Flowcharts depicting various manufacturing processes according to aspects of the present disclosure are shown. More specifically, Fig. 20In the embodiment, step 200 generally shows the manufacturing process of different capacitors. For example, different MFM capacitors can be formed on a substrate based on: (i) FeFET, such as a planar MFM-based FeFET, (ii) FRAM, such as a deep trench 3D MFM RAM, and (iii) MIM DRAM, such as a deep trench 3D DRAM. In these configurations, the insulator layer (BOX) and the wafer should be pre-patterned. As shown in step 202, the MFM and oxide materials are combined with the substrate material to form an MFM-based FD-SOI.

[0080] As further shown in step 204, a gate stack may be deposited on the substrate. The gate stack may include the following material configurations as shown in step 206: (i) MIS, (ii) MFIS, (iii) MFMIS, and (iv) MFMFIS, where "M" is a metal electrode, "F" is a ferroelectric material, "I" is an insulator material, and "S" is a semiconductor material. These different materials can be deposited by conventional deposition methods (e.g., CVD), as known to those skilled in the art. After depositing the gate material, at step 208, the gate stack may be patterned, at step 210, the gate stack may be etched, and at step 212, source and drain contacts may be formed as described herein. At step 214, the structure may undergo dopant activation and crystallization of the ferroelectric material. At step 216, back-end of line (BEOL) features are formed, as known in the art.

[0081] Fig.21 More details of a manufacturing process according to aspects of the present disclosure are shown. For example, at step 300, a substrate is prepared. At step 302, a decision is made as to whether the capacitor is a planar capacitor. If not planar, then at step 304, a trench is formed by conventional photolithography and etching processes. At step 306, the capacitor material is deposited as a planar configuration or within the trench. In an embodiment, the capacitor can be, for example, (i) a planar MFM based on a FeFET design, (ii) a deep trench MFM based on a FRAM design, or (iii) a deep trench MIM based on a DRAM design. These different materials can be deposited by conventional deposition methods (e.g., CVD), as known to those skilled in the art.

[0082] After forming the capacitor, at step 308, a buried oxide material may be deposited. At step 310, the buried oxide may be planarized, and then at step 312, an etching process may be performed to form oxide vias. At step 314, a channel material may be deposited, and at step 316, as described above with respect to FIG. Fig. 20 The gate stack is deposited as described.

[0083] After the gate material is deposited, at step 318, the gate stack may be patterned. At step 320, the gate stack may be etched, and at step 322, the source and drain may be formed by ion implantation processes known in the art, so that no further explanation is required herein for a complete understanding of the present invention. At step 324, spacer material may be deposited and patterned on the sides of the formed gate stack. Contacts may be formed as already described herein. At step 326, the structure may undergo dopant activation and crystallization of the ferroelectric material. At step 328, back-end of line (BEOL) features are formed, as known in the art.

[0084] The method as described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in a packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier, whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier, which has one or both of surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0085] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: A semiconductor-on-insulator substrate comprising a semiconductor channel material, a buried insulator layer below the semiconductor channel material, and a substrate material below the semiconductor channel material; a ferroelectric capacitor disposed below the buried insulator layer and comprising a bottom electrode, a top electrode, and a ferroelectric material disposed between the bottom electrode and the top electrode; a gate stack located above the semiconductor channel material; an additional buried insulator layer located below the ferroelectric capacitor; a trench isolation region extending into the substrate material and isolating the ferroelectric capacitor from the semiconductor channel material and the substrate material in combination with the buried insulator layer and the additional buried insulator layer; a first terminal contact connected to the bottom electrode of the ferroelectric capacitor; as well as A second terminal contact is connected to the top electrode of the ferroelectric capacitor.

2. The semiconductor structure according to claim 1, wherein: The ferroelectric material is a binary oxide based high-k dielectric material.

3. The semiconductor structure according to claim 2, wherein: The binary oxide based high-k dielectric material includes an extrinsic dopant element.

4. The semiconductor structure according to claim 1, wherein: The ferroelectric material has a remnant polarization that controls the surface potential of the semiconductor channel material.

5. The semiconductor structure according to claim 1, wherein: The second terminal contact is a combination of a source terminal contact and a via contact located below a source region of the gate stack on the semiconductor channel material and extending through the buried insulator layer to contact the top electrode.

6. The semiconductor structure according to claim 5, wherein: The first terminal contact is a substrate terminal in contact with the substrate material.

7. The semiconductor structure according to claim 5, wherein: The first terminal contact is a via contact extending through the semiconductor channel material, the buried insulator layer, the top electrode and the ferroelectric material to contact the bottom electrode.

8. The semiconductor structure according to claim 5, wherein: The first terminal contact comprises a drain contact terminal.

9. The semiconductor structure according to claim 1, wherein: The ferroelectric capacitor includes at least one additional ferroelectric material and an intermediate electrode, the intermediate electrode being located between the additional ferroelectric material and the ferroelectric material.

10. The semiconductor structure according to claim 1, wherein: The gate stack is a metal-ferroelectric-insulator-semiconductor MFIS gate stack, a metal-ferroelectric-metal-insulator-semiconductor MFMIS gate stack, or a metal-ferroelectric-metal-insulator-ferroelectric-insulator-semiconductor MFMFIS gate stack.

11. The semiconductor structure according to claim 1, wherein: The gate stack includes two metal-ferroelectric-metal structures, each metal-ferroelectric-metal structure having its own gate terminal.

12. The semiconductor structure according to claim 1, wherein: The ferroelectric capacitor is at least one ferroelectric deep trench capacitor integrated in the substrate material and located below the buried insulator layer.

13. The semiconductor structure of claim 1, further comprising: An insulator layer is located between the substrate material and the ferroelectric capacitor.

14. A semiconductor structure comprising: Ferroelectric capacitors, which are located beneath a buried insulator material in semiconductor-on-insulator SOI technology; A field effect transistor FET comprising a channel region on said buried insulator material; additional buried insulator material beneath the ferroelectric capacitor; a trench isolation region extending into the substrate material beneath the buried insulator material and isolating the ferroelectric capacitor from the channel region and the substrate material in combination with the buried insulator material and the additional buried insulator material; as well as to the bottom and top electrodes of the ferroelectric capacitor and to the different contacts of the FET, Wherein, writing and reading operations are decoupled between the ferroelectric capacitor and the FET independent of the interface layer in the gate stack of the FET.

15. The semiconductor structure according to claim 14, wherein: The ferroelectric capacitor includes a ferroelectric material between the top electrode and the middle electrode and between the middle electrode and the bottom electrode.

16. The semiconductor structure according to claim 14, wherein: The ferroelectric capacitor is at least one deep trench ferroelectric capacitor located within the substrate in the SOI technology and below the buried insulator material.

17. The semiconductor structure according to claim 14, wherein: The FET includes a metal-ferroelectric-metal-insulator-semiconductor MFIS gate stack, a metal-ferroelectric-metal-insulator-semiconductor MFMIS gate stack, or a metal-ferroelectric-metal-insulator-ferroelectric-insulator-semiconductor MFMFIS gate stack.

18. The semiconductor structure of claim 14, further comprising: An insulator layer is positioned beneath the ferroelectric capacitor.

19. A semiconductor structure comprising: Substrate material; a buried oxide layer located on the substrate material; a semiconductor material located on the buried oxide layer, the semiconductor material representing a channel region of a field effect transistor FET; a ferroelectric capacitor integrated with the substrate material and located below the buried oxide layer, the ferroelectric capacitor comprising a top electrode in contact with the buried oxide layer, a bottom electrode in contact with the substrate material, and a ferroelectric material located between the top electrode and the bottom electrode; an additional buried insulator layer located below the ferroelectric capacitor; a trench isolation region extending into the substrate material and isolating the ferroelectric capacitor from the semiconductor material and the substrate material in combination with the buried oxide layer and the additional buried insulator layer; a via contact extending through the buried oxide layer and contacting the top electrode; a contact electrically connected to the bottom electrode; a source contact electrically connected to a source region of the FET; a drain contact electrically connected to a drain region of the FET; as well as A gate contact is electrically connected to a gate electrode of the FET.

20. The semiconductor structure of claim 19, wherein: The contact electrically connected to the bottom electrode is a through-hole contact located on the drain side or the source side of the FET.

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