Switching control circuit and power supply circuit

Abstract

The switching control circuit of the present application is a switching control circuit that controls switching of a transistor in a power supply circuit that includes an inductor to which a rectified voltage corresponding to an alternating voltage is applied and the transistor that controls an inductor current flowing in the inductor, the power supply circuit generating an output voltage from the alternating voltage, the switching control circuit including a first operation circuit that operates a first period from when the transistor is turned off until the inductor current reaches a predetermined value, based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on, and a drive circuit that turns on the transistor for a second period corresponding to the second voltage and turns off the transistor for the first period.

Description

Technical Field

[0001] This invention relates to switch control circuits and power supply circuits. Background Technology

[0002] In power factor improvement ICs used in AC-DC converters, the transistors sometimes operate in a critical mode where the inductor current flowing through the AC-DC converter's inductor is almost zero. In such power factor improvement ICs, the timing of this near-zero inductor current is sometimes calculated based on input and output voltages (e.g., Patent Document 1, Patent Document 2, and Patent Document 3). Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent No. 5326804 Patent Document 2: Japanese Patent Application Publication No. 2017-070192 Patent Document 3: International Publication No. 2010 / 061654 Summary of the Invention The technical problem that the invention aims to solve

[0004] However, since the values ​​of the components in the AC-DC converter used to generate voltages corresponding to the input and output voltages deviate from their rated values, the power factor improvement IC used in the critical mode using the above calculation method will operate in a continuous mode where the transistor is turned on while there is still inductor current flowing through it.

[0005] The present invention was made in view of the above-mentioned existing problems, and its object is to provide a technology that enables the AC-DC converter to operate in critical mode even when the component values ​​of the AC-DC converter deviate from the rated values. Technical solutions adopted to solve technical problems

[0006] To solve the above problems, the present invention provides a switching control circuit for controlling the switching of a transistor in a power supply circuit. The power supply circuit includes: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and the transistor to control the inductor current flowing through the inductor. The power supply circuit generates an output voltage based on the AC voltage. The switching control circuit includes: a first operational circuit that performs calculations based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on, for a first period from when the transistor is turned off until the inductor current reaches a predetermined value; and a driving circuit that turns on the transistor during a second period corresponding to the second voltage and turns it off during the first period.

[0007] To solve the above problems, the present invention provides a switching control circuit for controlling the switching of a transistor in a power supply circuit. The power supply circuit includes: an inductor to which a rectified voltage corresponding to an AC voltage is applied; and the transistor to control the inductor current flowing through the inductor. The power supply circuit generates an output voltage based on the AC voltage. The switching control circuit includes a storage circuit and an arithmetic circuit. The arithmetic circuit includes a first arithmetic unit, which performs calculations on a first period from when the transistor is turned off until the inductor current reaches a predetermined value, based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on.

[0008] To solve the above problems, the power supply circuit of the present invention is a power supply circuit that generates an output voltage based on an AC voltage, comprising: an inductor to which a rectified voltage corresponding to the AC voltage is applied; a transistor that controls the inductor current flowing through the inductor; a first operational circuit that performs calculations on a first period from when the transistor is turned off until the inductor current reaches a predetermined value, based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on; and a drive circuit that turns on the transistor during a second period corresponding to the second voltage and turns the transistor off during the first period. Invention Effects

[0009] This invention provides a technique that enables an AC-DC converter to operate in critical mode even when the values ​​of its components deviate from their rated values. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating an example of the structure of the AC-DC converter 10. Figure 2 This is an example diagram showing the drive signal Vdr and voltage Vcs when the resistance is 30-33 ohms and the resistance is at its rated value. Figure 3 This is an example diagram showing the drive signal Vdr and voltage Vcs when the resistance value of resistors 30 to 33 deviates from the rated value. Figure 4 This is a diagram illustrating an example of the structure of the power factor improvement IC24. Figure 5 This is a diagram showing an example of the structure of the first operational circuit 44. Figure 6 This is a diagram used to illustrate the operation of the first operational circuit 44. Figure 7 is a flowchart showing the operation of the power factor correction IC 24. Figure 8 is a diagram showing an example of the drive signal Vdr and the voltage Vcs when the AC-DC converter 10 operates in critical mode. Figure 9 is a diagram showing an example of the configuration of the power factor correction IC 100. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] At least the following matters can be understood from the descriptions in this specification and the accompanying drawings.

[0012] =====PRESENT EMBODIMENT===== Figure 1 is a diagram showing an example of the configuration of an AC-DC converter 10 according to one embodiment of the present invention. The AC-DC converter 10 is a boost chopper type power supply circuit that generates an output voltage Vout of a target level using the AC voltage Vac from a commercial power supply.

[0013] The load 11 is, for example, a DC-DC converter or an electronic device that operates under a DC voltage.

[0014] <Overview of AC-DC Converter 10> The AC-DC converter 10 is configured to include a full-wave rectifier circuit 20, capacitors 21 and 23, a diode 22, a power factor correction IC 24, an NMOS transistor 25, and resistors 26 and 30 to 33.

[0015] The full-wave rectifier circuit 20 performs full-wave rectification on a specified AC voltage Vac, and applies the resulting voltage as a rectified voltage Vin to the capacitor 21 and the inductor L1.

[0016] In addition, the rectified voltage Vin is directly applied to the inductor L1, but it may also be applied to the inductor L1 via an element such as a resistor (not shown), for example. The capacitor 21 is an element that filters the rectified voltage Vin.

[0017] Further, the inductor L1, together with the diode 22, the capacitor 23 and the NMOS transistor 25, constitutes a boost chopper circuit. Therefore, the charging voltage of the capacitor 23 is the DC output voltage Vout.

[0018] The power factor correction IC 24 is an integrated circuit that improves the power factor of the AC-DC converter 10 and controls the switching of the NMOS transistor 25 so that the level of the output voltage Vout reaches a target level. Specifically, the power factor correction IC 24 drives the NMOS transistor 25 based on the inductor current IL flowing through the inductor L1, the rectified voltage Vin, and the output voltage Vout.

[0019] Details about the power factor correction IC24 will be provided later. The power factor correction IC24 has terminals VIN, FB, OUT, CS, and GND. In addition to the five terminals VIN, FB, OUT, CS, and GND mentioned above, the power factor correction IC24 also has other terminals, but these are omitted here for simplicity. Furthermore, the GND terminal is grounded.

[0020] The NMOS transistor 25 is a transistor used to control the power supplied by the AC-DC converter 10 to the load 11. In this embodiment, the NMOS transistor 25 is a MOS (Metal Oxide Semiconductor) transistor, but it is not limited to this. The NMOS transistor 25 can be any transistor capable of controlling power; for example, it could be a bipolar transistor. Furthermore, the gate electrode of the NMOS transistor 25 is connected to the terminal OUT, thereby driving the gate electrode of the NMOS transistor 25 using the drive signal Vdr from the terminal OUT.

[0021] The resistor 26 on the ground side of the NMOS transistor 25 is a component that generates a voltage Vcs corresponding to the inductor current IL when the NMOS transistor 25 is turned on. Furthermore, the voltage Vcs generated across resistor 26 is applied to terminal CS.

[0022] Resistors 30 and 31 form the first voltage divider circuit to divide the rectified voltage Vin and generate the input voltage Vin_l used to switch the NMOS transistor 25. Additionally, the input voltage Vin_l generated at the node connected to resistors 30 and 31 is applied to terminal VIN.

[0023] Resistors 32 and 33 form a second voltage divider circuit that divides the output voltage Vout and generates the feedback voltage Vfb used to switch the NMOS transistor 25. Additionally, the feedback voltage Vfb generated at the node connected to resistors 32 and 33 is applied to terminal FB.

[0024] In addition, the AC-DC converter 10 is equivalent to a "power supply circuit", and the power factor improvement IC24 is equivalent to a "switch control circuit".

[0025] Figure 2 This is a graph showing the relationship between the drive signal Vdr and the voltage Vcs when the resistance is 30-33 ohms and the resistance is at its rated value.

[0026] The following explains the relationship between the period during which the NMOS transistor 25 is turned on (the on-time ton) and the period during which the NMOS transistor 25 is turned off (the off-time tooff). Furthermore, after the on-time ton has elapsed, the power factor correction IC 24 outputs a low-level (L-level) drive signal Vdr from a high-level (hereinafter referred to as "H") drive signal Vdr. Then, after the off-time tooff, the power factor correction IC 24 again outputs an "H" level drive signal Vdr.

[0027] In the AC-DC converter 10, if the current flowing through ton during the conduction period is denoted as current Ion, and the inductance value of inductor L1 is denoted as L, then current Ion can be expressed as follows.

[0028] Ion=Vin / L×ton···(1)

[0029] On the other hand, if the current flowing through toff during the cutoff period is denoted as Ioff, then Ioff can be expressed as follows.

[0030] Ioff=(Vout-Vin) / L×toff···(2)

[0031] When the AC-DC converter 10 is operated in critical mode, the current Ion is equal to the current Ioff. Therefore, according to equations (1) and (2), the cutoff period tooff is expressed as follows.

[0032] toff=ton×Vin / (Vout-Vin)···(3)

[0033] Therefore, as Figure 2 As shown, if the power factor improvement IC24 turns on the NMOS transistor 25 when the inductor current is almost zero, and turns off the NMOS transistor 25 during the toff period shown in Equation (3), then the AC-DC converter 10 operates in critical mode.

[0034] However, in the actual AC-DC converter 10, the rectified voltage Vin and the output voltage Vout are obtained as voltages Vin_1 and Vfb generated by the first voltage divider circuit and the second voltage divider circuit, and the cutoff period toff is calculated as shown in the following formula.

[0035] toff=ton×Vin_l / (Vfb-Vin_l)···(4) In addition, the first voltage divider circuit divides the rectified voltage Vin to reduce it to 1 / N (where N is a positive number), generating a voltage Vin_1. Similarly, the second voltage divider circuit divides the output voltage Vout to reduce it to 1 / N (where N is a positive number), generating a voltage Vfb. The voltage division ratios of the first and second voltage divider circuits are the same. In different cases, the calculation of equation (4) can be adjusted.

[0036] Furthermore, the resistance values ​​of resistors 30 to 33, which constitute the first and second voltage divider circuits, generally deviate from their rated values. For example, if the resistance value of resistor 31 is less than its rated value, the voltage Vin_1 becomes smaller, and the cutoff period tooff calculated according to equation (4) is shorter than the cutoff period tooff calculated according to equation (3). As a result, if... Figure 3 As shown, during the off period toff, the inductor current IL will not drop to zero, and the AC-DC converter 10 will operate in continuous mode.

[0037] Therefore, in the AC-DC converter 10 of this embodiment, a power factor improvement IC24 is provided so that even if the resistance value of resistors 30 to 33 deviates from the rated value, the power factor improvement IC24 enables the AC-DC converter 10 to operate in critical mode.

[0038] "Structure of Power Factor Improvement IC24" Figure 4 This is a diagram illustrating an example of the structure of the power factor improvement IC24. The power factor improvement IC24 is configured to include analog-to-digital converter (ADC) circuits 40-42, an on-time output circuit 43, a first operational circuit 44, and a drive circuit 45.

[0039] In addition, Figure 4 In order to simplify the explanation, in different ways... Figure 1 The terminals are drawn at their designated positions, but the wiring and components connected to each terminal are not shown. Figure 1 and Figure 4 It's the same in the middle.

[0040] In addition, ADC40 converts the voltage Vcs at terminal CS into a digital value and outputs it to the first arithmetic circuit 44.

[0041] ADC41 converts the voltage Vin_1 at terminal VIN into a digital value and outputs it to the first arithmetic circuit 44.

[0042] The ADC42 converts the voltage Vfb at terminal FB into a digital value and outputs it to the first operational circuit 44. Furthermore, the voltages Vcs, Vin_1, and Vfb input to the first operational circuit 44 will be described below as digital values, but will be simply referred to as voltages Vcs, Vin_1, and Vfb.

[0043] During conduction, output circuit 43 outputs the digital value of conduction period ton, which represents the error between voltage Vfb and a reference voltage (not shown) that serves as the reference for the output voltage Vout, which is the target level, to first arithmetic circuit 44 and drive circuit 45.

[0044] The first operational circuit 44 is a circuit that performs calculations on tof_comp during the off-time from when the NMOS transistor 25 is turned off until the inductor current IL is almost zero. Details of this circuit will be described later. "The inductor current IL is almost zero" means that the inductor current IL reaches a current value that is almost zero (e.g., 1mA). Furthermore, for convenience, "almost zero" will be simply referred to as zero below.

[0045] The driving circuit 45 is a circuit that turns on the NMOS transistor 25 during the on-time ton and turns off the NMOS transistor 25 during the off-time toff_comp.

[0046] In addition, ADC41 is equivalent to the "first analog-to-digital conversion circuit", ADC42 is equivalent to the "second analog-to-digital conversion circuit" and ADC40 is equivalent to the "third analog-to-digital conversion circuit".

[0047] Furthermore, voltage Vin_l corresponds to the "first voltage," voltage Vfb corresponds to the "second voltage," and voltage Vcs corresponds to the "third voltage." Additionally, the digital value of voltage Vin_l corresponds to the "first digital value," the digital value of voltage Vfb corresponds to the "second digital value," and the digital value of voltage Vcs corresponds to the "third digital value." Moreover, during conduction, output circuit 43 corresponds to the "output circuit."

[0048] The Structure of the First Operational Circuit 44 Figure 5 This is a diagram illustrating an example of the structure of the first operational circuit 44. The first operational circuit 44 is configured to include a second operational circuit 50, a third operational circuit 51, and a fourth operational circuit 52.

[0049] The first operational circuit 44 is a circuit that performs calculations on the cutoff period tooff_comp from the time the NMOS transistor 25 is turned off until the inductor current becomes zero, based on voltages Vin_l, Vfb, and Vcs.

[0050] By calculating the cutoff period toff_comp during which the inductor current IL becomes zero, the AC-DC converter 10 can be made to operate in critical mode. Additionally, the voltage Vcs is the voltage generated by resistor 26 when the inductor current IL flows through it.

[0051] The following is for reference Figure 6The second operational circuit 50, the third operational circuit 51, and the fourth operational circuit 52 will be described.

[0052] The second operational circuit 50 is a circuit that calculates the cutoff period tooff in tooff_comp based on the voltage Vin_l, the voltage Vfb, and the on-time ton during which the NMOS transistor 25 is turned on. Specifically, the second operational circuit 50 calculates the cutoff period tooff using the above equation (4) based on the on-time ton, the voltage Vin_l, and Vfb from the on-time output circuit 43.

[0053] The third operational circuit 51 is a circuit that calculates the rate of decrease of the inductor current IL when the NMOS transistor 25 is turned off. Specifically, the third operational circuit 51 is as follows: Figure 6 As shown, during the conduction period ton, near the center (ton / 2), the voltage Vcs corresponding to the inductor current IL is acquired at least twice, and the rate of increase of the inductor current IL IL during the conduction period ton, Son, is calculated. Son=[Vcs(ton / 2)-Vcs(ton / 2-Δt)] / (Δt)···(5)

[0054] In addition, Figure 6 In this context, the increase rate Son is equal to the change in voltage Vcs during the conduction period ton, and is therefore represented by the slanted line shown by the solid line. Here, the center of the conduction period ton (ton / 2) corresponds to the "specified timing".

[0055] Then, the third operational circuit 51 calculates the decrease rate Soff of the inductor current IL during the off-time toff using the following formula, based on the on-time ton, the off-time toff calculated by the second operational circuit 50, and the increase rate Son. Additionally, in Figure 6 In this context, the reduction rate Soff is equal to the change in voltage Vcs during the cutoff period tooff, and is therefore represented by the dashed line shown.

[0056] Soff = Son × ton / toff···(6)

[0057] In addition, the third operation circuit 51 calculates the increase rate Son based on the voltage Vcs near the center of the conduction period ton, but it can also calculate the increase rate Son based on the voltage Vcs at a timed interval after a specified period has elapsed since the start of the conduction period ton.

[0058] Among them, calculating the increase rate Son based on the voltage Vcs after a specified period (ton / 2) can suppress the influence of noise when the NMOS transistor 25 is turned on, and is therefore preferred.

[0059] The fourth operational circuit 52 is configured to include an offset operational circuit 60, a period operational circuit 61, and an adder circuit 62. It is a circuit that performs calculations on the cutoff period toff_comp that turns off the NMOS transistor 25 based on the reduction rate Soff.

[0060] The offset calculation circuit 60 is a circuit that calculates the offset value Voffset, which represents the deviation between the inductor current IL and a specified value, based on the inductor current IL at the center (ton / 2) of the conduction period and the increase rate Son.

[0061] Specifically, the offset calculation circuit 60 calculates the offset value Voffset using the following formula based on the value Vcsdet of the voltage Vcs corresponding to the inductor current IL at the center (ton / 2) of the conduction period ton.

[0062] Voffset=Vcsdet-Son×ton / 2···(7)

[0063] The period calculation circuit 61 is a circuit that calculates the offset period toff_offset by dividing the offset value Voffset by the reduction rate Soff. Specifically, the period calculation circuit 61 uses the following formula to calculate the offset period toff_offset.

[0064] toff_offset=Voffset / Soff···(8)

[0065] The adder circuit 62 is a circuit that adds the offset period tooff_offset to the cutoff period tooff calculated by the second arithmetic circuit 50 to calculate the cutoff period tooff_comp. Specifically, the adder circuit 62 uses the following formula to calculate the cutoff period tooff_comp.

[0066] toff_comp=toff+toff_offset···(9)

[0067] In addition, the fourth operation circuit 52 uses the offset operation circuit 60, the period operation circuit 61, and the adder circuit 62 to calculate the cutoff period toff_comp. However, the fourth operation circuit 52 can also calculate the cutoff period toff_comp using the following formula based on the peak value Vcspk and the reduction rate Soff of the inductor current IL.

[0068] toff_comp=Vcspk / Soff···(10)

[0069] In addition, the peak value of the inductor current IL, Vcspk, can be obtained from the value of the final voltage Vcs of ton during the conduction period, or it can be calculated using the following formula.

[0070] Vcspk=Vcsdet+Son×ton / 2···(11)

[0071] Additionally, the cutoff period toff_comp corresponds to the "first period," the conduction period ton corresponds to the "second period," the cutoff period toff corresponds to the "third period," and the offset period toff_offset corresponds to the "fourth period." Furthermore, the case where the inductor current IL is zero is equivalent to the inductor current IL reaching the "specified value."

[0072] "The Operation of Power Factor Improvement IC24" Figure 7 This is a flowchart illustrating the operation of the power factor improvement IC24. Figure 8 This is a diagram illustrating an example of the operation of the power factor improvement IC24.

[0073] The following is for reference Figure 7 and Figure 8 The operation of the power factor improvement IC24 will be explained. exist Figure 8 At time t0, the power factor improvement IC24 outputs a "H" level drive signal Vdr, and the conduction period begins at ton.

[0074] After the conduction period ton begins, the second operation circuit 50 calculates the cutoff period toff using the above formula (4) based on the conduction period ton, voltage Vin_l, and Vfb from the conduction period output circuit 43 (S100).

[0075] After time t0, time t1 is ton / 2. The third operation circuit 51 obtains the value Vcsdet1 of the voltage Vcs corresponding to the inductor current IL and performs calculation on the increase rate Son (S101).

[0076] Then, the third operational circuit 51 calculates the decrease rate Soff using the above equation (6) based on the on-time ton and off-time tooff and the increase rate Son of the inductor current IL when the NMOS transistor 25 is turned on (S102).

[0077] Next, the offset calculation circuit 60 calculates the offset value Voffset using the above formula (7) based on the value Vcsdet1 and the increase rate Son (S103).

[0078] Furthermore, the period calculation circuit 61 uses the above equation (8) to calculate the offset period toff_offset (S104).

[0079] Finally, the adder circuit 62 adds the offset period tooff_offset to the cutoff period tooff and performs an operation on the cutoff period tooff_comp (S105).

[0080] Afterwards, at time t2 after the conduction period ton, the power factor improvement IC24 outputs a "L" level drive signal Vdr, which turns off the NMOS transistor 25 (S106).

[0081] Then, at time t3 after the cutoff period tof_comp, the power factor improvement IC24 outputs a "H" level drive signal Vdr, which turns on the NMOS transistor 25 (S107).

[0082] Additionally, after time t3, the power factor improvement IC24 repeats. Figure 7 The processes S100 to S107 are shown. Then, when the NMOS transistor 25 is turned on by the power factor improvement IC24 outputting a "H" level drive signal Vdr, if the inductor current IL becomes zero, the offset period tof_offset also becomes zero. Therefore, the off-time tof_comp equals the off-time tof, and the AC-DC converter 10 operates in critical mode.

[0083] Therefore, the power factor improvement IC24 in this embodiment assumes that... Figure 8 Even if the inductor current IL when the NMOS transistor 25 is turned on, as shown at time t0, does not become zero, the AC-DC converter 10 can continue to operate in critical mode.

[0084] ===Transformation Examples=== Figure 9 This diagram illustrates an example of the structure of a power factor improvement IC100 that includes digital signal processing (DSP) circuitry. Additionally, Figure 9 In the middle, it is marked with Figure 4 Circuits with the same reference designation and Figure 4 Same.

[0085] The power factor improvement IC100 is configured to include analog-to-digital conversion circuits (ADC) 40-42, on-time output circuit 43, DSP 70, and drive circuit 45.

[0086] The DSP70 is configured to include a memory 80 that stores a program for operating the power factor improvement IC100, and a core circuit 81 that performs calculations for operating the AC-DC converter 10 in critical mode.

[0087] The core circuit 81 implements various functional modules in the DSP 70 by executing programs stored in the memory 80. The core circuit 81 implements a first arithmetic unit 90 for performing operations that cause the AC-DC converter 10 to operate in critical mode.

[0088] Furthermore, detailed descriptions are omitted, but the first arithmetic unit 90 corresponds to the first arithmetic circuit 44 of the power factor improvement IC24 and performs the operations executed by the first arithmetic circuit 44. Figure 7 The various processes are handled. Therefore, when using such a power factor improvement IC100, the AC-DC converter 10 can also operate in critical mode. Furthermore, the memory 80 is equivalent to a "storage circuit", and the core circuit 81 is equivalent to an "operation circuit".

[0089] ===Summary=== The AC-DC converter 10 of this embodiment has been described above. The first operational circuit 44 of the power factor improvement IC 24 calculates the cutoff period tooff_comp from when the NMOS transistor 25 is turned off until the inductor current IL becomes zero, based on the voltages Vin_l, Vfb, and Vcs when the NMOS transistor 25 is turned on. Therefore, even if the resistance values ​​of the circuits 30-33 constituting the first and second voltage divider circuits deviate from their rated values, the power factor improvement IC 24 can enable the AC-DC converter 10 to operate in critical mode.

[0090] The first operational circuit 44 calculates the off-period toff based on the voltages Vin_l and Vfb and the on-period ton, and also calculates the reduction rate Soff, thereby calculating the off-period toff_comp. Thus, without continuously measuring the inductor current IL flowing through ton during the on-period, the inductor current IL flowing through ton during the on-period and the inductor current IL flowing through toff_comp during the off-period can be made substantially equal. Furthermore, the power factor improvement IC 24 enables the AC-DC converter 10 to operate in critical mode. In addition, there is no need to provide an auxiliary winding or a negative detection resistor for detecting the inductor current IL when the NMOS transistor 25 is off.

[0091] The third operational circuit 51 calculates the reduction rate Soff based on the on-time ton, the off-time tooff, and the increase rate Son. Therefore, the reduction rate Soff can be calculated without measuring the inductor current IL when the NMOS transistor 25 is off.

[0092] The third operational circuit 51 calculates the increase rate Son based on the voltage Vcs at ton / 2 during the conduction period ton. Thus, as described above, the decrease rate Soff can be calculated without measuring the inductor current IL when the NMOS transistor 25 is off.

[0093] By detecting the voltage Vcs at ton / 2 during the conduction period, the noise effect of the NMOS transistor 25 during conduction can be suppressed.

[0094] The fourth operational circuit 52 calculates the offset value Voffset, representing the deviation of the inductor current IL from zero, based on the inductor current IL at ton / 2 of the on-time ton and the increase rate Son. It then divides the offset value Voffset by the decrease rate Soff to calculate the offset period toff_offset, and adds the offset period toff to the off-time toff to calculate the off-time toff_comp. Therefore, the offset value Voffset and the off-time toff_comp can be calculated without being affected by the noise when the NMOS transistor 25 is on.

[0095] During the cutoff period, tof_comp can also be calculated based on the peak value Vcspk of the final voltage Vcs during the conduction period.

[0096] During conduction, ton can perform calculations based on the error between the voltage Vfb and the reference voltage Vfb, which represents the voltage Vout when the output voltage reaches the target level.

[0097] The first operational circuit 44 of the power factor improvement IC24 can perform calculations on the cutoff period toff_comp based on the digital values ​​of voltages Vin_l, Vfb, and Vcs.

[0098] The power factor improvement IC24 enables the AC-DC converter 10 to operate in critical mode based on the on-time ton and off-time toff_comp.

[0099] The power factor improvement IC24 can include digital signal processing circuitry. The circuit in this embodiment is preferably used as a power supply circuit.

[0100] The above-described embodiments are provided for ease of understanding of the present invention and are not intended to limit or explain the present invention. Furthermore, modifications or improvements can be made to the present invention without departing from its spirit, and equivalent inventions are also included within the scope of the present invention. Label Explanation

[0101] 10 AC-DC converter 11 Load 20 Full-wave rectifier circuit Capacitors 21 and 23 22 Diode 24, 24a, 100 Power Factor Improvement ICs 25 NMOS transistors 26, 30-33 resistors 40-42 Analog-to-Digital Conversion Circuit (ADC) 43 Output circuit during conduction 44 First Operational Circuit 45. Drive Circuit 50 Second Operational Circuit 51 Third Operational Circuit 52 Fourth Operational Circuit 60 Offset Operation Circuit 61-period operational circuit 62 Adder Circuit 80 Memory 81 Core Circuit 90 First Arithmetic Division.

Claims

1. A switch control circuit for controlling the switching of transistors in a power supply circuit, the power supply circuit comprising: An inductor to which a rectified voltage corresponding to an AC voltage is applied; The power supply circuit, which controls the inductor current flowing through the inductor and generates an output voltage based on the AC voltage, is characterized by comprising: A first operational circuit performs calculations based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on, for a first period from when the transistor is turned off until the inductor current becomes a predetermined value; and A driving circuit that turns on the transistor during a second period corresponding to the second voltage and turns the transistor off during a first period. The first operational circuit includes: A second operational circuit performs calculations on a third period during which the transistor is turned off, based on the first voltage, the second voltage, and the second period during which the transistor is turned on. A third operational circuit calculates the rate of increase of the inductor current when the transistor is turned on based on a third voltage corresponding to the inductor current at a predetermined timing during the second period, and calculates the rate of decrease of the inductor current when the transistor is turned off based on the second period, the third period, and the rate of increase; and A fourth operational circuit that performs calculations on the first period during which the transistor is turned off based on the reduction rate.

2. The switch control circuit as described in claim 1, characterized in that, The specified timing is the timing after a specified period has elapsed since the start of the second period.

3. The switch control circuit as described in claim 1 or 2, characterized in that, The fourth operational circuit includes: An offset calculation circuit calculates an offset value representing the deviation of the inductor current from the predetermined value based on the inductor current and the rate of increase at the predetermined timing. A period calculation circuit that calculates the fourth period by dividing the offset value by the reduction rate; and An adder circuit that adds the fourth period to the third period to perform an operation on the first period.

4. The switch control circuit as described in claim 1 or 2, characterized in that, The fourth operational circuit performs calculations on the first period based on the peak value of the inductor current and the rate of decrease.

5. The switch control circuit as described in claim 1 or 2, characterized in that, It also includes an output circuit that outputs the second period corresponding to the error between the second voltage and a reference voltage that serves as a reference for the output voltage.

6. The switch control circuit as described in claim 1 or 2, characterized in that, Also includes: A first analog-to-digital converter circuit converts the first voltage from a first voltage divider circuit that divides the rectified voltage to generate the first voltage into a first digital value. A second analog-to-digital converter circuit converts the second voltage from a second voltage divider circuit that divides the output voltage to generate the second voltage into a second digital value. as well as A third analog-to-digital converter circuit converts the voltage generated on the resistor on the ground side of the transistor into a third digital value.

7. The switch control circuit as described in claim 1 or 2, characterized in that, The specified value is used to make the power supply circuit operate in a critical mode.

8. A switch control circuit for controlling the switching of transistors in a power supply circuit, the power supply circuit comprising: An inductor to which a rectified voltage corresponding to an AC voltage is applied; The power supply circuit, which controls the inductor current flowing through the inductor and generates an output voltage based on the AC voltage, is characterized by comprising: Storage circuits; and Operational circuits The arithmetic circuit includes a first arithmetic unit, which performs calculations based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on, for a first period from when the transistor is turned off until the inductor current becomes a predetermined value. The first arithmetic unit includes: The second arithmetic unit performs calculations on a third period during which the transistor is turned off, based on the first voltage, the second voltage, and a second period during which the transistor is turned on corresponding to the second voltage. A third calculation unit calculates the rate of increase of the inductor current when the transistor is turned on based on a third voltage corresponding to the inductor current at a predetermined timing during the second period, and calculates the rate of decrease of the inductor current when the transistor is turned off based on the second period, the third period, and the rate of increase; and A fourth arithmetic unit performs calculations on the first period during which the transistor is turned off based on the reduction rate.

9. A power supply circuit that generates an output voltage based on an AC voltage, characterized in that it comprises: An inductor to which a rectified voltage corresponding to the AC voltage is applied; A transistor that controls the inductor current flowing through the inductor; A first operational circuit performs calculations on a first period from when the transistor is turned off until the inductor current becomes a predetermined value, based on a first voltage corresponding to the rectified voltage, a second voltage corresponding to the output voltage, and the inductor current when the transistor is turned on. as well as A driving circuit that turns on the transistor during a second period corresponding to the second voltage and turns the transistor off during a first period. The first operational circuit includes: A second operational circuit performs calculations on a third period during which the transistor is turned off, based on the first voltage, the second voltage, and the second period during which the transistor is turned on. A third operational circuit calculates the rate of increase of the inductor current when the transistor is turned on based on a third voltage corresponding to the inductor current at a predetermined timing during the second period, and calculates the rate of decrease of the inductor current when the transistor is turned off based on the second period, the third period, and the rate of increase; and A fourth operational circuit that performs calculations on the first period during which the transistor is turned off based on the reduction rate.

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