Power converter and controller for a power converter and mode of operation thereof

Abstract

A power supply including a power converter having a transformer, a low-side switch configured to draw current from a supply voltage through a primary winding of the transformer, and a high-side switch configured to couple the primary winding of the transformer to a buffer capacitor. A controller is configured to control the power converter by generating drive signals that control opening and closing of the high-side switch and the low-side switch. The controller is configured to selectively control the high-side switch according to various operating modes that depend on operating conditions such as input voltage and load power consumption. The operating modes can include, for example, a mode in which the high-side switch is closed and then opened once in each cycle of a series of switching cycles, and an operating mode in which the high-side switch is closed and then opened twice in each cycle of a series of switching cycles.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 039,728, filed June 16, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of power converters. More specifically, this invention relates to power converters and controllers for power converters. Background Technology

[0003] An offline power supply receives power from an alternating current (AC) source and provides a voltage-regulated direct current (DC) output that can be used to power a load. An exemplary offline power supply includes a power factor correction (PFC) stage and a DC-to-DC power converter stage. The PFC stage receives the AC input signal, performs rectification, and keeps the current drawn from the AC source substantially in phase with the AC voltage, thus making the power supply a resistive load to the AC source. The DC-to-DC converter stage receives the rectified output from the PFC stage and generates a voltage-regulated DC output that can be used to power a load. A voltage rectifier, such as a full-bridge rectifier and a smoothing capacitor, can be used instead of the PFC stage, in which case the DC-to-DC stage can receive the rectified voltage from the voltage rectifier as its input. In either case, the input to the DC-to-DC stage typically has a higher voltage than the output of the DC-to-DC stage, and the regulation is more relaxed.

[0004] A flyback power converter (or more simply, a flyback converter) can be used in DC-DC power converters. A flyback converter uses a transformer that transfers energy from its input to its output and provides electrical isolation between the input and output. By closing a switch, an input voltage, such as the rectified output voltage of a PFC stage or rectifier, is applied across the primary winding of the transformer; as a result, current flows in the primary winding and the magnetic flux in the transformer increases, thus storing energy in the transformer. When the switch is opened, the voltage is removed, and the primary winding current decreases, while the magnetic flux decreases. As a result, a current is induced in the secondary winding of the transformer. This induced current charges the output capacitor to produce the output voltage used to power the load.

[0005] Power supplies can withstand a variety of input voltages and load conditions. Importantly, such power supplies must operate efficiently to minimize power consumption. Therefore, an improved technology for power supplies is needed that adapts to different operating conditions and achieves efficient operation. This technology is further needed for power supplies employing flyback power converters. Summary of the Invention

[0006] According to one embodiment, a power supply includes a power converter with a transformer, a low-side switch configured to draw current from a power supply voltage through the primary winding of the transformer, and a high-side switch configured to couple the primary winding of the transformer to a snubber capacitor. A controller is configured to control the power converter by generating a drive signal that controls the opening and closing of the high-side and low-side switches. The controller is configured to selectively control the high-side switch according to various operating modes depending on operating conditions such as input voltage and load power consumption. Operating modes may include, for example, a mode in which the high-side switch closes and then opens once in each cycle of a series of switching cycles, and an operating mode in which the high-side switch closes and then opens twice in each cycle of a series of switching cycles.

[0007] These and other embodiments are disclosed herein. Attached Figure Description

[0008] The invention has been described with reference to specific exemplary embodiments thereof, and reference is made accordingly to the accompanying drawings, wherein:

[0009] Figure 1 A schematic block diagram of a two-stage, offline power supply according to an embodiment of the present invention is shown;

[0010] Figure 2 A flyback converter suitable for DC-DC converters according to an embodiment of the present invention is shown;

[0011] Figure 3 The voltage waveform of a flyback converter in a high-line, light-load operating mode (also referred to herein as the "first" operating mode) according to an embodiment of the present invention is shown.

[0012] Figure 4 The voltage waveform of the flyback converter in an alternative high-line, light-load operating mode (also referred to herein as the "second" operating mode) according to an embodiment of the present invention is shown.

[0013] Figure 5 The voltage waveform of the flyback converter in another alternative high-line, light-load operating mode (also referred to herein as the "combined" first and second operating modes) according to an embodiment of the present invention is shown.

[0014] Figure 6 The voltage waveform of the flyback converter in yet another alternative high-line, light-load operating mode (also referred to herein as the "third" operating mode) according to an embodiment of the present invention is shown.

[0015] Figure 7 The voltage waveform of a flyback converter in a high-line, heavy-load operating mode (also referred to herein as the "first" operating mode) according to an embodiment of the present invention is shown.

[0016] Figure 8 The voltage waveforms of the flyback converter in alternative high-line, heavy-load operating modes (also referred to herein as "combined" second and third operating modes) according to embodiments of the present invention are shown.

[0017] Figure 9 The voltage waveform of a flyback converter in a low-line, light-load operating mode (also referred to herein as the "third" operating mode) according to an embodiment of the present invention is shown.

[0018] Figure 10 The voltage waveforms of a flyback converter in alternative low-line, light-load operating modes (also referred to herein as "combined" first and second operating modes) according to an embodiment of the invention are shown.

[0019] Figure 11 The voltage waveforms of a flyback converter in an alternative low-line, light-load operating mode (also referred to herein as a “combined” second and third operating modes) according to an embodiment of the invention are shown.

[0020] Figure 12 The voltage waveform of a flyback converter in a low-line, heavy-load operating mode (also referred to herein as the "third" operating mode) according to an embodiment of the present invention is shown.

[0021] Figure 13 A graph showing the relationship between the switching frequency and input power of a flyback converter according to an embodiment of the present invention is shown.

[0022] Figure 14 A flyback converter and control circuit according to an embodiment of the present invention are shown;

[0023] Figure 15 A controller integrated circuit for a DC-DC converter according to an embodiment of the present invention is shown;

[0024] Figure 16 A high-side driver control circuit for a flyback converter according to an embodiment of the present invention is shown;

[0025] Figure 17 A low-side driver control circuit for a flyback converter according to an embodiment of the present invention is shown;

[0026] Figure 18 A differential signal converter in a control circuit for a flyback converter according to an embodiment of the present invention is shown;

[0027] Figure 19 An oscillator in a control circuit for a flyback converter according to an embodiment of the present invention is shown;

[0028] Figure 20 A comparator in a control circuit for a flyback converter according to an embodiment of the present invention is shown; and

[0029] Figure 21 A timer in a control circuit for a flyback converter according to an embodiment of the present invention is shown. Detailed Implementation

[0030] This invention relates to power converters and controllers for power converters, as well as their operation. The converter can be, for example, a flyback power converter used in offline switching power supplies. According to an embodiment of the invention, the power converter employs two synchronously operating transistor switches on the primary side of a transformer. The first of the transistor switches couples the primary winding of the transformer to a ground node and is referred to herein as the "low-side" switch. The second of the two transistor switches couples the primary winding of the transformer to the input supply voltage via a snub capacitor and is referred to herein as the "high-side" switch. The switching (i.e., opening and closing) of the low-side switch is controlled in a feedback loop to generate a regulated DC output voltage on the secondary side of the transformer. To maximize the efficiency of the power converter, the switching of the high-side switch is controlled, for example, synchronously with the low-side switch. Herein, efficiency refers to the transfer of power from the input of the power converter to its output.

[0031] According to an embodiment of the present invention, a controller for a power converter is provided. The controller is configured to control a power converter having a transformer, a low-side switch, and a high-side switch. The low-side switch draws current from the input power supply voltage through the primary winding of the transformer. When the low-side switch is open, energy from the primary winding of the transformer is transferred to a snubber capacitor through the high-side switch. The high-side switch can also be used to discharge the snubber capacitor. The controller controls the opening and closing of the low-side and high-side switches to generate an regulated output voltage.

[0032] According to an embodiment of the present invention, the low-side switch typically operates under the following conditions: (1) frequency control mode, wherein the switching frequency is controlled in the frequency control mode feedback loop to adjust the output voltage; (2) current control mode, wherein the peak current in the primary winding of the transformer for each switching cycle is controlled in the current control mode feedback loop to adjust the output voltage.

[0033] According to an embodiment of the invention, the high-side switch operates in a manner that is normally synchronized with the low-side switch, although this synchronization can occur at any time according to one of several synchronization operation modes. In some cases, the high-side switch may be temporarily disabled (i.e., kept open or "closed"). A voltage (V) is generated at the node between the low-side and high-side switches. L In each switching cycle, after the low-side switch opens, V LThe level will rise, and then V L The level will eventually decrease from its peak.

[0034] According to an embodiment of the first operating mode of the high-side switch, when the voltage V L The high-side switch closes when the voltage rises to and equals or is very close to the voltage level on the buffer capacitor. This voltage level on the buffer capacitor is typically related to the input voltage V. IN The voltage level plus the voltage V across the buffer capacitor CSN The voltage levels are the same. Closing the high-side switch discharges the buffer capacitor. When V... L The level drops to V IN When the voltage level is [value missing], the high-side switch can be opened. This indicates that the buffer capacitor has discharged.

[0035] According to an embodiment of the second operating mode of the high-side switch, at voltage V L After the voltage has dropped from its peak and is equal to or very close to the voltage level on the buffer capacitor, the high-side switch closes, and the voltage level on the buffer capacitor is typically equal to the input voltage V. IN The voltage level plus the voltage V across the buffer capacitor CSN The voltage levels are the same. Closing the high-side switch discharges the buffer capacitor. When V... L The level drops to V IN When the voltage level is [value missing], the high-side switch can be opened. This indicates that the buffer capacitor has discharged. Both the first and second operating modes can be performed with the high-side switch operating under zero-volt switching conditions. Compared to the second operating mode, the high-side switch closes earlier in each switching cycle in the first operating mode. This is because in the first operating mode, when the high-side switch closes, V [value missing]. L The voltage level rises, and in the second operating mode, when the high-side switch is closed, V L The level decreases from its peak value.

[0036] According to the alternative to the second operating mode of the high-side switch, V is first allowed before the high-side switch is closed. L The voltage level oscillates for one or more oscillation cycles. Similar to the second operating mode described above, when the voltage V... L When the voltage level is equal to or very close to the voltage level across the buffer capacitor, the high-side switch closes, and the voltage level across the buffer capacitor is typically equal to the input voltage V. IN The voltage level plus the voltage V across the buffer capacitor CSN The level of V. L The level drops to V IN When the voltage level is 0, the high-side switch can be turned off, indicating that the buffer capacitor has been discharged.

[0037] The switching power supply can be operated, for example, under the following conditions for operating the high-side switch: according to a first operating mode; according to a second operating mode; or according to both the first and second operating modes simultaneously. When both the first and second operating modes are executed simultaneously, while the low-side switch remains open, the high-side switch closes and then opens, then closes and then opens again. In other words, for each cycle of the low-side switch, the high-side switch cycles on and then off twice.

[0038] According to an embodiment of the third operating mode of the high-side switch, at least the disconnection of the high-side switch does not reference or respond to V. L Under the condition of monitoring the voltage level, the high-side switch is closed and then opened. In this operating mode, when the voltage V... L The high-side switch can be closed when the voltage level is equal to or very close to that on the buffer capacitor. However, the high-side switch can then be opened in response to a level transition of a pulse of fixed or adjustable duration, regardless of V. L The pulse is generated during the low-side switch closure in each switching cycle. The precise timing of the pulse signal generation and duration can be controlled by the power supply controller. For example, this third operating mode can be entered when the input voltage of the flyback converter drops below a predetermined input voltage threshold or under light load conditions. Alternatively, in another operating mode of the high-side switch, the high-side switch remains open or off, while the body diode of the high-side switch transistor performs passive rectification. This operating mode can also be entered, for example, when the input voltage of the flyback converter drops below a predetermined input voltage threshold or under light load conditions.

[0039] The switching power supply can be operated, for example, under the following conditions for operating the high-side switch: according to a first operating mode; according to a second operating mode; according to a third operating mode; or according to a combination of multiple operating modes. When two operating modes are executed together (e.g., the first and second modes or the second and third modes), while the low-side switch remains open, the high-side switch closes and then opens, then closes and then opens again. In other words, for each cycle of the low-side switch, the high-side switch cycles on and then off twice.

[0040] The term "Continuous On-Mode" or "CCM" refers to the continuous flow of current in the primary winding of a power converter's transformer throughout consecutive switching cycles. The term "Discontinuous On-Mode" or "DCM" refers to a period within each switching cycle (i.e., the "dead zone") during which the current in the primary winding of the transformer is allowed to drop to zero. The term "Critical On-Mode" or "CRM" refers to operation at or near the boundary between CCM and DCM operating modes. In other words, during CRM, the current in the primary winding is allowed to drop to zero just before it rises again.

[0041] Operation in a CRM is useful during high-load conditions to achieve high efficiency. However, as the load decreases, the current level in the primary winding required to maintain the regulated output voltage also decreases. As a result, operation at lower load levels tends to revert to DCM (Direct Current Management). The level of the input voltage also affects operation. For example, when the input voltage is higher, the "dead time" duration in the DCM tends to increase, while when the input voltage is lower, the "dead time" duration in the DCM tends to decrease. The input voltage level can vary depending on the level of the AC line voltage. For example, different countries use different AC line voltage levels as their respective standards. The load also affects the input voltage level. For example, an increase in current drawn from the AC power supply will decrease its voltage level.

[0042] In one embodiment, under light load conditions, the switching power supply is operated according to the DCM (Distributed Control Mode). Under light load conditions, the switching power supply can be operated in the frequency control mode feedback loop to adjust the output voltage. Alternatively, under light load conditions, the high-side switch can be operated, for example, according to a first operating mode of the high-side switch, or according to a second operating mode of the high-side switch, or according to both the first and second operating modes of the high-side switch (the first and second modes can operate together), or according to the second and third operating modes of the high-side switch (the second and third modes can operate together).

[0043] In this embodiment, under heavy load conditions, the switching power supply is operated according to CRM. Under heavy load conditions, the switching power supply can operate in a current control mode feedback loop to adjust the output voltage. Alternatively, under heavy load conditions, the high-side switch can be operated, for example, according to a second operating mode, a third operating mode, or both a first and a second mode of the high-side switch (the first and second modes can operate simultaneously).

[0044] In one embodiment, under transitional load conditions where the load level is between light and heavy load conditions, the switching power supply preferably switches its operation between a frequency control mode feedback loop with hysteresis and a current control mode feedback loop. Furthermore, under transitional load conditions, the switching power supply can operate in either DCM or CRM. This can also be based on hysteresis, such that operation under transitional load conditions can depend on whether the power supply operates in DCM or CRM just before operating under transitional load conditions. Similarly, under transitional load conditions, the high-side switch is preferably operated according to one or more operating modes of the high-side switch, wherein the high-side switch operates just before entering operation under transitional load conditions.

[0045] Figure 1 A schematic block diagram of a two-stage, offline power supply 100 according to an embodiment of the present invention is shown. Figure 1As shown, the first stage 102 has an input coupled to an AC source. The first stage 102 performs rectification on the AC input signal. The first stage 102 can also perform power factor correction (PFC), in which case the first stage 102 also keeps the current drawn from the AC source substantially in phase with the AC voltage, so that the power supply 100 behaves as a resistive load on the AC power supply. The PFC stage can be replaced by a voltage rectifier, such as a full-bridge rectifier and a smoothing capacitor.

[0046] The first stage 102 generates a loosely regulated voltage V. DC This voltage is supplied as input to the DC-to-DC converter 104. Using input power supply V... DC The DC-to-DC converter stage 104 generates a voltage-regulated DC output V. O It can be used to power a load. V DC The level is preferably at a level higher than the output V of the DC-to-DC converter stage 104. O A higher voltage is applied and is more loosely regulated. The output V of the first stage 102 DC The nominal level can be, for example, approximately 380 volts DC, while the voltage-regulated output V of the DC-to-DC converter stage 104 is... O This could be, for example, approximately 15.0 volts of DC. Input voltage V AC Different voltage levels and frequencies are possible, depending on availability. For example, in the United States, 120 volts at 60 Hz is typically available, while in China, 220 volts at 50 Hz is typically available.

[0047] Figure 2 A flyback converter 150 according to an embodiment of the present invention is shown. The flyback converter 150 is suitable for DC-to-DC converters in switching power supplies, such as... Figure 1 DC-to-DC converter 104. Flyback converter 150 from power supply V. IN Receive input voltage, power supply V IN It can be the output of a rectifier or the output of a PFC stage. DC It may be received from other sources, such as electromagnetic interference (EMI) filters.

[0048] like Figure 2 As shown, the input voltage source V IN Coupled to capacitor C SN The first terminal of capacitor C is the first terminal of the primary winding of transformer T1. SN Used as a buffer capacitor. In capacitor C SN Both ends form as Figure 2 The voltage V shown has polarity CSNThe second terminal of the primary winding of transformer T1 is coupled to the first terminal of switch SW1 (“low-side” switch) and the first terminal of switch SW2 (“high-side” switch). A voltage V is formed at the node between the low-side switch SW1, the high-side switch SW2, and the second terminal of the primary winding of transformer T1. L The second terminal of switch SW1 is coupled to the first ground node. The second terminal of switch SW2 is coupled to capacitor C. SN The second terminal. Switch SW1 is controlled by the LOWOUT signal, while switch SW2 is controlled by the HIGHOUT signal.

[0049] The low-side switch SW1 and the high-side switch SW2 are each preferably implemented by a corresponding power MOSFET. Therefore, the body diode associated with each of the switches SW1 and SW2 is shown.

[0050] The first terminal of the secondary winding of transformer T1 is coupled to the anode of Zener diode D1. The cathode of diode D1 is coupled to the first terminal of capacitor C1. The second terminal of the secondary winding of transformer T1 is coupled to the second terminal of capacitor C1 and also coupled to a second grounding node. The first grounding node and the second grounding node are preferably electrically isolated from each other.

[0051] The flyback converter 150 is operated by opening and closing switches SW1 and SW2. Transformer T1 transfers energy from the input of the flyback converter 150 to its output and provides isolation between the input and output of the flyback converter 150. In operation, when switch SW1 is closed (switch "on"), voltage source V... IN An electric current is applied across the primary winding of transformer T1. As a result, the current in the primary winding and the magnetic flux in transformer T1 increase, thereby storing energy in transformer T1. Then, when switch SW1 is opened (turning the switch to "off"), the current and magnetic flux in the primary winding decrease. As a result, a current is induced in the secondary winding of transformer T1, which charges capacitor C1 to generate an output voltage V for supplying power to the load. O .

[0052] The level of power delivered to the load can be controlled by adjusting the switching duty cycle of switch SW1 (e.g., by controlling the peak input current), the switching frequency of switch SW1, or both. Controlling the duty cycle is referred to herein as peak current control, while controlling the switching frequency is referred to herein as frequency control.

[0053] When switch SW1 is open and switch SW2 is closed (switch SW2 is "on"), the current in the primary winding of transformer T1 can reach the buffer capacitor C through switch SW2. SNAlternatively, when switch SW1 is open and switch SW2 is in the open position (switch SW2 is "off"), the current in the primary winding of transformer T1 can reach the buffer capacitor C through the body diode of switch SW2. SN According to the buffer capacitor C SN Compared to V L The voltage level is such that closing switch SW2 can also affect the buffer capacitor C. SN Discharge is performed.

[0054] In a typical switching cycle, the high-side switch SW2 is preferably controlled such that when the low-side switch SW1 is closed (conducting), the high-side switch SW2 is open (off). Then, when switch SW1 is open (off) and energy from transformer T1 is transferred to output capacitor C1, voltage V... L It will become equal to or almost equal to the capacitor C. SN The voltage at the point. Under these conditions, switch SW2 can be briefly closed (conducted). Therefore, switch SW2 can operate under zero-volt switching (ZVS) conditions. Closing switch SW2 will make V L The level is equal to V IN +V CSN The level. Then, once V L and V IN +V CSN If the voltages are essentially equal, then switch SW2 can be turned off. After switch SW2 is turned off, the voltage V... L The voltage drop is such that when switch SW1 is closed, the voltage across it can be zero or near zero. Therefore, switch SW1 can also operate under zero-volt switching (ZVS) conditions. This cycle is then repeated. As mentioned above, operating switches SW1 and SW2 according to ZVS may be advantageous, but it is not always necessary.

[0055] In summary, during a typical switching cycle, the low-side switch SW1 is turned off; then, before turning the low-side switch SW1 back on, the high-side switch SW2 is turned on and then turned off. This cycle is then repeated (i.e., SW1 off, SW2 on, SW2 off, SW1 on, SW1 off, ...). Therefore, before each low-side switch SW1 turn-on event, the high-side switch SW2 is turned on and then turned off once (or twice, as described herein). Similarly, for each cycle of the low-side switch SW1, the high-side switch SW2 is turned on and then turned off once (or twice) (while the low-side switch SW1 is turned off). In other words, each of the switches SW1 and SW2 is turned on and then off while the other switch is turned off.

[0056] In one embodiment, both switches SW1 and SW2 operate under ZVS. In other embodiments, switches SW1 and SW2 do not operate under ZVS or operate only partially under ZVS. For example, according to an embodiment of the invention, depending on V... IN When the voltage level is reached, the high-side switch SW2 is disconnected. In this case, switch SW2 can be disconnected under non-ZVS conditions because it is at V... L The level is equal to V IN +V CSN Disconnect before or after. In another example, the high-side switch SW2 may disconnect in response to a fixed or adjustable duration pulse signal, as described in more detail here; in this case, switch SW2 may not operate exactly as ZVS intended.

[0057] The flyback converter 150 has a resonant switching frequency. The resonant frequency depends on the physical characteristics of the flyback converter 150, including the inductance of the primary winding of transformer T1 and the parasitic capacitances of switches SW1 and SW2. When switch SW2 is closed, this introduces a snubber capacitor C. SN The capacitance effectively changes the instantaneous resonant frequency of the flyback converter 150 when switch SW2 is closed.

[0058] The diode D1, coupled to the secondary winding of transformer T1, functions as a freewheeling diode, allowing current in the secondary winding of transformer T1 to charge capacitor C1 and preventing capacitor C1 from discharging through transformer T1. Diode D1 can alternatively be replaced by a switch (synchronous rectification) that operates synchronously with switches SW1 and SW2.

[0059] Depending on the operating conditions, the switching can be performed according to various operating modes, particularly the switching of the high-side switch SW2. These operating conditions can include, for example, input voltage and load. In this embodiment, the AC input voltage can be divided into two ranges: "high" and "low". In this case, a 220-volt AC input can be considered to be in the "high" range (here, the "high" range is also referred to as the "high line"), while a 120-volt AC input can be considered to be in the "low" range (the "low" range is also referred to herein as the "low line"). The dividing line between the low input voltage range and the high input voltage range can be between 120 and 220 volts AC (e.g., approximately 170 volts AC). Similarly, the load can be divided into two ranges: "light" and "heavy". Load refers to the power level required by the load to which the power supply provides power. The power supply described herein can provide power to loads with multiple power demands, including loads that may require different power levels at different times.

[0060] In summary, variations in input voltage and load power operating conditions can result in at least four distinct possible operating “regions”: (1) high line and light load; (2) high line and heavy load; (3) low line and light load; and (4) low line and heavy load. By changing the operating mode in response to these operating conditions, the efficiency of the power supply can be improved. While two ranges for input voltage and load power have been described, other ranges can obviously be provided. For example, the load could be “light,” “medium,” and “heavy,” rather than just light and heavy load. Similarly, one or more additional ranges can be provided for the input voltage. As explained herein, transitional “regions” of operation can also be provided to allow for transitions between the aforementioned operating regions.

[0061] Figure 3 The voltage waveform of a flyback converter in a high-line, light-load operating mode (also referred to herein as the "first" operating mode) according to an embodiment of the present invention is shown. This waveform represents V for two switching cycles. L Level. For example... Figure 3 As shown, switch SW1 is closed (conducted) at time t0, causing V L The voltage level is essentially zero volts. This causes current to flow in the primary winding of transformer T1, which infuses energy into the primary winding of transformer T1. Then, at time t1, switch SW1 is opened (turned off). As a result, V L The level rose rapidly to above V IN The current can then flow through the body diode of switch SW2, while the energy from transformer T1 induces a current in the secondary winding of transformer T1, which charges the output capacitor C1. Then, when the voltage V... L Rise and equal to V IN +V CSN or almost equal to V IN +V CSN At time t2, switch SW2 closes (conducts). This tends to cause V to... L The level and V IN +V CSN The voltage levels are equal, thus causing capacitor C to... SN Discharge. Then, at time t3, switch SW2 is opened (turned off). When V L The level is equal to or almost equal to V. IN When the voltage V is at a certain level, switch SW2 can be opened. Then, the voltage V... L The voltage drops, then rises again, oscillating according to the resonant frequency of the primary side of the converter. And, at time t4, switch SW1 closes (conducts). This causes V to... LThe voltage level drops to zero volts, and the switching cycle described above is repeated. As mentioned above, since the voltage across switch SW2 is zero or close to zero when it is closed and open, the high-side switch SW2 essentially operates under ZVS.

[0062] exist Figure 3 The waveform of the signal "READYHIGHON" is also shown. In embodiments of the invention, the READYHIGHON signal must be a logic high voltage for switch SW2 to close. Therefore, the period during which the READYHIGHON signal is a logic high voltage is a "window" of time during which the high-side switch SW2 can close. In other words, the READYHIGHON signal provides "permission" for switch SW2 to close. As described herein, the READYHIGHON signal can be used to determine the operating mode of switch SW2. Figure 3 As shown, the READYHIGHON level is initially a logic low voltage, meaning that switch SW2 is not permitted to close. However, during the time interval t1 and t2, the READYHIGHON level transitions to a logic high voltage, which permits switch SW2 to close. As mentioned above, when voltage V... L equals V IN +V CSN At time t2, switch SW2 closes. Then, at time t3, switch SW2 opens. Shortly after time t3, the READYHIGHON signal transitions to a logic high voltage.

[0063] Figure 4 The voltage waveform of the flyback converter in an alternative high-line light-load operating mode (also referred to herein as the "second" operating mode) according to an embodiment of the invention is shown. Figure 4 The waveform represents V over two switching cycles. L Level. For example... Figure 4 As shown, switch SW1 is initially closed (conducted) at time t0, causing V L The voltage level is essentially zero volts. This causes current to flow in the primary winding of transformer T1, which infuses energy into the primary winding of transformer T1. Then switch SW1 is turned off at time t1. As a result, V L The level rose rapidly to above V IN The current can then flow through the body diode of switch SW2, while the energy from transformer T1 induces a current in the secondary winding of transformer T1, which charges the output capacitor C1. Then, the voltage V... L The oscillation can begin based on the resonant frequency of the converter. Then, when the voltage V... L Decrease and equal to V IN +V CSN or almost equal to V IN+V CSN At time t2, the high-side switch SW2 is briefly closed (conducted). This causes V L The level and V IN +V CSN The voltage levels are equal, thus causing capacitor C to... SN Discharge. Then at time t3, when V L Equal to or close to V IN At time t4, switch SW2 is open (off). And at time t4, switch SW1 closes again (on). This causes V... L The voltage level drops to zero volts, while current flows in the primary winding of transformer T1, and the switching cycle repeats.

[0064] Because when switch SW2 is closed, the voltage V L Preferably equal to or close to V IN +V CSN Therefore, switch SW2 can be closed under zero-volt switching (ZVS) conditions. Furthermore, since the voltage V is constant when switch SW2 is open... L Equal to or close to V IN Therefore, switch SW2 can be disconnected under ZVS conditions. By controlling the high-side switch SW2 synchronously with ZVS, more efficient operation can be provided by avoiding losses caused by non-ZVS switching, for example, and higher switching frequencies can be allowed, which also tends to improve the efficiency of flyback converters.

[0065] exist Figure 4 The waveform of the READYHIGHON signal is also shown. Figure 3 on the contrary, Figure 4 The READYHIGHON signal until V L The level rises to above V IN +V CSN Switch SW2 is only allowed to close after the voltage level has reached and started oscillating. More specifically, in Figure 4 In the above, the READYHIGHON voltage level transitions to logic high just before time t2, and then transitions to logic low shortly after time t3. Therefore, by comparing with Figure 3 The activation of the delayed signal READYHIGHON, and Figure 3 (It shows "first mode") Compared to this, this causes switch SW2 to... Figure 4 The switch closes later in the switching cycle (as in "second mode"). However, in Figure 3 and Figure 4 Within the time "window" provided by the READYHIGHON signal, the precise timing of closing and opening switch SW2 depends on monitoring V. L The level is used to maintain ZVS.

[0066] Figure 4 The V shown L The waveform assumes that the closing of switch SW2 is delayed, causing voltage V L It tends to oscillate. More specifically, Figure 4 The diagram shows two oscillations that occur before switch SW2 is closed at time t2. In this paper, this is referred to as the "valley switch". It is obvious that as long as V... L Equal to or almost equal to V IN +V CSN By closing switch SW2 at the specified time, more or less oscillation can occur while maintaining a zero-volt switch. For example, once the voltage V drops... L First, it equals V. IN +V CSN , or almost equal to V IN +V CSN This allows switch SW2 to be closed. In this paper, this is referred to as a "quasi-resonant" or "first-mound" switch. In either case, if V... L Equal to or almost equal to V IN +V CSN By closing switch SW2 at the specified time, zero-volt switching can be maintained. To adjust the output voltage, the flyback converter 150 can selectively operate according to quasi-resonant switching or valley switching based on conditions such as switching frequency, load conditions, and component values. These possibilities can be achieved by adjusting the timing of the level transition of the READYHIGHON signal.

[0067] Figure 5 The voltage waveform of a flyback converter operating in an alternative high-line, light-load operating mode (also referred to herein as “combined” first and second operating modes) according to an embodiment of the invention is shown. Figure 5 The waveform represents V over two switching cycles. L Level. For example... Figure 5 As shown, switch SW1 is initially closed (conducting) at time t0, therefore V L The voltage level is essentially zero volts. This causes current to flow in the primary winding of transformer T1, which infuses energy into the primary winding of transformer T1. Then, at time t1, switch SW1 is opened (turned off). As a result, V L The level rose rapidly to above V IN The level. Then, when the voltage V L Rise and equal to V IN +V CSN or almost equal to V IN +V CSN At time t2, switch SW2 closes (conducts). This causes V to... L The level and VIN +V CSN The voltage levels are equal, thus making the capacitor... CSN Discharge. Then, at time t3, switch SW2 is opened (turned off). When V L The level is equal to V IN When the voltage V is at a certain level, switch SW2 can be opened. Then, the voltage V... L The frequency decreases, then increases again, oscillating according to the resonant frequency of the primary side of the converter. Therefore, when switch SW1 is closed, switch SW2 operates according to the combination described above. Figure 3 The first operating mode is used for operation.

[0068] Reference Figure 5 After switch SW2 is closed (at time t2) and then opened (at time t3), V L The level drops, and then it may begin to oscillate. When V... L The level drops and is equal to or very close to the voltage V. IN +V CSN If so, then switch SW2 can be closed a second time within the same switching cycle. This is shown in... Figure 5 At time t4 in the diagram. Then, within the same switching cycle, switch SW2 can be turned off a second time. As shown at time t5 in the diagram, V at this time... L The level is equal to V IN The level. Therefore, the second cycle of switch SW2 can be based on the second operating mode of switch SW2, as described above. Figure 4 As described above, the second cycle of the high-side switch SW2 occurs while the low-side switch SW1 remains open. Therefore, during each switching cycle of the low-side switch SW1, the high-side switch SW2 closes and opens twice.

[0069] Figure 5 The signal waveform for the READYHIGHON signal is also shown. This waveform illustrates two time windows in which switch SW2 is permitted to close during each switching cycle. Figure 3 As shown, the first window begins when the READYHIGHON signal transitions to a logic high voltage shortly before time t2, and ends when the READYHIGHON signal transitions to a logic low voltage shortly after time t3. This first window is related to... Figure 3 The window size is equivalent to the first window. The second window begins when the READYHIGHON signal transitions to logic high shortly before time t4. The first window ends when the READYHIGHON signal transitions to logic low shortly after time t5. This second window is equivalent to the first window. Figure 4 The window size is quite large. Therefore, as... Figure 5As shown in the two time windows, during each switching cycle of the low-side switch SW1, switch SW2 is permitted to close and open twice. Furthermore, the precise timing of each of these two cycles of switch SW2 within each window can be based on monitoring V. L Therefore, ZVS can be maintained in two cycles.

[0070] Figure 5 The voltage waveform shows the valley switching operation of switch SW2 when it is closed for the second time in each switching cycle. Figure 5 The diagram shows five oscillations that occurred before switch SW2 was closed. It is evident that more or fewer oscillations may have occurred before switch SW2 was closed. For example, in the case of two oscillations, switch SW2 could behave as follows: Figure 3 The area is closed as shown. According to... Figure 5 In one embodiment, during the portion of each switching cycle during which the low-side switch SW1 remains open, the high-side switch SW2 closes and opens twice. The high-side switch SW2 can be V L The first close occurs when the voltage level rises, and it can be closed at V. L The voltage level drops from its peak and then closes for the second time. Alternatively or additionally, the high-side switch SW2 can be closed at V. L The level oscillation first closes before one or more cycles, and can be in V L The signal oscillates at a certain level before closing a second time. These possibilities can be achieved by adjusting the timing of the level transition of the READYHIGHON signal.

[0071] like Figure 5 As shown, at time t5, switch SW1 is closed (conducting). This causes V L The voltage level drops to zero volts, and current flows back to the primary winding of transformer T1. Then the switching cycle repeats.

[0072] Figure 6 The voltage waveform of the flyback converter in an alternative high-line light-load operating mode (referred to herein as the "third" operating mode) according to an embodiment of the invention is shown. The third operating mode is somewhat similar to the first operating mode of the high-side switch SW2 (which in... Figure 3 (As shown in the diagram), because the high-side switch SW2 can be closed in a similar manner. However, in the third operating mode, the high-side switch SW2 is opened without reference or monitoring of V. L The level. In this operating mode, when the low-side switch SW1 remains closed, the high-side switch can be opened in response to a level transition of a fixed or adjustable duration pulse signal (e.g., the signal READYHIGHON).

[0073] Even more special, it is also Figure 6The signal READYHIGHON shown can be used to precisely control the timing of disconnecting the high-side switch SW2. Figure 3 and Figure 4 The time window for the formation of the READYHIGHON signal differs from that of the signal in V. L The level is equal to V IN The window closes before the READYHIGHON signal. Therefore, when the READYHIGHON signal transitions to logic low, this window closes, causing switch SW2 to immediately open. In other words, the READYHIGHON signal takes precedence over the logic low signal. Figure 3 and Figure 4 China V L With V IN The comparison occurs. Figure 6 In the third operating mode shown, the duration of the high-side switch SW2 closing is adjustable by controlling the duration of the READYHIGHON pulse. Typically, the duration of the high-side switch SW2 closing in this third operating mode is also shorter than the duration of the high-side switch SW2 closing in the first operating mode. Figure 3 ).

[0074] like Figure 6 As shown, the READYHIGHON signal transitions to a logic high voltage shortly before time t2. Then, once V... L The level is equal to or very close to the voltage V. IN +V CSN Then, switch SW2 can be closed. This occurs at time t2. The READYHIGHON signal transitions to a logic low voltage at time t3. This causes the high-side switch SW2 to immediately open at time t3. Therefore, switch SW2 remains closed during the time period between t2 and t3. Figure 6 The duration of the time interval t2-t3 shown can depend on V IN The level. For example, Figure 6 It can represent V IN The highest expected level, for example, 380 volts DC. However, it can be determined based on V. IN The level is used to adjust this time period. For example, when V IN Below 380V DC (e.g., 240V DC), the READYHIGHON level can transition to logic low more quickly, and switch SW2 can turn off more rapidly during the switching cycle, thus shifting time t3 closer to t2 and shortening the duration of the time interval between t2 and t3. The amount of shortening of the time interval t2-t3 can be correlated with V... IN The change in voltage level is proportional.

[0075] As explained in this document, switch SW2 is preferably based on Figure 6 The third operating mode shown is closed under ZVS conditions. However, switch SW2 can be opened under non-ZVS conditions. Opening the high-side switch SW2 under non-ZVS conditions helps to prevent the buffer capacitor C from being used under these conditions. SN ( Figure 2 Full discharge is used to improve efficiency.

[0076] In an alternative to the third operating mode of the high-side switch, the high-side switch SW2 remains off, while the body diode of the high-side switch transistor SW2 still performs rectification. This can be achieved by keeping the READYHIGHON level low throughout the switching cycle.

[0077] In another alternative to the third operating mode, closing the high-side switch SW2 can be done in response to the READYHIGHON signal and in conjunction with V. L The level is independent. This can be achieved by changing V. L The READYHIGHON level must be changed before the high-side switch SW2 is closed.

[0078] Figure 7 The voltage waveform of a flyback converter in a high-line, heavy-load operating mode (also referred to herein as the "first" operating mode) according to an embodiment of the present invention is shown. This waveform represents V for two switching cycles. L Level. For example... Figure 7 As shown, switch SW1 is closed (conducted) at time t0, causing V L The voltage level is essentially zero volts. This causes current to flow in the primary winding of transformer T1, which infuses energy into the primary winding of transformer T1. Then, at time t1, switch SW1 is opened (turned off). As a result, V L The level rose rapidly to above V IN The current can then flow through the body diode of switch SW2, while the energy from transformer T1 induces a current in the secondary winding of transformer T1, which charges the output capacitor C1. Then, when the voltage V... L It has risen to equal V IN +V CSN , or almost equal to V IN +V CSN At time t2, switch SW2 is closed (conducting). This tends to cause V to... L The level and V IN +V CSN The voltage levels are equal, thus causing capacitor C to... SN Discharge. V L The voltage level gradually decreases. Then, at time t3, switch SW2 is turned off. When V... LThe level is equal to or almost equal to V. IN When the voltage V is at a certain level, switch SW2 can be opened. L It continues to decrease at an even faster rate. And, at time t4, switch SW1 closes (conducts). This causes V... L The voltage level drops to zero volts, and current flows again in the primary winding of transformer T1, repeating the aforementioned switching cycle. Although a heavier load may affect V... L The final waveform, but the operation in this mode is different from... Figure 3 The operation is quite similar.

[0079] Figure 7 The diagram shows that the READYHIGHON signal transitions to a logic high voltage shortly before time t2, and then transitions to a logic low voltage shortly after time t3. Therefore, the precise timing of closing and opening the high-side switch SW2 can be achieved by monitoring V... L To determine.

[0080] Figure 8 The voltage waveform of the flyback converter in an alternative high-line, heavy-load operating mode (also referred to herein as the "combined" operating mode) according to an embodiment of the invention is shown. Figure 8 The waveform represents V over two switching cycles. L Level. For example... Figure 8 As shown, switch SW1 is initially closed (conducting) at time t0, therefore V L The voltage level is essentially zero volts. This causes current to flow in the primary winding of transformer T1, which infuses energy into the primary winding of transformer T1. Then, at time t1, switch SW1 is opened (turned off). As a result, V L The level rose rapidly to above V IN The level. Then, when the voltage V L Rise and equal to V IN +V CSN or almost equal to V IN +V CSN At time t2, switch SW2 closes (conducts). This causes V to... L The level and V IN +V CSN The voltage levels are equal, thus causing capacitor C to... SN Discharge. Then, at time t3, switch SW2 is opened (turned off).

[0081] Figure 8 The signal READYHIGHON is also shown. Here, the READYHIGHON signal transitions to a logic high voltage shortly before time t2. This allows monitoring of V... LTo determine the precise timing for closing the high-side switch SW2, SW2 can be turned off based on ZVS. The READYHIGHON signal transitions to a logic low voltage at time t3, causing the high-side switch SW2 to immediately open, in conjunction with V... L The voltage level is independent. Therefore, under non-ZVS conditions, the high-side switch SW2 can be turned off at time t3.

[0082] Voltage V L Then it decreases, then increases again, oscillating according to the resonant frequency of the primary side of the converter. (Refer to...) Figure 8 After switch SW2 is closed (at time t2) and then opened (at time t3), V L The voltage level drops and may also begin to oscillate. Shortly before time t4, the READYHIGHON voltage level transitions to a logic high voltage. When V... L The level drops and is equal to or very close to the voltage V. IN +V CSN If this happens, then switch SW2 can be closed a second time within the same switching cycle. This is in... Figure 8 The time t4 is shown in the figure. Then, within the same switching cycle, switch SW2 can be turned off a second time. This is shown in V in the figure. L The level is equal to V IN The level of READYHIGHON is at time t5. Shortly after time t5, the level of READYHIGHON transitions to a logic low voltage. This second cycle of the high-side switch SW2 occurs while the low-side switch SW1 remains open. Therefore, during each switching cycle of the low-side switch SW1, the high-side switch SW2 is opened and closed twice. As with the third operating mode, the first cycle of the high-side switch SW2 can be terminated by the signal READYHIGHON (rather than by monitoring V). L The second cycle of the high-side SW2 is based on monitoring V. L The signal terminates at a certain level.

[0083] Therefore, similar to Figure 5 , Figure 8 The READYHIGHON signal indicates two time windows in which the enable switch SW2 closes in each switching cycle. The first window begins when the READYHIGHON signal transitions to a logic high voltage shortly before time t2. However, with Figure 5 Unlike other windows, the first window preferably ends when the READYHIGHON signal transitions to a logic low voltage at time t3. This first window is different from... Figure 6The second window (third mode) is equivalent to this. The second window begins when the READYHIGHON signal transitions to logic high shortly before time t4. The first window ends when the READYHIGHON signal transitions to logic low shortly after time t5. This second window is equivalent to... Figure 4 The window (second mode) is equivalent. Therefore, as Figure 8 As shown in the two time windows, during each switching cycle of the low-side switch SW1, switch SW2 is permitted to cycle (i.e., close and open) twice.

[0084] Figure 9 The voltage waveform of a flyback converter in a low-line, light-load operating mode (also referred to herein as "third" operating mode) according to an embodiment of the present invention is shown. This operating mode of the high-side switch SW2 is similar to... Figure 6 The operating modes are quite similar. In this operating mode, the high-side switch SW2 is based on monitoring V. L The voltage level is closed, and then V is not referenced or monitored. L The high-side switch opens in response to a pulse signal of fixed or adjustable duration (e.g., the READYHIGHON signal) while the low-side switch SW1 remains closed. In this operating mode, the high-side switch opens in response to a pulse signal of fixed or adjustable duration (e.g., the READYHIGHON signal). (As in conjunction with...) Figure 6 The exemplary waveform is used to illustrate, Figure 9 The duration of the time interval t2-t3 shown can depend on V IN The level. And, as Figure 9 As shown, the READYHIGHON signal transitions to a logic high voltage just before time t2. The high-side switch SW2 opens at time t2. Then, at time t3, the READYHIGHON signal transitions to a logic low voltage, causing switch SW2 to open immediately. Therefore, switch SW2 can open under non-ZVS conditions.

[0085] In an alternative to this high-side switching operation mode, the high-side switch SW2 remains off, while the body diode of the high-side switching transistor SW2 performs rectification. This can be achieved by maintaining the READYHIGHON signal for the duration of the switching cycle.

[0086] Figure 10 The voltage waveforms of the flyback converter in an alternative low-line, light-load operating mode (also referred to herein as the "combined" first and second operating modes) according to an embodiment of the present invention are shown. This operating mode of the high-side switch SW2 is related to... Figure 5 The operating mode is quite similar. Figure 10 The waveform represents V over two switching cycles. L Level. For example... Figure 10 As shown, switch SW1 is initially closed (conducting) at time t0, therefore VL The voltage level is essentially zero volts. This causes current to flow in the primary winding of transformer T1, which infuses energy into the primary winding of transformer T1. Then, at time t1, switch SW1 is opened (turned off). As a result, V L The level rose rapidly to above V IN The level. Then, when the voltage V L Rise and equal to V IN +V CSN or almost equal to V IN +V CSN At time t2, switch SW2 closes (is on). This causes V L The level and V IN +V CSN The voltage levels are equal, thus making capacitor C SN Discharge. Then, at time t3, switch SW2 is opened (turned off). When V L The level is equal to V IN When the voltage V is at a certain level, switch SW2 can be opened. Then, the voltage V... L It drops, then rises again, and oscillates according to the resonant frequency of the primary side of the converter.

[0087] After switch SW2 is closed (at time t2) and then opened (at time t3), V L The level drops and may also begin to oscillate. When V L The level drops and is equal to or very close to the voltage V. IN +V CSN If this is the case, then switch SW2 can be closed a second time within the same switching cycle. This is in... Figure 10 The time t4 in the diagram is shown. Then, within the same switching cycle, switch SW2 can be turned off a second time. This is shown at t5 in the diagram, at which point V... L The level is equal to V IN The high-side switch SW2 operates at a certain level. While the low-side switch SW1 remains open, the second cycle of the high-side switch SW2 occurs. Therefore, during each switching cycle of the low-side switch SW1, the high-side switch SW2 is opened and closed twice.

[0088] Figure 10 The signal waveform for the READYHIGHON signal is also shown. This waveform illustrates two time windows in which switch SW2 is permitted to close during each switching cycle. Figure 3 and Figure 5As shown, the first window begins when the READYHIGHON signal transitions to a logic high voltage shortly before time t2. The first window ends when the READYHIGHON signal transitions to a logic low voltage shortly after time t3. The second window begins when the READYHIGHON signal transitions to a logic high voltage shortly before time t4. The first window ends when the READYHIGHON signal transitions to a logic low voltage shortly after time t5. Therefore, as... Figure 10 As shown in the two time windows provided by the READYHIGHON signal, during each switching cycle of the low-side switch SW1, switch SW2 is permitted to close and open twice. Furthermore, the timing of each of these two cycles of switch SW2 within each window can be based on monitoring V. L Therefore, ZVS can be maintained in two cycles.

[0089] Figure 10 The diagram shows five oscillations that occurred before the switch SW2 was closed. It is evident that more or fewer oscillations may have occurred before the switch SW2 was closed.

[0090] Figure 11 The voltage waveforms of the flyback converter in an alternative low-line, light-load operating mode (also referred to herein as "combined" second and third operating modes) according to an embodiment of the invention are shown. Figure 11 and Figure 10 The difference is that, Figure 11 The READYHIGHON signal transitions to a logic low voltage at time t3, causing the high-side switch SW2 to immediately open. Therefore, according to the non-ZVS condition, switch SW2 can open at time t3. Figure 11 In the process, the READYHIGHON signal transitions to a logic high voltage before time t2, thus allowing monitoring of V... L The voltage level is determined and switch SW2 is closed based on ZVS. Figure 10 Similarly, the READYHIGHON signal transitions to a logic high voltage before time t4 and returns to a logic low voltage after time t5. Therefore, the precise timing for opening and closing switch SW2 during the second cycle of switch SW2 can be based on monitoring V. L The level and under ZVS conditions.

[0091] Figure 12 The voltage waveform of a flyback converter in a low-line, heavy-load operating mode (also referred to herein as "third" operating mode) according to an embodiment of the present invention is shown. This operating mode of the high-side switch SW2 is similar to... Figure 6 and 9 The difference is significant. In this operating mode, the high-side switch SW2 is disconnected without needing to reference or monitor V.L The high-side switch SW2 can alternatively open in response to a level change of a fixed or adjustable duration pulse signal (e.g., the READYHIGHON signal) while the low-side switch SW1 remains closed. In this operating mode, the duration for which the high-side switch is closed in this mode is typically shorter than the duration for which it is closed in other operating modes (e.g., ...). Figure 3 ).like Figure 12 As shown, the READYHIGHON signal transitions to a logic high voltage shortly before time t2. Then, once V... L The level is equal to or very close to the voltage V. IN +V CSN Then, switch SW2 can be closed. This occurs at time t2. The READYHIGHON signal transitions to a logic low voltage at time t3. This causes the high-side switch SW2 to immediately open. Therefore, switch SW2 remains closed during the time period between t2 and t3. (As combined...) Figure 6 and 9 The exemplary waveform is used to illustrate, Figure 12 The duration of the time interval t2-t3 shown can depend on V IN The level.

[0092] In an alternative to this high-side switching operation mode, the high-side switch SW2 remains open, while the body diode of the high-side switching transistor continues to perform rectification. This can be achieved by maintaining the READYHIGHON signal for the duration of the switching cycle.

[0093] Figure 13 A graph showing the relationship between the switching frequency and input power of a flyback converter according to an embodiment of the present invention is shown. Switching frequency f sw Plotted on the vertical axis, and determined by the feedback error signal V. EAO (For example, Figure 14 The measured input power is plotted on the horizontal axis. For example... Figure 13 As shown, the flyback converter can operate in different operating regions depending on the load power: (1) operating region 10 for very light loads; (2) operating region 12 for light loads; (3) operating region 14 for moderate loads; and (4) operating region 16 for heavy loads. Although four operating regions 10, 12, 14, and 16 are shown based on the load, it is clear that more or fewer regions can be implemented.

[0094] When the feedback error signal V EAOBelow a low threshold (e.g., 0.75 volts), this indicates a very light load. In this operating region 10, the flyback converter can operate in either a "burst" or "reverse" mode. In this mode, the switches (SW1 and SW2) can pause between "bursts" to improve efficiency. Once V... EAO When the voltage level rises above the low threshold, the flyback converter enters the light-load operating region 12. In this region 12, the flyback converter can operate in frequency-controlled mode, where the switching frequency of the low-side switch SW1 is modulated in the feedback loop to adjust the output voltage V. O Once V EAO When the voltage level exceeds the median threshold (e.g., 2.0 volts), the flyback converter enters the transition load region 14. In this region 14, operation in frequency control mode can continue until V... EAO The voltage level exceeds a high threshold (e.g., 2.5 volts).

[0095] onceV EAO If the voltage level exceeds a high threshold (e.g., 2.5 volts), the flyback converter enters the overload region of operation 16. In this region 16, the switching frequency is clamped to a predetermined value f. clamp Furthermore, the flyback converter enters current control mode. In current control mode, the current sensing signal Isense (e.g., Figure 14 The peak current level sensed in each switching cycle (in the primary winding of transformer T1) is controlled in the feedback loop to adjust the output voltage V. O As the power level increases, such as Figure 13 As shown by the downward sloping lines in regions 14 and 16, the switching frequency can be further reduced. When the power level is close to full load, it is still best to perform voltage regulation primarily through the current-controlled feedback loop.

[0096] like Figure 13 As shown, the relationship between switching frequency and power is discontinuous. This discontinuity occurs when transitioning from frequency control to current control (e.g., when V...). EAO When the voltage rises above 2.5 volts, the switching frequency suddenly increases, while the peak current in the primary winding of the transformer decreases. Conversely, when transitioning from current control to frequency control (e.g., when V...), the switching frequency increases suddenly, and the peak current in the primary winding of the transformer decreases. EAO When the voltage drops below 2.0 volts, the switching frequency suddenly decreases, while the peak current in the primary winding of the transformer increases. In both modes, negative feedback is used to adjust the output voltage V. O Therefore, it is important that the flyback converter remains stable when switching between frequency and current control modes.

[0097] Figure 13The switching frequency versus power curve shows a hysteresis phenomenon during the transition between frequency control and current control. That is, once V... EAO When the voltage level rises above 2.5 volts and the switching converter switches from frequency control mode to current control mode, then V EAO The voltage level must drop below 2.0 volts to return to frequency control mode. Similarly, once V... EAO When the voltage level drops below 2.0 volts and the switching converter switches from current control mode to frequency control mode, then V EAO The voltage level must rise above 2.5 volts to return to current control mode. It is obvious that the 2.0 volt and 2.5 volt transition levels are exemplary, and different levels can be selected.

[0098] Still referencing Figure 13 In the very light load region 10 and the light load region 12, the flyback converter preferably operates according to the DCM. Under these load conditions (e.g., in...), Figure 13 In areas 10 and 12), the first operating mode of the high-side switch SW2 (such as...) can be determined based on the following: Figure 3 ) or according to the second operating mode (such as Figure 4 ) or according to the first and second operating modes of the high-side switch SW2 (such as Figure 5 (Operate in both modes 1 and 2) or according to mode 3 (e.g.) Figure 6 For example, one can experimentally determine the optimal overall efficiency and avoid impacting the buffer capacitor C. SN Overcharging modes are selected from the operating modes described above. For example, the above alternatives can assume the existence of "high line" conditions. However, under low line and light load conditions, a third mode (such as...) can be expected. Figure 9 ) or a combination of the first and second modes (such as Figure 10 This may be optimal. Under low-line conditions and light load conditions, operation can be based on a combination of second and third modes (such as...). Figure 11 ).

[0099] In one embodiment, under heavy load conditions (e.g., in Figure 13 In area 16), the switching power supply is preferably operated according to CRM. Under heavy load and "high line" conditions, for example, it can be operated according to the first operating mode of the high-side switch SW2 (such as...). Figure 7 (as shown) or according to the combined operating mode (such as Figure 8 The high-side switch can be operated according to the third operating mode of the high-side switch SW2 (as shown). Under heavy load and "low line" conditions, for example, the high-side switch can be operated according to the third operating mode of the high-side switch SW2 (as shown). Figure 12 (As shown).

[0100] In the embodiment, the load level is under transitional load conditions between light load conditions and heavy load conditions (e.g., ...). Figure 13 In region 14, the switching power supply can operate in either DCM or CRM mode. Whether the switching power supply operates in DCM or CRM mode can, for example, depend on whether the operation prior to entering region 14 was DCM or CRM. More specifically, if the operation prior to entering region 14 was DCM, DCM operation can continue in region 14 until the error signal exceeds 2.5 volts. Conversely, if the operation prior to entering region 14 was CRM, CRM operation can continue in region 14 until the error signal drops below 2.0 volts. Furthermore, under transient load conditions, the high-side switch preferably operates according to the second operating mode of the high-side switch (e.g., Figure 4 (Or as shown in 5) Similarly, the operating mode in transition region 14 can remain the same as the operating mode before entering transition region 14 until the load power crosses the opposite side of transition region 14. More specifically, the operating mode present in region 16 can continue into region 14 until the load power crosses into region 12. Conversely, the operating mode present in region 12 can continue into region 14 until the load power crosses into region 16.

[0101] Figures 3 to 12 The waveform is also applicable to both current control and frequency control modes, although the time ratio will change depending on the operating mode.

[0102] Figure 14 A flyback converter 150 and a control circuit according to an embodiment of the present invention are shown. Figure 14 It shows Figure 2 An embodiment of the flyback converter 150 and its control circuit, and an embodiment of the second output stage. Figure 14 The flyback converter 150 and control circuitry are preferably configured to control the high-side switch SW2 and the low-side switch SW1. Specifically, a "low-drive" controller 152 generates a signal LOWOUT to control (i.e., open and close) the low-side switch SW1. As described herein, the low-drive controller 152 may use frequency control and / or peak current control in a feedback loop to control switch SW1 in order to adjust the output voltage V. O The low-side driver controller 152 preferably also generates the READYHIGHON signal described herein. As described herein, the "high-side driver" controller 154 is based on the monitored V... L and V IN The signal level and the signal HIGHOUT generated based on the signal READYHIGHON control (i.e., open and close) the high-side switch SW2.

[0103] like Figure 14As shown, a resistor divider and an optocoupler network 156 are coupled to the output of the flyback converter 150, and include resistors R1, R2, and R3, capacitor C2, and photodiode P. 1A And a parallel voltage regulator U1. Photodiode P1A is optically coupled to phototransistor P. 1B Phototransistor P 1B It is coupled to the compensation resistor R4 and capacitor C3. A voltage signal V is generated across the compensation resistor R4 and capacitor C3. EAO Signal V EAO Indicates the error signal (V) O The level and V O The difference between the expected and actual levels (and also represents the level of the input power of the flyback converter 150). Signal V EAO With output voltage V O Electrical isolation, and instead of ground reference, the ground level of the primary side of transformer T1.

[0104] Transformer T1 may include a secondary winding. For example... Figure 14 As shown, the first terminal of the secondary winding of transformer T1 is coupled to the anode of diode D2. The cathode of diode D2 is coupled to the first terminal of capacitor C4. The second terminal of the secondary winding of transformer T1 is coupled to the second terminal of capacitor C4 and also coupled to the first ground node. A voltage V is formed across capacitor C4. CC And voltage V CC This can be used to power the control circuitry of the flyback converter 150. The resistor divider includes resistors R5 and R6 and generates a voltage representing V. CC The voltage signal ZCD represents the voltage level. Signal ZCD also represents V. L The level.

[0105] Similarly, Figure 14 As shown, capacitor C VL The first terminal is coupled to the node between the high-side switch SW2 and the low-side switch SW1. Capacitor C VL The second terminal of capacitor C is coupled to the first ground node. VL tending to make V L The signal waveform is smooth. Additionally, the current sensing resistor R... SENSE Coupled between the second terminal of transistor switch SW1 and the first ground node. In resistor R SENSE Current sensing signal I is formed at both ends SENSE .

[0106] Low-frequency driver controller 152 receives signals ZCD, I SENSE V EAOAnd the oscillator signal OSC is used as input, and these signals are used to generate the signal LOWOUT to control the transistor switch SW1, as described in this article. Signal V EAO Represents load power and is used to adjust the output voltage in the feedback loop based on peak current control or switching frequency control. Signal I SENSE The current in transformer T1 is represented and used to control the peak current in the primary winding of the transformer during switching. The oscillator signal OSC is used to control the timing of the switching. The signal ZCD represents V. L The voltage level is used to turn on switch SW1.

[0107] The low-driver controller 152 generates a differential signal READYHIGHON, which the high-driver controller 154 uses to control the transistor switch SW2, as described herein. The READYHIGHON signal informs the high-driver controller 154 that it can (i.e., has permission) turn on the switch SW2, although the high-driver controller 154 typically determines the timing of turning on the switch SW2. The READYHIGHON signal is preferably a differential signal because the low-driver controller 152 and the high-driver controller 154 preferably have different ground reference nodes. Specifically, the low-driver controller 152 references a first ground node, while the high-driver controller 154 preferably uses a voltage V. L As its grounding reference.

[0108] Similarly, Figure 14 As shown, the first high-voltage resistor R HV1 The first terminal is coupled to capacitor C SN The second terminal. Resistor R HV1 The second terminal is coupled to the high driver controller 154. This provides the high driver controller 154 with a representative voltage V. CSN The signal CS. Second high-voltage resistor R. HV2 The first terminal is coupled to the input voltage V IN Resistor R HV2 The second terminal is coupled to the high-frequency driver controller 154. Capacitor C RVIN Preferably with resistor R HV2 Parallel coupling. This provides a representative voltage V for the high-drive controller 154. IN signal R VIN Capacitor C RVIN Helps to smooth signal R VIN Especially under light load conditions. Voltage V L The signal is also coupled to the high driver controller 154. The high driver controller 154 uses signal R. VIN CS, V LThe READYHIGHON signal is used to generate the HIGHOUT signal, which controls (i.e., opens and closes) switch SW2, as explained herein. For example, when V... L Greater than V IN And CS is basically equal to V L At this time, the high-drive controller 154 turns on switch SW2. Switch SW2 normally remains on until V. L Basically equal to V IN Then switch SW2 is turned off. However, as described in this article, the timing of switch SW2 turning on and off can also depend on other factors, such as the input voltage V. IN The level. When the READYHIGHON signal is deactivated, switch SW2 can also be turned off.

[0109] Also in Figure 14 As shown, voltage V CC This can be used as a power supply for components in the low-frequency driver controller 152. Voltage V BOOT This can be used as a power supply for components of the high-drive controller 154. Voltage V BOOT It can be obtained from V, for example, via a diode. CC The voltage V is obtained by drawing current. BOOT Then for capacitor C VBOOT Charging. Voltage V BOOT It can also be used to indicate the load level of the power converter 150, as explained in this document.

[0110] An exemplary switching cycle is executed as follows. The low-side switch SW1 is turned on. Then, once the peak current in the primary winding of transformer T1 is reached, as indicated by the current sensing signal I... SENSE As shown, the low-side switch SW1 is turned off. The peak current depends on V. EAO The level: (1) When V EAO Below a threshold (e.g., 2.5 volts), the flyback converter is in frequency control mode, and the peak current is essentially a fixed value (although the peak current preferably varies with V). EAO (1) gradually decreases as V decreases to improve efficiency and suppress audible noise in burst mode; (2) when V EAO When the voltage exceeds a threshold (e.g., 2.5 volts), the flyback converter then enters current control mode, and the peak current depends on V. EAO (And the switching frequency is clamped). Once the low-side switch SW1 is open, the voltage V... L It then soared, eventually reaching a value higher than the input voltage V. INThe low-side driver 152 then activates and sends a READYHIGHON signal to the high-side driver 154. The READYHIGHON signal is activated at a time depending on the switching frequency and other factors. Upon receiving the READYHIGHON signal, the high-side driver 154 determines V... L V IN With a large and appropriate margin, and in response to this determination, the high-side driver 154 turns on the high-side switch SW2. The high-side switch SW2 remains on for a period of time, for example, until V. L The level drops to V IN The high-side driver 154 turns off the high-side switch SW2 until the READYHIGHON signal is deactivated, or until the high-side driver 154 turns off the high-side switch SW2. As explained herein, it can also be determined based on V. IN The level of V is used to adjust the timing when the high-side driver 154 disconnects the high-side switch SW2. More specifically, this is achieved by adjusting the level of V. IN The level quantity, the high-side switch SW2 can be at V L Descending to V IN Disconnect before the level. When V L When the voltage level drops to zero, the low-side switch SW1 can be turned on again.

[0111] For the third operating mode (e.g., Figure 6 , 8 (9 and 11-12), the READYHIGHON signal can be used as a pulse signal, and the high driver 154 is used to disconnect the high-side switch SW2. For example, the high driver 154 can be configured to open switch SW2 solely based on the READYHIGHON signal, without referencing or monitoring V. L The high-side switch SW2 can remain open for a predetermined or adjustable time period. For example, the high-side switch SW2 can remain open depending on the monitored R. VIN The level (and therefore depends on V) IN The time closure of the pulse signal (level). In this case, the duration of the pulse signal depends on V. IN The level. Alternatively, this can be achieved by adjusting resistor R. HV2 The duration of the pulse signal is adjusted by the resistance value. In this "third" operating mode, the low-driver controller 152 can generate a READYHIGHON signal, while the high-driver controller 154 can operate without using V. LThe high-side switch SW2 is opened by controlling the voltage level. Therefore, the timing of opening switch SW2 is controlled by the low-driver controller 152 instead of the high-driver controller 154. The low-driver controller 152 achieves this by initiating a READYHIGHON pulse signal, which the high-driver 154 then uses to open driver SW2. This indirect control of the high-side switch SW2 can result in non-ZVS operation, but with improved efficiency.

[0112] An alternative to the third operating mode of the high-side switch, in which the body diode of the high-side switch transistor SW2 remains off while rectification is still being performed, can be similarly implemented by a high driver 154 configured to turn on switch SW2 only when the signal READYHIGHON is activated (i.e., a logic high voltage). However, in this alternative third operating mode, the low driver 152 can retain the READYHIGHON signal, thereby causing the high driver 154 to keep the high-side switch SW2 off. In this case, the body diode of the high-side switch SW2 performs rectification passively. Therefore, this alternative third mode operation can also be initiated by the low driver controller 152.

[0113] Figure 15 A controller integrated circuit (IC) for a DC-DC converter according to an embodiment of the present invention is shown. In a preferred embodiment, the IC controller is implemented as an IC package 200, which includes a low-driver controller 152 as a first monolithic IC chip and a high-driver controller 154 as a second monolithic IC chip, both included in the same 18-pin IC package. In one embodiment, a switch SW2 is integrated into the high-driver controller 154 IC chip. Furthermore, in one embodiment, a resistor R... HV1 and R HV2 Included in the IC package. Resistor R HV1 and R HV2 One or both can be integrated into the high-drive controller 154IC chip. Additionally, resistor R... HV2 It can be partially integrated into the high-drive controller 154 IC chip. As described herein, each of the two IC chips has a different ground reference. Communication between the two chips is performed via a differential signal READYHIGHON.

[0114] Figure 15 The signal assigned to each of the 18 pins is shown:

[0115]

[0116]

[0117] Pins 2, 4, and 14 are not used; they are marked "N / C" or "No Connection". A diode is connected between pins 13 and 16. The OTP can be an overtemperature protection pin that supplies current to an external thermistor, whose voltage can then be compared to a reference (e.g., 1.0 volts) to detect overtemperature conditions. SSD This is the ground pin. After entering protection mode, the packaged IC can be reset using the RESET pin. Reset can be achieved by pulling the RESET pin down to a voltage lower than the reference voltage (e.g., 2.5 volts).

[0118] Figure 16 The control circuit of the high driver 154 according to an embodiment of the present invention is shown. Comparator 158 represents the input power supply voltage V. IN signal R VIN This is compared with a pair of reference currents I1 and I2 generated by current sources 160 and 162, respectively. Current sources 160 and 162 are coupled to V. L As a reference voltage. In one embodiment, current I1 is set to 2 μA (2 microamps) and current I2 is set to 60 μA (60 microamps). For example, to compensate for signal path delay during high-frequency operation, the signal at the input of comparator 158 can be further adjusted.

[0119] The output of comparator 158 is logic signal I. LIMIT When comparator 158 from R VIN When the level of the received current is between the levels of I1 and I2, I LIMIT It is the first logic level; otherwise, I LIMIT It is the second logic level. Signal I LIMIT Used to control the timing of turning on the high-side switch SW2. More specifically, R VIN The current level must be between the levels of I1 and I2 in order to turn on the high-side switch SW2 during the switching cycle (and the READYHIGHON signal must be activated). Therefore, comparator 158 is a window comparator whose output indicates R. VIN Is the current signal between the levels of I1 and I2? Comparator 158 determines V. L V IN With a large and appropriate margin, and in response to this determination, the high-side driver 154 turns on the high-side switch SW2. Therefore, the comparison window implemented by comparator 158 determines the moment SW2 is turned on (at...). Figure 3 and Figure 4 (As shown at time t2 in the diagram). Providing a comparison window helps to counteract the noise effects associated with high signal change rates and adapt to R... VIN resistor R VH2 parasitic capacitance ( Figure 2 ), and avoid in VIN and V L When they intersect (when one rises, the other falls, and vice versa), change I. LIMIT The logic level.

[0120] The output of comparator 158 is inverted by inverter 164 to form logic signal I. LIMIT -bar. Signal I LIMIT -bar is coupled via logic OR gate 165 to the input of NAND gate 166, the inverted set input S-bar of flip-flop FF1, the input of NAND gate 168, and the inverted set input S-bar of flip-flop FF2. Signal I LIMIT The inverted set input S-bar of flip-flop FF3 is coupled to the input of single-flip-flop circuit 170. The inverted output of single-flip-flop circuit 170 is coupled to the inverted reset input R-bar of flip-flop FF2. The inverted output Q-bar of flip-flop FF2 is coupled to the input of NAND gate 166.

[0121] The READYHIGHON signal is coupled to the input of NAND gate 166, the first inverted reset input R1-bar of flip-flop FF1, the input of delay unit 172, and the input of NAND gate 168. The inverted undervoltage lockout signal U... VLO -bar is coupled to the first inverting reset input R1 of flip-flop FF3, and to the second inverting reset input R of flip-flop FF1. s -bar. The output Q of flip-flop FF1 is coupled to the input of NAND gate 168. The output of delay unit 168 is coupled to the input of NAND gate 168.

[0122] The output of NAND gate 166 is coupled to the first inverted set input S1-bar of flip-flop FF4. The output of NAND gate 168 is coupled to the second inverted set input S2-bar of flip-flop FF4. The output Q of flip-flop FF4 is coupled to the input of AND gate 174. The inverted output of gate 174 is coupled to the second inverted reset input of flip-flop FF3. The non-inverted output of gate 174 forms the signal HIGHOUT. The generated signal HIGHOUT is used to control switch SW2.

[0123] Signal R VIN It is also compared with current I3 by comparator 176. Current I3 is generated by adjustable current source 178. Current source 178 is coupled to V, which serves as a reference voltage. L The current I3 is determined by V. IN The level is adjusted. The output of comparator 176 is coupled to the first input of NAND gate 180. The signal HIGHOUT is coupled to the second input of NAND gate 180. The output of NAND gate 180 is coupled to the first input of NAND gate 182. The inverse undervoltage lockout signal U...VLO The R-bar is coupled to the second input of NAND gate 182. The output of NAND gate 182 is coupled to the inverted reset input R-bar of flip-flop FF4 and the first input of sampling / logic circuit 184.

[0124] Signal R VIN Coupled to the second input of the sampling / logic circuit 184. The NAND gate 182 generates a high-side off signal, which the sampling / logic circuit 184 uses to adjust V. IN Sampling is performed. More specifically, each time the high-side switch SW2 is turned off (i.e., opened), the sampling circuit preferably waits for a delay of approximately 250 to 300 nanoseconds before sampling V. IN The level. Therefore, approximately at V L Sampling is performed at zero volts. This can be done for V. IN Continuous sampling and averaging are performed to ensure that the monitored V IN The voltage level does not change rapidly. The sampling / logic circuit 184 generates a representative value V. IN Level signal ~V IN (Steady state). This signal is used to generate current I3, which also represents V. IN The level.

[0125] like Figure 3-5 As shown in 7, 8 and 10, Figure 16 Component detection V L The voltage level controls the switching of SW2. The READYHIGHON signal informs the high driver controller 154 that it can (i.e., has permission) turn on switch SW2. The high driver controller 154 then determines the timing for turning on switch SW2: when V... L Reaching V IN The level (such as signal I) LIMIT When (as shown), the high driver controller 154 turns on switch SW2.

[0126] Trigger FF1 and delay block 172 are used to delay the on-state of switch SW2 to avoid premature on-state switching. In undervoltage conditions, U VLO Signal disable switch.

[0127] Switch SW2 remains on until it is turned off according to the comparison performed by comparator 176. More specifically, when V IN A bias of a certain amount is applied so that it is substantially equal to V. L When switch SW2 is turned off (open), the bias amount is ~V IN (Steady-state) level indication. Comparator 176 preferably performs its comparison with hysteresis to avoid multiple changes in the level of its output at the crossover of the input signal levels of comparator 176.

[0128] like Figure 16 As shown, voltage source V BOOT It can be coupled to the third input of the sampling / logic circuit 184. This can be used to determine whether the power converter 150 is under light or heavy load conditions. For example, V can be... BOOT Adjust to approximately 15 volts DC. When V BOOT A rise to a threshold level above 15 volts indicates a light load. Conversely, when V... BOOT When the voltage drops below the threshold level of 15 volts, it indicates that the load is no longer light. According to an embodiment of the invention, when the converter 150 is under light load conditions, V-based... IN The voltage level is used to disconnect the function of switch SW2. More specifically, when V... BOOT When the level is higher than the threshold, it can be based on ~V IN The (steady-state) voltage level has zero effect on the regulation of current I3. When this occurs, comparator 176 can adjust V... IN The level (e.g., R) VIN (represented by) and V L The voltage levels are compared to determine when to disconnect switch SW2. Under these conditions, switch SW2 can be disconnected under ZVS. Additionally, when V... IN When the level is at the maximum threshold (e.g., 380 volts DC), based on ~V IN The level (steady state) of V can also have a zero effect on the current I3. However, when V BOOT The level is higher than the threshold (while V) IN When the voltage level is below its maximum threshold, the voltage level of current I3 can represent V. IN The level, so that switch SW2 is partially based on the monitored V. IN (i.e. ~V) IN Disconnect by (steady-state) level.

[0129] The sampling / logic circuit 184 can also be used to determine when the high-side driver controller 154 enters the third operating mode. More specifically, the sampling / logic circuit 184 can use R... VIN and V BOOTSignals are used to make this determination, as those signals represent the input voltage and load power, respectively. A high-side pulse enable signal is activated to indicate that the high-side driver controller 154 has entered the third operating mode. This signal is applied to a logic OR gate 165, which takes precedence over the high-side driver controller 154's determination of the timing of turning on the switch SW2. Instead, in response to receiving a READYHIGHON signal, switch SW2 is indicated to turn on and / or off. It is evident that the high-side driver 154 can determine whether to enter the third mode in another manner. This could include, for example, monitoring the input voltage and load power and / or bypassing V in another manner. L The switch SW2 is switched on in another way by sensing. Alternatively, it is not necessary to generate a high-side pulse enable signal. In this case, the logic OR gate 165 can be omitted, and the signal I can be... LIMIT -bar is coupled to a logic NAND gate 166. In this case, to close the high-side switch, signal I... LIMIT -bar and the READYHIGHON signal must both be active.

[0130] Figure 17 A control circuit for a low-frequency driver 152 according to an embodiment of the present invention is shown. For example... Figure 17 As shown, the low-frequency driver 152 includes a current control section 186, a frequency control section 188, a timer section 190, a switching logic 192, and a switching driver 194.

[0131] Within the current control section 186 of the low-frequency driver 152, the signal V EAO The first input of comparator 196 is coupled to the second input of comparator 196. The second input of comparator 196 receives a first reference voltage (e.g., 2.5 volts), while the third input of comparator 196 receives a second reference voltage (e.g., 2.0 volts). Comparator 196 transmits the signal V... EAO The signal "V" is generated by comparing it with the first and second reference voltages. EAO >2.5v-bar”; when V EAO When the voltage rises above the first reference voltage, the signal "V" EAO >2.5v-bar” is activated; when V EAO When the voltage drops below the second reference voltage, the signal "V" EAO >2.5V-bar” deactivates. Therefore, comparator 196 performs its comparison with hysteresis. Comparator 196 determines whether the low-drive controller 152 performs switching based on peak current control or frequency control. When V EAO When the voltage rises above 2.5 volts, switching is controlled by peak current; when V EAOWhen the voltage drops below 2.0 volts, switching is initiated via frequency control. Therefore, "V" EAO The logic level of ">2.5V-bar" determines whether the switch is based on peak current control or frequency control.

[0132] Signal I SENSE The signal is coupled to the input of the first amplifier 198 and the input of the second amplifier 200. For example, amplifier 198 may have a gain of 15, while amplifier 200 may have a gain of, for example, 7.5. The output of amplifier 198 is coupled to the first input of comparator 202 via switch S1. The output of amplifier 200 is coupled to the first input of comparator 202 via switch S2. Signal V EAO Coupled to the second input of comparator CMP4. Signal "V" EAO >2.5V-bar is coupled to control switch S2 and, via inverter 204, controls switch S1. Therefore, depending on the signal "V EAO ">2.5V-bar", one of switches S1 and S2 is closed while the other is open. Therefore, depending on V EAO The outputs of amplifiers 198 and 200 are selectively coupled to the first input of comparator 202. The output of comparator 202 is coupled to the input of switching logic 192.

[0133] According to current control, the amplifier 198 with higher gain is activated so that amplification is performed through comparator 202 with V. EAO In the comparison I SENSE The effect is that, according to frequency control, amplifier 200 is activated, employing a lower gain to reduce the impact of I in the comparison. SENSE The influence of this makes the frequency control section 188 the main control switch.

[0134] Within the frequency control section 188 of the low-frequency driver 152, signal I... SENSE The input of amplifier 206 is coupled to the input of amplifier 206. Amplifier 206 may have a gain of, for example, 7.5. The output of amplifier 206 is coupled to the first input of comparator 208. The second input of the comparator is coupled to a reference voltage, which may be, for example, approximately 2.5 volts. The output of comparator 208 is coupled to the input of switching logic 178.

[0135] The current control section 186 and the frequency control section 188 control the timing of turning off the low-side switch SW1 in each switching cycle via the switching logic 192.

[0136] The timer section 190 of the low-side driver 152 controls the switching frequency and the timing of turning on the low-side switch SW1 in each switching cycle. The timer section 190 also generates a signal HON, which is used to generate the signal READYHIGHON (see...). Figure 18 The READYHIGHON signal is used by the high-side driver controller 154 to control switch SW2 for the first and second operating modes of the high-side switch SW2, and also to generate a pulse signal for the third operating mode of the high-side switch SW2. Within the timer section 190, the signal V... EAO The first input of the oscillator 210 is coupled to the signal "V" from the comparator 196. EAO A 2.5V-bar signal is coupled to the second input of oscillator 210. Oscillator 210 generates a periodic ramp signal, which is coupled to the input of timer / logic block 212.

[0137] Timer / logic block 212 generates logic signals HON and ONSET, which are coupled to switching logic 192. Signal HON is controlled by low-driver controller 152. Figure 14 The READYHIGHON signal is used to generate the high-drive controller 154. For peak current control, this READYHIGHON signal is generated at fixed intervals. The ONSET signal is used to turn on the low-side switch SW1. For example, a 3.33 microsecond timer can be reset for each switching cycle; the READYHIGHON signal is activated 500 nanoseconds before the timer expires. Furthermore, the ONSET signal can be activated when the timer expires, and once ZCD is greater than zero. Once ONSET is activated, the low-side switch SW1 can be closed at the valley of the ZCD signal (because ZCD represents V). L This allows switch SW1 to operate under zero-volt switching (ZVS) conditions. The 500 nanosecond difference ensures that HON is activated before ONSET.

[0138] The signal ZCD is referenced to the same ground level as the low-side driver controller 152. The signal ZCD also represents V. L The level of the signal ZCD. Therefore, the low-side driver controller 152 uses the signal ZCD as V. L The representative is used to operate switch SW1 under ZVS conditions.

[0139] For current control, instead of a fixed timer interval of 3.33 microseconds, for example, the timer interval is based on V EAO The voltage level varies. Therefore, the timer interval affects the switching frequency used to adjust the output voltage in the feedback loop.

[0140] The 3.33 microsecond timer interval corresponds to the switching frequency used for peak current control at 300 kHz. In this embodiment, the switching frequency f can be adjusted by appropriately selecting the timing component. clamp Clamped at 500kHz, 300kHz, 145kHz or some other selected frequencies.

[0141] The output of switch logic 192 is coupled to driver 194. Driver 194 generates the signal LOWOUT.

[0142] During the switching cycles of switches SW1 and SW2, once the low-side switch SW1 is disconnected, V L The level immediately rose to V IN The voltage level is above the specified level. Under light load conditions, the energy stored on the primary side of transformer T1 cannot be effectively transferred to its secondary side. Therefore, in each switching cycle, the buffer capacitor C... SN The energy stored in it will increase, thus the energy becomes overcharged, and the buffer capacitor C SN Thus, when the low-side switch SW1 is disconnected, V L The voltage level will rise to an excessively high level. These effects of light load conditions can be mitigated by turning on the high-side switch SW2 earlier in the switching cycle. Therefore, according to an embodiment of the invention, under certain light load conditions, the high-side switch SW2 is turned on earlier in the switching cycle than otherwise. Similarly, when the input power supply voltage V... IN When it is at a high level, this will also cause the buffer capacitor C to... SN Overcharging. This can also be mitigated by turning on the high-side switch SW2 earlier in the switching cycle. When the input voltage V IN Using frequency control to control the switch instead of current control when the voltage is high can also help mitigate these problems. Therefore, according to embodiments of the invention, frequency control is used under certain high input voltage conditions.

[0143] In the embodiment, comparator 214 is included Figure 17 In the current control section 186, the comparator 214 will convert the signal R VIN The level (representing voltage V) IN Compare with a reference. For example... Figure 17 As shown, signal R VIN The voltage can be gradually reduced using a voltage divider, which includes a resistor R. 11 and R 12 The gradually decreasing voltage is represented by V. IN The level, and the reference voltage V REF2 Comparison. When the comparison indicator V INWhen the voltage level is greater than a threshold (e.g., 226 volts DC), the output of comparator 214 disables comparator 196. As a result, switch S1 opens and switch S2 closes, thus activating amplifier 200. This causes the frequency control section 188 of the flyback converter control circuit to primarily control the switches, rather than the current control section 186. Therefore, the flyback converter controller detects a power supply voltage condition (e.g., when V...) IN When the threshold is greater than 226 volts DC, it operates in frequency control mode.

[0144] In an embodiment, Figure 17 The timer section 190 in the middle includes a comparator 216. The comparator 216 is configured to represent V... IN (in resistor R) 11 and R 12 The gradually decreasing voltage level at the node between the reference voltage V REF3 A comparison is made. When the comparison indicates V IN When the level is below a threshold, the output of comparator 216 generates a signal LOWLINE, which is coupled to timer 212. In response, timer / logic 212 can generate a pulse signal discussed herein, which is then used to generate a signal HON. Low driver 152 uses signal HON to generate READYHIGHON according to the third operating mode of high-side switch SW2.

[0145] Figure 18 A differential signal converter 300 in a control circuit for a flyback converter according to an embodiment of the present invention is shown. The differential signal converter 300 converts a single-ended signal HON into a differential logic signal READYHIGHON. The logic signal HON is coupled to the input of a first inverter 302. The output of the first inverter 302 is coupled to the input of a second inverter 304 and controls MOSFET M5. The output of the second inverter 304 is coupled to control MOSFET M6. MOSFET M7 and current source 306 are coupled in series with MOSFET M5. MOSFET M8 and current source 308 are coupled in series with MOSFET M6. Current source 310 is coupled in series with MOSFET M9 and MOSFET M6. 10 Series coupling. Reference current flows through MOSFETs M9 and M... 10Depending on the level of HON, the signal HON activates either MOSFET M5 or M7. Depending on which MOSFET M5 or M7 is active, the reference current is mirrored in either MOSFET M8 or MOSFET M7. The state of the differential signal READYHIGHON depends on which MOSFET M5 or M7 is active. Therefore, converter 300 converts the logic signal HON into the differential logic signal READYHIGHON.

[0146] Figure 19 An oscillator in a control circuit for a flyback converter according to an embodiment of the present invention is shown. Figure 19 It shows Figure 15 Additional details about the oscillator 190. (See below for further details.) Figure 19 As shown, signal V EAO The first input of amplifier AMP1 is coupled via switch S3. A reference voltage, for example 2.5 volts, is coupled to the second input of amplifier AMP1 via switch S4. The third input of amplifier AMP1 is coupled to an adjustable resistor R. OSC1 First terminal and resistor R OSC2 The first terminal. The output of amplifier AMP1 is coupled to MOSFET M. 11 The control terminal of MOSFET M. 11 The output terminal is coupled to resistor R OSC1 First terminal and resistor R OSC2 The first terminal. Resistor R OSC1 The second terminal is coupled to the ground node via switch S5. Resistor R OSC2 The second terminal is coupled to the ground node via switch S6.

[0147] Power supply voltage V CC Coupled to MOSFET M 12 Input terminals and MOSFETs 13 The input terminal of the MOSFET. 12 The output terminal is coupled to MOSFET M 12 Control terminals, MOSFETs 13 Control terminals and MOSFETM 11 The input terminal of the MOSFET. 13 The output terminal is coupled to the adjustable capacitor C. T The first terminal is coupled to the first input terminal (inverting) of comparator CMP6 and the first input terminal (non-inverting) of comparator CMP7. Adjustable capacitor C TThe second terminal of the comparator is coupled to the ground node. The second input terminal of comparator CMP6 is coupled to the reference voltage Vrefh. The second input terminal of comparator CMP7 is coupled to the reference voltage Vrefl. The output of comparator CMP6 is coupled to the inverting set input S-bar of flip-flop FF5. The output of comparator CMP7 is coupled to the inverting reset input R-bar of flip-flop FF5. The output Q of flip-flop FF5 is coupled to control switch S7. Switch S7 is coupled to capacitor C. T Both ends.

[0148] Switches S3 and S5 are controlled by signal "V" EAO >2.5V” control, while switches S4 and S6 are controlled by the logic signal “V”. EAO >2.5V-bar” control. Therefore, when V EAO When the voltage is greater than the 2.5V threshold, switches S3 and S5 are closed, while switches S4 and S6 are open. When V EAO Below the 2.0 volt threshold, switches S4 and S6 are closed, while switches S3 and S5 are open. As explained in this document, the signal "V..." EAO >2.5v” and its reverse “V” EAO ">2.5v-bar" is generated using hysteresis.

[0149] Oscillator 190 at capacitor C T A periodic ramp signal RTCT is generated at both ends. Transistor M 12 and M 13 Forming a current mirror, allowing current to pass through transistor M 13 The current in capacitor C T Charging. When capacitor C T When the voltage across the capacitor reaches Vrefh, closing switch S7 causes capacitor C to... T Discharge until capacitor C T The voltage across the terminals drops below Vrefl. Then, switch S7 is disconnected.

[0150] The frequency of the ramp signal RTCT is based on the logic signal "V". EAO It changes depending on the state of >2.5v. More specifically, when V EAO When less than 2.0 volts (signal "V") EAO >2.5V” is logic “0”), the flyback converter operates in frequency control mode, in which the switching frequency depends on V. EAO The voltage level. This is achieved by closing switch S3 so that V... EAO Coupled to amplifier AMP1, which is relative to V EAO The level of the conducting MOSFET M 11 Therefore, MOSFET M 12 and M13 The current level in the current mirror is affected by V EAO The level of influence, while V EAO The voltage level also affects capacitor C. T The charging rate and the frequency of the ramp signal RTCT. The frequency of the ramp signal RTCT is the same as the switching frequency of the flyback converter. Therefore, in this frequency control mode, the switching frequency is controlled in the feedback loop to adjust the output voltage, where the switching frequency depends on V. EAO .

[0151] Unless V EAO The voltage must rise above 2.5 volts; otherwise, frequency control mode will continue. When V... EAO Rise to above 2.5 volts and the signal "V" EAO When the voltage >2.5V changes to logic "1", switch S3 is then turned off and switch S4 is closed. This couples the fixed reference voltage to the input of amplifier AMP1, so that capacitor C... T The charging current is essentially constant. This results in an essentially constant switching frequency for the flyback converter. In this mode, the current is controlled in the feedback loop to adjust the output voltage.

[0152] The frequency of the ramp signal RTCT and the switching frequency of the flyback converter depend on C. T The value of and resistance R OSC1 and R OSC2 In current control mode, switch S6 is closed, causing resistor R to... OSC2 This affects the switching frequency, and when switch S5 is off, it causes resistor R to... OSC1 It does not affect the switching frequency. In frequency control mode, switch S6 is open, thus resistor R... OSC2 The switching frequency is no longer affected, and with switch S5 closed, the resistance R... OSC1 It does affect the switching frequency.

[0153] Choose C T R OSC1 and R OSC2 The value of is used to appropriately set the nominal switching frequency in frequency control mode and the basically fixed switching frequency in current control mode. Additionally, resistor R... OSC1 and capacitor C T The value can preferably be fine-tuned, for example, by laser or fuse trimming, to ensure a smooth transition between frequency control and current control modes. For this purpose, it is best to adjust the resistor R... OSC1 Merging Figure 15 The IC package shown.

[0154] The selection of oscillator components may first include resistor R OSC2 Select a value that sets the clamping frequency f.clamp Then, the capacitor C, preferably located inside the low-frequency driver controller IC 152, is adjusted. T This is done to fine-tune the clamping frequency. Finally, the internal resistor R is adjusted. OSC1 The resistor is also preferably located inside the low-drive controller IC 152 to fine-tune the switching frequency when switching between current control and frequency control operating modes.

[0155] Figure 20 A comparator in a control circuit for a flyback converter according to an embodiment of the present invention is shown. It can be used... Figure 20 The comparator replaces Figure 15 The comparator CMP5 is shown in the frequency mode control section 174. (As shown...) Figure 10 and 14 As shown, the comparator receives signal I. SENSE x7.5 is used as an input, which is compared with a 2.5V reference voltage to generate an OFF signal. The OFF signal is used to disconnect the main switch SW1. Figure 20 The comparator also accepts signal V EAO As input. Signal V EAO Lowering the effective level of the reference voltage allows for faster generation of the OFF signal, thus reducing the switching frequency. This is useful for reducing switching noise in burst mode.

[0156] Figure 21 An embodiment of a timer / logic according to an embodiment of the present invention is shown. It can be used... Figure 21 Replace the timer / logic 218 Figure 17 Timer 212. (e.g.) Figure 21 As shown, the timer / logic 218 accepts a "Load Condition" signal and an "Input Condition" signal (corresponding to the LOWLINE signal in this document), as well as an oscillator signal OSC as input. The timer / logic 218 uses these signals to generate the signals HON and ONSET as described herein. The load condition and input condition signals are binary (i.e., each has two possible states, such as true / false or zero / one), and respectively indicate when the current load is light and the input voltage V. IN When is it high? Because signal V EAO The load condition signal indicates the load, so it can be equivalent to the logic signal "V". EAO >2.5v–bar.

[0157] and Figure 17 Similar to timer 212, Figure 21Timer 218 generates logic signals HON and ONSET, which are coupled to switching logic 178. Signal HON is used to generate the signal READYHIGHON for the high-side controller 154. For frequency control, signals HON and ONSET are generated at intervals depending on the switching frequency determined by the frequency of the oscillator signal OSC. For example, a timer with a variable duration can be reset for each switching cycle. This duration will vary depending on the switching frequency. The duration at a particular frequency could be, for example, 3.33 microseconds. Signal HON is activated moment before the timer expires. The amount of time before HON activation occurs before the timer expires also depends on the switching frequency, but also on the levels of the load conditions and input condition signals, so that the high-side switch SW2 is turned on earlier in the switching cycle. For example, when the switching frequency results in a timer duration of 3.33 microseconds, under normal circumstances, activation might occur 500 nanoseconds before the timer expires. However, if one or both of the "Load Condition" and "Input Condition" signals indicate a light load condition or a high input voltage condition, the duration can be adjusted (e.g., increased to 1000 nanoseconds or 1.0 microsecond) to turn on the activation signal HON earlier in the switching cycle, and thus turn on the switch SW2 earlier in the switching cycle as well.

[0158] As explained in this document, the signal HON can be used to generate the signal READYHIGHON, which is controlled by the high-drive controller 154 ( Figure 14 The low-driver controller 152 is used to control the operating mode of the high-side switch SW2. Therefore, the low-driver controller 152 can determine the operating mode of the high-side switch SW2 (e.g., a "first" mode, a "second" mode, a "third" mode, or a combination thereof, as described herein). More specifically, the timer / logic 218 of the low-driver controller 152 can determine the operating mode of the high-side switch SW2.

[0159] The foregoing detailed description of the invention is provided for illustrative purposes and is not exhaustive or intended to limit the invention to the disclosed embodiments. Therefore, the scope of the invention is defined by the appended claims.

Claims

1. A controller configured to control a power converter, the power converter having a transformer, a low-side switch for drawing current from a power supply voltage through the primary winding of the transformer, and a high-side switch for coupling the primary winding of the transformer to a snubber capacitor, wherein, The controller is configured to generate a drive signal that controls the low-side switch to open and close once in each cycle of a series of switching cycles to form an adjusted output voltage, and wherein the controller is configured to selectively control the high-side switch in such a way as: An operating mode in which the high-side switch closes and then opens once in each cycle of a series of switching cycles; and An operating mode in which the high-side switch closes and then opens twice in each cycle of a series of switching cycles. The controller is configured to select between an operating mode in which the high-side switch closes and then opens once in each of the series of switching cycles, and an operating mode in which the high-side switch closes and then opens twice in each of the series of switching cycles, depending on the power level supplied to the load.

2. The controller according to claim 1, wherein, The controller is configured to control a flyback converter that performs DC-to-DC power conversion.

3. The controller according to claim 1, wherein, The controller is configured to control the power converter such that an output voltage is formed by the current induced in the secondary winding of the transformer, and wherein the output voltage is adjusted in a feedback loop.

4. The controller according to claim 1, wherein, The controller is configured to select an operating mode in which the high-side switch closes and then opens twice in each of the series of switching cycles when the power level delivered to the load is low.

5. The controller according to claim 1, wherein, The controller is configured to monitor a first voltage generated at the node between the low-side switch and the high-side switch to determine the timing for closing and opening the high-side switch.

6. The controller according to claim 5, characterized in that, in, When the operating mode in which the high-side switch closes and then opens once in each cycle of the series of switching cycles is selected, the high-side switch closes when the level of the first voltage drops.

7. The controller according to claim 5, characterized in that, in, When the operating mode in which the high-side switch closes and then opens once in each cycle of the series of switching cycles is selected, the high-side switch closes when the level of the first voltage rises.

8. The controller according to claim 5, wherein, The high-side switch is closed according to the zero-volt switch.

9. The controller according to claim 1, wherein, The controller is also configured to select between an operating mode in which the high-side switch is closed and then opened once in each of the series of switching cycles, and an operating mode in which the high-side switch is closed and then opened twice in each of the series of switching cycles, based on the level of the line voltage that can be used as the input to the power converter.

10. A switching power supply, comprising: The controller according to claim 1; And a power converter, which includes the transformer, the low-side switch, the high-side switch and the buffer capacitor.

11. A controller configured to control a power converter having a transformer, a low-side switch for drawing current from a power supply voltage through the primary winding of the transformer, and a high-side switch for coupling the primary winding of the transformer to a snubber capacitor, wherein a first voltage is generated at a node between the low-side switch and the high-side switch, and wherein the controller is configured to generate a drive signal that controls the opening and closing of the low-side switch to form an adjusted output voltage, and wherein... The controller is configured to operate selectively in the following modes: Based on the comparison between the power supply voltage and the first voltage, the closing mode of the high-side switch in each cycle of a series of switching cycles, and In each cycle of a series of switching cycles, the high-side switch remains open, thereby enabling passive rectification of the current passing through the high-side switch by the body diode of the high-side switch. And among them, The controller is configured to select between operating modes based on the level of the power supply voltage or the load power.

12. The controller according to claim 11, wherein, The controller is configured to control a flyback converter that performs DC-to-DC power conversion.

13. The controller according to claim 11, wherein, The controller is configured to control the power converter such that an output voltage is formed by the current induced in the secondary winding of the transformer, and wherein the output voltage is adjusted in a feedback loop.

14. The controller according to claim 11, wherein, The controller includes a high-side driver controller configured to control the high-side switch, wherein a signal notifies the high-side driver controller that it has permission to close the high-side switch.

15. The controller according to claim 14, wherein, The controller includes a low-side driver controller configured to control the low-side switch, wherein the low-side driver controller and the high-side driver controller have different ground reference voltages, and wherein a signal notifying the high-side driver controller that the high-side driver controller has permission to close the high-side switch is transmitted by the low-side driver to the high-side driver controller via a differential signal.

16. A switching power supply, comprising: The controller according to claim 11; And a power converter, which includes the transformer, the low-side switch, the high-side switch and the buffer capacitor.

17. A controller configured to control a power converter having a transformer, a low-side switch for drawing current from a power supply voltage through the primary winding of the transformer, and a high-side switch for coupling the primary winding of the transformer to a buffer capacitor, wherein a first voltage is generated at a node between the low-side switch and the high-side switch, and wherein the controller is configured to generate a drive signal that controls the opening and closing of the high-side switch to form an adjusted output voltage. The controller is configured to operate selectively in the following modes: Based on the comparison between the power supply voltage and the first voltage, the closing mode of the high-side switch in each cycle of a series of switching cycles, and In response to a pulse signal, the high-side switch closes in the following pattern during each cycle of a series of switching cycles: Furthermore, the controller selects between operating modes based on the level of the power supply voltage or the load power.

18. The controller according to claim 17, wherein, The controller is configured to control a flyback converter that performs DC-to-DC power conversion.

19. The controller according to claim 17, wherein, The controller is configured to control the power converter such that an output voltage is formed by the current induced in the secondary winding of the transformer, and wherein the output voltage is adjusted in a feedback loop.

20. The controller according to claim 17, wherein, The controller includes: a low-side driver controller configured to control the low-side switch; and a high-side driver controller configured to control the high-side switch, wherein the low-side driver controller and the high-side driver controller have different ground reference voltages, and a signal notifying the high-side driver controller that the high-side driver controller has permission to close the high-side switch, the signal being transmitted from the low-side driver to the high-side driver controller via a differential signal.

21. The controller according to claim 17, wherein, The duration of the pulse signal determines the duration of the high-side switch closure.

22. The controller according to claim 21, wherein, The duration of the pulse signal determines the duration of the high-side switch closure.

23. The controller according to claim 17, wherein, The duration of the pulse signal depends on the level of the power supply voltage.

24. The controller according to claim 23, wherein, The duration of the pulse signal can be adjusted by adjusting the resistor value.

25. A switching power supply, comprising: The controller according to claim 17; And a power converter, which includes the transformer, the low-side switch, the high-side switch and the buffer capacitor.

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