Method for manufacturing low-voltage discharge tube chip

Abstract

A method for manufacturing a low-voltage discharge tube chip. Before forming an anode layer, an anode buried layer is formed. The anode buried layer is located on a part of the surface of the substrate layer. The second conductive type impurity ions are injected into the anode buried layer region to a depth of a first thickness, and then an anode layer, a cathode layer and an isolation layer are formed. Since the discharge tube chip is a PNPN structure, concentration superposition is continuously performed during the formation process, so the doping concentration of the substrate layer is relatively the lightest and the impedance is the highest. In the present invention, the anode buried layer is arranged inside the substrate, so that the length of the N-type substrate layer with high impedance can be reduced, that is, the total length of the part with high impedance is reduced, so that the impedance of the discharge tube chip is reduced, and then the conduction voltage drop is reduced, thereby improving the performance of the low-voltage discharge tube chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for manufacturing a low-voltage discharge tube chip. Background Art

[0002] TSS (Thyristor Surge Suppressor, voltage switching transient suppression diode) is also called semiconductor discharge tube, or solid discharge tube, etc. As a surge protection device, TSS can not only absorb the induced voltage generated by lightning and power on and off, but also absorb the overvoltage caused by accidental contact or wrong operation between high-voltage lines and signal lines, which is of great significance. Its working principle is similar to that of a gas discharge tube. It is connected in parallel with the protected circuit. When the overvoltage at both ends of TSS exceeds the breakdown voltage of TSS, TSS clamps the overvoltage to a potential lower than the breakdown voltage. At this time, this lower potential can be called the conduction voltage drop. The conduction voltage drop should be close to 0V, so that the line where the TSS device is located is short-circuited. TSS continues the short-circuit state under this conduction voltage drop until the overcurrent flowing through TSS drops below the critical value, and TSS returns to the open circuit state. However, the actual conduction voltage drop of TSS devices cannot reach 0V. The conduction voltage drop of current TSS devices is generally 1V-3V. For some circuits, the surge protection capability is still limited.

[0003] Therefore, a method for manufacturing a low-voltage discharge tube chip that can lower the conduction voltage drop is needed to make it have better protection performance. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a method for manufacturing a low-voltage discharge tube chip, which can reduce the conduction voltage drop of the low-voltage discharge tube and make its performance better.

[0005] According to the first aspect, an embodiment provides a method for manufacturing a low-voltage discharge tube chip, comprising:

[0006] A substrate layer of a first conductivity type is provided, wherein the substrate layer has a first surface and a second surface opposite to the first surface, and a device layer is formed on the first surface of the substrate layer, wherein the step of forming the device layer comprises:

[0007] defining an anode buried layer region, the anode buried layer region being located on a portion of the surface of the substrate layer, and implanting impurity ions of the second conductivity type at a depth of a first thickness into the anode buried layer region to form an anode buried layer of the first thickness;

[0008] Implanting impurity ions of a second conductivity type into the first surface of the substrate layer at a depth of a second thickness to form an anode layer of a second thickness, wherein the second thickness is less than the first thickness;

[0009] Defining a cathode region on the anode region, and injecting impurity ions of a first conductivity type into the cathode region to form a cathode layer, wherein the thickness of the cathode layer is less than the thickness of the anode layer;

[0010] defining an isolation region, performing an etching process on the isolation region to form an isolation layer, and covering the isolation layer with a passivation material;

[0011] An electrode layer is formed on the upper surface of the anode region.

[0012] Optionally, before forming the anode layer, the method further includes the following steps:

[0013] A heavily doped region is defined, and impurity ions of the first conductivity type are injected into the heavily doped region to form a heavily doped layer, wherein the injection depth of the heavily doped layer is greater than the thickness of the anode layer.

[0014] Optionally, injecting impurity ions of the first conductivity type into the location of the heavily doped region includes: injecting impurity ions of the first conductivity type at a concentration of 1×1019 / cm3-1×1021 / cm3 into the location of the heavily doped region.

[0015] Optionally, the anode buried layer is single and located on one side of the substrate layer, and the heavily doped layer is single and located on the other side of the substrate layer.

[0016] Optionally, there are multiple heavily doped layers, which are evenly distributed around the substrate layer.

[0017] Optionally, there are multiple buried anode layers, which are evenly distributed around the substrate.

[0018] Optionally, it also includes: forming a device layer on the second surface of the substrate layer, the structure of the device layer on the second surface is the same as the structure of the device layer on the first surface, and the manufacturing method of the device layer on the second surface is the same as the manufacturing method of the device layer on the first surface.

[0019] Optionally, the sheet resistivity of the anode layer is 1 ohm / □-10 ohm / □.

[0020] Optionally, the doping concentration of the buried anode layer is greater than the doping concentration of the anode layer.

[0021] According to the manufacturing method of the low-voltage discharge tube chip of the above embodiment, since an anode buried layer is formed before forming the anode layer, the anode buried layer is located on a part of the surface of the substrate layer, and the second conductive type impurity ions are injected into the position of the anode buried layer region with a depth of the first thickness, and then the anode layer, the cathode layer and the isolation layer are further formed. Since the discharge tube chip is a PNPN structure, the concentration is continuously superimposed during the formation process, so the doping concentration of the substrate layer is relatively the lightest and the impedance is the highest. In the present invention, the anode buried layer is arranged inside the substrate so that the length of the N-type substrate layer with high impedance can be reduced, that is, the total length of the part with high impedance is reduced, so that the impedance of the discharge tube chip is reduced, and then the conduction voltage drop thereof is reduced, thereby improving the performance of the low-voltage discharge tube chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of a low-voltage discharge tube chip provided by an embodiment of the present invention;

[0023] Figure 2 A top view of a low-voltage discharge tube chip structure provided by an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of a structure for forming an anode buried layer in a method for manufacturing a low-voltage discharge tube chip provided in an embodiment of the present invention;

[0025] Figure 4 for Figure 3 a top view from the first surface;

[0026] Figure 5 A top view of a structure for forming an anode buried layer in a method for manufacturing a low-voltage discharge tube chip provided by another embodiment of the present invention;

[0027] Figure 6 A schematic diagram of the structure of forming a heavily doped layer and an anode layer in a method for manufacturing a low-voltage discharge tube chip provided in an embodiment of the present invention;

[0028] Figure 7 A schematic diagram of a structure for forming a cathode layer in a method for manufacturing a low-voltage discharge tube chip provided in an embodiment of the present invention;

[0029] Figure 8 A schematic diagram of a structure for forming an isolation groove in a method for manufacturing a low-voltage discharge tube chip provided in an embodiment of the present invention;

[0030] Fig. 9 A schematic diagram of a structure for forming an isolation layer in a method for manufacturing a low-voltage discharge tube chip provided in an embodiment of the present invention;

[0031] Fig.10 A schematic structural diagram of forming an electrode layer in a method for manufacturing a low-voltage discharge tube chip provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0033] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0034] The serial numbers of the components in this document, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings).

[0035] It can be seen that the conduction voltage drop of the low-voltage discharge tube chip can affect the current of the circuit of the protected electrical device. If the conduction voltage drop of the low-voltage discharge tube chip is lower, the short-circuit effect of the circuit where the low-voltage discharge tube chip is located will be better, and the impact on the circuit where the protected electrical device is located will be smaller. Therefore, it is necessary to provide a low-voltage discharge tube chip with a lower conduction voltage drop, so as to improve the performance of the low-voltage discharge tube chip.

[0036] The low-voltage discharge tube chip and the manufacturing method thereof in the present embodiment include a substrate layer having a first conductivity type and a device layer arranged on the substrate layer, wherein the device layer includes an anode layer located on the surface of the substrate layer and an anode buried layer extending into the interior of the substrate layer, wherein the anode layer and the anode buried layer both have a second conductivity type. Since the structure of the discharge tube chip is a PNPN type, the substrate layer is an N type and the doping concentration of impurity ions is relatively lightest and the impedance is highest, the provision of the anode buried layer can reduce the length of the N type substrate layer, thereby reducing the total length of the portion with high impedance, thereby reducing the impedance of the discharge tube chip, reducing the on-state voltage, allowing the TSS to play a protective role while reducing the on-state voltage drop, thereby improving the device performance.

[0037] refer to Figure 1 and Figure 2 This embodiment provides a low-voltage discharge tube chip, including: a substrate layer 10 and a device layer on the first surface 11 or the second surface 12 of the substrate layer 10.

[0038] In this embodiment, the substrate layer 10 is of the first conductivity type, has a thickness of 150 μm-250 μm, and has a first surface 11 and a second surface 12 opposite to the first surface 11. Device layers can be formed on both the first surface 11 and the second surface 12 of the substrate layer 10. When only one side is provided with a device layer, it can be a unidirectional semiconductor discharge tube (TSS), and when both sides are provided with a device layer, it can be a bidirectional TSS. In the bidirectional TSS, the structures of the device layers on the first surface 11 and the second surface 12 are the same.

[0039] The device layer includes: an anode buried layer 101 , an anode layer 103 , an electrode layer 300 , a cathode layer 104 and an isolation layer 201 .

[0040] The buried anode layer 101 is of the second conductivity type and extends from part of the first surface 11 into the interior of the substrate layer 10, and the depth is the first thickness. It can be seen that in the process of forming a PN junction of the TSS device, a higher concentration superposition is required, so the ion doping concentration of the substrate layer 10 is relatively the lowest and the impedance is the highest. Since the buried anode layer 101 is provided in the substrate layer 10, the length of the substrate layer 10 with a relatively low concentration is reduced, thereby reducing the impedance in the substrate layer 10 and reducing the conduction voltage drop in the TSS.

[0041] In some embodiments, there are multiple buried anode layers 101 evenly distributed inside the substrate layer 10. The on-state voltage drop is adjusted by adjusting the number of buried anode layers 101. The even distribution of buried anode layers 101 can make the device more stable.

[0042] In this embodiment, the number of the anode buried layer 101 is single and is disposed on one side of the substrate layer.

[0043] The anode layer 103 is located on the first surface 11 and contacts the upper surface of the anode buried layer 101 , and is of the second conductivity type.

[0044] In this embodiment, the sheet resistivity of the anode layer is 1 ohm / □-10 ohm / □. The doping concentration of the buried anode layer is the same as the doping concentration of the anode layer.

[0045] In some embodiments, the doping concentration of the buried anode layer is greater than the doping concentration of the anode layer.

[0046] A metal electrode layer 300 is disposed on the upper surface of the anode layer 103 , and can be used to form an electrical connection with an external circuit.

[0047] The cathode layer 104 is between the anode layer 103 and the metal layer, and the cathode layer 104 is of the first conductivity type.

[0048] In this embodiment, there are multiple cathode layers 104 . By adjusting the number of the cathode layers 104 , the relative relationship between the cathode layer 104 and the anode layer 103 can be adjusted, so that the maintaining current can be controlled.

[0049] In this embodiment, the relationship between the cathode layer 104 and the anode layer 103 is adjusted so that the current is maintained at 50 mA-300 mA.

[0050] In this embodiment, a heavily doped layer 102 is further included, and the heavily doped layer 102 is located between the isolation layer 201 and the anode region and extends to the surface or the inside of the substrate. The heavily doped layer 102 is of the first conductivity type, and the doping concentration of the heavily doped layer 102 is greater than the doping concentration of the substrate layer 10.

[0051] It is understandable that the doping concentration of the substrate layer of the surge protection device usually determines the breakdown voltage of the low-voltage discharge tube chip. For example, the higher the doping concentration of the substrate layer, the lower the breakdown voltage of the protection device. In the circuit, a lower breakdown voltage is usually used to protect the circuit. However, in the process of manufacturing high-concentration silicon substrate chips, a higher concentration superposition is required to form a PN junction, which not only increases the manufacturing cost of the chip, but also increases the number of defects inside the device due to the high concentration of the silicon substrate, resulting in poor stability and controllability. However, in this embodiment, a heavily doped layer is provided between the isolation layer 201 and the anode region. Since the anode layer 103 has a second conductivity type, the substrate layer 10 and the heavily doped layer 102 have a first conductivity type, and the concentration of the first conductivity type impurity ions doped in the heavily doped region is greater than the concentration of the first conductivity type impurity ions in the substrate layer 10, the anode layer 103 first breaks down with the heavily doped region during the process of the voltage at both ends of the TSS gradually increasing, and then breaks down with the substrate layer 10 under the transient high voltage generated by the breakdown, so that even at a lower doping concentration, the substrate layer 10 can meet a lower breakdown voltage. Therefore, in this embodiment, in combination with the common structural effect of the heavily doped layer 102 and the anode buried layer 101, a substrate layer 10 with a lower doping concentration can be used, so as to achieve low capacitance and better stability and controllability, and at the same time, the TSS can also meet a low breakdown voltage and a low conduction voltage.

[0052] In this embodiment, the number of the heavily doped layer 102 is single, and the layer is disposed on the other side of the substrate relative to the anode buried layer 101 .

[0053] In some embodiments, the number of the heavily doped layers 102 is multiple, the width of the heavily doped layers 102 may be 10 μm-30 μm, and the multiple heavily doped layers 102 are evenly distributed, which can make the device more stable. By adjusting the concentration of the heavily doped layer 102, the concentration difference between the heavily doped layer 102 and the substrate layer 10 can be controlled. The impurity ion concentration of the heavily doped layer 102 may be 10 times the concentration of the doped ions in the substrate layer 10. 2 -10 6 times, and the breakdown voltage of the device is adjusted by adjusting the concentration difference between the heavily doped layer 102 and the substrate 10.

[0054] In this embodiment, since the heavily doped layer 102 is formed before the anode layer 103 is formed or simultaneously with the anode layer 103, the concentration of the heavily doped layer 102 can be higher, up to 1×10 19 Pieces / cm 3 -1×10 21 Pieces / cm 3, thus obtaining a TSS device with lower breakdown voltage and lower capacitance.

[0055] The isolation layer 201 surrounds the outer periphery of the anode layer 103 and extends to the interior of the substrate layer 10, so that the internal area surrounded by the isolation layer 201 is the effective device area of ​​the TSS device. The isolation layer 201 in this embodiment is a mesa-type isolation groove, which makes the effective device area of ​​the TSS device large and the utilization rate high.

[0056] The isolation layer 201 structure includes an isolation groove and a passivation material on the surface of the isolation groove, and the passivation material is a glass powder insulating material. The isolation layer 201 is in contact with the anode layer 103 and the substrate layer 10 at the same time, that is, the depth of the isolation layer 201 is greater than the thickness of the anode layer 103, so that the anode area has no electrical connection with the outside world, which serves as a terminal protection of the PN junction. When the TSS device process is completed, a single TSS device can be prepared by slicing along the bottom of the isolation layer 201.

[0057] In this embodiment, the first conductivity type is N-type, that is, the semiconductor material is doped with N-type conductive impurity ions to make the semiconductor material an electron conductive semiconductor, and the second conductivity type is P-type, that is, the semiconductor material is doped with P-type conductive impurity ions to make the semiconductor material a hole conductive semiconductor, wherein the N-type conductive impurity ions are N-type impurity ions, such as arsenic ions, phosphorus ions, etc., and the P-type conductive impurity ions are P-type impurity ions, such as boron ions.

[0058] refer to Figures 3 to 10 In this embodiment, a method for manufacturing TSS is provided. The cross-sectional structure diagram of the bidirectional TSS is shown in Figure 1 As shown, the bidirectional TSS includes a substrate layer 10 having a first conductivity type, the substrate layer 10 having a first surface 11 and a second surface 12 opposite to the first surface 11, a first device 110 and a second device layer 120 are formed on the first surface 11 and the second surface 12 of the substrate layer 10, the two device layers are symmetrically arranged, and the preparation method is the same. The steps of forming the device layer are as follows:

[0059] Step 1, providing a substrate layer 10, defining an anode buried layer 101 region on a portion of the first surface 11, and injecting impurity ions of a second conductivity type into the anode buried layer 101 region to form an anode buried layer 101 of a first thickness.

[0060] Specifically, a silicon substrate layer 10 with a low concentration of N-type impurity ions is provided, and a first oxide layer is grown on its first surface 11, where the first oxide layer may be silicon oxide, and then a buried anode layer 101 region is defined on the first oxide layer using photolithography and wet etching methods, and boron source impurity ions are injected into the buried anode layer 101 region using the first oxide layer as a mask.

[0061] In this embodiment, an anode buried layer 101 region is defined on one side of the substrate layer, for example, Figure 3 and Figure 5 ,in, Figure 3 is a schematic top view of some structures in the provided manufacturing method, Figure 5 yes Figure 3 The cross-sectional view only defines the anode buried layer 101 region on the right side of the first surface in the figure.

[0062] In some embodiments, reference may be made to Figure 4 , Figure 4 It is a schematic top view of a part of the structure in the manufacturing method provided in some embodiments, wherein the defined anode buried layer 101 area can be evenly distributed around the substrate layer.

[0063] Step 2, reference Figure 6 , impurity ions of a second conductivity type are implanted into the first surface 11 of the substrate layer 10 to form an anode layer 103 of a second thickness, wherein the second thickness is less than the first thickness.

[0064] Before implanting impurity ions of the second conductivity type into the first surface 11 , the first oxide layer needs to be removed.

[0065] In this embodiment, the substrate layer 10 is doped with dopant ions of the second conductivity type, for example, by implanting boron ions, so as to form the anode layer 103 on the surface of the substrate layer 10. The resistivity of the anode layer 103 may be 1 ohm / □-10 ohm / □.

[0066] It should be noted that in order to prepare the second device layer 120, the second conductive type of impurity ions can be doped on the second surface 12 to form an anode buried layer 101 and an anode layer 103 on the second surface 12. Since the preparation method of the second device layer 120 is the same as the preparation method of the first device layer 110, it will not be repeated below.

[0067] In this embodiment, before forming the anode layer 103, a heavily doped region is defined, that is, the first conductive type of impurity ions can be injected into the heavily doped region to form a heavily doped layer 102. In this way, since the substrate layer 10 is a low-concentration N-type substrate before the anode layer 103 is formed, a higher concentration of doping can be achieved, thereby forming a heavily doped region with a doping concentration several times that of the substrate layer 10.

[0068] In some embodiments, after the heavily doped region is defined, the first conductivity type impurity ion injection into the heavily doped region and the second conductivity type impurity ion injection into the heavily doped region except the heavily doped region may be simultaneously completed. The first conductivity type impurity ion injection into the heavily doped region is performed to form a heavily doped layer 102, and the second conductivity type impurity ion injection into the heavily doped region except the heavily doped region is performed to form an anode layer 103. In this way, the second conductivity type impurity ion can also be diffused at a higher concentration in the heavily doped region.

[0069] It should be noted that by adjusting the concentration relationship between the anode layer 103 and the heavily doped layer 102, TSS devices with different breakdown voltages can be formed according to their respective concentrations. The higher the injection concentration of the heavily doped region, the lower the breakdown voltage of the TSS device. The structure in this embodiment enables the concentration of the heavily doped layer 102 to reach 1×10 19 Pieces / cm 3 -1×10 21 Pieces / cm 3 .

[0070] In this embodiment, the heavily doped layer 102 is formed in a single layer and is disposed on the other side of the substrate relative to the buried anode layer 101 .

[0071] In some embodiments, the number of the heavily doped layers 102 is multiple, the width of the heavily doped layers 102 may be 10 μm-30 μm, and the multiple heavily doped layers 102 are evenly distributed, which can make the device more stable. By adjusting the concentration of the heavily doped layer 102, the concentration difference between the heavily doped layer 102 and the substrate layer 10 can be controlled. The impurity ion concentration of the heavily doped layer 102 may be 10 times the concentration of the doped ions in the substrate layer 10. 2 -10 6 times, and the breakdown voltage of the device is adjusted by adjusting the concentration difference between the heavily doped layer 102 and the substrate 10.

[0072] It should be noted that the concentrations of diffusion performed when forming the anode buried layer and the anode layer may be the same or different.

[0073] In this embodiment, the concentration of the second conductivity type impurity ions doped into the buried anode layer is the same as the concentration of the second conductivity type impurity ions doped into the anode layer.

[0074] Step 3, reference Figure 7 A cathode region is defined on the anode region, and impurity ions of the first conductivity type are implanted into the cathode region to form a cathode layer 104 , wherein the thickness of the cathode layer 104 is less than the thickness of the anode layer 103 .

[0075] Specifically, a second oxide layer is produced on the upper surface of the anode region, and the second oxide layer may be silicon oxide. Then, a cathode region is defined on the second oxide layer by photolithography and wet etching methods. The second oxide layer is used as a mask to inject N-type impurity ions such as arsenic ions and phosphorus ions into the cathode region.

[0076] Step 4, reference Figure 8 and Fig. 9 , define an isolation layer 201 region, perform an etching process on the isolation layer 201 region to form an isolation trench 200 , and form a passivation material in the isolation trench 200 to form an isolation layer 201 .

[0077] Specifically, after removing the second oxide layer, a photomask is used to define the isolation layer 201 region, and the isolation trench 200 is etched under the mask of the photomask, wherein the depth of the isolation trench 200 is greater than the thickness of the anode layer 103 .

[0078] In some embodiments, an etching solution is used to etch the isolation trench 200 under the mask of the photomask, and the etching solution is a mixed solution of nitric acid, hydrofluoric acid and glacial acetic acid.

[0079] Furthermore, the isolation trench 200 is filled with a passivation material, for example, polysilicon, silicon dioxide and glass coating can be used for passivation, which has the advantages of high reliability and moisture resistance.

[0080] Step 5, reference Fig.10 An electrode layer 300 is formed on the surface of the anode layer 103 , and the plurality of cathode layers 104 are located between the electrode layer 300 and the anode layer 103 .

[0081] In this embodiment, metal or metal alloy is formed on the upper surface of the anode layer 103 as the electrode layer 300. The covering area of ​​the electrode layer 300 is in contact with the packaging support.

[0082] In some embodiments, the second device layer 120 has the same structure as the first device layer 110 and can be prepared using the method for preparing the first device layer 110. After the first device layer 110 and the second device layer 120 are prepared, the prepared devices are packaged to obtain a bidirectional TSS device.

[0083] Compared with the conventional device, the TSS device manufactured in this embodiment can meet the performance of low voltage and low capacitance due to the provision of the heavily doped layer 102, thereby meeting the requirements of stability and controllability. In addition, since the heavily doped layer 102 in the manufacturing method is formed before the anode layer 103 is formed, the injection concentration of the heavily doped region can be further increased, and the breakdown voltage can be below 5V. In addition, the coordinated arrangement of the heavily doped layer 102 and the anode buried layer 101 enables the TSS device to meet the requirements of stability and controllability while also having the performance of lower on-state voltage drop. The on-state voltage drop of the low-voltage discharge tube chip manufactured by the device can be as low as below 1.2V, and the protection capability for the protected device is better.

[0084] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.

Claims

1. A method for manufacturing a low-voltage discharge tube chip, characterized in that: include: A substrate layer of a first conductivity type is provided, wherein the substrate layer has a first surface and a second surface opposite to the first surface, and a device layer is formed on the first surface of the substrate layer, wherein the step of forming the device layer comprises: An anode buried layer region is defined, the anode buried layer region is located on a portion of the surface of the substrate layer, and impurity ions of the second conductivity type are injected into the anode buried layer region to form an anode buried layer; the anode buried layer region is evenly distributed around the substrate layer; Implanting impurity ions of a second conductivity type into the first surface of the substrate layer to a depth of a second thickness to form an anode layer, wherein the second thickness is less than the first thickness; Defining a cathode region on the anode layer, and injecting impurity ions of a first conductivity type into the cathode region to form a cathode layer, wherein the thickness of the cathode layer is less than the thickness of the anode layer; defining an isolation region, performing an etching process on the isolation region to form an isolation layer, and covering the isolation layer with a passivation material; forming an electrode layer on the upper surface of the anode layer; The method further comprises, before forming the anode layer, the following steps: Defining a heavily doped region, and injecting impurity ions of the first conductivity type into the heavily doped region to form a heavily doped layer, wherein the injection depth of the heavily doped layer is greater than the thickness of the anode layer; Wherein, in forming the anode layer, the second conductive type impurity ions are implanted into the region except the heavily doped region to form the anode layer.

2. The manufacturing method according to claim 1, characterized in that Injecting impurity ions of the first conductivity type into the heavily doped region comprises: injecting impurity ions of a concentration of 1×10 19 Pieces / cm 3 -1×10 21 Pieces / cm 3 impurity ions of the first conductivity type.

3. The manufacturing method according to claim 1, characterized in that: The anode buried layer is single and located on one side of the substrate layer, and the heavily doped layer is single and located on the other side of the substrate layer.

4. The manufacturing method according to claim 1, characterized in that: There are multiple heavily doped layers, which are evenly distributed around the substrate layer.

5. The manufacturing method according to claim 1, characterized in that: The number of the anode buried layers is multiple and evenly distributed around the substrate.

6. The manufacturing method according to claim 1, characterized in that: Also includes: A device layer is formed on the second surface of the substrate layer, the structure of the device layer on the second surface is the same as that of the device layer on the first surface, and the manufacturing method of the device layer on the second surface is the same as that of the device layer on the first surface.

7. The manufacturing method according to claim 1, characterized in that: The sheet resistivity of the anode layer is 1 ohm / □-10 ohm / □.

8. The manufacturing method according to claim 1, characterized in that: The doping concentration of the buried anode layer is greater than the doping concentration of the anode layer.

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