Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device having a silicon film for a diode formed on a semiconductor substrate via an insulating film, and a first wiring and a second wiring formed on an upper layer of the silicon film, and a manufacturing method thereof. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Japanese Patent Application No. 2020-104950, filed on June 18, 2020, the contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices and methods of manufacturing the same, and is applicable to, for example, semiconductor devices having diodes and methods of manufacturing the same. Background Technology

[0004] In semiconductor devices with field-effect transistors (FETs) such as power MOSFETs (metal-oxide-semiconductor field-effect transistors) that carry large currents, techniques are known to provide temperature detection to protect the FETs from overheating. For example, this temperature detection can be achieved by placing a diode near the FET and detecting the voltage generated in that diode. In this case, the forward current-voltage characteristic of the diode varies with temperature.

[0005] Japanese Patent Application Publication No. 2011-187650 (Patent Document 1) discloses technology related to a semiconductor device including a power MOSFET and a diode for temperature detection. Summary of the Invention

[0006] The goal is to improve the reliability of semiconductor devices with diodes.

[0007] Other objects and novel features of the invention will be apparent from the description in this specification and the accompanying drawings.

[0008] According to one embodiment, a semiconductor device includes: a semiconductor substrate; a silicon film for a diode, the silicon film being formed on the semiconductor substrate via a first insulating film; and a first electrode and a second electrode for the diode, the first electrode and the second electrode being formed on an upper layer of the silicon film. The silicon film has a first silicon region of a first conductivity type and a plurality of second silicon regions of a second conductivity type opposite to the first conductivity type. In a plan view, each of the plurality of second silicon regions is surrounded by a first silicon region. The first silicon region is electrically connected to the first electrode, and the plurality of second silicon regions are electrically connected to the second electrode.

[0009] According to one embodiment, a semiconductor device has a semiconductor substrate and a silicon film for a diode, the silicon film being formed on the semiconductor substrate via a first insulating film. The silicon film has a first silicon region of a first conductivity type and a second silicon region of a second conductivity type opposite to the first conductivity type. In a plan view, the second silicon region is surrounded by the first silicon region. The second silicon region is exposed on the upper surface of the silicon film, and the first silicon region is located below the second silicon region.

[0010] According to one implementation method, the reliability of a semiconductor device can be improved. Attached Figure Description

[0011] Figure 1 This is a plan view of a semiconductor device according to one embodiment.

[0012] Figure 2 This is a plan view of the main parts of a semiconductor device according to one embodiment.

[0013] Figure 3 This is a plan view of the main parts of a semiconductor device according to one embodiment.

[0014] Figure 4 This is a cross-sectional view of the main part of a semiconductor device according to one embodiment.

[0015] Figure 5 This is a cross-sectional view of the main part of a semiconductor device according to one embodiment.

[0016] Figure 6 This is a cross-sectional view of the main part of a semiconductor device according to one embodiment.

[0017] Figure 7 This is a plan view of the main parts of a semiconductor device, presented as a discussion example.

[0018] Figure 8 This is a cross-sectional view of the main parts of a semiconductor device in the form of a review example.

[0019] Figure 9 This is a graph showing the characteristics of a diode.

[0020] Figure 10 This is a graph showing the characteristics of a diode.

[0021] Figure 11 It is a cross-sectional view of the main part of a semiconductor device according to one embodiment during the manufacturing process.

[0022] Figure 12 It is during the manufacturing process and Figure 11 A cross-sectional view of the main parts of the same semiconductor device.

[0023] Figure 13 Is Figure 11 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0024] Figure 14 It is during the manufacturing process and Figure 13 A cross-sectional view of the main parts of the same semiconductor device.

[0025] Figure 15 Is Figure 13 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0026] Figure 16 It is during the manufacturing process and Figure 15 A cross-sectional view of the main parts of the same semiconductor device.

[0027] Figure 17 Is Figure 15 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0028] Figure 18 It is during the manufacturing process and Figure 17 A cross-sectional view of the main parts of the same semiconductor device.

[0029] Figure 19 Is Figure 17 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0030] Figure 20 It is during the manufacturing process and Figure 19 A cross-sectional view of the main parts of the same semiconductor device.

[0031] Figure 21 Is Figure 19 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0032] Figure 22 It is during the manufacturing process and Figure 21 A cross-sectional view of the main parts of the same semiconductor device.

[0033] Figure 23 Is Figure 21 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0034] Figure 24 It is during the manufacturing process and Figure 23 A cross-sectional view of the main parts of the same semiconductor device.

[0035] Figure 25 Is Figure 23 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0036] Figure 26 It is during the manufacturing process and Figure 25 A cross-sectional view of the main parts of the same semiconductor device.

[0037] Figure 27 Is Figure 25 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0038] Figure 28 It is during the manufacturing process and Figure 27 A cross-sectional view of the main parts of the same semiconductor device.

[0039] Figure 29 Is Figure 27 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0040] Figure 30 It is during the manufacturing process and Figure 29 A cross-sectional view of the main parts of the same semiconductor device.

[0041] Figure 31 Is Figure 29 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0042] Figure 32 It is during the manufacturing process and Figure 31 A cross-sectional view of the main parts of the same semiconductor device.

[0043] Figure 33 It is a plan view of the main parts of a semiconductor device based on a modified example.

[0044] Figure 34 It is a plan view of the main parts of a semiconductor device based on a modified example.

[0045] Figure 35 It is a cross-sectional view of the main part of a semiconductor device based on a modified example.

[0046] Figure 36 This is a plan view of the main part of a semiconductor device according to another embodiment.

[0047] Figure 37 This is a plan view of the main part of a semiconductor device according to another embodiment.

[0048] Figure 38 This is a cross-sectional view of the main part of a semiconductor device according to another embodiment.

[0049] Figure 39 This is a cross-sectional view of the main part of a semiconductor device according to another embodiment.

[0050] Figure 40 This is a cross-sectional view of the main part of a semiconductor device according to another embodiment during the manufacturing process.

[0051] Figure 41 It is during the manufacturing process and Figure 40 A cross-sectional view of the main parts of the same semiconductor device.

[0052] Figure 42 Is Figure 40 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0053] Figure 43 It is during the manufacturing process and Figure 42 A cross-sectional view of the main parts of the same semiconductor device.

[0054] Figure 44 Is Figure 42 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0055] Figure 45 It is during the manufacturing process and Figure 44 A cross-sectional view of the main parts of the same semiconductor device.

[0056] Figure 46 Is Figure 44 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0057] Figure 47 It is during the manufacturing process and Figure 46 Cross-sectional view of the main part of the same semiconductor device.

[0058] Figure 48 Is Figure 46 Cross-sectional view of the main parts of the semiconductor device during the subsequent manufacturing process.

[0059] Figure 49 It is during the manufacturing process and Figure 48 Cross-sectional view of the main part of the same semiconductor device.

[0060] Figure 50 This is a plan view of the main parts of a semiconductor device according to yet another embodiment.

[0061] Figure 51 This is a plan view of the main parts of a semiconductor device according to yet another embodiment.

[0062] Figure 52 This is a cross-sectional view of the main part of a semiconductor device according to yet another embodiment.

[0063] Figure 53 This is a cross-sectional view of the main part of a semiconductor device according to yet another embodiment. Detailed Implementation

[0064] In the embodiments described below, for convenience, the invention will be described in multiple parts or embodiments as needed. However, unless otherwise stated, these parts or embodiments are not unrelated to each other, and one relates to all or part of another as an example of modification, detail, or supplement to its description. Furthermore, in the embodiments described below, when referring to the number of elements (including number of pieces, values, quantities, ranges, etc.), the number of elements is not limited to a specific number unless otherwise stated or clearly limited in principle to a specific number, and numbers greater than or less than a specific number also apply. Moreover, in the embodiments described below, it is self-evident that components (including element steps) are not always indispensable unless otherwise stated or unless the component is clearly indispensable in principle. Similarly, in the embodiments described below, when referring to the shape of parts, their positional relationships, etc., unless otherwise stated or unless it can be imagined that they are clearly excluded in principle, this includes substantially similar and similar shapes, etc. The same applies to the aforementioned values ​​and ranges.

[0065] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that throughout the drawings used to describe the embodiments, components having the same function are indicated by the same reference numerals, and repeated descriptions will be omitted. Furthermore, unless specifically required in the following embodiments, descriptions of the same or similar parts will generally not be repeated.

[0066] Furthermore, in some of the figures used in the following embodiments, even in the cross-sectional views, the shading lines have been omitted to make the figures easier to read. Additionally, shading lines have been used even in the plan views to make the figures easier to read.

[0067] In this application, field-effect transistors are described as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) or simply MOS, but non-oxide films as gate insulating films are not excluded. The aforementioned MOSFETs are not limited to cases where the gate insulating film is formed of an oxide film, and are assumed to include MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors) where the gate insulating film is extensively formed of an insulating film. That is, although the term MOSFET is used here for convenience, it is also used herein as a term intended to include MISFETs. Therefore, in the following description, MOSFET can be used instead of MISFET.

[0068] (First Implementation)

[0069] <Structure of Semiconductor Devices>

[0070] A semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. Figure 1 This is a plan view of the semiconductor device (semiconductor chip) CP according to this embodiment. Figure 1 An overall plan view of the upper surface side of the semiconductor device CP is shown. Figure 2 and Figure 3 Each of these is a plan view of the main portion of the semiconductor device CP according to this embodiment, and a plan view of the diode forming region RG1 is shown. Note that... Figure 2 and Figure 3 The same planar region is shown. Figure 2 The silicon film SF is shown, where the n-type silicon region NS and the p-type silicon region PS are represented by shaded lines. Figure 3 yes Figure 2 The image further includes views of contact holes CTA and CTC, as well as wirings M1A and M1C; contact holes CTA and CTC are indicated by dashed lines; and wirings M1A and M1C are indicated by double-dotted lines. Figure 3 No shading was used. Figures 1 to 3 The X and Y directions shown are generally parallel to the main surface of the semiconductor substrate SUB that constitutes the semiconductor device CP, and the X and Y directions are intersecting each other (more specifically, orthogonal to each other). Figures 4 to 6 Each of these is a cross-sectional view of a major part of the semiconductor device CP according to this embodiment.

[0071] Figures 1 to 6 The semiconductor device CP shown in this embodiment is a semiconductor device including a diode and a power MOSFET. In the semiconductor device CP, the region (planar region) where the diode DD is formed is called the diode forming region RG1, and the region (planar region) where the power MOSFET is formed is called the MOSFET forming region RG2. In the semiconductor device CP, the MOSFET forming region RG2 occupies a considerable area. Figure 4 and Figure 5 This is a cross-sectional view of the diode formation region RG1. However, Figure 2 and Figure 3 Each cross-sectional view at position A1-A1 in the diagram essentially corresponds to Figure 4 Cross-sectional view in the middle, Figure 2 and Figure 3 Each cross-sectional view at position A2-A2 in the diagram basically corresponds to Figure 5 Cross-sectional view of the image. Figure 6 A partial cross-sectional view corresponding to the MOSFET formation region RG2.

[0072] The semiconductor substrate SUB constituting the semiconductor device CP has: an n-type impurity such as arsenic (as) introduced into it. +The semiconductor substrate SUB is a substrate body (semiconductor substrate, semiconductor wafer) SB made of, for example, n-type single crystal silicon; and an epitaxial layer (semiconductor layer) EP made of, for example, n-type single crystal silicon and formed on the main surface of the substrate body SB. Therefore, the semiconductor substrate SUB is a so-called epitaxial wafer.

[0073] In the MOSFET formation region RG2, multiple unit transistor cells constituting a power MOSFET are formed on the semiconductor substrate SUB, and the power MOSFET is formed by connecting these multiple unit transistor cells disposed in parallel in the MOSFET formation region RG2. Each unit transistor cell is formed by, for example, an n-channel power MOSFET having a trench gate structure.

[0074] The semiconductor substrate SUB functions as the drain region of the aforementioned unit transistor cell. A back electrode BE for the drain is formed on the entire back side of the semiconductor substrate SUB. The back electrode BE serves as the drain terminal (drain electrode) of the power MOSFET.

[0075] Note that in a semiconductor substrate SUB, the main surface on the side opposite to the side on which the trench for the trench gate electrode TG is formed is called the back surface of the semiconductor substrate SUB.

[0076] A p-type semiconductor region PR is formed in the semiconductor substrate SUB within the MOSFET formation region RG2, and this p-type semiconductor region PR functions as the channel formation region of the aforementioned unit transistor cell (see [link]). Figure 6 ).

[0077] Furthermore, in the semiconductor substrate SUB within the MOSFET formation region RG2, an n-type semiconductor region PR is formed. + Type semiconductor region NR, and the n + The type semiconductor region NR functions as the source region (semiconductor region for the source) of the aforementioned unit transistor cell (see [reference]). Figure 6 ). In n + Below the n-type semiconductor region NR, there exists a p-type semiconductor region PR. The semiconductor substrate SUB in the portion between the p-type semiconductor region PR and the back electrode BE maintains the n-type conductivity type and functions as the drain region of the aforementioned unit transistor cell.

[0078] like Figure 6As shown, a trench TR extending from the main surface of the semiconductor substrate SUB along the thickness direction of the semiconductor substrate SUB is formed in the MOSFET formation region RG2, and the trench gate electrode TG is embedded in the trench TR via a gate insulating film GF. Since the gate insulating film GF, made of an insulating film such as silicon oxide, is formed on the bottom and side surfaces of the trench TR, the gate insulating film GF is inserted between the trench gate electrode TG embedded in the trench TR and the semiconductor substrate SUB. The trench gate electrode TG is made of a conductive film embedded in the trench TR of the semiconductor substrate SUB, and is made of, for example, a doped polysilicon film. Although not shown, in the plan view, the trench TR is formed on the main surface of the semiconductor substrate SUB, for example, in a strip or lattice pattern. The trench TR is formed to penetrate n from the upper surface of the semiconductor substrate SUB. + The trench consists of a p-type semiconductor region (NR) and a p-type semiconductor region (PR), terminating at an n-type semiconductor substrate (SUB) (epitaxy layer EP). Therefore, the bottom surface of the trench TR is larger than that of the n-type semiconductor substrate. + The bottom surface of the n-type semiconductor region NR is deeper than the bottom surface of the p-type semiconductor region PR, and is located in the middle of the depth direction of the n-type semiconductor substrate SUB (epitaxy layer EP). It should be noted that the planar view of the components of the semiconductor device CP corresponds to the view from a plane substantially parallel to the main surface of the semiconductor substrate SUB constituting the semiconductor device CP. Furthermore, the planar shape of the components of the semiconductor device CP corresponds to the shape in the planar view (planar shape).

[0079] Figure 6 Each trench TR and each trench gate electrode TG embedded therein are shown along a perpendicular line. Figure 6 The sheet extends in the direction of the material, but the trench gate electrode TG is integrally coupled to the sheet. Figure 6 The area not shown in the cross-sectional diagram.

[0080] In addition, such as Figures 2 to 5 As shown, the silicon film (semiconductor film) SF for the diode DD is formed on the semiconductor substrate SUB via an insulating film ZM within the diode forming region RG1. That is, the insulating film ZM is formed on the semiconductor substrate SUB, and the silicon film SF constituting the diode DD is formed on the insulating film ZM. More specifically, the silicon film SF is a polycrystalline silicon film and is patterned into a predetermined planar shape (e.g., a rectangular shape).

[0081] The silicon film SF has a p-type silicon region (p-type semiconductor region) PS and multiple n-type silicon regions (n-type semiconductor regions) NS, each of the multiple n-type silicon regions NS being surrounded by a p-type silicon region PS in a planar view. From another viewpoint, the silicon film SF is formed by the p-type silicon region PS and the multiple n-type silicon regions NS surrounded by the p-type silicon region PS. Each of the multiple n-type silicon regions NS is adjacent to the p-type silicon region PS.

[0082] In the silicon film SF, since the part other than the part that is to become the n-type silicon region NS is the p-type silicon region PS, it is possible to regard the silicon film SF as a p-type silicon film and consider forming multiple n-type silicon regions NS in the p-type silicon film.

[0083] In the silicon film SF, multiple n-type silicon regions NS are formed separately from each other. Therefore, p-type silicon regions PS are inserted between adjacent n-type silicon regions NS, and in a planar view, each n-type silicon region NS is surrounded by a p-type silicon region PS. Each n-type silicon region NS is in contact with a p-type silicon region PS, and a PN junction is formed between each n-type silicon region NS and p-type silicon region PS (at the interface).

[0084] Each of a plurality of n-type silicon regions NS formed on a silicon film SF is exposed on the upper surface of the silicon film SF. The depth of the bottom surface of each of the plurality of n-type silicon regions NS formed on the silicon film SF is shallower than the depth of the lower surface of the silicon film SF. Therefore, the thickness of each n-type silicon region NS is less than the thickness of the silicon film SF, and a p-type silicon region PS exists below the bottom surface of each n-type silicon region NS. Therefore, the side and bottom surfaces of each n-type silicon region NS are in contact with the p-type silicon region PS, and a PN junction is formed on the side and bottom surfaces of each n-type silicon region NS.

[0085] Multiple n-type silicon regions NS formed on the silicon film SF each extend in the X direction and are separated and aligned in the Y direction, which intersects (more specifically, is orthogonal to) the X direction in a planar view. In the planar view, each of the multiple n-type silicon regions NS formed on the silicon film SF has a rectangular planar shape with its longitudinal direction in the X direction. The length L1 of the planar shape of each n-type silicon region NS in the X direction can be, for example, about 2 to 40 micrometers. Furthermore, the width W1 of the planar shape of each n-type silicon region NS in the Y direction can be, for example, about 0.2 to 1.0 micrometers. Furthermore, the distance S1 between the n-type silicon regions NS in the Y direction can be, for example, about 0.8 to 2.0 micrometers. Note that the length L1, width W1, and spacing S1 are as follows: Figure 2 As shown.

[0086] A diode DD is formed by creating a PN junction (at the interface) between a p-type silicon region PS and each of a plurality of n-type silicon regions NS. That is, the p-type silicon region PS of the silicon film SF serves as the anode (anode region) of the diode DD, and each of the plurality of n-type silicon regions NS of the silicon film SF serves as the cathode (cathode region) of the diode DD. The diode DD is used for temperature sensing.

[0087] like Figures 4 to 6 As shown, an insulating film IL is formed on the entire main surface of the semiconductor substrate SUB to cover the trench gate electrode TG, the insulating film ZM, and the silicon film SF. The insulating film IL is an interlayer insulating film made of, for example, silicon oxide. The insulating film IL is formed in the MOSFET formation region RG2 and the diode formation region RG1.

[0088] Contact holes (openings, through holes) CT are formed in the insulating film IL. The contact holes CT include contact holes CTS for the source, contact holes (not shown) for the gate, contact holes CTA for the anode, and contact holes CTC for the cathode.

[0089] The contact hole CTS for the source is formed in n + On the NR region of the type semiconductor, the n-type semiconductor is penetrated. + The n-type semiconductor region NR extends to the p-type semiconductor region PR. Therefore, n + The n-type semiconductor region NR and the p-type semiconductor region PR are exposed at the bottom of the contact hole CTS for the source electrode. The contact hole CTA for the anode is formed on the p-type silicon region PS of the silicon film SF, and the p-type silicon region PS of the silicon film SF is exposed at the bottom of the contact hole CTA for the anode. The contact hole CTC for the cathode is formed on each of the plurality of n-type silicon regions NS of the silicon film SF, and each of the n-type silicon regions NS is exposed at the bottom of the contact hole CTC. A gate drawer (not shown) integrally formed with the trench gate electrode TG extends on the semiconductor substrate SUB outside the trench TR, and a contact hole (not shown) for the gate is formed on the gate drawer.

[0090] A conductive plug (contact plug, an embedded conductor portion for connection) PG is formed in the contact hole CT of the insulating film IL. The plug PG is made of, for example, a tungsten (W) film. The plug PG penetrates the insulating film IL. The plug PG includes: a source plug (contact plug) PGS formed in the contact hole CTS; a gate plug (not shown) formed in the contact hole for the gate; an anode plug (contact plug) PGA formed in the contact hole CTA; and a cathode plug (contact plug) PGC formed in the contact hole CTC. The source plug PGS is electrically connected to n + The device consists of an n-type semiconductor region NR and a p-type semiconductor region PR. An anode plug PGA, embedded in a contact hole CTA, contacts and is electrically connected to the p-type silicon region PS exposed at the bottom of the contact hole CTA. A cathode plug PGC, embedded in a contact hole CTC, contacts and is electrically connected to the n-type silicon region NS exposed at the bottom of the contact hole CTC.

[0091] A wiring (electrode) M1 is formed on an insulating film IL with embedded plugs PG. Wiring M1 includes a source wiring (electrode) M1S, a gate wiring (not shown), an anode wiring (electrode) M1A, and a cathode wiring (electrode) M1C. The upper surface of the source plug PGS contacts and is electrically connected to the source wiring M1S. The upper surface of the anode plug PGA contacts and is electrically connected to the anode wiring M1A. The upper surface of the cathode plug PGC contacts and is electrically connected to the cathode wiring M1C. Wiring M1 is formed from a patterned conductive film. Wiring M1 is made of a metal film, for example, containing aluminum (Al) as a main component, specifically an aluminum film or an aluminum alloy film.

[0092] The source wiring M1S is formed almost entirely within the MOSFET formation region RG2. The source contact via CTS is formed within the MOSFET formation region RG2 and is located in the source region (n) of multiple unit transistor cells within the MOSFET formation region RG2. + The P-type semiconductor region (NR) and the channel formation region (P-type semiconductor region PR) are electrically connected to the common wiring M1S via source plugs PGS embedded in multiple contact holes CTS. Wiring M1S can also be considered as a source electrode. In addition, the trench gate electrodes TG of multiple unit transistor cells are electrically connected to the gate wiring (not shown) via gate leads (not shown) and gate plugs (not shown) integrally formed with the trench gate electrodes TG.

[0093] Wirings M1A and M1C are formed in an upper layer higher than the silicon film SF. The p-type silicon region PS of the silicon film SF is electrically connected to the anode wiring (electrode) M1A via an anode plug PGA. Wiring M1A can also be considered as an anode electrode. Furthermore, multiple n-type silicon regions NS formed on the silicon film SF are electrically connected to the cathode wiring (electrode) M1C via multiple cathode plugs PGC. That is, plugs PGC are arranged on each of the multiple n-type silicon regions NS formed on the silicon film SF, and in the plan view, wiring M1C is arranged to overlap with the multiple plugs PGC, such that the multiple n-type silicon regions NS formed in the silicon film SF are electrically connected to the common wiring M1C via multiple plugs PGC. Wiring M1C can also be considered as a cathode electrode. Plugs PGA and PGC penetrate the insulating film (interlayer insulating film) IL formed between the silicon film SF and wirings M1A and M1C. In the planar view, the anode plug PGA overlaps with the p-type silicon region PS of the silicon film SF, and also overlaps with the anode wiring M1A. In the planar view, multiple cathode plugs PGC are different from the multiple n-type silicon regions NS formed on the silicon film SF, and overlap with the cathode wiring M1C.

[0094] exist Figure 2 and Figure 3 In the case of n having a rectangular planar shape with the vertical direction as the X direction, + The semiconductor region NR has a rectangular planar shape with the longitudinal direction (X) as its axis. The plug PGC contacts the n-type silicon region NS but not the p-type silicon region PS. Furthermore, in... Figure 3 In this case, the plug PGA has a rectangular planar shape with its longitudinal direction in the Y direction in the planar view, and multiple (here, two) plug PGAs are arranged to be separated in the X direction. The number of plug PGAs can be any one or more. The plug PGA contacts the p-type silicon region PS, but not the n-type silicon region NS.

[0095] The illustration and description of the structure above wiring M1 will be omitted here. For example, the bonding pad can also be formed by forming an insulating film (protective film, passivation film) on the insulating film IL to cover wiring M1 and expose wiring M1 from the opening of the insulating film. Optionally, this embodiment may have a structure in which an insulating film (interlayer insulating film) is formed on the insulating film IL to cover wiring M1 and a second layer of wiring is formed on the insulating film.

[0096] In a semiconductor device with this structure, the operating current of the power MOSFET flows between the wiring M1S for the source and the back electrode BE for the drain. That is, the operating current of the trench-gate MOSFET formed in the MOSFET formation region RG2 flows along the thickness direction of the semiconductor substrate SUB.

[0097] Furthermore, in this embodiment, the application of trench gate MISFET as a field-effect transistor formed on semiconductor substrate SUB has been described, but the present invention is not limited thereto, and another type of field-effect transistor may also be formed in the MOSFET forming region RG2 of semiconductor substrate SUB.

[0098] For example, a trench gate IGBT can also be formed in the MOSFET formation region RG2 of the semiconductor substrate SUB, instead of a trench gate MISFET.

[0099] Alternatively, LDMOSFETs (laterally diffused metal-oxide-semiconductor field-effect transistors) can be formed in the MOSFET formation region RG2 of the semiconductor substrate SUB, instead of trench gate MOSFETs.

[0100] The diode DD formed in the diode formation region RG1 is used to detect the temperature of the power MOSFET formed in the MOSFET formation region RG2, and can be regarded as a diode used to detect the heat generation of the power MOSFET formed in the MOSFET formation region RG2.

[0101] Since the voltage-current characteristics of a diode change with temperature, the temperature of the diode DD in the semiconductor device CP can be detected by detecting (monitoring) the voltage-current characteristics of the diode DD formed in the diode formation region RG1. Therefore, in the semiconductor device CP, by arranging the diode DD (diode formation region RG1) near the power MOSFET (MOSFET formation region RG2), the temperature (heat generation) of the power MOSFET can be detected by the diode DD.

[0102] For example, in a semiconductor device CP, when the power MOSFET formed in the MOSFET formation region RG2 generates excessive heat and the temperature of the diode DD becomes higher than a predetermined upper limit temperature, the aforementioned control circuit provides an OFF signal (or stops providing an ON signal) to the gate of the power MOSFET in the semiconductor device CP, thereby switching the power MOSFET to the OFF state. Therefore, in the semiconductor device CP, when the power MOSFET generates excessive heat, since the excessive heat is detected by the diode DD, the power MOSFET can quickly switch to the OFF state.

[0103] <Discussion Background>

[0104] Figure 7 This is a plan view of the main parts of the semiconductor device described in the examples discussed by the inventors. Figure 8 This is a cross-sectional view of the main part of the semiconductor device described in the examples discussed by the inventors. Figure 7 and Figure 8 The diode formation region in the semiconductor device discussed in the example is shown. Figure 7 The cross-sectional view at position B1-B1 in the diagram corresponds to Figure 8 Cross-sectional view.

[0105] In the semiconductor devices discussed as examples, such as Figure 7 and Figure 8 As shown, a silicon film SF10 made of polycrystalline silicon is formed on a semiconductor substrate SUB10 via an insulating film ZM10. The silicon film SF10 consists of a p-type silicon region PS10 and an n-type silicon region NS10, with the n-type silicon region NS10 surrounded by the p-type silicon region PS10 in the planar view.

[0106] An n-type silicon region NS10 is formed to penetrate the silicon film SF10 in the thickness direction. That is, the thickness of the n-type silicon region NS10 is approximately the same as the thickness of the silicon film SF10. Therefore, the n-type silicon region NS10 is exposed on both the upper and lower surfaces of the silicon film SF10. Consequently, the p-type silicon region PS10 is not present beneath the n-type silicon region NS10.

[0107] Therefore, the side surface of the n-type silicon region NS10 contacts the p-type silicon region PS10, and a PN junction is formed on the side surface of the n-type silicon region NS10. No PN junction is formed on the bottom surface of the n-type silicon region NS10. The p-type silicon region PS10 serves as the anode (anode region) of the diode DD10, and the n-type silicon region NS10 serves as the cathode (cathode region) of the diode DD10. The p-type silicon region PS10 is electrically connected to the anode wiring M1A10 via plug PGA10, and the n-type silicon region NS10 is electrically connected to the cathode wiring M1C10 via plug PGC10.

[0108] The diode DD10 formed in the semiconductor device of the discussed example can be used for temperature sensing, for example, in a power MOSFET formed in the semiconductor device of the same discussed example. However, when the heat generated by the diode DD10 is high, the reliability of the diode DD10 may decrease due to the heat generated. For example, the risk of thermal damage (destruction due to heat) of the diode DD10 may increase. This leads to a decrease in the reliability of the semiconductor device having the diode. Furthermore, when the heat generated by the diode DD10 is high, a temperature rise occurs due to the heat generated by the diode DD10, which may reduce the temperature sensing accuracy of the diode DD10. This leads to a decrease in the performance of the semiconductor device including the diode.

[0109] The PN junction constituting diode DD10 includes the PN junction surface between the p-type silicon region PS10 and the n-type silicon region NS10, and the PN junction surface corresponds to the side surface of the n-type silicon region NS10. Current flowing through diode DD10 flows through this PN junction surface. The operating resistance of diode DD10 depends on the area of ​​the PN junction surface constituting diode DD10. When the area of ​​the PN junction surface is small, the operating resistance of diode DD10 increases; when the area of ​​the PN junction surface is large, the operating resistance of diode DD10 decreases. It should be noted that the operating resistance of the diode corresponds to the resistance value when a reference current (current reference value) flows.

[0110] The heat generated by diode DD10 (Joule heating) decreases with decreasing operating resistance under the same current flow conditions, meaning the heat generation decreases with increasing PN junction surface area. Therefore, increasing the PN junction surface area of ​​diode DD10 is effective in reducing its heat generation to improve reliability. This requires increasing the size of the silicon film SF10. However, increasing the size of the silicon film SF10 increases the planar dimensions (planar area) of the semiconductor device (semiconductor chip) including the diode, resulting in a larger semiconductor device (larger area). Furthermore, when the size of the silicon film SF10 increases and the power MOSFET formation area decreases, the current flowing through the power MOSFET decreases, leading to performance degradation of the semiconductor device. Simultaneously, if the size of the silicon film SF10 decreases, the PN junction surface area decreases, thus increasing the operating resistance of diode DD10. This results in an increase in the heat generated by diode DD10 as described above, potentially causing the problems mentioned above that depend on this increase.

[0111] <Main Features and Effects>

[0112] The semiconductor device CP of this embodiment is a semiconductor device including a diode DD. The semiconductor device CP includes: a semiconductor substrate SUB; a silicon film SF for the diode DD, which is formed on the semiconductor substrate SUB via an insulating film ZM (first insulating film); and wiring M1A (first electrode) and wiring M1C (second electrode) formed on the upper layer of the silicon film SF. The silicon film SF has a p-type silicon region PS (first silicon region) and a plurality of n-type silicon regions NS (second silicon regions), each of the plurality of n-type silicon regions NS being surrounded by a p-type silicon region PS in a plan view. The p-type silicon region PS of the silicon film SF is electrically connected to wiring M1A, and the plurality of n-type silicon regions NS of the silicon film SF are electrically connected to wiring M1C.

[0113] As explained in the background section above, when a diode is formed from a silicon film having p-type and n-type silicon regions, it is desirable to increase the area of ​​the PN junction while suppressing the planar dimensions of the silicon film.

[0114] Therefore, in this embodiment, a plurality of n-type silicon regions NS (second silicon regions) are provided in the silicon film SF for the diode DD, and in a planar view, each of the plurality of n-type silicon regions NS is surrounded by p-type silicon PS. Thus, while suppressing the planar dimensions of the silicon film SF, the area of ​​the PN junction formed in the silicon film SF for the diode DD can be increased.

[0115] That is, in this embodiment, a plurality of n-type silicon regions NS are provided in the silicon film SF for the diode DD, and in a plan view, each of the plurality of n-type silicon regions NS is surrounded by a p-type silicon region PS, thereby forming a PN junction on each side surface of the plurality of n-type silicon regions NS. When the number of n-type silicon regions NS formed in the silicon film SF increases, the total number of side surfaces of the n-type silicon regions NS on which PN junctions are formed increases, making it possible to increase the area of ​​the PN junction formed in the silicon film SF. Therefore, compared with the case where only one n-type silicon region NS10 is provided in the silicon film SF10 as in the example discussed above, when a plurality of n-type silicon regions NS are provided in the same silicon film SF as in this embodiment, the total number of side surfaces of the n-type silicon regions NS on which PN junctions are formed can be increased even more. Therefore, the total area of ​​the side surfaces of the n-type silicon regions NS on which PN junctions are formed can be increased. Therefore, the total area of ​​the PN junction constituting the diode DD can be increased.

[0116] Furthermore, the p-type silicon region PS of the silicon film SF is electrically connected to wiring M1A, and the plurality of n-type silicon regions NS of the silicon film SF are electrically connected to wiring M1C. Therefore, the p-type silicon region PS of the silicon film SF can be used as the anode of the diode DD, and each of the plurality of n-type silicon regions NS of the silicon film SF can be used as the cathode of the diode DD. When a predetermined voltage is applied between wiring M1A and wiring M1C, current flows through the diode DD, and current can flow through the PN junction surface between the p-type silicon region PS and the plurality of n-type silicon regions NS of the silicon film SF. Therefore, since any one of the plurality of n-type silicon regions NS of the silicon film SF can be used as the cathode (cathode region) of the diode DD, increasing the number of n-type silicon regions NS of the silicon film SF allows for an increase in the total area of ​​the PN junction between the cathode region (n-type silicon region NS) and the anode region (p-type silicon region PS) of the diode DD.

[0117] In this embodiment, a plurality of n-type silicon regions NS are provided in the silicon film SF used for diode DD, and in a plan view, each of the plurality of n-type silicon regions NS is surrounded by a p-type silicon region PS. By doing so, the plurality of n-type silicon regions NS are electrically connected to the wiring M1C. This allows for an increase in the total area of ​​the PN junction constituting diode DD and a decrease in the operating resistance of diode DD. Therefore, heat generation of diode DD can be suppressed. Consequently, the reliability of diode DD can be improved, and correspondingly, the reliability of the semiconductor device CP including diode DD can be improved. For example, the risk of thermal damage (destruction due to heat) of diode DD can be suppressed, and the durability of diode DD against thermal damage can be improved. Furthermore, since the heat generation of diode DD can be suppressed, when using diode DD for temperature detection, the temperature rise caused by the heat generation of diode DD can be suppressed, thereby improving the accuracy of temperature detection of diode DD. Therefore, the performance of the semiconductor device including diode DD can be improved.

[0118] Furthermore, in this embodiment, by providing multiple n-type silicon regions NS in the silicon film SF used for diode DD, the total area of ​​the PN junction constituting diode DD can be increased, allowing for an effective increase in the total area of ​​the PN junction constituting diode DD without increasing the planar dimensions. Therefore, the total area of ​​the PN junction constituting diode DD can be increased while suppressing the planar dimensions (planar area) of the silicon film SF. Thus, the planar dimensions of the silicon film SF used for diode DD can be suppressed, and the semiconductor device CP can be miniaturized (its area can be reduced). Furthermore, since the planar dimensions of the silicon film SF constituting diode DD can be suppressed, the area of ​​the MOSFET formation region RG2 in the semiconductor device CP can be ensured. This makes it possible to increase the current flowing through the power MOSFET and also improves the performance of the semiconductor device CP in this respect.

[0119] Furthermore, in this embodiment, each of the plurality of n-type silicon regions NS formed in the silicon film SF is exposed on the upper surface of the silicon film SF. This facilitates the electrical connection of each of the plurality of n-type silicon regions NS formed in the silicon film SF to the wiring M1C via the plug PGC. Additionally, since each of the plurality of n-type silicon regions NS is surrounded by a p-type silicon region PS in the plan view, the p-type silicon region PS is also exposed on the upper surface of the silicon film SF. This facilitates the electrical connection of the p-type silicon region PS of the silicon film SF to the wiring M1A via the plug PGA.

[0120] Furthermore, in this embodiment, the p-type silicon region PS exists beneath each of the plurality of n-type silicon regions NS in the silicon film SF. Therefore, a PN junction is formed on the side surface and bottom surface (lower surface) of each of the plurality of n-type silicon regions NS formed in the silicon film SF. Since the PN junction is formed not only on the side surface of each of the plurality of n-type silicon regions NS formed in the silicon film SF, but also on the bottom surface, the total area of ​​the PN junction between the cathode region (n-type silicon region NS) and the anode region (p-type silicon region PS) of the diode DD can be further increased. This allows for a further reduction in the operating resistance of the diode DD, thereby further suppressing the heat generated by the diode DD. This allows for a further improvement in the reliability of the diode DD, thereby further improving the reliability of the semiconductor device CP including the diode DD. Furthermore, when the diode DD is used for temperature sensing, the accuracy of temperature sensing by the diode DD can be further improved, thus further improving the performance of the semiconductor device including the diode DD. Furthermore, since the area of ​​the PN junction formed in the silicon film SF for diode DD can be increased more effectively while suppressing the planar size of the silicon film SF, the planar size of the silicon film SF for diode DD can be further increased, and the semiconductor device CP can be further miniaturized (making the area smaller).

[0121] Furthermore, in this embodiment, the number of n-type silicon regions NS formed in the silicon film SF is two or more. Figure 2 and Figure 3 The examples illustrate the case where three n-type silicon regions (NS) are formed in the silicon film SF. The number of n-type silicon regions (NS) formed in the silicon film SF is larger in the total area of ​​the PN junction constituting the diode DD than the number of regions (2). Furthermore, the number of n-type silicon regions (NS) formed in the silicon film SF can be four or more.

[0122] Figure 9 and Figure 10 Each graph shows the characteristics of the diode applied according to this embodiment. Figure 9 The horizontal axis of the curve in the graph and Figure 10 The horizontal axis of the curve in the graph corresponds to the length L1 in the X direction of each of the multiple n-type silicon regions NS formed in the silicon film SF. Figure 9 The vertical axis of the graph corresponds to the voltage VF (hereinafter referred to as the VF value) when the current reference value flows through the diode. For example, any current value from approximately 50 to 100 μA can be used as the current reference value. Furthermore, Figure 10 The vertical axis of the graph corresponds to the area of ​​the silicon SF film. Note that... Figure 9 and Figure 10 Each curve corresponds to the case where the length L1 of the n-type silicon region NS is changed while the total area of ​​the PN junction remains constant.

[0123] As from Figure 9 As can be seen from the graph, when the length L1 of the n-type silicon region NS in the X direction is 40 micrometers or less, the VF value remains almost unchanged. However, when the length L1 is greater than 40 micrometers, the VF value exceeds the upper limit (1.03 times the target value). The VF value increases with increasing length L1. This is because: when the length L1 of the n-type silicon region NS in the X direction is 40 micrometers or less, almost the entire side surface of the n-type silicon region NS can serve as a current path; and when the length L1 of the n-type silicon region NS in the X direction exceeds 40 micrometers, portions of the side surface of the n-type silicon region NS that do not serve as current paths appear. Therefore, to ensure that the entire side surface of the n-type silicon region NS serves as a current path and to effectively guarantee the effective area of ​​the PN junction serving as a current path, the length L1 of the n-type silicon region NS in the X direction is preferably 40 micrometers or less.

[0124] As from Figure 10 As can be seen, when the total area of ​​the PN junction is constant, increasing the length L1 reduces the area of ​​the silicon film SF, while decreasing the length L1 increases the area of ​​the silicon film SF. Therefore, in order to suppress the planar dimensions (planar area) of the silicon film SF while ensuring the area of ​​the PN junction, it is desirable that the length L1 of the n-type silicon region NS in the X direction is not too small. From this perspective, the length L1 of the n-type silicon region NS in the X direction is preferably 2 micrometers or greater.

[0125] Therefore, the length L1 of the n-type silicon region NS in the X direction is preferably 2 micrometers or more and 40 micrometers or less. This allows for an effective increase in the effective area of ​​the PN junction, which acts as a current path, while suppressing the planar dimensions (planar area) of the silicon film SF.

[0126] <Semiconductor Device Manufacturing Process>

[0127] Next, we will refer to Figures 11 to 32 An example describing the manufacturing process of the semiconductor device of this embodiment. Figures 11 to 32 Each of these is a cross-sectional view of a major component of the semiconductor device according to this embodiment during the manufacturing process. Note that... Figures 11 to 32 In Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 19 , Figure 21 , Figure 23 , Figure 25 , Figure 27 , Figure 29 and Figure 31 The above is shown Figure 4The cross-section corresponding to the cross-section of the diode forming region RG1. Furthermore, Figures 11 to 32 In Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 , Figure 28 , Figure 30 , Figure 32 The above is shown Figure 6 The corresponding cross section (therefore, the cross section of the MOSFET forming region RG2).

[0128] To manufacture semiconductor devices, firstly, as... Figure 11 and Figure 12 As shown, a semiconductor substrate SUB (semiconductor wafer) is prepared. The semiconductor substrate SUB has a structure consisting of n... + The substrate body SB is made of n-type single crystal silicon, etc., and the epitaxial layer EP is formed on the main surface of the substrate body SB by an n-type single crystal silicon.

[0129] Next, in the MOSFET formation region RG2, trenches TR are formed in the main surface of the semiconductor substrate SUB (epitaxy layer EP) using photolithography and etching techniques (see...). Figure 12 ).

[0130] Next, the trench gate electrode TG is formed in the trench TR through the gate insulating film GF (see Figure 12 For example, an insulating film for the gate insulating film GF is formed on the side and bottom surfaces of the trench TR and the top surface of the semiconductor substrate SUB using methods such as thermal oxidation. Subsequently, a conductive film (e.g., a polysilicon film) for the trench gate electrode TG is formed on the insulating film to fill the interior of the trench. Then, the conductive film outside the trench TR is removed by an etch-back process. This allows for the formation of the trench gate electrode TG and the gate insulating film GF.

[0131] Next, as Figure 13 and Figure 14 As shown, an insulating film ZM is formed on a semiconductor substrate SUB. Then, a silicon film SF is formed on the insulating film ZM using a method such as CVD (chemical vapor deposition). Thus, the silicon film SF is formed on the semiconductor substrate SUB via the insulating film ZM. At this stage, the silicon film SF is made of undoped polycrystalline silicon.

[0132] Next, p-type impurities are introduced into the silicon film SF using methods such as ion implantation. At this point, by introducing p-type impurities (e.g., boron) into the entire silicon film SF, the silicon film SF becomes a p-type silicon film (p-type polycrystalline silicon film).

[0133] Next, as Figure 15 and Figure 16 As shown, a stacked film consisting of an insulating film ZM and a silicon film SF on the insulating film ZM is patterned using photolithography and etching techniques. Therefore, the silicon film SF is patterned into a predetermined planar shape. At this time, in the MOSFET formation region RG2 ( Figure 16 In the diode formation region RG1, the silicon film SF and the insulating film ZM are removed. Figure 15 In the process, the patterned silicon film SF is retained and becomes the silicon film SF used for the diode DD.

[0134] Next, as Figure 17 and Figure 18 As shown, in the MOSFET formation region RG2 ( Figure 18 In the process of forming a semiconductor substrate SUB, a p-type semiconductor region PR is formed by ion implantation of p-type impurities into the main surface of the substrate SUB. The p-type semiconductor region PR is formed on the upper layer (epitaxy layer EP) of the semiconductor substrate SUB. At this time, the diode formation region RG1 is formed. Figure 17 The silicon film SF in the ) is covered by a photoresist layer (not shown) to prevent ion implantation from being introduced.

[0135] Next, as Figure 19 and Figure 20 As shown, in the MOSFET formation region RG2 ( Figure 20 In this process, n-type impurity ions are implanted into the main surface of the semiconductor substrate SUB to form n... + Type semiconductor region NR. + The depth of the n-type semiconductor region NR is shallower than the depth of the p-type semiconductor region PR, and n + The p-type semiconductor region NR is formed on the p-type semiconductor region PR. During this ion implantation, the diode formation region RG1 ( Figure 19 The silicon film SF in the ) is covered by a photoresist layer (not shown) to prevent ion implantation from being introduced.

[0136] Next, as Figure 21 and Figure 22 As shown, an insulating film IL, which serves as an interlayer insulating film, is formed on the main surface of the semiconductor substrate SUB (on the entire main surface) to cover the trench gate electrode TG and the silicon film SF.

[0137] Next, as Figure 23 and Figure 24 As shown, contact holes CTS and CTA are formed in the insulating film IL using photolithography and etching techniques. Contact hole CTS is formed in the MOSFET formation region RG2. Figure 24 A contact hole CTA is formed on the silicon film SF in the diode forming region RG1. Figure 23 The contact hole CTS in the MOSFET forming region RG2 and the contact hole CTA in the diode forming region RG1 can be formed in the same step or in separate steps.

[0138] Next, as Figure 25 and Figure 26 As shown, a photoresist pattern RP1 is formed on the insulating film IL using photolithography, and then the insulating film IL is etched using the photoresist pattern RP1. In this way, a contact hole CTC is formed in the insulating film IL. The contact hole CTC is formed on the silicon film SF in the diode formation region RG1. Figure 25 ).

[0139] Next, as Figure 27 and Figure 28 As shown, multiple n-type silicon regions NS are formed on the silicon film SF by implanting n-type impurity (e.g., arsenic) ions into the silicon film SF exposed from the contact holes CTC. Multiple contact holes CTC are formed on the silicon film SF, and the number of n-type silicon regions NS is the same as the number of contact holes CTC. An insulating film IL can be used as a mask layer for forming the n-type silicon regions NS on the silicon film SF by ion implantation. Furthermore, during ion implantation, the ion implantation energy is adjusted such that the depth of the bottom surface of the n-type silicon regions NS in the silicon film SF becomes shallower than the depth of the bottom surface of the silicon film SF. That is, the thickness of the n-type silicon regions NS is less than the thickness of the silicon film SF.

[0140] Before the formation of the n-type silicon region NS, the silicon film SF is already a p-type polycrystalline silicon film, and the entire silicon film SF is already a p-type silicon region. This means that when the n-type silicon region NS is formed, the portion of the silicon film SF that is not yet an n-type silicon region NS becomes a p-type silicon region PS. Therefore, in the diode forming region RG1, a silicon film SF with a p-type silicon region PS and multiple n-type silicon regions NS is formed.

[0141] Next, as Figure 29 and Figure 30 As shown, plugs PG (PGS, PGA, PGC) are formed in the contact holes CT (CTS, CTA, CTC).

[0142] For example, after forming a barrier conductor film on the insulating film IL including the bottom surface and sidewalls of the contact hole CT (CTS, CTA, CTC), a dominant body film (e.g., a tungsten film) is formed on the barrier conductor to fill the contact hole CT (CTS, CTA, CTC). Then, unnecessary dominant body films and barrier conductor films outside the contact hole CT (CTS, CTA, CTC) are removed by methods such as CMP. This makes it possible to form plugs PG (PGS, PGA, PGC).

[0143] Next, as Figure 31 and Figure 32 As shown, wiring M1 (M1S, M1A, M1C) is formed on an insulating film IL with embedded plugs PG (PGS, PGA, PGC). For example, after forming a conductive film (e.g., an aluminum alloy film) for forming wiring M1 on the insulating film IL with embedded plugs PG (PGS, PGA, PGC), the conductive film is patterned using photolithography and etching techniques, enabling the formation of wiring M1 (M1S, M1A, M1C) made from the patterned conductive film. Descriptions of subsequent steps will be omitted here.

[0144] Note that after forming the top protective film, the back side of the semiconductor substrate SUB is ground or polished as needed to reduce the thickness of the semiconductor substrate SUB. Then, a back electrode BE can be formed on the entire back side of the semiconductor substrate SUB. After forming the back electrode BE, the semiconductor substrate SUB is divided (separated and cut) by dicing or the like to obtain a single semiconductor chip (semiconductor device) from the semiconductor substrate SUB.

[0145] <Modification Example>

[0146] Figure 33 and Figure 34 This is a plan view of the main parts of a modified example of a semiconductor device according to this embodiment. Figure 35 This is a cross-sectional view of the main part of a modified example of a semiconductor device according to this embodiment. Figures 33 to 35 Corresponding to the first embodiment Figures 2 to 4 . Figure 33 and Figure 34 The cross-sectional view taken along line C1-C1 basically corresponds to Figure 35 Cross-sectional view.

[0147] exist Figures 33 to 35 In the modified example shown, multiple n-type silicon regions NS formed on the silicon film SF are arranged in a matrix (mesh) in a planar view. The multiple n-type silicon regions NS arranged in the matrix are electrically connected to the wiring M1C via multiple plugs PGC.

[0148] Also in Figures 33 to 35 In the modified example shown, by increasing the total number of side surfaces of the n-type silicon region NS, the total area of ​​the side surfaces of the n-type silicon region NS is increased, and by forming PN junctions not only on the side surfaces of the n-type silicon region NS but also on its bottom surface, the total area of ​​the PN junction constituting the diode DD can be increased.

[0149] In addition, such as Figures 33 to 35 The matrix arrangement of the multiple n-type silicon regions NS shown can also be applied to the second embodiment described later.

[0150] (Second Implementation)

[0151] Figure 36 and Figure 37 This is a plan view of the main parts of the semiconductor device according to the second embodiment. Figure 38 and Figure 39 This is a cross-sectional view of the main part of the semiconductor device according to the second embodiment. Figures 36 to 39 Corresponding to the first embodiment as described above Figures 2 to 5 . Figure 36 and Figure 37 The cross-sectional views at the respective line D1-D1 positions in the diagrams basically correspond to Figure 38 Cross-sectional view, Figure 36 and Figure 37 The cross-sectional views at the respective line D2-D2 positions in the diagrams basically correspond to Figure 39 Cross-sectional view.

[0152] Note that, except for the structure of the diode DD, the structure of the semiconductor device according to the second embodiment is almost identical to the structure of the semiconductor device CP in the first embodiment. Therefore, in the second embodiment, the following will mainly describe one difference in the structure of the diode DD compared to the first embodiment.

[0153] Similarly, in the second embodiment, the silicon film SF constituting the diode DD has a p-type silicon region PS and a plurality of n-type silicon regions NS, each of the plurality of n-type silicon regions NS being surrounded by a p-type silicon region PS in a plan view.

[0154] In the first embodiment described above, the depth of the bottom surface of each of the plurality of n-type silicon regions NS formed in the silicon film SF is shallower than the depth of the lower surface of the silicon film SF. Therefore, each of the plurality of n-type silicon regions NS does not penetrate the silicon film SF in the thickness direction. Thus, in the first embodiment described above, each n-type silicon region NS is not exposed on the lower surface of the silicon film SF, and a p-type silicon region PS already exists beneath the bottom surface of each n-type silicon region NS.

[0155] Conversely, in this second embodiment, each of the plurality of n-type silicon regions NS is formed to penetrate the silicon film SF in the thickness direction. That is, the thickness of each n-type silicon region NS is approximately the same as the thickness of the silicon film SF. Therefore, in this second embodiment, each of the plurality of n-type silicon regions NS formed on the silicon film SF is exposed on both the upper and lower surfaces of the silicon film SF. Therefore, in this second embodiment, there is no p-type silicon region PS beneath each n-type silicon region ns.

[0156] Therefore, in the first embodiment described above, the side and bottom surfaces of each n-type silicon region NS are in contact with the p-type silicon region PS, and a PN junction is formed on the side and bottom surfaces of each n-type silicon region NS. Conversely, in this second embodiment, the side surface of each n-type silicon region NS is in contact with the p-type silicon region PS, and a PN junction is formed on the side surface of each n-type silicon region NS. However, the bottom surface of each n-type silicon region NS is not in contact with the p-type silicon region PS, therefore, no PN junction is formed on the bottom surface of each n-type silicon region NS.

[0157] Apart from the above description, the configuration of the semiconductor device according to the second embodiment is almost the same as the configuration of the semiconductor device CP according to the first embodiment, so its repeated description will be omitted here.

[0158] Similarly, in the second embodiment, a plurality of n-type silicon regions NS are provided in the silicon film SF for the diode DD, such that each of the plurality of n-type silicon regions NS is surrounded by a p-type silicon region PS in a planar view. This allows for an increase in the total number of side surfaces of the n-type silicon regions NS on which PN junctions are formed, and correspondingly increases the total area of ​​the side surfaces of the n-type silicon regions NS on which PN junctions are formed. Therefore, the total area of ​​the PN junction constituting the diode DD can be increased. In other words, the total area of ​​the PN junction constituting the diode DD can be increased while suppressing the planar dimensions (planar area) of the silicon film SF. Therefore, since the operating resistance of the diode DD can be reduced, the heat generation of the diode DD can be suppressed. Therefore, the reliability of the diode DD can be improved, and correspondingly, the reliability of the semiconductor device CP including the diode DD can be improved. Moreover, the performance of the semiconductor device can be improved. Furthermore, the semiconductor device can be miniaturized (making the area smaller).

[0159] However, in the first embodiment, the PN junction is formed not only on the side surface of each n-type silicon region NS, but also on its bottom surface. In the second embodiment, the PN junction is formed on the side surface of each n-type silicon region NS, but no PN junction is formed on the bottom surface of each n-type silicon region NS. Therefore, when comparing the first and second embodiments, the first embodiment allows the total area of ​​the PN junction constituting the diode DD to be larger than the total area of ​​the second embodiment, because the PN junction is also formed on the bottom surface of each n-type silicon region NS. Therefore, since the operating resistance of the diode DD in the first embodiment is smaller (lower) than that in the second embodiment, the heat generation of the diode DD can be further suppressed. Therefore, the first embodiment is more advantageous than the second embodiment in terms of improving the reliability of the semiconductor device CP including the diode DD.

[0160] Next, we will refer to Figures 40 to 49 An example describing the manufacturing process according to the second embodiment. Figures 40 to 49 Each of these is a cross-sectional view of a major part of the semiconductor device according to the second embodiment during the manufacturing process. Note that... Figures 40 to 49 In Figure 40 , Figure 42 , Figure 44 , Figure 46 and Figure 48 It shows the relationship with Figure 38 The corresponding cross-section (therefore, the cross-section of the diode forming region RG1) is as described above. Furthermore, Figures 40 to 49 In Figure 41 , Figure 43 , Figure 45 , Figure 47 and Figure 49 The above is shown Figure 39 The corresponding cross section (therefore, the cross section of the MOSFET forming region RG2).

[0161] Because until obtained Figure 17 and Figure 18 Prior to the structure described above, the manufacturing process of this second embodiment is the same as that of the first embodiment described above, so its repeated description is omitted here.

[0162] Obtained in the same manner as in the first embodiment Figure 17 and Figure 18 After the structure is completed, in this second embodiment, as shown Figure 40 and Figure 41 As shown, the MOSFET formation region RG2 is exposed. Figure 41 ), and a photoresist pattern (mask layer) RP2 is formed by using photolithography to cover the silicon film SF in the diode formation region RG1. Figure 40 The photoresist pattern RP2 has an opening OP1 that exposes the area in the silicon film SF where the n-type silicon region NS should be exposed.

[0163] Next, execute the steps to form n. + The process involves an ion implantation step in the p-type semiconductor region NR and the n-type silicon region NS. In this ion implantation step, an n-type impurity (e.g., arsenic) is implanted. Through this ion implantation step, the n-type impurity is implanted into the semiconductor substrate SUB (specifically, the upper part of the p-type semiconductor region PR) in the MOSFET formation region RG2 to form an n-type semiconductor region NS. +In the diode formation region RG1, n-type impurities are implanted into the portion of the silicon film SF exposed from the opening OP1 of the photoresist pattern RP2 to form an n-type silicon region NS. Since multiple openings OP1 are formed on the silicon film SF, multiple n-type silicon regions NS are formed on the silicon film SF. The photoresist pattern RP2 can be used as a mask layer for forming multiple n-type silicon regions NS on the silicon film SF by ion implantation. Furthermore, in this ion implantation step, it is desirable to adjust the ion implantation energy so that the n-type impurities used as the source region are... + The NR-type semiconductor region has an appropriate thickness.

[0164] Next, as Figure 42 and Figure 43 As shown, an insulating film IL, which serves as an interlayer insulating film, is formed on the main surface (above the entire main surface) of the semiconductor substrate SUB to cover the trench gate electrode TG and the silicon film SF.

[0165] Next, as Figure 44 and Figure 45 As shown, contact holes CTS, CTA, and CTC are formed in the insulating film IL using photolithography and etching techniques. Contact hole CTS is formed in the MOSFET formation region RG2. Figure 45 Contact holes CTA and CTC are formed on the silicon film SF in the diode formation region RG1. Figure 44 Contact hole CTA and contact hole CTC can be formed in the same process. Contact hole CTS can be formed in the same step as contact hole CTA and CTC, or in separate steps.

[0166] The subsequent steps of the second embodiment are almost identical to those of the first embodiment. That is, as follows: Figure 46 and Figure 47 As shown, the plugs PG (PGS, PGA, PGC) are formed in the contact holes CT (CTS, CTA, CTC) in the same manner as in the first embodiment described above. Then, as... Figure 48 and Figure 49 As shown, wiring M1 (M1S, M1A, M1C) is formed on an insulating film IL in which plugs PG (PGS, PGA, PGC) are embedded, in the same manner as in the first embodiment.

[0167] In this second embodiment, n is formed in the semiconductor substrate SUB for forming the MOSFET formation region RG2. + The ion implantation steps for forming multiple n-type silicon regions NS in the silicon film SF are performed in the same manner as those for the n-type semiconductor region NR. This results in the advantage of being able to reduce the number of ion implantation steps in the manufacturing process of this second embodiment.

[0168] Meanwhile, in the first embodiment, the ion implantation step for forming a plurality of n-type silicon regions NS in the silicon film SF can adjust the ion implantation energy according to the thickness of the n-type silicon regions NS to be formed. Therefore, the depth position of the bottom surface of the n-type silicon regions NS can be easily controlled. Therefore, a structure can be formed more precisely in which the depth position of the bottom surface of the n-type silicon regions NS is shallower than the depth position of the lower surface of the silicon film SF, as described in the first embodiment.

[0169] (Third Implementation)

[0170] Figure 50 and Figure 51 This is a plan view of the main parts of the semiconductor device according to the third embodiment. Figure 52 and Figure 53 This is a cross-sectional view of the main part of the semiconductor device according to the third embodiment. Figures 50 to 53 Corresponding to the first embodiment Figures 2 to 5 . Figure 50 and Figure 51 The cross-sectional views at the respective line E1-E1 positions in the diagrams basically correspond to Figure 52 Cross-sectional view, Figure 50 and Figure 51 The cross-sectional views at the respective line E2-E2 positions in the diagrams basically correspond to Figure 53 Cross-sectional view.

[0171] Note that, except for the structure of the diode DD, the structure of the semiconductor device in the third embodiment is almost identical to the structure of the semiconductor device CP in the first embodiment described above. Therefore, in the third embodiment, the following will mainly describe one difference in the structure of the diode DD compared to the first embodiment.

[0172] In the first embodiment described above, the silicon film SF constituting the diode DD has a p-type silicon region PS and a plurality of n-type silicon regions NS, and each of the plurality of n-type silicon regions NS is surrounded by a p-type silicon region PS in a plan view.

[0173] Conversely, in this third embodiment, the silicon film SF constituting the diode DD has a p-type silicon region PS and an n-type silicon region NS, the n-type silicon region NS being surrounded by the p-type silicon region PS, but the number of n-type silicon regions NS formed in the silicon film SF is 1.

[0174] This third embodiment is almost identical to the first embodiment described above, except that the depth of the bottom surface of the n-type silicon region NS formed in the silicon film SF is shallower than the depth of the lower surface of the silicon film SF. Therefore, also in this third embodiment, the thickness of the n-type silicon region NS is less than the thickness of the silicon film SF. Therefore, the n-type silicon region NS does not penetrate the silicon film SF in the thickness direction. Therefore, also in this third embodiment, the n-type silicon region NS is not exposed on the lower surface of the silicon film SF, while the p-type silicon region PS exists below the bottom surface of the n-type silicon region NS. Therefore, also in this third embodiment, the side and bottom surfaces of the n-type silicon region NS are in contact with the p-type silicon region PS, and a PN junction is formed on the side and bottom surfaces of the n-type silicon region NS.

[0175] In this third embodiment, the n-type silicon region NS formed on the silicon film SF is electrically connected to the wiring M1C via a plug PGC. Therefore, although the plug PGC is arranged on the n-type silicon region NS of the silicon film SF, the number of plug PGCs can be any one or more. Figure 51 One scenario is illustrated where two plug PGCs are arranged on an n-type silicon region NS of a silicon film SF; and the n-type silicon region NS and wiring M1C are electrically connected via the two plug PGCs. Figure 51 In this case, the plug PGC has a rectangular planar shape with its longitudinal direction in the Y direction in the plan view, and the two plug PGCs are arranged to be separated from each other in the X direction.

[0176] Apart from the points mentioned above, the configuration of the semiconductor device in this second embodiment is almost the same as the configuration of the semiconductor device CP in the first embodiment described above, so a repeated description of it will be omitted here.

[0177] In this third embodiment, the PN junction is formed not only on the side surface of the n-type silicon region NS, but also on the bottom surface of the n-type silicon region NS. Therefore, this differs from the previously discussed example where no PN junction is formed on the bottom surface of the n-type silicon region NS10. Figure 7 and Figure 8 In contrast, the third embodiment of the present invention, which forms a PN junction on the bottom surface of the n-type silicon region NS, [is different]. Figures 50 to 53 This allows for a larger total surface area of ​​the PN junction constituting the diode DD. In other words, the total area of ​​the PN junction constituting the diode DD can be increased while suppressing the planar dimensions (planar area) of the silicon film SF. Therefore, since the operating resistance of the diode DD can be reduced, the heat generation of the diode DD can be suppressed. Consequently, the reliability of the diode DD can be improved, and correspondingly, the reliability of the semiconductor device CP including the diode DD can be improved. Furthermore, the performance of the semiconductor device CP including the diode DD can be improved. In addition, the semiconductor device can be miniaturized (making the area smaller).

[0178] The first to third embodiments described above are designed to increase the total area of ​​the PN junction constituting the diode DD. There are two methods for increasing the total area of ​​the PN junction constituting the diode DD. The first method is to surround the n-type silicon region NS with a p-type silicon region PS in a planar view, such that the PN junction is formed on the side surface of the n-type silicon region NS; by increasing the number of n-type silicon regions NS formed on the silicon film SF (two or more), the total number of side surfaces of the n-type silicon regions NS is increased; thereby increasing the total area of ​​the side surfaces of the n-type silicon regions NS. The second method is to make the depth of the bottom surface of the n-type silicon region NS shallower than the depth of the lower surface of the silicon film SF, so that the p-type silicon region PS exists below the bottom surface of the n-type silicon region NS; and the PN junction is formed not only on the bottom surface of the n-type silicon region NS but also on the bottom surface of the n-type silicon region NS. The third embodiment of the present invention applies the second method, the second embodiment applies the first method, and the first embodiment applies both the first and second methods.

[0179] Therefore, the first embodiment in the first to third embodiments described above can maximize the total area of ​​the PN junction constituting the diode DD, thereby minimizing the operating resistance of the diode DD. Therefore, the first embodiment described above is most advantageous in terms of improving the reliability of the semiconductor device CP including the diode DD.

[0180] As described above, the inventor's invention has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from its scope, which is self-evident.

Claims

1. A semiconductor device equipped with a diode, comprising: Semiconductor substrate; A silicon film for the diode, the silicon film being formed over the semiconductor substrate via a first insulating film; as well as A first electrode is used for the diode, and a second electrode is formed on the upper layer of the silicon film. The silicon film has a first silicon region of a first conductivity type and a plurality of second silicon regions of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. In the plan view, each of the plurality of second silicon regions is surrounded by the first silicon region. The first silicon region is electrically connected to the first electrode, and The plurality of second silicon regions are electrically connected to the second electrode; In the plan view, each of the plurality of second silicon regions extends along a first direction and is arranged to be separated from each other along a second direction intersecting the first direction; The diode is formed by forming a PN junction between the first silicon region and each of the plurality of second silicon regions; The first silicon region exists below each of the plurality of second silicon regions; The first conductivity type is p-type. The second conductivity type is n-type, and A PN junction is formed on the side and bottom surfaces of each of the plurality of second silicon regions.

2. The semiconductor device according to claim 1, Each of the plurality of second silicon regions is exposed on the upper surface of the silicon film.

3. The semiconductor device according to claim 2, Each of the plurality of second silicon regions is exposed on the lower surface of the silicon film.

4. The semiconductor device according to claim 3, The first conductivity type is p-type. The second conductivity type is n-type, and The PN junction is formed on each side surface of the plurality of second silicon regions.

5. The semiconductor device according to claim 1, in, In the plan view, each of the plurality of second silicon regions has a rectangular planar shape, the longitudinal direction of which is the first direction.

6. The semiconductor device according to claim 5, The planar shape of each of the plurality of second silicon regions has a length of 2 to 40 micrometers in the first direction.

7. The semiconductor device according to claim 1, The first silicon region is electrically connected to the first electrode via a first contact plug, and The plurality of second silicon regions are electrically connected to the second electrode via a plurality of second contact plugs.

8. The semiconductor device of claim 7, further comprising an interlayer insulating film formed between the silicon film and the first electrode and the second electrode. The first contact plug and the plurality of second contact plugs each penetrate the interlayer insulating film.

9. The semiconductor device according to claim 8, In the plan view, the first contact plug overlaps with the first electrode, and in the plan view, the first contact plug overlaps with the first silicon region. In the plan view, the plurality of second contact plugs overlap with the plurality of second silicon regions, and in the plan view, the plurality of second contact plugs overlap with the second electrode.

10. The semiconductor device according to claim 1, The first conductivity type is p-type. The second conductivity type is n-type, and The PN junction is formed between the first silicon region and the plurality of second silicon regions.

11. The semiconductor device according to claim 1, further comprising: A field-effect transistor is formed in the first region of the semiconductor substrate. The silicon film is formed on a second region of the semiconductor substrate via the first insulating film.

12. The semiconductor device according to claim 1, The diode mentioned above is a diode used for temperature detection.

13. A semiconductor device comprising a diode, the semiconductor device comprising: Semiconductor substrate; as well as A silicon film for the diode, the silicon film being formed on the semiconductor substrate via a first insulating film; as well as A first electrode is used for the diode, and a second electrode is formed on the silicon film. The silicon film has a first silicon region of a first conductivity type and a plurality of second silicon regions of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. In the plan view, each of the plurality of second silicon regions is surrounded by the first silicon region. Each of the plurality of second silicon regions is exposed on the upper surface of the silicon film, and The first silicon region exists beneath each of the plurality of second silicon regions, and a PN junction is formed on the side and bottom surfaces of each of the plurality of second silicon regions. The first silicon region is electrically connected to the first electrode via a first contact plug, and Each of the plurality of second silicon regions is electrically connected to the second electrode via a second contact plug; The diode is formed by forming a PN junction between the first silicon region and each of the plurality of second silicon regions; The first conductivity type is p-type. The second conductivity type is n-type, and The PN junction is formed on the side and bottom surfaces of the second silicon region.

14. A method of manufacturing a semiconductor device according to claim 13, the semiconductor device being provided with a diode, the method comprising: (a) A silicon film of a first conductivity type is formed on a semiconductor substrate via a first insulating film and is used for the diode; (b) Forming a mask layer with openings that partially expose the silicon film; as well as (c) Implanting impurity ions of a second conductivity type into the silicon film exposed from the opening to form a silicon region of the second conductivity type in the silicon film, the second conductivity type being opposite to the first conductivity type; Wherein the thickness of the silicon region formed in (c) is less than the thickness of the silicon film, and The PN junction is formed on the side and bottom surfaces of the silicon region.

15. The method of manufacturing a semiconductor device according to claim 14, The mask layer is an interlayer insulating film, and The method further includes: (d) After (c), a contact plug is formed in the opening of the mask layer.

16. The method of manufacturing a semiconductor device according to claim 14, further comprising: (d) Forming a trench gate electrode for a field-effect transistor on the semiconductor substrate; as well as (e) Forming a source region for the field-effect transistor on the semiconductor substrate by ion implantation. The ion implantation in (c) and the ion implantation in (e) are performed by the same ion implantation steps.

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