Reduced leakage transistor with germanium-rich channel region

Abstract

The present invention relates to reduced leakage transistors having germanium-rich channel regions. Techniques for fabricating semiconductor transistor devices configured with sub-fin insulating layers that reduce parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with the transistor) are disclosed. Parasitic leakage is reduced by fabricating transistors in which a sacrificial layer in a sub-fin region of the substrate is below at least one channel region of the fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced in whole or in part with a dielectric material. The dielectric material increases the resistivity of the substrate between corresponding source and drain portions of the fin, thereby reducing parasitic leakage.

Description

[0001] This application is a divisional application. The invention name of the parent application is "Transistor with reduced leakage having a germanium-rich channel region". The application date is December 24, 2025, and the application number is 201580085500.2. Background Art

[0002] FinFET is a transistor built around a thin strip of semiconductor material (commonly referred to as a fin) extending from the underlying substrate. The fin-shaped semiconductor element acts as the channel region of the device. The transistor includes a standard field effect transistor (FET) node, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the transistor effectively exists on each side of the fin below the gate dielectric. Specifically, the current runs along the two sidewalls of the fin / in the two sidewalls of the fin (i.e., on the side perpendicular to the surface of the underlying substrate) and along the top of the fin (i.e., on the side parallel to the surface of the underlying substrate). Since the conductive channel of such a configuration exists essentially along three different external planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor. Other types of FinFET configurations are also available, such as so-called dual-gate FinFETs, in which the conductive channel exists mainly only along the two sidewalls of the fin (and not along the top of the fin). A nanowire transistor (sometimes referred to as a gate-all-around transistor) is actually a fin with a relatively low aspect ratio, because some of the bottom portions of the fin are removed so that the gate stack material can surround the channel region on all sides. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1A and Figure 1B A method for preparing a substrate for forming a reduced leakage transistor according to various embodiments of the present disclosure is illustrated.

[0004] Figure 1C A method for fabricating a reduced leakage transistor using a sub-fin insulation layer according to various embodiments of the present disclosure is illustrated.

[0005] Figure 2A -D illustrates the implementation of various embodiments according to the present disclosure. Figure 1A and 1B The example structure is formed when the method is used.

[0006] Figure 3A -H illustrates the implementation of various embodiments according to the present disclosure Figure 1C The example structure is formed when the method is used.

[0007] Figure 4 A computing system implemented using integrated circuit structures or devices formed using the techniques disclosed herein is illustrated in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0008] Disclosed are techniques for fabricating semiconductor transistor devices configured with a sub-fin insulating layer that reduces parasitic leakage (i.e., current leakage through a portion of an underlying substrate between a source region and a drain region associated with the transistor). In some embodiments, the integrated circuit includes a channel region having a germanium concentration of at least 60 atomic percent ("at. %). Parasitic leakage is reduced by fabricating a transistor with a sacrificial layer in a sub-fin region of a substrate below at least one channel region of a fin. During processing, the sacrificial layer in the sub-fin region is removed and replaced in whole or in part with a dielectric material. The dielectric material increases the resistivity of the substrate between the corresponding source and drain portions of the fin (i.e., the gate-free region below the active channel), thereby reducing parasitic leakage.

[0009] General overview.

[0010] As the size of transistors has been reduced to the nanometer scale, improving the performance of successive generations of semiconductor devices has become more challenging. As the size of transistors has been reduced, materials that were once used only for select applications have been explored for wider applicability of transistors. One such material is germanium (Ge). Using germanium as part of a transistor (particularly the source, drain, and channel regions) improves certain aspects of transistor performance. But using high concentrations of germanium (e.g., more than 40 at. %) in the source, drain, and channel regions also increases current leakage through the substrate in the sub-fin region between the source region of a non-planar transistor (e.g., a finFET) to the drain region of a non-planar transistor. Regardless of the composition of the transistor, "parasitic currents" degrade transistor performance because of increased power consumption and increased heat generation. One solution to address parasitic currents is to fabricate transistors on a substrate that includes a semiconductor layer on an underlying capping layer of an electrical insulator across the entire substrate. This configuration is sometimes referred to as a buried oxide (BOX) layer configuration or a semiconductor-on-insulator (or "XOI," where X is any semiconductor) substrate. An example of a specific XOI substrate includes silicon dioxide (SiO2) on a silicon (Si) substrate. 2 ) capping layer. Transistors that are prone to parasitic leakage fabricated on XOI substrates are more likely to perform well because the capping insulating layer extending across the entire substrate blocks the parasitic leakage path, regardless of where the transistor is fabricated on the substrate. However, the fabrication of XIO substrates and devices can have various disadvantages. Disclosed herein are methods of fabricating structures that include many of the advantages of XOI substrates (e.g., reduced parasitic leakage), even when using "bulk" (e.g., non-XOI) substrates.

[0011] To this end, various embodiments of the present disclosure include transistors and methods of manufacturing transistors, the transistors including an insulating layer in a sub-fin region between an upper channel layer and an underlying substrate. In some embodiments, the insulating layer extends below the channel region of the transistor. In other embodiments, the insulating layer further extends below a portion or all of the source region and / or drain region of the transistor. In some embodiments, the insulating layer does not extend into regions of the substrate other than those corresponding to the source, drain, and channel regions (as opposed to a typical BOX or XOI configuration). In other embodiments, the insulating layer does not extend into inactive regions of the substrate (e.g., regions including electrically inactive or so-called dummified structures provided as part of a global formation process). As will be appreciated, these various embodiments are different from BOX or XOI substrates, in which a capping layer of an insulator extends globally throughout all regions of the substrate, and not just under the channel, source, and drain regions or otherwise in a localized manner. As such, various embodiments of the present disclosure may improve transistor performance by reducing current leakage through the underlying semiconductor substrate without the inconvenience and overhead of BOX / XOI processing, which would otherwise be prone to parasitic leakage.

[0012] In order to improve the electrical isolation between the source and drain regions of the transistor, some of the embodiments of the present disclosure include a technique for providing a sacrificial layer in a sub-fin region (approximately corresponding to the fin of a fin-based transistor) below the source, drain, and channel regions of the transistor. In some embodiments, the sacrificial layer is removed from the sub-fin region approximately corresponding to at least the channel region, thereby etching a cavity below the channel region of the fin. In other embodiments, the sacrificial layer is removed from some or all of the sub-fin regions corresponding to the source, drain, and channel regions so that the cavity below the channel continues at least partially below the source and / or drain regions. It is noted that once the sacrificial layer is removed, the upper channel portion of the fin actually becomes a nanowire channel. Similarly, if the sacrificial layer is also removed from below the source / drain portion of the fin, they actually also become a nanowire-based source / drain. In any such embodiment, the cavity formed by etching is filled in whole or in part with a dielectric material so that the walls of the cavity are at least partially coated with a dielectric material. Whether the cavity is partially or completely coated and / or filled with a dielectric material, the resistivity of the sub-fin region between the source region and the drain region is increased so that parasitic current leakage is reduced or eliminated. This improves the performance of transistors and semiconductor devices that would otherwise be prone to parasitic source-to-drain or drain-to-source leakage. In yet other embodiments, the dielectric-coated cavity is not filled and includes an air gap, or is further filled with some other material, and in one such embodiment, the dielectric-coated cavity is at least partially filled with a gate electrode material (e.g., a metal), so that the dielectric-coated cavity is exposed during a subsequent gate formation process or a so-called replacement metal gate (RMG) process. It is noted that once the sacrificial layer is removed, the upper channel portion of the fin actually becomes a nanowire channel.

[0013] When analyzed (e.g., using scanning / transmission electron microscopy (SEM / TEM), compositional mapping, secondary ion mass spectrometry (SIMS), atom probe imaging, 3D tomography, etc.), a structure or device configured in accordance with one or more embodiments will effectively show a cavity coated or filled with a dielectric layer, or a cavity coated with a dielectric layer and having an air gap (not filled), or a cavity coated with a dielectric and further at least partially filled with an additional material. In any such case, the cavity will be disposed in or on a substrate underlying a channel region of a fin of a non-planar transistor configuration, as described in various ways herein. In some examples, the analysis will show a void within a conformally deposited dielectric layer of the cavity.

[0014] Layer architecture and methodology: sacrificial layer and channel layer blanket deposition .

[0015] Figure 1A and 1BTwo example methods 100 and 130 are illustrated, respectively, for fabricating fins, sacrificial layers, and other structures associated with integrated circuits according to one or more embodiments of the present disclosure. Figure 2A -D illustrate some embodiments of various structures made using the example methods 100 and 130. The example methods 100 and 130 produce Figure 2B and 2D Regardless of which fin formation method 100 or 130 is used, Figure 1C Method 160 illustrates an example method for further processing a fin-based structure resulting from the results produced by example methods 100 and 130. In one embodiment, example method 160 is used to fabricate an integrated circuit transistor device having low current leakage (i.e., "parasitic leakage") through the sub-fin portion of the substrate from the source region to the drain region of the transistor using an insulating layer disposed in a sub-fin region below at least one channel region of the fin. The embodiments described herein may be applied to any number of transistor designs, doping levels, and fin compositions, including fins having a germanium concentration of at least 60 at. %. Figures 3A-3H The picture is provided by Figure 1C The method 160 is used to fabricate an example structure.

[0016] Now turn to Figure 1A In the exemplary method 100, a silicon substrate 104 is provided. Although the method 100 indicates that a silicon substrate is used as a starting point for the process, Figure 1B As with method 130 of the present invention, it will be understood that this is merely for ease of explanation. Any number of suitable substrate configurations may be used as a replacement for silicon, including bulk substrates or multilayer substrate structures of other semiconductors. In a more general sense, any substrate on which a sacrificial fin may be formed may be used. In other implementations, a semiconductor substrate may be formed using an alternative material, which may include, but is not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide (to name a few examples). A substrate may also be formed using semiconductor materials classified as Group III-V or Group IV materials of the periodic table. Although several examples of materials from which a substrate may be formed are described herein, any material that may serve as a basis for constructing a semiconductor device falls within the spirit and scope of the present disclosure.

[0017] In the exemplary method 100, a sacrificial layer is deposited 108 as a blanket layer conforming to a planar surface of a provided substrate. Figure 2A A diagram of this configuration is shown in Figure 2AIn some embodiments, the sacrificial layer 208 is conformally deposited on the substrate 204. In some embodiments, the sacrificial layer 208 is silicon (Si). In still other embodiments, the sacrificial layer 208 is an alloy of germanium and tin (Sn). In still other embodiments, the sacrificial layer 208 is an alloy of silicon and germanium (SiGe). In some embodiments, regardless of the element that forms the alloy with the germanium, the germanium content of the sacrificial layer is less than approximately 40 at.%. In some embodiments, as will be explained in more detail below, the sacrificial layer 208 includes a germanium content of at least 10 at.%, which is less than the germanium content of the subsequent doped channel layer 212 that is ultimately used to make the fin of the non-planar transistor. In still other embodiments, the sacrificial layer 208 includes a germanium content that is at least 20 at.% less than the germanium content of the subsequent doped channel layer 212. This can include a sacrificial layer of silicon (Si). In some examples, the sacrificial layer 208 can include carbon, whether locally concentrated in a carbon-rich region or carbon-rich precipitate, or evenly distributed throughout the sacrificial layer 208. In other embodiments, the sacrificial layer 208 may include a strain-relaxed buffer layer (not shown) of germanium, GeSn, or SiGe adjacent to the substrate 204. In a more general sense, the sacrificial layer 208 is a material that exhibits sufficient selectivity to the channel layer 212 so that when the sacrificial layer 208 is etched away, the channel layer 212 remains substantially intact.

[0018] The sacrificial layer 208 (regardless of composition) is either native to the substrate or deposited using any suitable technique, including chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), rapid thermal CVD (RTCVD), gas source MBE (GS-MBE), and others.

[0019] Continuing with the example method 100, and continuing with reference to Figure 2A, a channel layer 212 is conformally deposited 112 as a capping layer on a sacrificial layer 208. The channel layer corresponds to a material used to form a fin in a fin-based transistor when etched. In some embodiments, the channel layer 212 is an alloy of a semiconductor material with a high germanium content. For example, in some embodiments, the germanium content of the channel layer 212 is at least 60 at.%. In other embodiments, the germanium content of the channel layer 212 is at least 70 at.%. In other embodiments, the germanium content of the channel layer 212 is at least 80 at.%. In other embodiments, the germanium content of the channel layer 212 is at least 90 at.%. In some embodiments, regardless of the specific concentration value of germanium in the channel layer 212, the concentration is at least 10 at.% higher than the germanium concentration in the sacrificial layer 208, or at least 20 at.%. In other embodiments, the concentration of germanium in the channel layer 212 is approximately 10 at.% to approximately 90 at.% higher than the germanium concentration in the sacrificial layer 208. In still other embodiments, the germanium concentration in the channel layer 212 is at least 98 at. % higher than the germanium concentration in the sacrificial layer 208.

[0020] although Figure 2B The channel layer 212 of the embodiment in is shown as including a single composition, but in other embodiments the channel layer 212 may include more than one layer, each of which has a different germanium concentration (e.g., from approximately 10 at.% to approximately 70 at.% higher than the germanium concentration of the sacrificial layer 208). In other examples, the channel layer 212 may include a configuration of multiple layers, some of which have a germanium concentration from approximately 10 at.% to approximately 70 at.% higher than the germanium concentration in the sacrificial layer 208, and others of which are insulating layers or layers of similar composition to the sacrificial layer 208, such that those layers are removed along with the sacrificial layer 208 to free up the remaining channel layer 212 having a higher germanium at.%. These latter examples may be used, for example, to fabricate nanowires or nanoribbons from the channel layer 212 in a given channel region.

[0021] Regardless of the final structure of the fin, the channel layer 212 may be deposited using any suitable technique, such as CVD, ALD, MBE, and others.

[0022] The example method 100 continues by applying a pattern mask and etching 116 trenches through both the channel layer 212 and the sacrificial layer 208, and into the substrate 204. When etching 116 the trenches, the separate columns of the sacrificial layer 208 and the channel layer 212 are referred to as "fins." In some examples, the width of the etched trenches can be determined to produce fins having a height (H) to width (W) aspect ratio of at least 3 to 1.

[0023] As in Figure 2B As shown in FIG. 1 , a dielectric material 216 is deposited 120 in the trenches to electrically isolate the fins from each other. This structure 216 may be referred to as "shallow trench isolation" or "STI." Although only the structure 216 is shown disposed in FIG. Figure 2B The space between the two fins in FIG. 1 is filled with a trench having STI 216 , but it will be appreciated that this is for ease of illustration only and that the structure may be repeated thousands or millions of times within each semiconductor device.

[0024] In some embodiments, the pattern mask application and etching 116 can be accomplished, for example, using standard photolithography and includes wet or dry etching, or a combination of etching (if desired). The geometry of the groove (width, depth, shape, etc.) can vary depending on the embodiment (as will be appreciated), and the embodiments described herein are not intended to be limited to any particular groove geometry. In a specific example embodiment, a hard mask (i.e., a mask formed of, for example, a silicon oxide and / or silicon nitride layer and not an organic photolithography mask) deposited on the surface of the channel layer 212 is used to protect the area corresponding to the fin from the dry etching used to form the groove. As will be appreciated, any number of groove configurations can be used depending on the desired fin height. The grooves can then be filled using any number of appropriate deposition processes. In a specific embodiment having a silicon substrate, the insulating STI dielectric material is SiO 2 , but any number of suitable isolation dielectric materials may be used to form the shallow trench isolation structures herein. In general, the isolation dielectric material deposited or otherwise grown to fill the trench may be selected, for example, based on compatibility with the native oxide of the substrate material.

[0025] exist Figure 2B In the embodiment shown in , the deposited STI 216 and exposed surfaces of the channel layer 212 are planarized 124 using, for example, chemical mechanical planarization (CMP) or other suitable process capable of planarizing the structure. In the example embodiment shown, any mask on the fin and STI is completely removed. Other embodiments may utilize selective planarization configured to leave a portion of the mask in place (which may be used in subsequent processing).

[0026] Figure 2B The resulting example structure shown in therefore includes a plurality of fins (only two of which are shown in this case), each of which includes a sacrificial layer 208 in contact with and disposed between the substrate 204 and the channel layer 212 .

[0027] Layer architecture and methodology: sacrificial and channel layer growth .

[0028] Figure 1B Example method 130 illustrates an alternative method for making a similar structure. Figure 1B and 2C In both cases, the exemplary method 130 begins by providing 134 a silicon substrate 204. Figure 1A As explained in the context of the example method 100, the composition of the substrate 204 can be any of a number of semiconductors. In this example, for ease of explanation only, the substrate 204 is presented as silicon. Compared to the method 100 of depositing a capping layer that is subsequently etched to create a trench and then filled with a dielectric material, the method 130 etches 138 a trench into the substrate 204 using any of the etching techniques already described above. As described in Figure 2C As shown in , STI 216 is then utilized to fill the trenches etched into substrate 204 , thus defining “native” fins 220 having the same composition as substrate 204 (in this case silicon).

[0029] The example method 130 continues with etching 146 the native fin 200 to create trenches between regions of the STI 216. In some embodiments, the STI 216 is protected using a mask, which can be any suitable material that will be subjected to the recessed etching of the unmasked fin and also subjected to any subsequent processing to fill the recess with the material described below. Any suitable etching process (e.g., wet and / or dry etching with masking and / or etching selectivity) can be used. In an example embodiment, the recess etch is a selective etch that will remove the unmasked fin material but not the STI or mask material. In this case, it is noted that the mask material can also be implemented using STI materials (e.g., silicon dioxide) or any other material that resists fin recess etching (e.g., silicon nitride). In a specific example embodiment, the native fin is silicon and the mask is silicon dioxide and / or silicon nitride, and the recess etch is implemented using a wet etch (e.g., potassium hydroxide or other suitable etchants that will etch the unmasked silicon fin but not the STI and mask).

[0030] The depth of the native fin etch may vary according to different embodiments. In the example method 130, the native fin etch 146 removes a portion of the fin. In some embodiments, the etching process may change the width of the recess, wherein in some such cases the top of the trench is wider than the bottom. In another embodiment where the original native fin is wider at the bottom than the top, the top may widen to a width closer to the bottom or exceeding the width at the bottom. In yet another embodiment, the recess may end in a micro-hourglass shape that is wider at the top and bottom than in the middle. In yet another embodiment, the width may remain essentially unchanged by the etching process. In a more general sense, the shape of the recess / fin may be changed by the etching process, but not necessarily. The thickness of the sacrificial layer and the extent of the native fin removal (i.e., the depth of the resulting trench) determine the height of the replacement fin and therefore the size of the portion of the replacement fin that contacts the gate that will form the channel. Because non-native materials (e.g., non-Si) may sometimes be more difficult to passivate (when compared to typical STI materials (e.g., SiO 2 ) contact), so in some embodiments the replacement fin is configured so that its entire height contacts the gate stack. In other embodiments, the replacement fin can extend under the gate and into the substrate.

[0031] The example method 130 continues with deposition 150 of a sacrificial layer 208 at the bottom of the native fin trench corresponding to the bottom of the native fin trench. Figure 2D 1. Once the sacrificial layer 208 is deposited, the channel layer 212 is deposited 154 on top of the sacrificial layer 208. The deposition 150 and 154 of the sacrificial layer 208 and the channel layer 212 are performed using any suitable technique, including those masking, deposition, and etching techniques described above.

[0032] In the example method 100 and Figure 1A and 2B Example compositions of the sacrificial layer 208 and the channel layer 212 are described in the context of and are equally applicable to the example compositions fabricated by the example method 130 and in Figure 2D The embodiment shown in FIG.

[0033] As above Figure 1A As described in the context of the method 100 shown in FIG. 1 , the exposed surfaces of the deposited 142 , 154 channel layer 212 and STI 216 are planarized 158 . Thus, the example method 130 produces Figure 2D The structure shown in FIG. 1 is similar to that of Figure 2B The example structure produced by method 100 is shown in FIG.

[0034] Germanium-Rich Channel Region Architecture and Methodology .

[0035] Whether the example method 100, the example method 130, a variation of the method 100 or 130, or another method is used to make Figure 2B and 2D The structure shown in (or equivalent structure) is Figure 1C An example method 160 is shown in FIG. 1 to illustrate one example method of fabricating a transistor having a germanium-rich channel region with low parasitic leakage. Figures 3A-3H Examples of structures fabricated by performance of method 160 are provided.

[0036] The example method 160 provides 164 such as in Figure 2B and 2D , both structures include fins that include a sacrificial layer 208 disposed between a substrate 204 and a channel layer 212. As shown, the fins are interdigitated by STI 216. A portion of the STI 216 is removed by etching, leaving a remaining layer of STI 216 between the fins 212 (which include the sub-fin portions of the sacrificial layer 208) and on the substrate 204.

[0037] As in Figure 3A As shown in , a dummy gate electrode 304 and a dummy gate dielectric 308 are deposited 172 on a portion of each of the fins. The dummy gate dielectric 308 can be provided prior to the deposition of the dummy gate electrode 304 material. The gate dielectric 308 is referred to as a dummy gate dielectric in the sense that in some embodiments the dummy gate dielectric can be removed and replaced in a subsequent RMG process. Example dummy gate dielectric materials include, for example, silicon dioxide, and example dummy gate electrode materials include polysilicon, although any suitable dummy / sacrificial gate dielectric and / or electrode materials may be used. As will be appreciated, the size of the gate material will vary according to different embodiments and can be configured as desired, depending on factors such as desired device performance attributes, device size, and gate isolation. In some embodiments, processing of the portion of the fin to be used as a source and drain, such as dopant implementation, is performed.

[0038] Figure 3BA structure is illustrated in which (one or more) additional insulator layers 312 are deposited 176 on top of the dummy gate electrode material 304 and planarized to the top of the dummy gate electrode material 304 according to an embodiment of the present disclosure. Any suitable deposition process (e.g., CVD, PVD, ALD) may be used, and the deposited insulator material may be, for example, the same material as the STI fill material (e.g., silicon dioxide) or any suitable material having the desired insulating / dielectric properties for a given application. Planarization of the additional insulator material 312 may be performed, for example, using CMP with the dummy gate electrode material 304 as an etch stop. The dummy gate electrode 304 and the dummy gate dielectric 308 are also removed 176 to leave an additional insulator layer on the fin. The dummy gate stack removal process may be performed, for example, via an etching process that is selective to the dummy gate material, and the dummy gate stack removal process does not significantly remove the additional insulator material 312 or the underlying fin material. As will be appreciated, many etching schemes may be used. This exposes a portion of each fin that will correspond to the channel region below the final gate dielectric and the final gate electrode in the final transistor.

[0039] Figure 3C Graphic by Figure 3B The structure indicated in Figure 3B A cross-sectional view of the structure in . Figure 3C As shown in , additional dielectric material 312 is disposed at opposite ends of each channel layer 212, leaving exposed a central portion of each channel layer 212 that will correspond to the channel region in the active FinFET or nanowire device (which was previously covered by the dummy gate electrode 304 and the dummy gate dielectric 308). Figure 3C As shown in FIG. 2 , a sacrificial layer 208 is disposed between each channel layer 212 and the substrate 204. In some embodiments, the sacrificial layer 208 is disposed parallel to and in contact with the corresponding channel layer 212. Figure 3C In the embodiment shown in , the sacrificial layer 208 is coextensive with the corresponding channel layer 212 (i.e., the two layers have the same length). In other embodiments, the sacrificial layer 208 is arranged to be parallel to and in contact with a portion of the corresponding channel layer 212 (such as only the channel region, or only a portion of the channel region and the source / drain region, or only the channel region and all the source / drain regions).

[0040] Despite Figure 3C Not shown in the cross-sectional view of , the remaining layer of dielectric material 216 is disposed in the plane of sacrificial layer 208 and may have a height that is entirely coextensive with sacrificial layer 208 or only partially coextensive with sacrificial layer 208 .

[0041] Regardless of the degree of overlap between the remaining layers of STI 216, the fins and the sacrificial layer 208, the remaining layers of STI 216 are etched 180 using any of the above techniques to expose a step of the sacrificial layer 208. This configuration is in Figure 3F Zhongcong Figure 3B 20 (obtaining a cross section perpendicular to the fin). That is, the remaining layer of STI 216 adjacent to sacrificial layer 208 is etched such that the exposed "top" surface of STI 216 is slightly lower than the interface between channel layer 212 and sacrificial layer 208, thereby exposing the top portion or "step" of the sidewall of sacrificial layer 208. In one embodiment, the exposed step of sacrificial layer 208 is about 1 nm to about 10 nm in height from the exposed "top" surface of dielectric material 212 to the interface between sacrificial layer 208 and channel layer 212. Although in Figure 3F Only one side is shown as including one step, but both sides of the remaining STI layer 216 may be etched to expose the step of the sacrificial layer 208 .

[0042] by Figure 1C The example method 160 shown in FIG. 1 continues by etching 184 the sacrificial layer, after thus exposing the step length of the sacrificial layer 208. The etch 184 removes the sacrificial layer 208 to form a cavity 320. The cavity 320 is defined by the surrounding surface of the channel layer 212, the remaining layers of the STI 216, and the substrate 204. Figure 3D China-Israel Figure 3C The same view is shown (obtaining a cross section parallel to the fin). Note that the Figure 3C The sacrificial layer 208 is shown in FIG. Figure 3D The remaining layers of STI 216 are shown now exposed in this view by the removal of sacrificial layer 208. Figure 3G Zhong Cong and Figure 3F The same view shows the configuration (obtaining a cross section perpendicular to the fin). Because the sacrificial layer has been removed, Figure 3F The "step size" of the sacrificial layer in is now Figure 3G The "gap" in .

[0043] In some examples, the etch 184 used to remove the sacrificial layer 208 is selective to the composition used to make the sacrificial layer 208. That is, in one embodiment, the etch 184 selectively removes materials having a germanium concentration less than approximately 40 at.%, regardless of other alloying elements present in the sacrificial layer 208. In still other examples, the etch 184 selectively removes compositions having a germanium content less than at least 10 at.% of the germanium content of the channel layer 212. In still other examples, the etch 184 selectively removes compositions having a germanium content less than at least 20 at.% of the germanium content of the channel layer 212. In other examples, the etch 184 selectively removes silicon. In some embodiments, the etch 184 enables the channel layer 212 having a germanium content greater than 60 at.% or 80 at.% to remain substantially unaffected by the etch 184 while the sacrificial layer 208 is removed to create the chamber 320.

[0044] After creating cavity 320, cavity 320 may now be filled by depositing 188 a dielectric layer 324 within cavity 320. Figure 3E Zhong Cong and Figure 3C The same perspective shows the structure (obtaining a cross section parallel to the fin). Figure 3H Zhong Cong and Figure 3F The same viewing angle shows the structure (taking a cross section perpendicular to the fin). Because dielectric layer 324 is disposed in whole or in part between channel layer 212 and substrate 204 , dielectric layer 324 provides insulation between those portions.

[0045] In one embodiment, the deposition 188 of the dielectric layer 324 is performed using atomic layer deposition (ALD) to deposit a conformal layer on the surfaces of the walls defining the cavity 320. Figure 3E and 3H An example structure is shown in FIG. In this example, a dielectric layer 324 has been deposited on each surface of the cavity 320 so as to coat the cavity walls but not completely fill the cavity. Figure 3E The dashed lines in FIG. 3 (indicating that the elongated void is shown within the dielectric layer 324) and Figure 3H328 in the solid line 328 to indicate an air gap or void 328 within the conformally deposited dielectric layer. In the example shown, the length of the elongated void is parallel to the length of the fin. In other embodiments, the cavity 320 is completely filled with the dielectric layer 324. In still other embodiments, the cavity 320 is not completely filled with the dielectric layer 324, but rather the cavity 320 is pinched-off at the gap. To this end, the degree to which the cavity 320 is filled may vary according to different embodiments, depending on factors such as when the pinch-off occurs and the size of the gap. In other embodiments, methods other than ALD may be used to deposit 188 the insulating layer 324 within the cavity 320. These other methods may include, among others, CVD.

[0046] Example materials for replacing insulating layer 324 include silicon dioxide, silicon nitride, or other dielectric materials described above.

[0047] After the dielectric layer 324 is deposited, the formation of the transistor can be completed by depositing the final gate dielectric and gate electrode material, for example, as part of a "replacement metal gate" (RMG) process. It is noted that, according to some embodiments, the dielectric layer 324 can be provided when the replacement gate dielectric is provided. In addition, in some embodiments, if the gap is not pinched off, the cavity 320 can be further filled with a replacement gate metal. It is noted that pinching off of the gap can occur at any point during the various deposition processes (which is good), as long as the cavity 320 wall is coated with a dielectric material 324 sufficient to prohibit leakage of the sub-fin. In addition or alternatively, the completion of the transistor includes forming an electrical contact on the source / drain region of the fin. This can be achieved, for example, by first depositing an additional insulator material and flattening the additional insulator material to provide a surface suitable for any further processing. Then, a contact trench through the additional insulator material can then be etched on the source / drain region. The trench is then filled with contact material using any of a variety of deposition methods. Example source drain contact materials include, for example, tungsten, titanium, silver, gold, aluminum, copper, cobalt, and alloys thereof. The contact may include multiple layers, such as a work function tuning layer, a resistance reducing layer, and a cap layer.

[0048] Example system.

[0049] Figure 4A computing system 1000 is illustrated that is implemented using an integrated circuit structure or device formed using the techniques disclosed herein, according to an example embodiment. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a number of components, including but not limited to a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to the motherboard 1002, or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, either a motherboard, a daughterboard mounted on a motherboard, or a board of the system 1000 alone, and the like.

[0050] Depending on its application, the computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any of the components included in the computing system 1000 may include one or more integrated circuit structures or devices formed using the technology disclosed in accordance with the example embodiments. In some embodiments, multiple functions may be integrated into one or more chips (e.g., for example, it is noted that the communication chip 1006 may be part of the processor 1004 or otherwise integrated into the processor 1004).

[0051] The communication chip 1006 enables wireless communication for data to and from the computing system 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc. that can convey data through non-solid media using modulated electromagnetic radiation. The term does not mean that the associated device does not contain any wires, although in some embodiments they may not contain any wires. The communication chip 1006 can implement any of many wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. The computing system 1000 can include multiple communication chips 1006. For example, the first communication chip 1006 may be dedicated to shorter range wireless communications (such as WiFi and Bluetooth) and the second communication chip 1006 may be dedicated to longer range wireless communications (such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others).

[0052] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the integrated circuit die of the processor includes on-board circuitry implemented using one or more integrated circuit structures or devices formed using the disclosed techniques as described in various ways herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0053] The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed technology as described in various ways herein. As will be appreciated in view of this disclosure, it is noted that multi-standard wireless capabilities can be directly integrated into the processor 1004 (e.g., in this case the functionality of any chip 1006 is integrated into the processor 1004, rather than having a separate communication chip). It is further noted that the processor 1004 can be a chipset with such wireless capabilities. In short, any number of processors 1004 and / or communication chips 1006 can be used. Likewise, any one chip or chipset can have multiple functions integrated therein.

[0054] In various implementations, the computing device 1000 may be a laptop computer, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques as described in various ways herein.

[0055] Further example embodiments .

[0056] The following examples pertain to further embodiments from which numerous permutations and configurations will be apparent.

[0057] Example 1 is an integrated circuit transistor device, comprising: a substrate; a semiconductor fin extending from the substrate, the fin comprising: a channel layer including a channel region, a source region, and a drain region; and a sub-fin insulating layer including a cavity, the cavity being disposed between the channel layer and the underlying substrate, wherein the cavity is defined by a wall lined with a dielectric material.

[0058] Example 2 includes the subject matter of Example 1, wherein the cavity disposed between the channel layer and the underlying substrate further extends such that it is also between the substrate and at least a portion of one or both of the source and drain regions of the fin.

[0059] Example 3 includes the subject matter of Examples 1-2, further comprising a gate dielectric material on the channel region; and a gate electrode material on the gate dielectric material.

[0060] Example 4 includes the subject matter of Example 3, wherein the dielectric material lining the cavity is the same as the gate dielectric material.

[0061] Example 5 includes the subject matter of Example 4, wherein the cavity lined with the gate dielectric material is further at least partially filled with the gate electrode material.

[0062] Example 6 includes the subject matter of any of Examples 1 and 2, further comprising: a gate dielectric material on the channel region; and a gate electrode material on the gate dielectric material, wherein the dielectric material forming the lining of the cavity is a different material than the gate dielectric material.

[0063] Example 7 includes the subject matter of any of Examples 1-6, wherein the channel layer comprises at least 80 at. % germanium.

[0064] Example 8 includes the subject matter of any of Examples 1-7, wherein the sub-fin insulation layer has a length corresponding to an entire length of the fin.

[0065] Example 9 includes the subject matter of any of Examples 1-8, wherein the sub-fin insulation layer has a width corresponding to a width of the fin.

[0066] Example 10 includes the subject matter of any of Examples 1-9, wherein the dielectric material lining the walls of the cavity further defines an elongated void having a length parallel to a length of the fin.

[0067] Example 11 includes the subject matter of any of Examples 1-10, wherein the cavity comprises an air gap.

[0068] Example 12 includes the subject matter of any of Examples 1-11, wherein the cavity is pinched off.

[0069] Example 13 includes the subject matter of any of Examples 1-12, wherein the cavity is at least partially filled with another material different than the dielectric material lining the walls of the cavity.

[0070] Example 14 includes the subject matter of any of Examples 1-13, wherein the wall of the cavity is completely coated with a dielectric material that forms a lining of the wall of the cavity such that all portions of the cavity wall are coated with the dielectric material.

[0071] Example 15 includes the subject matter of any of Examples 1-14, further comprising an inactive fin proximate the fin, the inactive fin comprising: an inactive channel layer extending from the substrate and a sub-fin region below the inactive channel layer, the sub-fin region having a same composition as the substrate.

[0072] Example 16 is a computing system comprising the integrated circuit of any of Examples 1-14.

[0073] Example 17 is a semiconductor device comprising: a substrate; a plurality of active fins extending from the substrate, each of the active fins comprising: a channel layer comprising a channel region, a source region, and a drain region; and a sub-fin insulating layer comprising a cavity, the cavity being disposed between the channel layer and an underlying substrate, and between the substrate and at least a portion of each of the source region and the drain region, wherein the cavity is defined by a wall lined with a dielectric material; and a plurality of inactive fins extending from the substrate, each of the inactive fins comprising: an inactive channel layer extending from the substrate; and a sub-fin region below the inactive channel layer, the sub-fin region having the same composition as the substrate.

[0074] Example 18 includes the subject matter of Example 17, and further includes a gate dielectric material on the channel region and a gate electrode material on the gate dielectric material.

[0075] Example 19 includes the subject matter of Example 18, wherein the dielectric material lining the cavity is the same as the gate dielectric material.

[0076] Example 20 includes the subject matter of Example 19, wherein the cavity lined with the gate dielectric material is further at least partially filled with the gate electrode material.

[0077] Example 21 includes the subject matter of Example 18, further comprising a gate dielectric material on the channel region and a gate electrode material on the gate dielectric material, wherein the dielectric material lining the cavity is a different material than the gate dielectric material.

[0078] Example 22 includes the subject matter of any of Examples 17-21, wherein the channel layer comprises at least 80 at. % germanium.

[0079] Example 23 includes the subject matter of any of Examples 17-22, wherein the sub-fin insulation layer has a length corresponding to an entire length of the fin.

[0080] Example 24 includes the subject matter of any of Examples 17-23, wherein the sub-fin insulation layer has a width corresponding to a width of the fin.

[0081] Example 25 includes the subject matter of any of Examples 17-24, wherein the dielectric material lining the walls of the cavity further defines an elongated void having a length parallel to a length of the fin.

[0082] Example 26 includes the subject matter of any of Examples 17-25, wherein the cavity comprises an air gap.

[0083] Example 27 includes the subject matter of any of Examples 17-26, wherein the cavity is pinched off.

[0084] Example 28 includes the subject matter of any of Examples 17-27, wherein the cavity is at least partially filled with another material different than the dielectric material lining the walls of the cavity.

[0085] Example 29 includes the subject matter of any of Examples 17-28, wherein the wall of the cavity is completely coated with a dielectric material that forms a lining of the wall of the cavity such that all portions of the cavity wall are coated with the dielectric material.

[0086] Example 30 is a computing system comprising the integrated circuit of any of Examples 17-29.

[0087] Example 31 is a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising: at least one fin including a channel layer, a dielectric layer between each of the at least one fin, and a sacrificial layer in a sub-fin area between the substrate and the channel layer; removing a portion of the dielectric material between each of the at least one fin to expose the sacrificial layer; removing at least a portion of the sacrificial layer from the sub-fin area between the substrate and the channel layer, thereby exposing a cavity; and depositing a dielectric material in the cavity.

[0088] Example 32 includes the subject matter of Example 31, wherein the sacrificial layer in the sub-fin region does not extend under the dielectric layer between at least one fin.

[0089] Example 33 includes the subject matter of any of Examples 31 and 32, wherein the dielectric material is conformally deposited on a surface of a wall defining the cavity.

[0090] Example 34 includes the subject matter of any of claims 31-33, wherein the conformal deposition of the dielectric defines an elongated void within the cavity.

[0091] Example 35 includes the subject matter of any of claims 31-34, wherein the deposition of the dielectric causes pinching off at an opening of the cavity, the opening corresponding to the step size.

[0092] Example 36 includes the subject matter of any of claims 31-35, wherein the portion of the sacrificial layer to be removed is disposed below a channel region of the at least one fin.

[0093] Example 37 includes the subject matter of any of claims 31-36, wherein the portion of the sacrificial layer to be removed is disposed below the channel region and at least a portion of the source and drain regions of the at least one fin.

[0094] Example 38 includes the subject matter of any of claims 31-37, and further includes disposing an additional material in the cavity, the additional material being different from the dielectric material.

[0095] The foregoing description of the example embodiments has been given for the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in view of the disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but by the claims appended hereto. Future applications filed claiming priority to this application may claim the disclosed subject matter in different ways, and such future applications filed may generally include any set of one or more limitations as disclosed or otherwise set forth herein in a variety of ways.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate and a channel layer on the substrate, wherein at least one fin including the channel layer is between a source region and a drain region, a dielectric layer is between each of the at least one fin, and a sacrificial layer is in a sub-fin region between the substrate and the channel layer; removing a portion of the dielectric material between each of the at least one fin to expose a step of the sacrificial layer; removing at least a portion of the sacrificial layer from the sub-fin region between the substrate and the channel layer, thereby exposing the cavity defined by the wall; as well as A dielectric material is deposited in the cavity such that walls defining the cavity are completely lined with the dielectric material and the dielectric material-lined cavity defines an air gap. 2 . The method of claim 1 , wherein the sacrificial layer in the sub-fin region does not extend under the dielectric layer between at least one fin.

3. The method of any of claims 1-2, wherein the dielectric material is conformally deposited on surfaces of walls defining the cavity.

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