Substrate-less semiconductor device assembly having multiple semiconductor devices and method for manufacturing the same
CN113838822BActive Publication Date: 2025-03-28MICRON TECHNOLOGY INC
-1 Cites -1 Cited by
Patent Information
- Application Number
- CN202110623214.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-06-08
- Filing Date
- 2021-06-04
- Publication Date
- 2025-03-28
- Estimated Expiration
- 2041-06-04
AI Technical Summary
Technical Problem
The prior art is difficult to effectively include multiple semiconductor dies in a single package, and the packaging process is complex and expensive.
Method used
By providing a semiconductor device assembly with an upper RDL and a lower RDL, each RDL is configured to be coupled to a corresponding die, the die is arranged back to back and electrically connected by an interconnect in the RDL.
Benefits of technology
The efficient inclusion of multiple semiconductor dies in a single package is achieved, simplifying the packaging process, reducing costs, and improving the overall performance of the package.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN113838822B_ABST
Abstract
The present application relates to a substrate-less semiconductor device assembly having a plurality of semiconductor devices and a method for manufacturing the same. A semiconductor device assembly comprises: a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die, the first semiconductor die being directly coupled to an upper surface of the first RDL through a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite to the lower outermost planar surface; a second semiconductor die, the second semiconductor die being directly coupled to a lower surface of the second RDL through a second plurality of interconnects; a packaging material, the packaging material being disposed between the first RDL and the second RDL and at least partially packaging the first semiconductor die and the second semiconductor die; and a third plurality of interconnects, the third plurality of interconnects extending completely between and directly coupled to the upper surface of the first RDL and the lower surface of the second RDL.
Need to check novelty before this filing date? Find Prior Art