Display device comprising lower metal lines

Abstract

A display device including a lower metal line is provided. The display device includes a display area including a plurality of pixels and a non-display area located around the display area. The display device further includes a base substrate, a lower metal line arranged on the base substrate and surrounding at least a portion of the display area in a plan view, and a gate layer arranged on the lower metal line. In the non-display area, the lower metal line does not overlap the gate layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0069122, filed on June 8, 2020, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device including a lower metal wire. Background Technology

[0004] Display devices are widely used in a wide variety of products. For example, they are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. The most common types of display devices are flat panel displays, such as liquid crystal displays (LCDs), field emission displays, and light-emitting displays such as organic light-emitting diode (OLED) displays. Summary of the Invention

[0005] The display device includes a display area comprising a plurality of pixels and a non-display area surrounding the display area. The display device includes a base substrate, a lower metal line disposed on the base substrate and surrounding at least a portion of the display area in a plan view, and thin-film transistors disposed on the lower metal line and included in the plurality of pixels. The thin-film transistor includes a channel, a first electrode, a second electrode, and a gate electrode overlapping the channel. The thin-film transistor includes a driving transistor and a switching transistor. The lower metal line overlaps only with one of the channels of the driving transistor and the switching transistor.

[0006] The display device includes a display area comprising a plurality of pixels and a non-display area surrounding the display area. The display device includes a base substrate, a lower metal line disposed on the base substrate and surrounding at least a portion of the display area in a plan view, and a gate layer disposed on the lower metal line. In the non-display area, the lower metal line does not overlap with the gate layer. Attached Figure Description

[0007] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0008] Figure 1 This is a perspective view showing a display device according to an exemplary embodiment of the present disclosure;

[0009] Figure 2 This is a plan view showing the folded state of a display device according to an exemplary embodiment of the present disclosure;

[0010] Figure 3 This is a plan view of a display panel according to an exemplary embodiment of the present disclosure;

[0011] Figure 4 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

[0012] Figure 5 This is a plan view of a display panel including a lower metal wire according to an exemplary embodiment of the present disclosure;

[0013] Figure 6 This is a circuit diagram specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0014] Figure 7 This is a plan view specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0015] Figure 8 This is a plan view specifically illustrating a sub-pixel with a lower metal line arranged according to an exemplary embodiment of the present disclosure;

[0016] Figure 9 yes Figure 8 A magnified view of region E1;

[0017] Figure 10 yes Figure 8 A magnified view of region E2;

[0018] Figure 11 It shows the arrangement of Figure 8 A diagram of the gate electrode region of the driving transistor;

[0019] Figure 12 yes Figure 5 An enlarged view of area A;

[0020] Figure 13 It is along Figure 12 A cross-sectional view taken by line I-I';

[0021] Figure 14 It is along Figure 12 A cross-sectional view taken from line II-II';

[0022] Figure 15 It is along Figure 12 A cross-sectional view taken from line III-III';

[0023] Figure 16 yes Figure 5 A magnified view of area B;

[0024] Figure 17 It is along Figure 16 A cross-sectional view taken by line IV-IV';

[0025] Figure 18 This is a plan view showing the lower side of the bent area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0026] Figure 19 This is a plan view showing the area between the display area and the bending area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0027] Figure 20 This is a circuit diagram specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0028] Figure 21 This is a plan view specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0029] Figure 22 yes Figure 21 A magnified view of region E3;

[0030] Figure 23 yes Figure 21 A magnified view of area E4;

[0031] Figure 24 yes Figure 21 A magnified view of area E5;

[0032] Figure 25 This is a circuit diagram specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0033] Figure 26 This is a plan view specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0034] Figure 27 yes Figure 26 A magnified view of area E6;

[0035] Figure 28 yes Figure 26 A magnified view of area E7;

[0036] Figure 29 yes Figure 26 A magnified view of area E8;

[0037] Figure 30 This is a circuit diagram specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0038] Figure 31 This is a plan view specifically illustrating a sub-pixel according to an exemplary embodiment of the present disclosure;

[0039] Figure 32 yes Figure 31 A magnified view of region E9;

[0040] Figure 33 yes Figure 31 A magnified view of area E10; and

[0041] Figure 34 yes Figure 31 A magnified view of region E11. Detailed Implementation

[0042] What will be understood is that when an element is referred to as relating to another element, such as by being “connected” or “linked” to another element, it can be directly connected to or linked to the other element, or an intermediate element may exist between them. Other expressions explaining the relationship between elements, such as “between” or “adjacent to”, should also be interpreted in the same way.

[0043] Throughout the specification, the same reference numerals may refer to the same or similar parts.

[0044] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not necessarily be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or section from another. Therefore, the terms “first element,” “component,” “area,” “layer,” or “part” discussed below may refer to a second element, component, area, layer, or section without departing from the teachings herein.

[0045] Unless the context clearly indicates otherwise, the terms “a(a)”, “an(an)”, “the”, and “at least one” as used herein do not indicate a limitation on quantity and are intended to include both singular and plural forms. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element”. “At least one” will not be construed as a limitation on “a(a)” or “an(an)”. “Or” means “and / or”. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that the terms “comprise” and / or “comprising”, or “include” and / or “including”, when used in this specification, indicate the presence of the referred features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0046] Furthermore, relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, relative terms are also intended to cover different orientations of the device. For example, if a device in a figure is flipped, an element described as being “below” the other element will be oriented as being “above” the other element. Thus, depending on the specific orientation of the figure, the exemplary term “lower” can cover both the orientations of “lower” and “upper”. Similarly, if a device in a figure is flipped, an element described as being “below” or “under” the other element will subsequently be oriented as being “above” the other element. Thus, the exemplary terms “below” or “under” can cover both the orientations of “above” and “below”.

[0047] Given the measurements discussed and the errors associated with a particular number of measurements (i.e., constraints of the measurement system), the terms "about" or "approximately" as used herein include the values ​​mentioned and mean within an acceptable range of deviation from the particular values ​​as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the values ​​mentioned and.

[0048] Exemplary embodiments are described herein with reference to cross-sectional views as schematic illustrations of idealized implementations. Therefore, variations in the shapes of the illustrations due to factors such as manufacturing techniques and / or tolerances are expected. Consequently, the embodiments described herein should not be construed as necessarily limited to the specific shapes of the regions shown herein, but will include shape deviations due to factors such as manufacturing. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not necessarily limited to the precise shapes of the regions.

[0049] Figure 1 This is a perspective view showing a display device 1 according to an exemplary embodiment of the present disclosure. Figure 2 This is a plan view showing the folded state of the display device 1 according to an exemplary embodiment of the present disclosure. Figure 3 This is a plan view of a display panel 100 according to an exemplary embodiment of the present disclosure. Figure 4 This is a block diagram illustrating a display device 1 according to an exemplary embodiment of the present disclosure.

[0050] In this specification, the second direction DR2 can be a direction parallel to the short side of the display device 1 in a plan view, for example, the horizontal direction of the display device 1. The first direction DR1 can be a direction parallel to the long side of the display device 1 in a plan view, for example, the vertical direction of the display device 1. The third direction DR3 can be the thickness direction of the display panel 100 of the display device 1.

[0051] Reference Figures 1 to 4 Display device 1 is a device for displaying moving or still images. Display device 1 can be used as a display screen for various devices such as televisions, laptops / notebooks, computer monitors, digital billboards and / or Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablets, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-books, portable multimedia players (PMPs), navigation devices and / or ultra-mobile PCs (UMPCs).

[0052] Display device 1 may be a light-emitting display device, such as an organic light-emitting diode (OLED) display using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, and / or a micro light-emitting display using light-emitting diodes (LEDs). In the following description, it is assumed that display device 1 is an organic light-emitting diode display device, but this disclosure is not necessarily limited thereto.

[0053] The display device 1 includes a display panel 100, a display driving circuit D_IC, and a circuit board FPCB (e.g., a flexible printed circuit board).

[0054] The display panel 100 may have a rectangular shape in plan view, having a pair of short sides extending in a second direction DR2 and a pair of long sides extending in a first direction DR1 intersecting the second direction DR2. The corner where the short side in the second direction DR2 and the long side in the first direction DR1 meet may be rounded to have a predetermined curvature or may be a right angle. The planar shape of the display panel 100 is not necessarily limited to a rectangular shape, but may be formed into other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be flat, but is not necessarily limited to this. For example, the display panel 100 may include curved portions formed at the left and right ends and having a predetermined curvature or a varying curvature. Additionally, the display panel 100 may be flexible, allowing it to be twisted, bent, folded, or rolled without damage.

[0055] Display device 1 may include a display area DA and a non-display area NDA surrounding the display area DA. A plurality of subpixels SP may be arranged in the display area DA. Subpixels SP may not be arranged in the non-display area NDA. Subpixels SP may be provided in the display area DA to display an image, but the image may not be displayed in the non-display area NDA. In addition to the subpixels SP, scan lines SL, light emission lines EL, data lines DL, and a first driving voltage line VDDL connected to the subpixels SP may also be arranged in the display area DA.

[0056] Multiple scan lines SL and multiple light-emitting lines EL can extend parallel to each other in the second direction DR2. Multiple data lines DL can extend parallel to each other in the first direction DR1, which intersects with the second direction DR2.

[0057] The first driving voltage lines VDDL can be arranged parallel to each other in the first direction DR1 within the display area DA. Multiple first driving voltage lines VDDL formed parallel to each other in the first direction DR1 within the display area DA can be connected to each other in the non-display area NDA. Alternatively, the multiple first driving voltage lines VDDL can include multiple first sub-driving voltage lines formed parallel to each other in the first direction DR1 within the display area DA and multiple second sub-driving voltage lines formed parallel to each other in the second direction DR2.

[0058] Although shown is a plurality of sub-pixels SP each connected to two scan lines SL, one data line DL, one light emission line EL, and a first drive voltage line VDDL, this disclosure is not necessarily limited thereto. For example, each of the plurality of sub-pixels SP may be connected to three scan lines SL instead of two scan lines SL.

[0059] like Figure 6 As shown, each of the plurality of sub-pixels SP may include a driving transistor DT, at least one transistor ST (e.g., ST1-ST6), a light-emitting element LEL, and a capacitor (e.g., C1). When a scan signal is applied from the scan line SL, the transistor ST is turned on, and therefore, the data voltage of the data line DL is applied to the gate electrode of the driving transistor DT. The driving transistor DT emits light by providing a driving current to the light-emitting element LEL according to the data voltage applied to the gate electrode. The driving transistor DT and at least one transistor ST may be thin-film transistors. The light-emitting element LEL emits light according to the driving current of the driving transistor DT. The light-emitting element LEL may be an organic light-emitting diode (OLED) including a first electrode, an organic light-emitting layer, and a second electrode. The capacitor may be used to maintain the data voltage applied to the gate electrode of the driving transistor DT for a predetermined time.

[0060] Although it is possible for a non-display area to exist within the display area DA, the non-display area NDA can be defined as the region extending from the boundary of the display area DA to the edge of the display panel 100. Within the non-display area NDA, a scan driver (shown as a combination of elements 410 and 420) for applying scan signals to the scan line SL, a fan-out line between the data line DL and the display driver circuit D_IC, and a first pad connected to the display driver circuit D_IC can be arranged. The first pad can be disposed in the first pad area. Furthermore, a second pad connected to the circuit board FPCB can also be included. The second pad can be disposed in the second pad area.

[0061] The first and second pad areas can be arranged in the non-display area NDA.

[0062] The non-display area NDA may include a bent area BA. The bent area BA may extend along the second direction DR2. In a plan view, the bent area BA may be positioned closer to the display area DA than the display driver circuit D_IC.

[0063] The scan driver can be connected to the display driver circuit D_IC via multiple scan control lines. The scan driver can receive scan control signals SCS and transmit control signals ECS from the display driver circuit D_IC via multiple scan control lines.

[0064] like Figure 4 As shown, the scan driver may include a scan signal output unit 410 and a transmit signal output unit 420. The scan signal output unit 410 may generate a scan signal in response to a scan control signal SCS and sequentially output the scan signal to scan lines SL. The transmit signal output unit 420 may generate a transmit signal in response to a transmit control signal ECS and sequentially output the transmit signal to light-emitting lines EL.

[0065] The scan driver may include multiple thin-film transistors. The scan driver may be arranged on the same layer as the thin-film transistors of the sub-pixel SP. Alternatively, the scan driver may be arranged on a different layer than the thin-film transistors of the sub-pixel SP.

[0066] The scan driver may be formed in a non-display area NDA on one side (e.g., the left side) of the display area DA, but is not necessarily limited to this. For example, the scan driver may be formed in non-display areas NDA on both sides (e.g., the left and right sides) of the display area DA.

[0067] The display driver circuit D_IC can be formed as an integrated circuit (IC) and attached to the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method, but this disclosure is not necessarily limited to this. For example, the display driver circuit D_IC can be attached to the circuit board FPCB by a chip-on-film (COF) method. Figure 4 As shown, the display driver circuit D_IC may include a timing controller 210, a data driver (shown as being within the display driver circuit D_IC), and a power supply unit 230.

[0068] The timing controller 210 receives digital video data DATA and timing signals from the circuit board FPCB. In response to the timing signals, the timing controller 210 generates a scan control signal SCS for controlling the operating timing of the scan signal output unit 410, a transmit control signal ECS for controlling the operating timing of the transmit signal output unit 420, and a data control signal DCS for controlling the operating timing of the data driver. The timing controller 210 can output the scan control signal SCS to the scan signal output unit 410 via multiple scan control lines, and output the transmit control signal ECS to the transmit signal output unit 420. The timing controller 210 can also output the digital video data DATA and the data control signal DCS to the data driver.

[0069] The data driver converts digital video data (DATA) into positive / negative analog data voltages and outputs them to the data line (DL) via a fan-out line. The sub-pixel (SP) is selected using the scan signal of the scan driver, and the data voltage is supplied to the selected sub-pixel.

[0070] The power supply unit 230 can generate a first driving voltage and provide the first driving voltage to a first driving voltage line VDDL. Furthermore, the power supply unit 230 can generate a second driving voltage and provide the second driving voltage to the cathode of the organic light-emitting diode (OLED) of each of the plurality of sub-pixels SP. The first driving voltage can be a high potential voltage for driving the OLED, and the second driving voltage can be a low potential voltage for driving the OLED. For example, the first driving voltage can have a higher potential than the second driving voltage.

[0071] An anisotropic conductive film can be used to attach the circuit board (FPCB) to the second pad. Accordingly, the leads of the FPCB can be electrically connected to the second pad. The FPCB can be a flexible film, such as a flexible printed circuit board, a printed circuit board, or a flip-chip film.

[0072] like Figure 1 and Figure 2 As shown, the display device 1 can be divided into a first region A1 to a third region A3 based on the operating state. In a plan view, the first region A1 can be positioned at the upper side in a first direction DR1 of the display device 1, the second region A2 connected to the first region A1 can be positioned below the first region A1, and the third region A3 connected to the second region A2 can be positioned below the second region A2. The first region A1 to the third region A3 can be arranged sequentially. The second region A2 can be arranged between the first region A1 and the third region A3.

[0073] The first region A1 to the third region A3 can be distinguished by a first fold line FL1 and a second fold line FL2. For example, the first region A1 and the second region A2 can be distinguished by the first fold line FL1 extending along the second direction DR2, and the second region A2 and the third region A3 can be distinguished by the second fold line FL2 extending along the second direction DR2. The display device 1 can be folded twice, once relative to the first fold line FL1 and again relative to the second fold line FL2.

[0074] like Figure 2 As shown, the folding operation of the display device 1 can be performed based on the second region A2, for example, by folding the first region A1 downwards along the first fold line FL1 so that the first region A1 is folded behind the second region A2, and by folding the third region A3 upwards along the second fold line FL2 so that the third region A3 is folded in front of the second region A2. In this case, when viewed from above, the third region A3 of the display device 1 can be positioned at the top.

[0075] However, the folding operations shown above are not necessarily limited to these.

[0076] Figure 5 This is a plan view of a display panel 100 including a lower metal line BML according to an exemplary embodiment of the present disclosure.

[0077] Reference Figure 5 The display panel 100 according to an exemplary embodiment of this disclosure may further include a lower metal line BML. A plurality of lower metal lines BML may each surround at least a portion of the display area DA. Figure 5 For the sake of simplicity, only the first lower metal line BML1 and the second lower metal line BML2, which are located outside the display area DA (i.e., in the non-display area NDA), are shown.

[0078] The display area DA may have a rectangular shape in a plan view. For example, the display area DA may include a pair of long sides extending along a first direction DR1 and a pair of short sides extending along a second direction DR2.

[0079] Multiple lower metal lines BML may include a first lower metal line BML1 and a second lower metal line BML2.

[0080] In a plan view, the second lower metal line BML2 can be positioned between the display area DA and the first lower metal line BML1.

[0081] The lower metal line (BML) can be electrically connected to the circuit board (FPCB). Multiple lower metal lines (BML) can each be electrically connected to the circuit board (FPCB) via a second pad. A constant voltage can be applied to the lower metal lines (BML) via the second pad.

[0082] For example, a plurality of first lower metal lines BML1 may be arranged based on bisecting lines extending in a first direction DR1 in the display panel 100, and may be respectively connected to second pads arranged in the second pad area, and may have a laterally symmetrical shape.

[0083] Multiple first lower metal lines BML1, each connected to a second pad, extend upward in a first direction DR1, bend in a second direction DR2 (to cover a portion of the lower short side of the display area DA), and then extend again in the first direction DR1 (to cover the left and right long sides of the display area DA). Subsequently, the first lower metal lines BML1 may bend in the second direction DR2 (to cover the upper short side of the display area DA).

[0084] The second lower metal line BML2 can be arranged between the first lower metal line BML1 and the display area DA.

[0085] Multiple second lower metal lines BML2 can be arranged based on bisecting lines extending in the first direction DR1 of the display panel 100, can be respectively connected to second pads arranged in the second pad area, and can have a laterally symmetrical shape.

[0086] Multiple second lower metal lines BML2, each connected to a second pad, extend upward in the first direction DR1 and bend toward the second direction DR2 (to cover a portion of the lower short side of the display area DA), and then extend again in the first direction DR1 (to cover portions of the left and right long sides of the display area DA).

[0087] Figure 6 This is a circuit diagram specifically illustrating a sub-pixel SP according to an exemplary embodiment of the present disclosure.

[0088] Reference Figure 6 Sub-pixel SP can be connected to the (k-1)th scan line Sk-1 (where k is an integer of 2 or greater), the kth scan line Sk, and the jth data line Dj (j is a positive integer). Additionally, sub-pixel SP can be connected to the first drive voltage line VDDL, which provides a first drive voltage, the initialization voltage line VIL, which provides an initialization voltage, and the second drive voltage line VSSL, which provides a second drive voltage.

[0089] The sub-pixel SP includes a driving transistor DT, a light-emitting element LEL, a switching element, and a capacitor C1. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6.

[0090] The driving transistor DT may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls the drain-source current (Ids) (hereinafter referred to as the "driving current") flowing between the first and second electrodes based on the data voltage applied to the gate electrode. The driving current (Ids) flowing through the channel of the driving transistor DT is proportional to the square of the difference between the threshold voltage and the voltage (Vgs) between the gate and source electrodes of the driving transistor DT, as shown in Equation 1.

[0091] Ids = k′ × (Vgs - Vth) 2 Equation 1

[0092] In Equation 1, k′ is a scaling factor determined by the structure and physical characteristics of the driving transistor DT, Vgs is the gate-source voltage of the driving transistor DT, and Vth is the threshold voltage of the driving transistor DT.

[0093] A light-emitting element (LEL) emits light through a driving current (Ids). The amount of light emitted by an LEL is proportional to the driving current (Ids).

[0094] The light-emitting element (LEL) can be an organic light-emitting diode (OLED), comprising an anode, a cathode, and an organic light-emitting layer disposed between the anode and cathode. Alternatively, the LEL can be an inorganic light-emitting element, comprising an anode, a cathode, and an inorganic semiconductor disposed between the anode and cathode. Alternatively, the LEL can be a quantum dot light-emitting element, comprising an anode, a cathode, and a quantum dot light-emitting layer disposed between the anode and cathode. Alternatively, the LEL can be a micro-light-emitting diode.

[0095] The anode of the light-emitting element LEL can be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode of the light-emitting element LEL can be connected to the second driving voltage line VSSL. A parasitic capacitance Cel can be formed between the anode and cathode of the light-emitting element LEL.

[0096] The first transistor ST1 can be configured as a dual transistor comprising a first-1 transistor ST1-1 and a first-2 transistor ST1-2. The first-1 transistor ST1-1 and the first-2 transistor ST1-2 are turned on by a scan signal at the k-th scan line Sk, connecting the gate electrode and the second electrode of the driving transistor DT. For example, when the first-1 transistor ST1-1 and the first-2 transistor ST1-2 are turned on, the driving transistor DT functions as a diode because its gate electrode and the second electrode are connected. The gate electrode of the first-1 transistor ST1-1 can be connected to the k-th scan line Sk, its first electrode can be connected to the second electrode of the first-2 transistor ST1-2, and its second electrode can be connected to the gate electrode of the driving transistor DT. The gate electrode of the first-2 transistor ST1-2 can be connected to the k-th scan line Sk, its first electrode can be connected to the second electrode of the driving transistor DT, and its second electrode can be connected to the first electrode of the first-1 transistor ST1-1.

[0097] The second transistor ST2 can be turned on by the scan signal of the k-th scan line Sk, so as to connect the first electrode of the driving transistor DT to the j-th data line Dj. The gate electrode of the second transistor ST2 can be connected to the k-th scan line Sk, its first electrode can be connected to the first electrode of the driving transistor DT, and its second electrode can be connected to the j-th data line Dj.

[0098] The third transistor ST3 can be configured as a dual transistor comprising transistors ST3-1 (3-1) and ST3-2 (3-2). Both transistors ST3-1 and ST3-2 are turned on by a scan signal at scan line Sk-1 (k-1), connecting the gate electrode of the driving transistor DT to the initialization voltage line VIL. The gate electrode of the driving transistor DT can be discharged to the initialization voltage of the initialization voltage line VIL. The gate electrode of transistor ST3-1 (3-1) can be connected to scan line Sk-1 (k-1), its first electrode can be connected to the gate electrode of the driving transistor DT, and its second electrode can be connected to the first electrode of transistor ST3-2 (3-2). The gate electrode of transistor ST3-2 (3-2) can be connected to scan line Sk-1 (k-1), its first electrode can be connected to the second electrode of transistor ST3-1 (3-1), and its second electrode can be connected to the initialization voltage line VIL.

[0099] The fourth transistor ST4 is turned on by the scan signal of the (k-1)th scan line Sk-1 to connect the anode of the light-emitting element LEL to the initialization voltage line VIL. The anode of the light-emitting element LEL can be discharged to the initialization voltage. The gate electrode of the fourth transistor ST4 is connected to the (k-1)th scan line Sk-1, its first electrode is connected to the anode of the light-emitting element LEL, and its second electrode is connected to the initialization voltage line VIL.

[0100] The fifth transistor ST5 is turned on by the emission control signal of the k-th light-emitting line Ek, so as to connect the first electrode of the driving transistor DT to the first driving voltage line VDDL. The gate electrode of the fifth transistor ST5 is connected to the k-th light-emitting line Ek, its first electrode is connected to the first driving voltage line VDDL, and its second electrode is connected to the first electrode of the driving transistor DT.

[0101] The sixth transistor ST6 is connected between the second electrode of the driving transistor DT and the anode of the light-emitting element LEL. The sixth transistor ST6 is turned on by the emission control signal of the k-th emission line Ek, connecting the second electrode of the driving transistor DT to the anode of the light-emitting element LEL. The gate electrode of the sixth transistor ST6 is connected to the k-th emission line Ek, its first electrode is connected to the second electrode of the driving transistor DT, and its second electrode is connected to the anode of the light-emitting element LEL. When both the fifth transistor ST5 and the sixth transistor ST6 are turned on, a drive current (Ids) can be supplied to the light-emitting element LEL.

[0102] A capacitor C1 is formed between the gate electrode of the driving transistor DT and the first driving voltage line VDDL. One electrode of the capacitor C1 can be connected to the gate electrode of the driving transistor DT, and the other electrode can be connected to the first driving voltage line VDDL.

[0103] When the first electrode of the driving transistor DT and each of the first transistors ST1 to ST6 is a source electrode, its second electrode can be a drain electrode. Alternatively, when the first electrode of the driving transistor DT and each of the first transistors ST1 to ST6 is a drain electrode, its second electrode can be a source electrode.

[0104] The active layer of each of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 may include polysilicon, amorphous silicon, and / or oxide semiconductor. When the semiconductor layer of each of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 is formed of polysilicon, the process used to form the semiconductor layer may be a low-temperature polysilicon (LTPS) process.

[0105] In addition, it has been described that the driving transistor DT and the first transistor ST1 to the sixth transistor ST6 are formed by p-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but they are not limited thereto and can be formed by n-type MOSFETs.

[0106] The characteristics of the driving transistor DT and the light-emitting element LEL can be taken into account to set the first driving voltage of the first driving voltage line VDDL, the second driving voltage of the second driving voltage line VSSL, and the initialization voltage of the initialization voltage line VIL. For example, the voltage difference between the initialization voltage and the data voltage supplied to the source electrode of the driving transistor DT can be set to be less than the threshold voltage of the driving transistor DT.

[0107] Lower metal wire T-BML (and) Figure 5 The lower metal line T-BML (which is the same as the BML) can overlap with the driving transistor DT. The lower metal line T-BML can overlap with the channel (or active layer) of the driving transistor DT, and can be spaced apart from the respective channels (or active layers) of the first transistor ST1 to the sixth transistor ST6 without overlapping them.

[0108] Figure 7 This is a plan view specifically illustrating a sub-pixel SP according to an exemplary embodiment of the present disclosure.

[0109] Reference Figure 7 The sub-pixel SP may include a driving transistor DT, a first transistor ST1 to a sixth transistor ST6, a capacitor C1, a first connection electrode and a second connection electrode VIE, and a data connection electrode.

[0110] Sub-pixel SP can overlap with the (k-1)th scan line Sk-1, the kth scan line Sk, the kth emission line Ek, the jth data line Dj, the first driving voltage line VDDL1, and the initialization voltage line VIL on the third direction DR3. Sub-pixel SP can be connected to the (k-1)th scan line Sk-1, the kth scan line Sk, the jth data line Dj, and the first driving voltage line VDDL1 via the first transistor ST1 to the sixth transistor ST6. The (k-1)th scan line Sk-1, the kth scan line Sk, the kth emission line Ek, and the initialization voltage line VIL can extend on the second direction DR2. The jth data line Dj can extend on the first direction DR1.

[0111] The first driving voltage line VDDL1 may include a first sub-driving voltage line SVDDL1 and a second sub-driving voltage line SVDDL2. The first sub-driving voltage line SVDDL1 extends in a first direction DR1, and the second sub-driving voltage line SVDDL2 extends in a second direction DR2. The first sub-driving voltage line SVDDL1 is disposed in the second direction DR2 between the j-th data line Dj and the first connection electrode. The second sub-driving voltage line SVDDL2 is disposed in the first direction DR1 between the k-th scan line Sk and the k-th emission line Ek. The first sub-driving voltage line SVDDL1 can be connected to the second sub-driving voltage line SVDDL2 through an eighth contact hole CNT8.

[0112] The driving transistor DT may include an active layer DT-ACT, a gate electrode DT-G, a first electrode, and a second electrode DT-D. The active layer DT-ACT of the driving transistor DT may overlap with the gate electrode DT-G of the driving transistor DT on a third-direction DR3. The gate electrode DT-G may be disposed on the active layer DT-ACT of the driving transistor DT.

[0113] The gate electrode DT-G can be connected to the first connection electrode through the first connection contact hole BCNT1. The first connection electrode can be connected to the second electrode D1-1 of the first-1 transistor ST1-1 through the second connection contact hole BCNT2. Since the first connection electrode extends in the first direction DR1, it can intersect with the k-th scan line Sk.

[0114] The first electrode of the driving transistor DT can be connected to the first electrode S2 of the second transistor ST2. The second electrode DT-D of the driving transistor DT can be connected to the first electrode S1-2 of the first-second transistor ST1-2 and the first electrode S6 of the sixth transistor ST6.

[0115] The first transistor ST1 can be configured as a dual transistor. The first transistor ST1 may include a first transistor ST1-1 and a first transistor ST1-2.

[0116] Transistor ST1-1 (first-1) may include an active layer ACT1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. The gate electrode G1-1 of transistor ST1-1 is part of the k-th scan line Sk and may be the region where the active layer ACT1-1 of transistor ST1-1 overlaps with the k-th scan line Sk on the third direction DR3. The first electrode S1-1 of transistor ST1-1 may be connected to the second electrode D1-2 of transistor ST1-2 (first-2). The second electrode D1-1 of transistor ST1-1 may be connected to the first connection electrode through the second connection contact hole BCNT2.

[0117] Transistor ST1-2 (first-second transistor) may include an active layer ACT1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. The gate electrode G1-2 of transistor ST1-2 is part of the k-th scan line Sk and may be the region where the active layer ACT1-2 of transistor ST1-2 overlaps with the k-th scan line Sk on the third direction DR3. The first electrode S1-2 of transistor ST1-2 may be connected to the second electrode DT-D of the driving transistor DT. The second electrode D1-2 of transistor ST1-2 may be connected to the first electrode S1-1 of transistor ST1-1 (first-second transistor).

[0118] The second transistor ST2 may include an active layer ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 is part of the k-th scan line Sk and may be the region on the third direction DR3 where the active layer ACT2 of the second transistor ST2 overlaps with the k-th scan line Sk. The first electrode S2 of the second transistor ST2 may be connected to the first electrode of the driving transistor DT. The second electrode D2 of the second transistor ST2 may be connected to a data connection electrode via a third contact hole. The data connection electrode may be connected to the j-th data line Dj (hereinafter referred to as "data line Dj") via a data contact hole.

[0119] The third transistor ST3 can be configured as a dual transistor. The third transistor ST3 may include the third-first transistor ST3-1 and the third-second transistor ST3-2.

[0120] Transistor ST3-1 (3-1) may include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of transistor ST3-1 is part of the (k-1)th scan line Sk-1 and may be the region where the active layer ACT3-1 of transistor ST3-1 overlaps with the (k-1)th scan line Sk-1. The first electrode S3-1 of transistor ST3-1 may be connected to a first connection electrode via a second connection contact hole BCNT2. The second electrode D3-1 of transistor ST3-1 may be connected to the first electrode S3-2 of transistor ST3-2 (3-2).

[0121] Transistor ST3-2 (3-2) may include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of transistor ST3-2 is part of the (k-1)th scan line Sk-1 and may be the region where the active layer ACT3-2 of transistor ST3-2 overlaps with the (k-1)th scan line Sk-1. The first electrode S3-2 of transistor ST3-2 may be connected to the second electrode D3-1 of transistor ST3-1 (3-1). The second electrode D3-2 of transistor ST3-2 (3-2) may be connected to the second connection electrode VIE through a fourth contact hole CNT4.

[0122] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 is part of the k-th scan line Sk and may be the region where the active layer ACT4 of the fourth transistor ST4 overlaps with the k-th scan line Sk. The first electrode S4 of the fourth transistor ST4 can be connected to the first anode connection electrode ANDE1 through the sixth contact hole CNT6. The anode of the light-emitting element LEL can be connected to the first anode connection electrode ANDE1 through the second anode connection electrode. The second electrode D4 of the fourth transistor ST4 can be connected to the second connection electrode VIE through the fourth contact hole CNT4. The initialization voltage line VIL can be connected to the second connection electrode VIE through the fifth contact hole, and the second connection electrode VIE can be connected to the second electrode D3-2 of the third-second transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 through the fourth contact hole CNT4. The second connection electrode VIE extends in the first direction DR1 and may intersect with the (k-1)-th scan line Sk-1.

[0123] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 is part of the k-th light-emitting line Ek and may be the region where the active layer ACT5 of the fifth transistor ST5 overlaps with the k-th light-emitting line Ek. The first electrode S5 of the fifth transistor ST5 can be connected to the first sub-driving voltage line SVDDL1 through the seventh contact hole CNT7. The second electrode D5 of the fifth transistor ST5 can be connected to the first electrode of the driving transistor DT.

[0124] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6 is part of the k-th light-emitting line Ek and may be the region where the active layer ACT6 of the sixth transistor ST6 overlaps with the k-th light-emitting line Ek. The first electrode S6 of the sixth transistor ST6 may be connected to the second electrode DT-D of the driving transistor DT. The second electrode D6 of the sixth transistor ST6 may be connected to the anode of the light-emitting element LEL through the sixth contact hole CNT6.

[0125] The first electrode of capacitor C1 is part of the second electrode DT-D of driving transistor DT, and the second electrode of capacitor C1 may be the second sub-driving voltage line SVDDL2 that overlaps with the second electrode DT-D of driving transistor DT.

[0126] The lower metal line T-BML may overlap with the driving transistor DT. The lower metal line T-BML may overlap with the channel of the driving transistor DT, and may be spaced apart from the channels of the first transistor ST1 to the sixth transistor ST6 without overlapping with them.

[0127] Figure 8 This is a plan view showing a sub-pixel SP with a lower metal line BML arranged according to an exemplary embodiment of the present disclosure.

[0128] Reference Figure 8 The lower metal line BML may overlap with the channel of the driving transistor DT in the thickness direction, but may not overlap with the channels of the first transistor ST1 to the sixth transistor ST6.

[0129] For example, the lower metal line BML may overlap with the gate electrode DT-G of the driving transistor DT in the thickness direction. The lower metal line BML may be larger than the gate electrode DT-G in a plan view. The lower metal line BML may completely cover the gate electrode DT-G. The lower metal line BML may extend further upwards and may intersect with the k-th scan line Sk, the (k-1)-th scan line Sk-1, and the initialization voltage line VIL. The lower metal line BML may extend further downwards and may intersect with the k-th emission line Ek.

[0130] Figure 9 yes Figure 8 An enlarged view of region E1. This figure is provided to more clearly illustrate the exemplary structure of the second transistor ST2, which includes the active layer ACT2 and the gate electrode G2, and its structural relationship with the lower metal line BML and the k-th scan line Sk.

[0131] First, we will refer to Figures 13 to 15 Describe the stacked structure of the display panel 100.

[0132] The thin-film transistor layer, the light-emitting element layer, and the encapsulation layer can be sequentially arranged on the substrate SUB.

[0133] The thin-film transistor layer includes a lower metal line BML, a buffer film BF, an active layer, a first gate layer, a second gate layer, a first data metal layer, a second data metal layer, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a protective film, a first organic film 160, and a second organic film.

[0134] The lower metal line (BML) can be disposed on one surface of the substrate SUB. The lower metal line (BML) can overlap with the active layer DT-ACT of the driving transistor DT on the third direction DR3 to block light incident on the active layer DT-ACT of the driving transistor DT. The third direction DR3 can be the thickness direction of the substrate SUB. The lower metal line (BML) can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) or alloys thereof.

[0135] A buffer film (BF) can be disposed on the lower metal line (BML). Alternatively, the buffer film (BF) can be disposed on the substrate (SUB) to protect the organic light-emitting layer of the thin-film transistor and light-emitting element layer from moisture that permeates through the substrate (SUB), which is susceptible to moisture penetration. The buffer film (BF) can be formed from multiple inorganic layers stacked alternately. For example, the buffer film (BF) can be formed from multiple layers of one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The buffer film (BF) can be omitted.

[0136] The active layer can be disposed on the substrate SUB or the buffer film BF. The active layer may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor. When the active layer is made of polycrystalline silicon or oxide semiconductor, the active layer doped with ions may be conductive. Accordingly, the active layer may include not only the respective active layers DT-ACT, ACT1-1, ACT1-2, ACT2, ACT3-1, ACT3-2, ACT4 to ACT6 of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6, but also the respective source electrodes S1-1, S1-2, S2, S3-1, S3-2, S4, S5 and S6 of the driving transistor DT and the first transistor ST1 to the sixth transistor ST6, and their respective drain electrodes DT-D, D1-1, D1-2, D2, D3-1, D3-2, D4, D5 and D6.

[0137] The gate insulating film 130 may be disposed on the active layer. The gate insulating film 130 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0138] The first gate layer may be disposed on the gate insulating film 130. The first gate layer may include not only the gate electrode DT-G of the driving transistor DT and the gate electrodes G1-1, G1-2, G2, G3-1, G3-2, G4 to G6 of the first transistor ST1 to the sixth transistor ST6, but also the (K-1)th scan line Sk-1 and the Kth scan line Sk and the Kth light-emitting line Ek. The first gate layer may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) or alloys thereof.

[0139] The first interlayer insulating film 141 may be disposed on the first gate layer. The first interlayer insulating film 141 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include multiple inorganic layers.

[0140] The second gate layer may be disposed on the first interlayer insulating film 141. The second gate layer may include an initialization voltage line VIL, a second sub-drive voltage line SVDDL2, and a shielding electrode. The second gate layer may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) or alloys thereof.

[0141] The second interlayer insulating film 142 may be disposed on the second gate layer. The second interlayer insulating film 142 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include multiple inorganic layers.

[0142] A first data metal layer may be disposed on a second interlayer insulating film 142. The first data metal layer may include a first sub-drive voltage line SVDDL1, a first connection electrode, a second connection electrode VIE, and a first anode connection electrode ANDE1. The first data metal layer may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) or alloys thereof.

[0143] A first organic film 160 for planarizing the stepped portions formed by the active layer, the first gate layer, the second gate layer, and the first data metal layer may be disposed on the first data metal layer. The first organic film 160 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0144] A protective film may be additionally formed between the first data metal layer and the first organic film 160. The protective film may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0145] A second data metal layer may be disposed on the first organic film 160. The second data metal layer may include a second anode connection electrode. The second data metal layer may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and / or copper (Cu) or alloys thereof.

[0146] A second organic film for planarizing the stepped portion can be disposed on the second data metal layer. The second organic film can be formed from an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0147] The first connection contact hole BCNT1 can penetrate the first interlayer insulating film 141 and the second interlayer insulating film 142 to expose the gate electrode DT-G of the driving transistor DT. The first connection electrode can be connected to the gate electrode DT-G of the driving transistor DT through the first connection contact hole BCNT1.

[0148] The second connection contact hole BCNT2 can penetrate the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D1-1 of the first-1 transistor ST1-1. The first connection electrode can be connected to the second electrode D1-1 of the first-1 transistor ST1-1 through the second connection contact hole BCNT2.

[0149] A data contact hole can penetrate the first organic membrane 160 to expose the data connection electrode. Each of the multiple data lines Dj and Dj+1 can be connected to the data connection electrode through the data contact hole.

[0150] The first contact hole CNT1 can penetrate the second interlayer insulating film 142 to expose the shielding electrode. The first sub-drive voltage line SVDDL1 can be connected to the shielding electrode through the first contact hole CNT1.

[0151] The third contact hole can penetrate the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the first electrode S2 of the second transistor ST2. The data connection electrode can be connected to the first electrode S2 of the second transistor ST2 through the third contact hole.

[0152] The fourth contact hole CNT4 can penetrate the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D3-2 of the third-second transistor ST3-2 and the second electrode D4 of the fourth transistor ST4. The second connection electrode VIE can be connected to the second electrode D3-2 of the third-second transistor ST3-2 and the second electrode D4 of the fourth transistor ST4 through the fourth contact hole CNT4.

[0153] The fifth contact hole can penetrate the second interlayer insulating film 142 to expose the initialization voltage line VIL. The second connection electrode VIE can be connected to the initialization voltage line VIL through the fifth contact hole.

[0154] The sixth contact hole CNT6 can penetrate the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the second electrode D6 of the sixth transistor ST6. The first anode connection electrode ANDE1 can be connected to the second electrode D6 of the sixth transistor ST6 through the sixth contact hole CNT6.

[0155] The seventh contact hole CNT7 can penetrate the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142 to expose the first electrode S5 of the fifth transistor ST5. The first sub-drive voltage line SVDDL1 can be connected to the first electrode S5 of the fifth transistor ST5 through the seventh contact hole CNT7.

[0156] The eighth contact hole CNT8 can penetrate the second interlayer insulating film 142 to expose the second sub-drive voltage line SVDDL2. The first sub-drive voltage line SVDDL1 can be connected to the second sub-drive voltage line SVDDL2 through the eighth contact hole CNT8.

[0157] The first anode contact hole can penetrate the protective film and the first organic film 160 to expose the first anode connection electrode ANDE1. The second anode connection electrode can be connected to the first anode connection electrode ANDE1 through the first anode contact hole.

[0158] The second anode contact hole can penetrate the second organic membrane to expose the second anode connection electrode.

[0159] The light-emitting element layer is disposed on the thin-film transistor layer. The light-emitting element layer includes light-emitting elements (LELs) and a pixel defining layer.

[0160] The light-emitting element (LEL) and the pixel defining layer are disposed on the first organic film 160. Each of the plurality of light-emitting elements (LELs) may include a first electrode, an organic light-emitting layer, and a second electrode.

[0161] The first electrode can be disposed on the first organic membrane 160. The first electrode can be connected to the second anode connection electrode through the second anode contact hole.

[0162] In a top-emitting structure that emits light toward the second electrode when viewed relative to the organic light-emitting layer, the first electrode can be formed of a metallic material with high reflectivity, having a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0163] A pixel defining layer can separate the first electrode on the planarization film to define the emission region of each of a plurality of sub-pixels SP. The pixel defining layer can cover the edge of the first electrode. The pixel defining layer can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0164] In the emission region of each of the multiple sub-pixels SP, a first electrode, an organic light-emitting layer, and a second electrode are stacked sequentially, and holes from the first electrode and electrons from the second electrode combine with each other in the organic light-emitting layer to emit light.

[0165] An organic light-emitting layer is disposed on the first electrode and the pixel defining layer. The organic light-emitting layer may include organic materials to emit light of a predetermined color. For example, the organic light-emitting layer may include a hole transport layer, an organic material layer, and an electron transport layer. Among a plurality of sub-pixels SP, the organic light-emitting layer of the first sub-pixel emits light of a first color, the organic light-emitting layer of the second sub-pixel emits light of a second color, and the organic light-emitting layer of the third sub-pixel emits light of a third color. Alternatively, the organic light-emitting layer of the sub-pixel SP may emit white light. In this case, the first sub-pixel may overlap with a color filter layer of the first color, the second sub-pixel may overlap with a color filter layer of the second color, and the third sub-pixel may overlap with a color filter layer of the third color. For example, the first color may be red, the second color may be green, and the third color may be blue, but they are not necessarily limited to these.

[0166] The second electrode is disposed on the organic light-emitting layer. The second electrode may cover the organic light-emitting layer. The second electrode may be a common layer disposed on multiple sub-pixels SP. A cover layer may be disposed on the second electrode.

[0167] In the top-emitting structure, the second electrode can be formed of a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transparent conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode is formed of a semi-transparent conductive material, the light emission efficiency can be improved due to the microcavity effect.

[0168] An encapsulation layer may be disposed on the light-emitting element layer. The encapsulation layer may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer. In addition, the encapsulation layer may include at least one organic layer to protect the light-emitting element layer from foreign matter such as dust.

[0169] Alternatively, a substrate can be disposed on the light-emitting element layer instead of an encapsulation layer, and the space between the light-emitting element layer and the substrate can be empty under vacuum conditions, or a filling film can be disposed in that space. The filling film can be an epoxy filling film or a silicon filling film.

[0170] Refer again Figure 8 The lower metal line BML may have a width d3 and a width d4. Each of the widths d3 and d4 of the lower metal line BML may be, for example, about 2.4 μm or greater.

[0171] The lower metal line BML may overlap with the initialization voltage line VIL. According to an exemplary embodiment of this disclosure, each of the widths d3 and d4 of the lower metal line BML may be the same width as the overlap between the lower metal line BML and the initialization voltage line VIL.

[0172] Since each of the widths d3 and d4 of the lower metal line BML has the same width as the overlap between the lower metal line BML and the initialization voltage line VIL, the area of ​​the overlap between the lower metal line BML and the initialization voltage line VIL can be minimized.

[0173] Additionally, the lower metal line BML can overlap with the data line Dj. The width of the overlap between the lower metal line BML and the data line Dj can be 10% or less of the width of the data line Dj. Because the width of the overlap between the lower metal line BML and the data line Dj is 10% or less of the width of the data line Dj, the area of ​​the overlap between the lower metal line BML and the data line Dj can be minimized.

[0174] Figure 10 yes Figure 8 A magnified view of region E2.

[0175] Reference Figure 8 and Figure 10 The active layer ACT5 and the lower metal line BML of the fifth transistor ST5 can be separate (e.g., spaced apart from each other). For example, the spacing width d1 between the active layer ACT5 and the lower metal line BML of the fifth transistor ST5 can be 50% or greater than the width d3 (or d4) of the lower metal line BML.

[0176] For example, the spacing d1 between the active layer ACT5 and the lower metal line BML of the fifth transistor ST5 can be about 1.9 μm or greater.

[0177] Figure 11 It shows the arrangement of Figure 8 A diagram of the gate electrode DT-G region of the driving transistor DT.

[0178] Reference Figure 8 and Figure 11 In the plan view, the lower metal line BML can extend outward relative to the gate electrode DT-G of the driving transistor DT. Furthermore, the extension width d2 of the lower metal line BML relative to the gate electrode DT-G of the driving transistor DT can be smaller than the previously mentioned... Figure 10 The spacing d1 between the active layer ACT5 and the lower metal line BML of the fifth transistor ST5 is described, and may be greater than 50% of the width d3 (or d4) of the lower metal line BML. For example, the extension width d2 of the lower metal line BML relative to the gate electrode DT-G of the driving transistor DT may be about 1.75 μm, but is not necessarily limited to this.

[0179] Figure 12 yes Figure 5An enlarged view of area A. Figure 13 It is along Figure 12 The cross-sectional view taken by line I-I'. Figure 14 It is along Figure 12 The cross-sectional view taken from line II-II'. Figure 15 It is along Figure 12 The cross-sectional view taken from line III-III'.

[0180] and Figure 5 Refer to together Figures 12 to 15 In the accompanying drawings, each of the first lower metal line BML1 and the second lower metal line BML2 can extend upwards, bend to extend to the left, and then extend upwards again. While extending upwards again, the second lower metal line BML2 can branch to extend to the right. The rightward branch of the second lower metal line BML2 can be electrically connected to the sub-pixel SP.

[0181] The initialization bus VBL may include a first initialization bus VBL1 and a second initialization bus VBL2.

[0182] The first initialization bus VBL1 may extend to the right and then bend upwards. The second initialization bus VBL2 may branch off from the middle of the upwardly extending first initialization bus VBL1 and may extend to the right. The second initialization bus VBL2 may be connected to the initialization voltage line VIL. The initialization bus VBL may be arranged on the first data metal layer. In some exemplary embodiments of this disclosure, the initialization bus VBL may be arranged on the second data metal layer.

[0183] The second initialization bus VBL2 may intersect with the first lower metal line BML1 and the second lower metal line BML2. The second initialization bus VBL2 may overlap with the first lower metal line BML1 and the second lower metal line BML2.

[0184] According to an exemplary embodiment of this disclosure, although the second initialization bus VBL2 overlaps with the first lower metal line BML1 and the second lower metal line BML2, the initialization bus VBL is arranged on the first data metal layer, thereby increasing the spacing distance between it and the first lower metal line BML1 and the second lower metal line BML2 in the thickness direction.

[0185] Multiple scan connection lines SCk-1 and SCk can electrically connect the scan signal output unit 410 to the sub-pixel SP. The scan connection line SCk-1 (or SCk) may include a first scan connection line SCk-1a (or SCka) connected to the scan signal output unit 410, a second scan connection line SCk-1c (or SCkc) connected to the scan line Sk-1 (or Sk) of the sub-pixel SP, and a third scan connection line SCk-1b (or SCkb) connecting the first scan connection line SCk-1a (or SCka) and the second scan connection line SCk-1c (or SCkc).

[0186] Multiple first scan connection lines SCk-1a and SCka, and multiple second scan connection lines SCk-1c and SCkc, may be arranged on the second gate layer. Multiple third scan connection lines SCk-1b and SCkb may be arranged on the first data metal layer. The multiple third scan connection lines SCk-1b and SCkb may intersect with the first lower metal line BML1 and the second lower metal line BML2 and overlap with them in the thickness direction.

[0187] According to an exemplary embodiment of this disclosure, a plurality of third scan connection lines SCk-1b and SCkb intersect with the first lower metal line BML1 and the second lower metal line BML2 and overlap with them in the thickness direction, and are arranged on the first data metal layer, thereby increasing the thickness direction spacing between the first lower metal line BML1 and the second lower metal line BML2 and the plurality of third scan connection lines SCk-1b and SCkb intersecting with the first lower metal line BML1 and the second lower metal line BML2 and overlapping them in the thickness direction.

[0188] In some exemplary embodiments of this disclosure, a plurality of first scan connection lines SCk-1a and SCka and a plurality of second scan connection lines SCk-1c and SCkc may be arranged on the first gate layer.

[0189] In some exemplary embodiments of this disclosure, a plurality of first scan connection lines SCk-1a and SCka may be arranged on a first gate layer, and a plurality of second scan connection lines SCk-1c and SCkc may be arranged on a second gate layer, and vice versa.

[0190] In some exemplary embodiments of this disclosure, a plurality of third scan connection lines SCk-1b and SCkb may be arranged on the second data metal layer.

[0191] According to an exemplary embodiment of this disclosure, data line Dj and first driving voltage line VDDL may be disposed on a first data metal layer. Data line Dj and first driving voltage line VDDL may overlap with second lower metal line BML2 in the thickness direction. However, as described above, data line Dj and first driving voltage line VDDL are disposed on the first data metal layer such that the thickness-direction spacing between the second lower metal line BML2 and each of the data line Dj and first driving voltage line VDDL that overlap with the second lower metal line BML2 in the thickness direction can be increased.

[0192] In some exemplary embodiments of this disclosure, such as Figure 15 As shown, the first driving voltage line VDDL may include a first driving voltage line portion VDDLa disposed on the first data metal layer and a second driving voltage line portion VDDLb disposed on the second data metal layer and connected to the first driving voltage line portion VDDLa.

[0193] Figure 16 yes Figure 5 A magnified view of area B. Figure 17 It is along Figure 16 A cross-sectional view taken from line IV-IV'.

[0194] Reference Figure 16 and Figure 17 The scan control line PSGL is connected to the scan driver (see...). Figure 4 (410), to send the scan control signal (see 410) Figure 4 The scan control line (PSGL) is provided to the scan signal output unit 410. The scan control line PSGL may be disposed on the first gate layer. In some exemplary embodiments of this disclosure, the scan control line PSGL may be disposed on the second gate layer.

[0195] Furthermore, the fan-out line FOL outputs the data voltage to the data line Dj. In a plan view, between the bend region BA and the display region DA, the first lower metal line BML1 and the second lower metal line BML2 can be arranged between the scan control line PSGL and the fan-out line FOL. For example, in a plan view, between the bend region BA and the display region DA, the first lower metal line BML1 and the second lower metal line BML2 are arranged between the scan control line PSGL and the fan-out line FOL, thereby minimizing crosstalk in the first lower metal line BML1 and the second lower metal line BML2 caused by the scan control line PSGL and the fan-out line FOL.

[0196] Furthermore, the lower metal wire BML1 (or BML2) may include a first lower metal wire portion BML1a (or BML2a) and a second lower metal wire portion BML1b (or BML2b) connected to the first lower metal wire portion BML1a (or BML2a). Multiple second lower metal wire portions BML1b and BML2b may extend upwards, and multiple first lower metal wire portions BML1a and BML2a may extend to the left.

[0197] Multiple second lower metal wire portions BML1b and BML2b may pass through the bending area BA. Multiple second lower metal wire portions BML1b and BML2b may overlap with the bending area BA.

[0198] Multiple first lower metal line portions BML1a and BML2a may be arranged between the buffer film BF and the substrate SUB, and multiple second lower metal line portions BML1b and BML2b may be arranged on multiple data metal layers (first data metal layer and second data metal layer).

[0199] According to an exemplary embodiment of this disclosure, a plurality of second lower metal wire portions BML1b and BML2b are arranged on a plurality of data metal layers (a first data metal layer and a second data metal layer), thereby preventing the plurality of second lower metal wire portions BML1b and BML2b from breaking in the bending region BA.

[0200] Reference Figure 17 The second lower metal line portion BML1b may include a second-first lower metal line portion BML1b-1 disposed on the first data metal layer and a second-second lower metal line portion BML1b-2 disposed on the second data metal layer. The second-first lower metal line portion BML1b-1 and the second-second lower metal line portion BML1b-2 may be electrically connected to each other and may overlap each other in the thickness direction.

[0201] According to an exemplary embodiment of this disclosure, the second-1 lower metal wire portion BML1b-1 and the second-2 lower metal wire portion BML1b-2 are electrically connected to each other and overlap each other in thickness, thereby preventing the second lower metal wire portion BML1b from breaking in the bending region BA.

[0202] Figure 18 This is a plan view showing the lower side of the bent region BA of a display panel 100 according to an exemplary embodiment of the present disclosure.

[0203] Reference Figure 18 and Figure 5Multiple second lower metal line portions BML1b and BML2b can each form a lower metal pad BMLp in the second pad region. The multiple second lower metal line portions BML1b and BML2b can be configured to receive a constant voltage from the lower metal pad BMLp located in the pad region.

[0204] As described above, multiple second lower metal line portions BML1b and BML2b may be arranged on the first data metal layer or the second data metal layer. The lower metal pad BMLp may be arranged on the same layer as the multiple second lower metal line portions BML1b and BML2b, but is not necessarily limited to this.

[0205] Multiple second lower metal line portions BML1b and BML2b may extend in a stepped manner along the upper left direction, but are not necessarily limited to this. In a plan view, the multiple second lower metal line portions BML1b and BML2b may intersect with the scan control line PSGL. The multiple second lower metal line portions BML1b and BML2b may overlap with the scan control line PSGL in the thickness direction.

[0206] According to an exemplary embodiment of this disclosure, a plurality of second lower metal line portions BML1b and BML2b are arranged on a first data metal layer or a second data metal layer, and are arranged on a different layer from the scan control line PSGL and as far away from the scan control line PSGL as possible in the thickness direction, thereby minimizing crosstalk caused by the scan control line PSGL.

[0207] Figure 19 This is a plan view showing the area between the display area DA and the bending area BA of a display panel 100 according to an exemplary embodiment of the present disclosure.

[0208] Reference Figure 19 and Figure 5 The second drive voltage line VSSL can cover the scan control line PSGL.

[0209] For example, the second drive voltage line VSSL can extend to the left and then bend to extend upward.

[0210] According to an exemplary embodiment of this disclosure, the second drive voltage line VSSL covers the scan control line PSGL, thereby enhancing the power of the second drive voltage.

[0211] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described. In the following embodiments, components identical to those in the above embodiments are indicated by the same reference numerals, and their descriptions will be omitted or simplified. Accordingly, to the extent that the descriptions of various elements have been omitted or simplified, it may be assumed that the descriptions are at least similar to the descriptions of corresponding elements provided elsewhere in this disclosure.

[0212] Figure 20 This is a circuit diagram specifically illustrating a sub-pixel SP_1 according to an exemplary embodiment of the present disclosure. Figure 21 This is a plan view specifically illustrating a sub-pixel SP_1 according to an exemplary embodiment of the present disclosure. Figure 22 yes Figure 21 A magnified view of region E3. Figure 23 yes Figure 21 A magnified view of region E4. Figure 24 yes Figure 21 A magnified view of area E5.

[0213] Reference Figures 20 to 24 The lower metal line T-BML-1 of sub-pixel SP_1 may overlap with the sixth transistor ST6. The lower metal line T-BML-1 may overlap with the channel (or active layer) of the sixth transistor ST6, and may be spaced apart from the respective channels (or active layers) of the first transistor ST1 to the fifth transistor ST5 and the driving transistor DT without overlapping with them.

[0214] Reference Figure 21 and Figure 22 The width d9 of the lower metal wire BML can be compared with the above reference. Figure 8 The widths d3 and d4 described are the same for each of them.

[0215] The lower metal line BML can be spaced apart from the active layer ACT3-1 of transistor ST3-1 by a fifth width d5.

[0216] The fifth width d5 ​​can be -10% to 10% of the width d9 of the lower metal line BML. For example, the fifth width d5 ​​can be about 1.2 μm, but is not necessarily limited to this.

[0217] According to an exemplary embodiment of this disclosure, the lower metal line BML is spaced apart from the active layer ACT3-1 of the 3-1st transistor ST3-1 by a fifth width d5, thereby minimizing crosstalk in the lower metal line BML caused by the 3-1st transistor ST3-1.

[0218] Furthermore, such as Figure 21 and Figure 23 As shown, the lower metal line BML may be larger than the sixth transistor ST6 in a plan view. Compared to the sixth transistor ST6, the lower metal line BML may extend further upward, downward, leftward, and rightward. The extension width d6 of the lower metal line BML extending from the sixth transistor ST6 may be approximately 1.75 μm, but is not necessarily limited to this.

[0219] In addition, such as Figure 21 and Figure 24As shown, in the plan view, the lower metal line BML may be spaced apart from the driving transistor DT. In the plan view, the lower metal line BML may be spaced apart from the driving transistor DT by an eighth width d8. The eighth width d8 may be smaller than the fifth width d5. For example, the eighth width d8 may be approximately 0.85 μm, but is not necessarily limited to this.

[0220] According to an exemplary embodiment of this disclosure, the lower metal line BML is spaced apart from the driving transistor DT in a plan view, thereby minimizing crosstalk in the lower metal line BML caused by the driving transistor DT.

[0221] Figure 25 This is a circuit diagram specifically illustrating a sub-pixel SP-2 according to an exemplary embodiment of the present disclosure. Figure 26 This is a plan view specifically illustrating a sub-pixel SP-2 according to an exemplary embodiment of the present disclosure. Figure 27 yes Figure 26 A magnified view of region E6. Figure 28 yes Figure 26 A magnified view of area E7. Figure 29 yes Figure 26 A magnified view of region E8.

[0222] Reference Figures 25 to 29 The lower metal line T-BML-2 of sub-pixel SP-2 may overlap with the first and second transistors ST1-2. The lower metal line T-BML-2 may overlap with the channel (or active layer) of the first and second transistors ST1-2, and may be spaced apart from the respective channels (or active layers) of the first and first transistors ST1-1, the second transistors ST2 to ST5, and the driving transistor DT without overlapping with them.

[0223] Reference Figure 26 and Figure 27 In a plan view, the lower metal line BML may be larger than the first and second transistors ST1-2. Compared to the first and second transistors ST1-2, the lower metal line BML may extend further upward, downward, leftward, and rightward. Each of the extension widths d14 and d16 of the lower metal line BML extending from the first and second transistors ST1-2 may be approximately 1.75 μm, but is not necessarily limited to this.

[0224] In addition, such as Figure 26 and Figure 27As shown, in a plan view, the lower metal line BML may be spaced apart from the second transistor ST2. In the plan view, the lower metal line BML may be spaced apart from the second transistor ST2 by a fifteenth width d15. The fifteenth width d15 may be -10% to 10% of the width d12 of the lower metal line BML. For example, the fifteenth width d15 may be approximately 1.1 μm, but is not necessarily limited to this.

[0225] According to an exemplary embodiment of this disclosure, the lower metal line BML is spaced apart from the active layer ACT2 of the second transistor ST2 by a width d15, thereby minimizing crosstalk in the lower metal line BML caused by the second transistor ST2.

[0226] In addition, such as Figure 26 and 28 As shown, in a plan view, the lower metal line BML may be spaced apart from the driving transistor DT and the sixth transistor ST6. In the plan view, the lower metal line BML may be spaced apart from the driving transistor DT by a seventeenth width d17, and may be spaced apart from the sixth transistor ST6 by an eighteenth width d18. The seventeenth width d17 may be, for example, about 0.95 μm, but is not necessarily limited to this. The eighteenth width d18 may be, for example, about 0.9 μm, but is not necessarily limited to this.

[0227] According to an exemplary embodiment of this disclosure, the lower metal line BML may be arranged in a plan view to be spaced apart from the driving transistor DT by a seventeenth width d17 and from the sixth transistor ST6 by an eighteenth width d18, thereby minimizing crosstalk in the lower metal line BML caused by the driving transistor DT and the sixth transistor ST6.

[0228] like Figure 26 and Figure 29 As shown, in the plan view, the lower metal line BML may be spaced apart from the 3-1 transistor ST3-1. In the plan view, the lower metal line BML may be spaced apart from the 3-1 transistor ST3-1 by an eighteenth width d18. The eighteenth width d18 may be, for example, -10% to 10% of the width d12 of the lower metal line BML. For example, the eighteenth width d18 may be approximately 1.1 μm, but is not necessarily limited to this.

[0229] Figure 30 This is a circuit diagram specifically illustrating a sub-pixel SP_3 according to an exemplary embodiment of the present disclosure. Figure 31 This is a plan view specifically illustrating a sub-pixel SP_3 according to an exemplary embodiment of the present disclosure. Figure 32 yes Figure 31 A magnified view of region E9. Figure 33 yes Figure 31 A magnified view of region E10. Figure 34yes Figure 31 A magnified view of region E11.

[0230] Reference Figures 30 to 34 The lower metal line T-BML-3 of sub-pixel SP_3 may overlap with the 3-2nd transistor ST3-2. The lower metal line T-BML-3 may overlap with the channel (or active layer) of the 3-2nd transistor ST3-2, and may be spaced apart from the respective channels (or active layers) of the 3-1st transistor ST3-1, the first transistor ST1, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the driving transistor DT without overlapping with them.

[0231] Reference Figure 31 and Figure 32 In a plan view, the lower metal line BML may be larger than the channel of transistor ST3-2 (the third-second transistor). Compared to the channel of transistor ST3-2, the lower metal line BML may extend further upward, downward, leftward, and rightward. Each of the extension widths d23 and d24 of the lower metal line BML extending leftward and rightward from the channel of transistor ST3-2 (the third-second transistor) may be approximately 1.25 μm, and the extension width d26 of the lower metal line BML extending downward from the channel of transistor ST3-2 (the third-second transistor) may be approximately 1.75 μm, but they are not necessarily limited to these.

[0232] Additionally, in the plan view, the lower metal line BML may be spaced apart from the respective channels of the third-first transistor ST3-1 and the fourth transistor ST4, which are adjacent to the lower metal line BML. In the plan view, the lower metal line BML may be spaced apart from the third-first transistor ST3-1 by a twenty-second width d22. The twenty-second width d22 may be, for example, about 0.95 μm, but is not necessarily limited to this. The lower metal line BML may be spaced apart from the fourth transistor ST4 by a twenty-fifth width d25. The twenty-fifth width d25 may be, for example, about 0.95 μm, but is not necessarily limited to this.

[0233] According to an exemplary embodiment of this disclosure, the lower metal line BML is spaced apart from the respective channels of the third-1 transistor ST3-1 and the fourth transistor ST4 adjacent to the lower metal line BML, thereby minimizing crosstalk in the lower metal line BML caused by the respective channels of the adjacent transistors ST3-1 and ST4.

[0234] like Figure 31 and Figure 33As shown, in a plan view, the lower metal line BML may be spaced apart from the channel of the adjacent second transistor ST2. In the plan view, the lower metal line BML may be spaced apart from the second transistor ST2 by a twenty-seventh width d27. The twenty-seventh width d27 may be, for example, about 1.3 μm, but is not necessarily limited to this.

[0235] According to an exemplary embodiment of this disclosure, the lower metal line BML is spaced apart from the channel of the adjacent second transistor ST2, thereby minimizing crosstalk in the lower metal line BML caused by the channel of the adjacent second transistor ST2.

[0236] like Figure 31 and Figure 34 As shown, in the plan view, the lower metal line BML may be spaced apart from the respective channels of the driving transistor DT and the fifth transistor ST5 adjacent to the lower metal line BML. In the plan view, the lower metal line BML may be spaced apart from the driving transistor DT by a twenty-eighth width d28. The twenty-eighth width d28 may be, for example, about 0.95 μm, but is not necessarily limited thereto. In the plan view, the lower metal line BML may be spaced apart from the fifth transistor ST5 by a twenty-ninth width d29. The twenty-ninth width d29 may be, for example, about 0.9 μm, but is not necessarily limited thereto.

[0237] According to an exemplary embodiment of this disclosure, in a plan view, the lower metal line BML is arranged to be spaced apart from the respective channels of the driving transistor DT and the fifth transistor ST5 adjacent to the lower metal line BML, thereby minimizing crosstalk in the lower metal line BML caused by the respective channels of the adjacent driving transistor DT and the fifth transistor ST5.

[0238] Although exemplary embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions may be made without departing from the scope and spirit of this disclosure.

Claims

1. A display device, comprising: A base substrate includes: a display area comprising a plurality of pixels and a non-display area at least partially surrounding the display area; and The lower metal lines are arranged on the base substrate and surround at least a portion of the display area, extending into the interior of the display area. Each of the plurality of pixels includes a plurality of thin-film transistors arranged on the lower metal line. The plurality of thin-film transistors include driving transistors and switching transistors, each of the driving transistors and the switching transistors including a channel, a first electrode, a second electrode, and a gate electrode overlapping the channel. The lower metal line overlaps only with one of the channels of the driving transistor and the switching transistor. The non-display area includes a pad area, and the lower metal line is configured to receive a constant voltage from the lower metal pad located in the pad area. The lower metal lines in the plurality of pixels are connected to each other. In a plan view, the lower metal line is spaced apart from the channels of the other thin-film transistors among the plurality of thin-film transistors, except for those whose channels overlap with the lower metal line.

2. The display device according to claim 1, wherein, The lower metal wire includes a first lower metal wire and a second lower metal wire that are separate from each other, and The second lower metal line is arranged between the first lower metal line and the display area.

3. The display device according to claim 2, wherein, The lower metal line overlaps with the driving transistor in the thickness direction, but the lower metal line does not overlap with the channel of the switching transistor.

4. The display device according to claim 3, further comprising: The data line is connected to the thin-film transistor and extends in the first direction. The width of the overlapping portion between the lower metal wire and the data wire is 10% or less of the width of the data wire.

5. The display device according to claim 4, further comprising: Initialize the voltage line and connect it to the thin-film transistor. The width of the lower metal line is the same as the width of the overlapping portion between the lower metal line and the initialization voltage line.

6. The display device according to claim 5, wherein, The width of the lower metal wire is 2.4 μm or greater.

7. The display device according to claim 5, further comprising: The luminous line extends along a second direction that intersects the first direction. The plurality of thin-film transistors further includes a first switching transistor connected to the driving transistor. The first switching transistor has a gate electrode connected to the light-emitting line and a first electrode connected to the first driving voltage line, and is connected to the first electrode of the driving transistor. Wherein, the spacing between the channel of the first switching transistor and the lower metal line is 50% or more of the width of the lower metal line.

8. The display device according to claim 7, wherein, In a plan view, the lower metal line extends outward from the gate electrode of the driving transistor, and Wherein, the width of the lower metal line extending outward from the gate electrode of the driving transistor is less than the spacing distance between the channel of the first switching transistor and the lower metal line, and greater than 50% of the width of the lower metal line.

9. The display device according to claim 2, further comprising: The luminous line extends along the first direction. The plurality of thin-film transistors further includes a first switching transistor connected to the driving transistor. The first switching transistor has a gate electrode connected to the light-emitting line and a second electrode connected to the anode of the light-emitting element. The first switching transistor is connected to the second electrode of the driving transistor. The lower metal line overlaps with the first switching transistor in the thickness direction, but does not overlap with the channel of the driving transistor.

10. The display device according to claim 9, further comprising: The scan line extends along the first direction. The plurality of thin-film transistors further include a second switching transistor, the second switching transistor having a first electrode connected to the gate electrode of the driving transistor, a gate electrode connected to the scan line, and a second electrode connected to the initialization voltage line; and The spacing between the channel of the second switching transistor and the lower metal line is -10% to 10% of the width of the lower metal line.

11. The display device according to claim 2, further comprising: Scan lines, extending along the first direction, The plurality of thin-film transistors further includes a first switching transistor, the first switching transistor having a first electrode connected to the second electrode of the driving transistor, a gate electrode connected to the scan line, and a second electrode connected to the gate electrode of the driving transistor. Wherein, the channel of the first switching transistor overlaps with the lower metal line, and The channel of the driving transistor does not overlap with the lower metal line.

12. The display device according to claim 2, further comprising: Scan lines, extending along the first direction, The plurality of thin-film transistors further includes a first switching transistor, which has a second electrode connected to a first connection electrode via a contact hole, a gate electrode connected to the scan line, and a first electrode connected to the second electrode of the driving transistor. The first connection electrode is connected to the gate electrode of the driving transistor via another contact hole. Wherein, the channel of the first switching transistor overlaps with the lower metal line, and The channel of the driving transistor does not overlap with the lower metal line.

13. The display device according to claim 2, further comprising: Scan lines, extending along the first direction, The plurality of thin-film transistors further includes a first switching transistor, which has a second electrode connected to a second connection electrode via a contact hole and a gate electrode connected to the scan line. The second connection electrode is connected to an initialization voltage line via another contact hole. Wherein, the channel of the first switching transistor overlaps with the lower metal line, and The channel of the driving transistor does not overlap with the lower metal line.

14. The display device according to claim 1, wherein, The plurality of thin-film transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first transistor has a gate electrode connected to a scan line, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the gate electrode of the driving transistor. The second transistor has a gate electrode connected to the scan line, a first electrode connected to the first electrode of the driving transistor, and a second electrode connected to the data line. The third transistor has a gate electrode connected to another scan line, a first electrode connected to the gate electrode of the driving transistor, and a second electrode connected to the initialization voltage line. The fourth transistor has a gate electrode connected to another scan line, a first electrode connected to the anode of the light-emitting element, and a second electrode connected to the initialization voltage line. The fifth transistor has a gate electrode connected to the light-emitting line, a first electrode connected to the first driving voltage line, and a second electrode connected to the first electrode of the driving transistor. The sixth transistor has a gate electrode connected to the light-emitting line, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the anode of the light-emitting element. One of the channels of the first transistor, the third transistor, and the sixth transistor overlaps with the lower metal line, while the channel of the driving transistor does not overlap with the lower metal line.

15. The display device according to claim 1, further comprising: A gate layer is disposed on the lower metal line, wherein the lower metal line does not overlap with the gate layer in the non-display area.

16. The display device according to claim 15, wherein, The display area has a rectangular shape comprising a pair of long sides and a pair of short sides. The driver is located adjacent to the long side of the display area in the non-display area. The gate layer includes scan lines that pass through one of the plurality of pixels and extend in a first direction. The driver is connected to the pixel via a scan connection line, and The scanning connection line intersects with the lower metal line, while being electrically isolated from the lower metal line.

17. The display device according to claim 16, further comprising: A data metal layer is disposed on the gate layer. The scan connection line includes a first scan connection line connected to the driver, a second scan connection line connected to the scan line, and a third scan connection line connecting the first scan connection line and the second scan connection line. The third scan connection line is arranged on the data metal layer, and The first scan connection line and the second scan connection line are arranged on the gate layer.

18. The display device according to claim 17, wherein, The gate layer further includes an initialization voltage line that passes through the pixel and extends along the first direction. The data metal layer includes an initialization bus, which comprises a first initialization bus extending along a second direction intersecting the first direction and disposed between the driver and the lower metal line, and a second initialization bus connected to the first initialization bus and extending along the first direction. Wherein, the second initialization bus is connected to the initialization voltage line, and The second initialization bus intersects with the lower metal line.

19. The display device according to claim 18, wherein, The data metal layer further includes a first driving voltage line and a data line extending along the second direction and connected to the pixel, and Each of the first driving voltage line and the data line overlaps with the lower metal line in the thickness direction.

20. The display device according to claim 19, wherein, The non-display area also includes a bent area. The gate layer further includes a fan-out line connected to the data line and a signal input line connected to the driver. The lower metal wire is arranged between the signal input line and the fan-out line, and between the bending area and the display area.

21. The display device according to claim 20, wherein, The lower metal line includes a first lower metal portion located between the bending area and the display area, and a second lower metal portion passing through the bending area and connected to the first lower metal portion. The second lower metal portion is disposed on the data metal layer.

22. The display device according to claim 21, wherein, On the lower side of the bending area, the signal input line intersects with the second lower metal portion.

23. The display device according to claim 22, further comprising: The second driving voltage line is connected to the cathode of the pixel. The second driving voltage line is arranged on the data metal layer, and The second driving voltage line covers the signal input line between the bent area and the display area.

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