Processor, system, and method for storing register data elements

Abstract

A method of storing register data elements interleaved with data elements of different registers, a processor (1212) thereof, and a system thereof, wherein each noncontiguous data element of a register is retrieved for storage interleaved with each noncontiguous data element of a different register when an interleaved store instruction is executed, wherein a mask instruction indicating a lane of storage space in which the noncontiguous data element is stored is executed in conjunction with the interleaved store instruction, and wherein a second type of processor (1222) is configured to emulate a first type of processor (1212) to store the same noncontiguous data elements as stored in the first type processor (1212).

Description

Background Technology

[0001] Digital signal processors (DSPs) are optimized for processing data streams derived from a variety of input signals, such as sensor data, video streams, voice channels, radar signals, biomedical signals, etc. DSPs that operate on real-time data can receive input data streams, perform filtering functions (e.g., encoding or decoding) on ​​the data streams, and output transformed data streams. Example applications require memory access to load data registers from a data register file, and then supply data from the data registers to the functional units that perform data processing.

[0002] One or more DSP processing cores can be combined with various peripheral circuits, memory blocks, etc., on a single integrated circuit (IC) die to form a system-on-a-chip (SoC). These systems can contain multiple interconnected processors sharing on-chip and off-chip memory. Processors may include a combination of instruction cache (ICache) and data cache (DCache) to improve processing. Furthermore, multiple processors (sharing memory among them) can be integrated into a single embedded system. Processors can physically share the same memory.

[0003] Modern microprocessors execute instructions in several steps. These steps include fetching instructions from memory, decoding instructions, reading values ​​to be operated on, performing the operation, and writing the results back to memory. Sometimes referred to as "pipeline processing," this process allows the processor to execute several instructions simultaneously at different stages (i.e., "in the pipeline"). In this mode of operation, the processor can fetch instructions while decoding a previous instruction, reading input values ​​for an earlier instruction, etc. Overlapping instruction execution increases the speed at which the processor can execute instructions.

[0004] In modern microprocessors, parallel operations on multiple data points by a single instruction are also possible. Parallel operations where a single instruction operates on multiple data points simultaneously are called Single Instruction Multiple Data (SIMD) processing. One way to improve the efficiency of SIMD processing is to load multiple data points from memory (e.g., main memory or higher-order cache) or store multiple data points in said memory.

[0005] Each microprocessor can differ from others in various ways. For example, a microprocessor with two banks of memory loads data from and stores data in memory or cache in a different way than a microprocessor with four banks of memory. Programs or code written for a microprocessor may need to be rewritten to run on microprocessors with different memory access and management architectures. Summary of the Invention

[0006] This description generally pertains to the field of DSP. More specifically, but without limitation, aspects of this description relate to a method for executing interleaved store instructions by a processor. According to these aspects, a second type of processor executes instructions for interleaving the values ​​of registers of a processor to be stored to emulate a first type of processor. According to these aspects, the instructions for interleaving values ​​executed by the second type of processor are translated from instructions into interleaved values ​​of registers of the first type of processor. According to some aspects, the registers of the first type of processor and the registers of the second type of processor have different sizes.

[0007] According to some aspects, the interleaved values ​​of the second-type processor registers include data elements of a vector stored in each of the second-type processor registers. The vector of each of the second-type processor registers is of a size that can also be stored in the first-type processor registers. The second-type processor blocks one or more channels of its registers such that the size of each register matches the size of its corresponding vector. Attached Figure Description

[0008] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0009] Figure 1 This section describes an example of a dual scalar / vector data path processor.

[0010] Figure 2 illustrate Figure 1 The register files and functional units in the dual scalar / vector data path processor described herein.

[0011] Figure 3 Explain the global scalar register file.

[0012] Figure 4 This describes the local scalar register file shared by the arithmetic function unit.

[0013] Figure 5 This describes the local scalar register file shared by the multiplication function unit.

[0014] Figure 6 This describes the local scalar registers shared by the load / store unit.

[0015] Figure 7 Explain the global vector register file.

[0016] Figure 8 Explain the predicate register file.

[0017] Figure 9 This describes the local vector register file shared by the arithmetic function unit.

[0018] Figure 10This describes the local vector register file shared by the multiplication and associative function units.

[0019] Figure 11 This describes the pipeline stages of the CPU in this instance.

[0020] Figure 12 Describe a system that interleaves data elements in storage registers with data elements in different registers; and

[0021] Figures 13A to 13D illustrate Figure 12 The system's registers and memory are described in the document. Detailed Implementation

[0022] In the diagrams, for consistency, identical components are represented by the same reference number.

[0023] Figure 1 The description includes an instance processor 100 containing dual scalar / vector data paths 115 and 116. Processor 100 includes a streaming engine 125, a Level 1 instruction cache (L1I) 121, and a Level 1 data cache (L1D) 123. Processor 100 further includes a Level 2 combined instruction / data cache (L2) 130 that stores both instructions and data.

[0024] Figure 1 This describes the connection between the L1I cache 121 and the L2 combined instruction / data cache 130 via a 512-bit bus 142. Figure 1 The connection between the L1D cache 123 and the L2 combined instruction / data cache 130 via the 512-bit bus 145 is further explained. In an example of processor 100, the L2 combined instruction / data cache 130 stores instructions that back up the L1I cache 121 and data that back up the L1D cache 123. In one example, the L2 combined instruction / data cache 130 uses... Figure 1 Known or later-developed memory system technologies not described herein are further connected to higher-level caches and / or memories.

[0025] In various instances, the L1I cache 121, L1D cache 123, and L2 cache 130 can be implemented in different sizes; in this instance, L1I cache 121 and L1D cache 123 are each 32 kilobytes, and L2 cache 130 is 1024 kilobytes. In one instance, the central processing unit core 110, L1I cache 121, L1D cache 123, and L2 combined instruction / data cache 130 are formed on a single integrated circuit. This single integrated circuit may contain other circuitry.

[0026] The central processing unit core 110, controlled by the instruction fetch unit 111, fetches instructions from the L1I cache 121. The instruction fetch unit 111 determines the next instruction to be executed and calls a set of fetch blocks of that instruction size. When a cache hit occurs, instructions are fetched directly from the L1I cache 121 (if those instructions are stored in the L1I cache 121). When a cache miss occurs (the specified instruction fetch block is not stored in the L1I cache 121), the instructions are searched in the L2 combined cache 130. In one instance, the cache line size in the L1I cache 121 is equal to the fetch block size, which is 512 bits.

[0027] The memory locations of these instructions are either hits or misses in the L2 combined cache 130. A hit is served from the L2 combined cache 130. A miss is served from a higher-level cache (not specified) or from main memory (not specified). In one instance, the requested instruction is simultaneously served to both the L1I cache 121 and the central processing unit core 110 to accelerate usage.

[0028] exist Figure 1 In this configuration, the central processing unit core 110 contains multiple functional units to execute data processing tasks specified by instructions. The instruction dispatch unit 112 determines the target functional unit for each fetched instruction. In one instance, the central processing unit 110 operates as a Very Long Instruction Word (VLIW) processor capable of simultaneously operating multiple instructions in corresponding functional units. Preferably, the compiler organizes instructions in execution groups executed together.

[0029] Instruction dispatch unit 112 directs each instruction to its target functional unit. The functional unit assigned to an instruction is entirely specified by the instructions generated by the compiler. The hardware of the central processing unit core 110 does not participate in this functional unit assignment. In one instance, instruction dispatch unit 112 can operate on several instructions in parallel. The number of such parallel instructions is set by the size of the execution group.

[0030] Part of the dispatching task of instruction dispatch unit 112 is to determine whether an instruction is executed on a functional unit on the scalar data path side A 115 or the vector data path side B 116. The instruction bit within each instruction, referred to as the s-bit, determines which data path the instruction controls.

[0031] Instruction decoding unit 113 decodes each instruction in the currently executing group. Decoding includes identifying the functional unit that executes the instruction, identifying the registers used to supply data from a possible register file for the corresponding data processing operation, and identifying the register destination for the result of the corresponding data processing operation. Instructions may sometimes contain a constant field in place of a register number operand field. The result of this decoding is a signal used to control the target functional unit to perform the data processing operation specified by the corresponding instruction on the given data.

[0032] The central processing unit core 110 includes a control register 114. The control register 114 stores information for controlling the functional units in the scalar data path side A 115 and the vector data path side B 116. This information may sometimes include mode information or similar.

[0033] Decoded instructions from instruction decoding unit 113 and information stored in control register 114 are supplied to scalar data path side A 115 and vector data path side B 116. Therefore, functional units within scalar data path side A 115 and vector data path side B 116 perform instruction-specified data processing operations on the instruction-specified data and store the results in the instruction-specified data register. Each of scalar data path side A 115 and vector data path side B 116 contains multiple functional units operating in parallel. Data path 117 between scalar data path side A 115 and vector data path side B 116 allows data exchange.

[0034] The central processing unit core 110 includes other non-instruction-based modules. The emulation unit 118 allows the determination of the machine state of the central processing unit core 110 in response to instructions. This capability can be used for algorithm development. The interrupt / exception unit 119 enables the central processing unit core 110 to respond to external asynchronous events (interrupts) and to respond to attempts to perform improper operations (exceptions).

[0035] Processor 100 includes a streaming engine 125. Streaming engine 125 supplies two data streams from a predetermined address, which can be cached in L2 combined cache 130, to the register file on the vector data path side B of central processing unit core 110. This provides controlled data movement directly from memory (such as cached in L2 combined cache 130) to function unit operand inputs.

[0036] Figure 1Further explanation of the example data widths of the buses between various components. L1I cache 121 supplies instructions to instruction fetch unit 111 via bus 141. In one example, bus 141 is a 512-bit bus. Bus 141 is unidirectional from L1I cache 121 to central processing unit 110. L2 combined cache 130 supplies instructions to L1I cache 121 via bus 142. In one example, bus 142 is a 512-bit bus. Bus 142 is unidirectional from L2 combined cache 130 to L1I cache 121.

[0037] L1D cache 123 exchanges data with the register file in scalar data path A 115 via bus 143. In one example, bus 143 is a 64-bit bus. L1D cache 123 exchanges data with the register file in vector data path B 116 via bus 144. In one example, bus 144 is a 512-bit bus. Buses 143 and 144 are described as bidirectional, thereby supporting both data reading and data writing to the central processing unit 110. L1D cache 123 exchanges data with L2 combined cache 130 via bus 145. In one example, bus 145 is a 512-bit bus. Bus 145 is described as bidirectional, thereby supporting cache services for both data reading and data writing to the central processing unit 110.

[0038] When a processor data request is cache-triggered, it is fetched directly from L1D cache 123 (if the requested data is stored in L1D cache 123). When a cache miss occurs (the specified data is not stored in L1D cache 123), the data is searched in L2 combined cache 130. The memory location of the requested data is either a hit or a miss in L2 combined cache 130. A hit is served from L2 combined cache 130. A miss is served from another level of cache (not specified) or from main memory (not specified). The requested data can be simultaneously supplied to both L1D cache 123 and the central processing unit core 110 for faster access.

[0039] L2 combination cache 130 supplies data of a first data stream to streaming engine 125 via bus 146. In one instance, bus 146 is a 512-bit bus. Streaming engine 125 supplies this first data stream to the functional unit of vector data path B 116 via bus 147. In one instance, bus 147 is a 512-bit bus. L2 combination cache 130 supplies data of a second data stream to streaming engine 125 via bus 148. In one instance, bus 148 is a 512-bit bus. Streaming engine 125 supplies this second data stream to the functional unit of vector data path B 116 via bus 149. In one instance, bus 149 is a 512-bit bus. According to one instance, buses 146, 147, 148, and 149 are described as unidirectional from L2 combination cache 130 to streaming engine 125 and to vector data path B 116.

[0040] When a streaming engine data request is cache-hit, it is fetched directly from the L2 combined cache 130 (if the requested data is stored in the L2 combined cache 130). When a cache miss occurs (the specified data is not stored in the L2 combined cache 130), the data is looked up from another level of cache (not specified) or from main memory (not specified). In some instances, it is technically feasible for the L1D cache 123 to cache data not stored in the L2 combined cache 130. If this is supported, then when a streaming engine data request misses in the L2 combined cache 130, the L2 combined cache 130 should probe the L1D cache 123 to find the data requested by the streaming engine 125. If the L1D cache 123 stores this data, its probe response will contain the data, which is then served to fulfill the streaming engine request. If the L1D cache 123 does not store this data, its probe response will indicate that the L2 combined cache 130 must serve this streaming engine request from another level of cache (unspecified) or from main memory (unspecified).

[0041] Figure 2Further details regarding the functional units and register files within scalar data path side A 115 and vector data path side B 116 are provided. Scalar data path side A 115 includes L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226. Scalar data path side A 115 also includes global scalar register file 211, L1 / S1 local register file 212, M1 / N1 local register file 213, and D1 / D2 local register file 214. Vector data path side B 116 includes L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246. Vector data path side B 116 includes global vector register file 231, L2 / S2 local register file 232, M2 / N2 / C local register file 233, and predicate register file 234. There are restrictions on which functional units can be read from or written to which register files.

[0042] The scalar data path side A 115 contains L1 unit 221. L1 unit 221 typically accepts two 64-bit operands and produces a 64-bit result. Each operand is retrieved from an instruction-specified register in either the global scalar register file 211 or the L1 / S1 local register file 212. L1 unit 221 preferably performs the following instruction selection operations: 64-bit addition / subtraction operations; 32-bit minimum / maximum operations; 8-bit single-instruction multiple-data (SIMD) instructions, such as absolute summation, minimum and maximum value determination; looping minimum / maximum operations; and various move operations between register files. The result can be written to the instruction-specified register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0043] The scalar data path side A 115 contains S1 unit 222. S1 unit 222 typically accepts two 64-bit operands and produces a 64-bit result. Each operand is called from an instruction-specified register in either the global scalar register file 211 or the L1 / S1 local register file 212. In one instance, S1 unit 222 performs the same type of operation as L1 unit 221. In another instance, there may be minor variations between the data processing operations supported by L1 unit 221 and S1 unit 222. The result may be written to an instruction-specified register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0044] The scalar data path A 115 contains M1 unit 223. M1 unit 223 typically accepts two 64-bit operands and produces a 64-bit result. Each operand is called from an instruction-specified register in either the global scalar register file 211 or the M1 / N1 local register file 213. In one instance, M1 unit 223 performs the following instruction selection operations: 8-bit multiplication; complex dot product; 32-bit counting; complex conjugate multiplication; and bitwise logical operations, shift operations, addition, and subtraction. The result can be written to an instruction-specified register in either the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0045] The scalar data path A 115 contains N1 unit 224. N1 unit 224 typically accepts two 64-bit operands and produces a 64-bit result. Each operand is called from the instruction specifying register in either the global scalar register file 211 or the M1 / N1 local register file 213. In one instance, N1 unit 224 performs the same type of operation as M1 unit 223. There may be some double operations (called double-issued instructions) that utilize both M1 unit 223 and N1 unit 224 together. The result can be written to the instruction specifying register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0046] The scalar data path side A 115 contains D1 unit 225 and D2 unit 226. D1 unit 225 and D2 unit 226 typically each accept two 64-bit operands and each produce a 64-bit result. D1 unit 225 and D2 unit 226 typically perform address calculations and corresponding load and store operations. D1 unit 225 is used for 64-bit scalar load and store. D2 unit 226 is used for 512-bit vector load and store. In one instance, D1 unit 225 and D2 unit 226 also perform: swapping, packing and unpacking payloads and storing data; 64-bit SIMD arithmetic operations; and 64-bit bitwise logic operations. The D1 / D2 local register file 214 typically stores the base address and offset address used in the address calculations for the corresponding load and store operations. The two operands are each called from the instruction-specified register in the global scalar register file 211 or the D1 / D2 local register file 214. The calculation results can be written to the instruction-specified registers of the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0047] The vector data path side B 116 contains L2 unit 241. L2 unit 241 typically accepts two 512-bit operands and produces a single 512-bit result. Each operand is called from an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, or the predicate register file 234. In one instance, L2 unit 241 executes instructions similar to those in L1 unit 221, except for the wider 512-bit data. The result can be written to an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, the M2 / N2 / C local register file 233, or the predicate register file 234.

[0048] The vector data path side B 116 contains S2 unit 242. S2 unit 242 typically accepts two 512-bit operands and produces a 512-bit result. Each operand is called from an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, or the predicate register file 234. In one instance, S2 unit 242 executes instructions similar to those in S1 unit 222, except for the wider 512-bit data. The result can be written to an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, the M2 / N2 / C local register file 233, or the predicate register file 234.

[0049] The vector data path side B 116 contains M2 unit 243. S2 unit 243 typically accepts two 512-bit operands and produces a single 512-bit result. Each operand is called from an instruction-specified register in either the global vector register file 231 or the M2 / N2 / C local register file 233. In one instance, M2 unit 243 executes instructions similar to those in M1 unit 223, except for the wider 512-bit data. The result can be written to an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, or the M2 / N2 / C local register file 233.

[0050] The vector data path side B 116 contains N2 unit 244. N2 unit 244 typically accepts two 512-bit operands and produces a 512-bit result. Each operand is called from the instruction specifying register in either the global vector register file 231 or the M2 / N2 / C local register file 233. In one instance, N2 unit 244 performs the same type of operation as M2 unit 243. There may be some dual operations (called dual instruction issuance) that utilize both M2 unit 243 and N2 unit 244. The result can be written to the instruction specifying register in the global vector register file 231, the L2 / S2 local register file 232, or the M2 / N2 / C local register file 233.

[0051] The vector data path side B 116 contains the associated (C) unit 245. C unit 245 typically accepts two 512-bit operands and produces a single 512-bit result. Each operand is called from an instruction-specified register in either the global vector register file 231 or the M2 / N2 / C local register file 233.

[0052] The vector data path side B 116 contains P unit 246. The vector predicate (P) unit 246 performs basic logic operations on the registers of the local predicate register file 234. P unit 246 directly accesses to read from or write to the predicate register file 234.

[0053] Figure 3 Description of Global Scalar Register File 211. There are 16 independent 64-bit wide scalar registers designated A0 to A15. Each register in Global Scalar Register File 211 can be read or written as 64-bit scalar data. All scalar data path-side functional units A115 (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read from or write to Global Scalar Register File 211. In one instance, Global Scalar Register File 211 can be read as 32 bits or as 64 bits, and written only as 64 bits. Instruction execution determines the size of the data to be read. The vector data path side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can be read from the global scalar register file 211 via cross path 117, subject to the restrictions which will be detailed below.

[0054] Figure 4 Description of D1 / D2 local register file 214. There are sixteen independent 64-bit wide scalar registers designated D0 to D15. Each register in D1 / D2 local register file 214 can be read or written as 64-bit scalar data. All scalar data path-side A115 function units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can be written to global scalar register file 211. Only D1 unit 225 and D2 unit 226 can be read from D1 / D2 local scalar register file 214. The data stored in D1 / D2 local scalar register file 214 is expected to contain the base address and offset address used in address calculations.

[0055] Figure 5Description of L1 / S1 Local Register File 212. In this example, L1 / S1 Local Register File 212 contains eight independent 64-bit wide scalar registers designated AL0 to AL7. In this example, instruction decoding allows L1 / S1 Local Register File 212 to contain up to 16 registers, but only eight registers are implemented to reduce circuit size and complexity. Each register in L1 / S1 Local Register File 212 can be read or written as 64-bit scalar data. All scalar data path-side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can be written to L1 / S1 Local Scalar Register File 212. Only L1 unit 221 and S1 unit 222 can be read from L1 / S2 Local Scalar Register File 212.

[0056] Figure 6 Description of M1 / N1 Local Register File 213. In this example, eight independent 64-bit wide scalar registers, designated AM0 through AM7, are implemented. In this example, instruction decoding allows M1 / N1 Local Register File 213 to contain up to 16 registers, but only eight registers are implemented to reduce circuit size and complexity. Each register in M1 / N1 Local Register File 213 can be read or written as 64-bit scalar data. All scalar data path-side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can be written to M1 / N1 Local Scalar Register File 213. Only M1 unit 223 and N1 unit 224 can be read from M1 / N1 Local Scalar Register File 213.

[0057] Figure 7 Description of Global Vector Register File 231. There are 16 independent 512-bit wide vector registers. Each register in Global Vector Register File 231 can be read or written as 64-bit scalar data specified as B0 to B15. Each register in Global Vector Register File 231 can be read or written as 512-bit vector data specified as VB0 to VB15. The instruction type determines the data size. All vector data path-side B116 function units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read from or write to Global Vector Register File 231. The scalar data path side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can be read from the global vector register file 231 via cross path 117, subject to the restrictions which will be detailed below.

[0058] Figure 8 The predicate (P) local register file 234 is described. Eight independent 64-bit wide registers exist, designated P0 through P7. Each register in the P local register file 234 can be read or written as 64-bit scalar data. Functional units L2 241, S2 242, C 244, and P 246 on the vector data path side B 116 can be written to the P local register file 234. Only L2 241, S2 242, and P 246 can be read from the P local scalar register file 234. Common intended uses of the P local register file 234 include: writing a single bit of a SIMD vector comparison result from L2 241, S2 242, or C 245; manipulating the SIMD vector comparison result by P 246; and using the manipulated result to control further SIMD vector operations.

[0059] Figure 9 Description of L2 / S2 local register file 232. In this example, eight independent 512-bit wide vector registers are implemented. In this example, instruction decoding allows L2 / S2 local register file 232 to contain up to 16 registers, but only eight registers are implemented to reduce circuit size and complexity. Each register in L2 / S2 local vector register file 232 can be read or written as 64-bit scalar data specified as BL0 to BL7. Each register in L2 / S2 local vector register file 232 can be read or written as 512-bit vector data specified as VBL0 to VBL7. Instruction type determines data size. All vector data path-side B 116 function units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can be written to L2 / S2 local vector register file 232. Only L2 unit 241 and S2 unit 242 can be read from L2 / S2 local scalar register file 232.

[0060] Figure 10Description of M2 / N2 / C local register file 233. In this example, eight independent 512-bit wide vector registers are implemented. In this example, instruction decoding allows M2 / N2 / C local register file 233 to contain up to 16 registers, but only eight registers are implemented to reduce circuit size and complexity. Each register in M2 / N2 / C local vector register file 233 can be read or written as 64-bit scalar data specified as BM0 to BM7. Each register in M2 / N2 / C local vector register file 233 can be read or written as 512-bit vector data specified as VBM0 to VBM7. All vector data path-side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can be written to M2 / N2 / C local vector register file 233. Only M2 unit 243, N2 unit 244 and P unit 245 can be read from M2 / N2 / C local vector register file 233.

[0061] Specifying that the global register file can be accessed by all functional units on one side, while the local register file can only be accessed by some functional units on one side, is a design choice. In another example, different accessibility specifications can be made, such as using only one type of register file corresponding to the global register file described herein.

[0062] Cross path 117 allows limited data exchange between scalar data path side A 115 and vector data path side B 116. During each operation cycle, a 64-bit data word can be called from global scalar register file A 211 to be used as an operand by one or more functional units on vector data path side B 116, and a 64-bit data word can be called from global vector register file 231 to be used as an operand by one or more functional units on scalar data path side A 115. Any functional unit on scalar data path side 115 (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read a 64-bit operand from global vector register file 231. This 64-bit operand is the least significant bit of the 512-bit data in the access registers of global vector register file 231.

[0063] Multiple scalar data path side A 115 functional units can use the same 64-bit cross-path data as the operands during the same operand cycle. However, in this example, only one 64-bit operand is transferred from the vector data path side B 116 to the scalar data path side A 115 in any single operand cycle. Any vector data path side B 116 functional unit (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read the 64-bit operand from the global scalar register file 211. If the corresponding instruction is a scalar instruction, then the cross-path operand data is treated as any other 64-bit operand. If the corresponding instruction is a vector instruction, then the upper 448 bits of the operand are filled with zeros. Multiple vector data path side B 116 functional units can use the same 64-bit cross-path data as the operands during the same operand cycle. In one instance, within any single operation loop, only one 64-bit operand is transferred from the scalar data path side A 115 to the vector data path side B 116.

[0064] Figure 11 The following pipeline phases are described: Program fetch phase 1110, dispatch and decode phase 1120, and execution phase 1130. Program fetch phase 1110 contains all three phases for each instruction. Dispatch and decode phase 1120 contains all three phases for each instruction. Execution phase 1130 contains one to four phases depending on the instruction.

[0065] Fetch phase 1110 includes Program Address Generation (PG) phase 1111, Program Access (PA) phase 1112, and Program Receiving (PR) phase 1113. During Program Address Generation phase 1111, the program address is generated in the processor, and a read request is sent to the memory controller for the L1I cache. During Program Access phase 1112, the L1I cache processes the request, accesses the data in its memory, and sends a fetch packet to the processor boundary. During Program Receiving phase 1113, the processor registers the fetch packet. Instructions are fetched from the fetch packet, which contains sixteen 32-bit wide words.

[0066] Processor Core 110 ( Figure 1 ) and L1I cache 121 pipeline ( Figure 1 They are decoupled from each other. The fetching of packets from the L1I cache may take a varying number of clock cycles, depending on external conditions, such as whether there is a hit in the L1I cache 121 or the L2 combined cache 130. Therefore, the program access phase 1112 may take several clock cycles instead of one clock cycle as in other stages.

[0067] Instructions executed in parallel constitute an execution group. In this example, an execution group can contain up to sixteen 32-bit wide time slots for sixteen instructions. Two instructions in an execution group cannot use the same functional unit. Time slots are one of five types: 1) self-contained instructions executed on one of the functional units of processor core 110 (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246); 2) unitless instructions, such as NOP (no operation) instructions or multiple NOP instructions; 3) branch instructions; 4) constant field extensions; and 5) condition code extensions.

[0068] Distribution and decoding phase 1120 ( Figure 11 The instruction dispatch process includes a phase 1121 (to the appropriate execution unit), a phase 1122 (instruction pre-decoding), and a phase 1123 (instruction decoding and operand fetching). During instruction dispatch in phase 1121, fetched packets are segmented into execution packets and assigned to the appropriate functional units. During phase 1122, source registers, destination registers, and associated paths are decoded to execute instructions within the functional unit. During phase 1123, more detailed unit decoding is performed, and operands are read from the register file.

[0069] Execution phase 1130 comprises execution (E1 to E5) phases 1131 to 1135. Different types of instructions require different numbers of these phases to complete their execution. These phases of the pipeline play a crucial role in understanding the device state at the processor's loop boundaries.

[0070] During phase E1 (1131), the conditions of the instruction are evaluated and the operands are operated on. For example, in... Figure 11 The description states that E1 stage 1131 can receive operands from either stream buffer 1141 or the register file, schematically shown as 1142. For load and store instructions, an address is generated, and the address modification is written to the register file. For branch instructions, the branch fetch group in stage PG (1111) is affected. (As shown in...) Figure 11 The diagram illustrates that load and store instructions access memory, schematically shown here as memory 1151. For single-loop instructions, the result is written to the destination register file. This assumes that any condition of the instruction evaluates to true. If the condition evaluates to false, then the instruction does not write any result or have any pipeline operation after E1 stage 1131.

[0071] During E2 phase 1132, the load instruction sends the address to memory. The store instruction sends the address and data to memory. In the event of saturation, a single-loop instruction that saturates the result sets the saturation (SAT) bit in the control status register (CSR). For a two-loop instruction, the result is written to the destination register file.

[0072] During E3 phase 1133, data memory access is performed. In the event of saturation, any multiplication instruction that saturates the result sets the SAT bit in the Control Status Register (CSR). For 3-loop instructions, the result is written to the destination register file.

[0073] During E4 stage 1134, load instructions bring data to the processor boundary. For the 4-loop instruction, the result is written to the destination register file.

[0074] During E5 stage 1135, the load instruction writes data into the register. This is in Figure 11 The input from memory 1151 to E5 stage 1135 is illustrated schematically.

[0075] In this example, the 512-bit register is used for... Figure 1 and 2 SIMD operations are performed on the processor. Depending on the size of the data elements, different numbers of operations can be executed in parallel. For example, in one instance, the word size is 32 bits (4 bytes), and the half-word is 16 bits (2 bytes). When the input data precision is half-word (2 bytes), there are 32 channels in the 512-bit (64-byte) register, allowing 32 parallel operations. When the data precision is 64 bits (8 bytes), there are 8 channels in the 512-bit (64-byte) register, allowing 8 parallel operations. When the data precision is 32 bits (4 bytes), there are 16 channels in the 512-bit (64-byte) register, allowing 16 parallel operations.

[0076] In one instance, the number of channels in a register is equal to the number of functional units performing arithmetic functions on the register. For example, when there are 32 channels in the register, 32 functional units perform arithmetic functions on the corresponding data elements in the register file. In this instance, when the register size is 512 bits, the size of the corresponding data element can be half a word (2 bytes).

[0077] Based on some aspects described herein, the compiler is configured to run on the processor and produce runtime. Figure 1 and 2The compiler is further configured to generate instructions that interleave vector data elements from multiple registers and store the interleaved values ​​in a single register, cache, or memory. Multiple instructions can be generated by the compiler to emulate instructions with different... Figure 1 and 2 The processor architecture described herein is defined by a specific set of instructions (ISAs), which includes vector sizes, how such operations are performed, and how data is passed in and out. At least when the first and second processors operate on vectors of different sizes, or retrieve values ​​from and store values ​​in registers of different sizes, the architecture of the first processor differs from that of the second processor.

[0078] Figure 12 This describes a system with two compilers, each configured to compile source code into executable code for its corresponding processor, where the processors have different architectures. In this example, the compiler for the second type of processor generates an executable for the second type of processor based on source code files prepared for the first type of processor. When the source code is executed on the second type of processor, the second type of processor can emulate the first type of processor. Simultaneously with emulating the first type of processor, the second type of processor can also emulate interleaved store instructions prepared for the first type of processor.

[0079] exist Figure 12 In the process, source files are written to execute on a first type of processor (processor 1212). To execute the source files on processor 1212, compiler 1211 compiles the source code to produce an executable file for processor 1212. Compiler 1211 can also operate as an assembler and linker to produce an executable file for processor 1212 based on the type and structure of the source files.

[0080] Figure 12 Translator 1201 translates source files written for processor 1212 into source files for a second type of processor (processor 1222). Compiler 1221, which compiles the source code generated by translator 1201, produces an executable file for processor 1222. Compiler 1221 may rely on routines, modules, or objects stored in libraries (e.g., virtual machine libraries) to produce the executable file for processor 1222.

[0081] When processor 1222 executes the executable file generated by compiler 1221, processor 1222 emulates the operation and functionality of processor 1212. Processor 1222 has a different architecture than processor 1212. For example, processor 1222 can operate on vectors wider (512 bits) than the vectors (320 bits) of processor 1212. Processor 1222 may have variable-width channels per register, such as 8, 12, 32, and 64 channels, to accommodate various operations based on vectors of different sizes or wider vectors. Processor 1212 may have a set of registers with 40-bit data elements, having a fixed number (8) of register channels. Processor 1222 may have a vector prediction mechanism that allows only certain channels of the registers to be stored, while processor 1212 may have interleaved store instructions that allow interleaved storage of its vectors. Processor 1222 emulates the interleaved store functionality of processor 1212 based on the interleaved store instructions and its vector prediction mechanism compiled by compiler 1221. Processor 1222 can be... Figure 1 and 2 The processor described in the document.

[0082] To emulate processor 1212, translator 1201 translates the source code of processor 1212, and compiler 1221 generates an executable file using the following instances of interleaved store instructions, such as VSTINLB, VSTINTLB4, VSTINTLH, VSTINTLW, and VSTINTLD. When processor 1222 executes these files, it emulates processor 1212 and its interleaved store instructions.

[0083] The VSTINTLB instruction takes two input vectors (input 1 and input 2) each 64 bytes (512 bits) wide, interleaves the even-numbered bytes from input 1 and input 2, and stores the interleaved output in a storage structure, such as another register, a higher-order cache, or memory.

[0084] Input 1: A63, A62, A61, A60, ... A4, A3, A2, A1, A0

[0085] Input 2: B63, B62, B61, B60, ... B4, B3, B2, B1, B0

[0086] Output: B62,A62,B60,A60,……………………B4,A4,B2,A2,B0,A0

[0087] In the preceding text, vector input 1 has 64 data elements A63 to A0, and vector input 2 has 64 data elements B63 to B0. When VSTINTLB is executed, a vector output of 64 data elements is stored, consisting of alternating even-numbered bytes from the two input vectors (i.e., vector input 1 and vector input 2).

[0088] The VSTINTLB4 instruction takes two input vectors (input 1 and input 2) each 64 bytes (512 bits) wide, interleaves every fourth byte element from input 1 and input 2, and stores the interleaved output (shown below) in a storage structure, such as another register, a higher-order cache, or memory.

[0089] Input 1: A63, A62, A61, A60, ... A4, A3, A2, A1, A0

[0090] Input 2: B63, B62, B61, B60, ... B4, B3, B2, B1, B0

[0091] Output: 0,0,...0,0,B60,A60,……………………B4,A4,B0,A0

[0092] The resulting interleaved output is still the size of an input vector (e.g., input 1 or input 2), and the upper half of the output is padded with zeros.

[0093] The VSTINTLH instruction takes an even number of half-words from two input vectors (input 1, input 2), each 512 bits wide, with half-word (2-byte) data elements, and stores the vector output in a storage structure such as another register, a higher-order cache, or memory.

[0094] Input 1: A31, A30, A29, A28, …..............A4, A3, A2, A1, A0

[0095] Input 2: B31, B30, B29, B28, ... B4, B3, B2, B1, B0

[0096] Output: B30, A30, B28, A28, ... B4, A4, B2, A2, B0, A0

[0097] The VSTINTLW instruction takes even numbers from two input vectors, each 512 bits wide, with word (4-byte) data elements, and stores these even-numbered data elements in a storage structure such that even-numbered data elements from one input vector are interleaved with those from the other input vector. This storage structure may be another register, a higher-order cache, or memory. The VSTINLD instruction takes even-numbered double words from two input vectors, each 512 bits wide, with double-word (8-byte) data elements, and stores these even-numbered double-word data elements in a storage structure such that even-numbered double-word data elements from one input vector are interleaved with those from the other input vector. This storage structure may be another register, a higher-order cache, or memory.

[0098] Figures 13A to 13D illustrate Figure 12 The registers and memory of processors 1212 and 1222. Figure 13A This describes the two vector registers of processor 1212: vector Vn and vector Vn+1. Each vector register of processor 1212 is 320 bits and has 8 channels. Figure 13B Explanation of storage when processor 1212 executes interleaved store instructions Figure 13A The memory of processor 1212 for the interleaved values ​​of vectors Vn and Vn+1. For example, in Figure 13B The description states that the data elements of vectors Vn and Vn+1 are stored and interleaved in the memory of processor 1212 at the rows at addresses addr and addr+16.

[0099] Figure 13C This describes the two vector registers of processor 1222: vector Vn and vector Vn+1. Each vector register of processor 1222 is 512 bits and has 16 channels. Figure 13D This describes the storage process when the translator 1201 translates the interleaved store instructions of the processor 1212 into VSTINLH instructions. Figure 13B The memory of processor 1222 for the interleaved values ​​of vectors Vn and Vn+1.

[0100] When translator 1201 translates instructions for processor 1212 into instructions for processor 1222, in addition to interleaved store instructions, translator 1201 also generates predictive instructions. The predictive instructions are executed by processor 1222 to mask the upper 8 channels of processor 1222's vector register, which has more channels than processor 1212's vector register. Figure 13C The value of "xxxxxxxx" in the register indicates an unused register channel. The predicate instruction sets the predicate to store only... Figure 13CThe remaining 8 channels of the registers. When the VSTINLH instruction is executed, the memory of processor 1222 stores data in the memory of processor 1212 (…). Figure 13B The same vector value ( Figure 13D ).

[0101] In this description, the statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can vary with Y or any number of other factors.

[0102] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. A method for storing the value of a register, the method comprising: An interleaved store instruction is executed on a first processor including a first set of registers, wherein each of the first set of registers is configured to store a corresponding vector having multiple data elements, wherein the execution of the interleaved store instruction involves the first set of registers being larger than the second set of registers of a second processor, and wherein the second processor is the processor to be emulated by the first processor. Block the first subset of each register in the first group of registers; Retrieve data elements from the plurality of data elements of the corresponding vectors in the second subset of each of the first set of registers; and The data element retrieved from the plurality of data elements of the corresponding vector of each of the first set of registers is stored in the memory structure of the first processor. Each of the data elements in the first register of the first set of registers is stored to be interleaved with each of the data elements in the second register of the first set of registers.

2. The method according to claim 1, The data elements mentioned therein are non-continuous data elements.

3. The method of claim 1, wherein the data element retrieved from the plurality of data elements of the corresponding vector in the second subset of each of the first set of registers includes an even number of data elements of the corresponding register of the first set of registers.

4. The method according to claim 1, The data element retrieved from the plurality of data elements of the corresponding vector in the second subset of each of the first set of registers includes every fourth data element of the corresponding register of the first set of registers.

5. The method according to claim 1, The size of the data element retrieved from the plurality of data elements of the corresponding vector in the second subset of each of the first set of registers is 1 byte, 2 bytes, 4 bytes, or 8 bytes.

6. The method according to claim 1, The execution of the interleaved storage instruction includes: The first subset of each register in the first set of registers is blocked in the following manner: Generate mask command; and Execute the masking instruction to block one or more channels of each of the first set of registers.

7. The method of claim 1, wherein storing the data elements such that a first portion of each of the plurality of data elements of the corresponding vector is stored in the storage structure without storing a second portion of the corresponding data element.

8. The method according to claim 7, wherein: The first part of each of the plurality of data elements is the lower half of the corresponding data element; and The second part of each of the plurality of data elements is the upper half of the corresponding data element.

9. The method of claim 1, wherein storing the data elements such that the order of the data elements in the storage structure is reversed relative to each of the first set of registers.

10. A memory system comprising, Source file, which is used for the first processor of the first type; A translator configured to translate the source file for the first processor into a source file for a second type of second processor; and A compiler configured to generate an executable file for the second processor based on the translated source file; The source file mentioned above includes interleaved storage instructions; The second processor includes a first set of registers; The size of each of the first set of registers is greater than the size of the second set of registers of the first processor; Each of the first set of registers is configured to store a corresponding vector with multiple data elements; and The executable file contains instructions that cause the second processor to perform the following steps: Block the first subset of each of the first set of registers; and Data elements are retrieved and stored from the plurality of data elements of the corresponding vectors in the second subset of each of the first set of registers; Each of the data elements in the first register of the first set of registers is stored to be interleaved with each of the data elements in the second register of the first set of registers.

11. The memory system according to claim 10, The data elements mentioned therein are non-continuous data elements.

12. The memory system according to claim 10, When the source file for the first processor is executed by the first processor, the data elements stored by the second processor are configured to be the same as the data elements to be stored by the first processor.

13. The memory system of claim 10, further comprising: The storage structure of the second processor is configured to store interleaved data elements.

14. The memory system of claim 13, wherein the memory structure includes the memory of the second processor or a higher-order cache.

15. The memory system according to claim 10, The data elements retrieved from the plurality of data elements of the corresponding vector of each of the first set of registers include the even-numbered data elements of the corresponding register of the first set of registers.

16. The memory system according to claim 10, The data element retrieved from the plurality of data elements of the corresponding vector of each of the first set of registers includes every fourth data element of the corresponding register of the first set of registers.

17. The memory system according to claim 10, The size of the data element retrieved from the plurality of data elements of the corresponding vector of each of the first set of registers is 1 byte, 2 bytes, 4 bytes, or 8 bytes.

18. The memory system according to claim 10, The executable file mentioned above includes mask instructions; and The second processor is configured to block one or more channels of each of the first set of registers by executing the masking instructions.

19. A first processor, comprising, First set of registers; and The storage structure, coupled to the first set of registers, Each of the registers in the first set is configured to store a corresponding vector with multiple data elements. The size of each register in the first set is greater than the size of the second set of registers in the second processor, and the second processor is the processor to be simulated by the first processor; and The first processor is configured to: Since the size of the first group of registers is greater than the size of the second group of registers, block the first subset of each register in the first group of registers; as well as Data elements are retrieved from the plurality of data elements of the corresponding vectors in the second subset of each of the first set of registers, and the retrieved data elements are stored in the storage structure based on interleaved storage instructions. When stored in the storage structure, each of the data elements in the first register of the first set of registers is configured to interleave with each of the data elements in the second register of the first set of registers.

20. The first processor according to claim 19, The data elements mentioned therein are non-continuous data elements.

21. The first processor according to claim 19, The data elements retrieved from the plurality of data elements of each of the first set of registers include the even-numbered data elements of the corresponding registers of the first set of registers.

22. The first processor according to claim 19, The data element retrieved from the plurality of data elements of each of the first set of registers includes every fourth data element of the corresponding register in the first set of registers.

23. The first processor according to claim 19, The size of the data element retrieved from the plurality of data elements of the corresponding vector of each of the first set of registers is 1 byte, 2 bytes, 4 bytes, or 8 bytes.

24. The processor according to claim 19, The first processor is configured to execute masking instructions to block the first subset of each register in the first set of registers.

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