Methods and systems for etch depth control in iii-v semiconductor devices

Abstract

A method of fabricating a vertical FET device includes providing a semiconductor substrate structure including a marker layer; forming a hard mask layer coupled to the semiconductor substrate structure, wherein the hard mask layer includes a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; probing the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in a recessed region disposed between adjacent ones of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 044,693, filed June 26, 2020, the disclosure of which is incorporated herein by reference in its entirety for all purposes. Background Technology

[0003] Power electronics are widely used in a variety of applications, including power conversion, motor drives, switching power supplies, and lighting. Power electronic devices such as transistors are typically used in such power switching applications. The operation of current-generation power transistor devices, especially those with high-voltage (>600V) handling capabilities, is hampered by low switching speeds and high specific on-resistance.

[0004] There is a need in the art to control the manufacturing process of transistors to improve their electrical performance, such as breakdown voltage, leakage current, and specific on-resistance. Summary of the Invention

[0005] Some embodiments of the present invention provide novel vertical-fin-based field-effect transistor (FET) devices and methods for manufacturing such FET devices with improved specific on-resistance, leakage current, and breakdown voltage. Some embodiments of the present invention provide novel metal-oxide-semiconductor field-effect transistor (MOSFET) devices and methods for manufacturing such MOSFET devices with improved specific on-resistance, leakage current, and breakdown voltage.

[0006] In one aspect of the invention, a method of manufacturing a FET device includes: providing a semiconductor substrate structure including a marker layer; forming a hard mask layer coupled to the semiconductor substrate structure, wherein the hard mask layer includes a set of openings operable to expose an upper surface portion of the semiconductor substrate structure; etching the upper surface portion of the semiconductor substrate structure to form a plurality of fins; etching at least a portion of the marker layer; probing the etching of the at least a portion of the marker layer; epitaxially growing a semiconductor layer in a recessed region disposed between adjacent fins of the plurality of fins; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the semiconductor layer.

[0007] In some embodiments, the substrate structure includes: a first epitaxial semiconductor layer coupled to a semiconductor substrate, wherein the first epitaxial semiconductor layer is characterized by having a first conductivity type and a first doping concentration; a second epitaxial semiconductor layer coupled to the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer is characterized by having the first conductivity type; a marker layer coupled to the second epitaxial semiconductor layer; a third epitaxial semiconductor layer coupled to the marker layer, wherein the third epitaxial semiconductor layer is characterized by having the first conductivity type; and a fourth epitaxial semiconductor layer coupled to the third epitaxial semiconductor layer, wherein the fourth epitaxial semiconductor layer is characterized by having the first conductivity type and a second doping concentration.

[0008] In some embodiments, the second semiconductor layer is characterized by having a first gradient doping concentration, which is a gradient that linearly increases from a first doping concentration to a third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

[0009] In some embodiments, the third semiconductor layer is characterized by having a second gradient doping concentration, which is a gradient that linearly increases from a third doping concentration to the second doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

[0010] In one aspect of the present invention, a method of manufacturing a FET device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; forming a marker layer coupled to the third semiconductor layer; and epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer... The method is characterized by having a first conductivity type and a second doping concentration; forming a hard mask layer coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth semiconductor layer; etching the fourth semiconductor layer using the hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by a recessed region of a plurality of recessed regions; etching at least a portion of the marker layer; probing the etching of the at least a portion of the marker layer; epitaxially growing a fifth semiconductor layer in the plurality of recessed regions, wherein the fifth semiconductor layer is characterized by having a second conductivity type opposite to the first conductivity type; forming a source metal layer on each of the plurality of fins; and forming a gate metal layer coupled to the fifth semiconductor layer.

[0011] In some embodiments, the second semiconductor layer is characterized by having a gradient doping concentration, which is a gradient that linearly increases from a first doping concentration to a third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

[0012] In one aspect of the invention, a FET device includes: a semiconductor substrate; a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; a plurality of fins coupled to the first semiconductor layer, each of the plurality of fins being separated by a recessed region of a plurality of recessed regions, wherein each of the plurality of fins includes: a marker layer coupled to the second semiconductor layer; a third semiconductor layer coupled to the marker layer, wherein the third semiconductor layer is characterized by having a first conductivity type; a fourth semiconductor layer coupled to the third semiconductor layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and a second doping concentration; a fifth semiconductor layer epitaxially grown in the plurality of recessed regions, wherein the fifth semiconductor layer is characterized by having a second conductivity type opposite to the first conductivity type; a source metal layer coupled to each of the plurality of fins; and a gate metal layer coupled to the fifth semiconductor layer.

[0013] In one aspect of the invention, a FET device includes: a semiconductor substrate; a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; a plurality of fins coupled to the second semiconductor layer, each of the plurality of fins being separated by a recessed region of a plurality of recessed regions, wherein each of the plurality of fins includes: a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type and a second doping concentration; a marker layer coupled to the third semiconductor layer; a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and a third doping concentration; a fifth semiconductor layer epitaxially grown in the plurality of recessed regions, wherein the fifth semiconductor layer is characterized by having a second conductivity type opposite to the first conductivity type; a source metal layer coupled to each of the plurality of fins; and a gate metal layer coupled to the fifth semiconductor layer.

[0014] In one aspect of the invention, a method of manufacturing a vertical FET device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; forming a marker layer coupled to the third semiconductor layer; epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and a second doping concentration; forming a hard mask layer coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose an upper surface portion of the fourth semiconductor layer; and using the hard mask... The process involves: etching the fourth semiconductor layer using a hard mask layer to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions; etching at least a portion of the marker layer; probing the etching of the at least a portion of the marker layer; depositing a dielectric spacer layer coupled to the hard mask layer and the plurality of recessed regions; forming a first photoresist layer coupled to the dielectric spacer layer; etching the dielectric spacer layer and the marker layer within the plurality of recessed regions; ion implanting dopant in the second semiconductor layer within the plurality of recessed regions to form a gate region; removing the first photoresist layer; forming a gate metal layer coupled to the gate region within the plurality of recessed regions; forming a second photoresist layer on the gate metal layer within the plurality of recessed regions; using the second photoresist layer as a mask to etch the dielectric spacer layer and the hard mask layer; removing the second photoresist layer; and forming a source metal layer coupled to the fourth semiconductor layer.

[0015] In one aspect of the invention, a method for manufacturing a MOSFET device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; forming a marker layer coupled to the third semiconductor layer; epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and a second doping concentration; forming a hard mask layer coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth semiconductor layer; and using... The hard mask layer is used as a mask to etch the fourth semiconductor layer to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions; at least a portion of the marker layer is etched; the etching of the at least a portion of the marker layer is probed; a dielectric spacer layer coupled to the hard mask layer and the plurality of recessed regions is deposited; a first photoresist layer coupled to the dielectric spacer layer is formed; the dielectric spacer layer and the marker layer in the plurality of recessed regions are etched; a metal dielectric layer is deposited on the third semiconductor layer in the plurality of recessed regions; the first photoresist layer is removed; a gate metal layer coupled to the metal dielectric layer is formed in the plurality of recessed regions; a second photoresist layer is formed on the gate metal layer in the plurality of recessed regions; the second photoresist layer is used as a mask to etch the dielectric spacer layer and the hard mask layer; the second photoresist layer is removed; and a source metal layer coupled to the fourth semiconductor layer is formed.

[0016] In one aspect of the invention, a method for manufacturing a MOSFET device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; forming a marker layer coupled to the third semiconductor layer; epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and a second doping concentration; forming a hard mask layer coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose an upper surface portion of the fourth semiconductor layer; etching the fourth semiconductor layer using the hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by a recessed region of a plurality of recessed regions; etching at least a portion of the marker layer; probing the etching of the at least a portion of the marker layer; and depositing... A dielectric spacer layer is coupled to the hard mask layer and the plurality of recessed regions; a first photoresist layer is formed coupled to the dielectric spacer layer; the first photoresist layer is etched back to expose the dielectric spacer layer on top of the hard mask layer; a portion of the dielectric spacer layer on top of the hard mask layer and a portion of the dielectric spacer layer on the sidewalls of the plurality of fins are removed to expose at least a portion of the sidewalls of the plurality of fins; the first photoresist layer is stripped from the dielectric spacer layer; a metal dielectric layer and a gate metal layer are formed coupled to the sidewall portions of the fourth semiconductor layer; a second photoresist layer is formed coupled to the gate metal layer; and so on. Using the second photoresist layer as a mask, the gate metal layer, the metal dielectric layer, and the hard mask layer are etched; a second oxide layer coupled to the gate metal layer and the fourth semiconductor layer is deposited; a third photoresist layer coupled to the second oxide layer is formed; the second oxide layer is etched back and forth using the third photoresist layer as a mask to expose the fourth semiconductor layer; a source metal layer coupled to the fourth semiconductor layer and the second oxide layer is formed; a fourth photoresist layer coupled to the source metal layer is formed; and the second oxide layer is etched using the fourth photoresist layer as a mask to expose the gate metal layer.

[0017] The methods of this invention offer numerous advantages over conventional techniques. For example, embodiments of the invention provide a method for manufacturing a vertical FET device with a marker layer, which improves product quality by precisely controlling the etching depth of the trench used to form the gate layer. In some embodiments of the invention that include semiconductor layers with gradient doping concentrations, by controlling the etching depth into the gradient doped layer, the drain-source on-resistance, threshold voltage, electric field (|E|), and drain-source leakage current can be maintained within desired ranges. These and other embodiments of the invention, along with many advantages and features of the invention, will be described in more detail below in conjunction with the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a partial cross-sectional view showing a vertical FET device manufactured according to an embodiment of the present invention.

[0019] Figures 2A to 2B This is a simplified flowchart illustrating a method for manufacturing a vertical FET device according to an embodiment of the present invention.

[0020] Figures 3A to 3G This is a partial cross-sectional view showing an intermediate stage of a method for manufacturing a vertical FET device according to an embodiment of the present invention.

[0021] Figure 4 This is a partial cross-sectional view showing a vertical FET device manufactured according to another embodiment of the present invention.

[0022] Figures 5A to 5B This is a simplified flowchart illustrating a method for manufacturing a vertical FET device according to an embodiment of the present invention.

[0023] Figures 6A to 6G This is a partial cross-sectional view showing an intermediate stage of a method for manufacturing a vertical FET device according to an embodiment of the present invention.

[0024] Figure 7A This is a partial schematic diagram illustrating a vertical FET device with hypothetical marker layers located at different depths according to an embodiment of the present invention.

[0025] Figure 7B This is a schematic diagram illustrating the doping concentration detected during the etching of a recessed region for the gate layer according to an embodiment of the present invention.

[0026] Figure 7C This is a schematic diagram illustrating the doping concentration detected during the etching of a recessed region for the gate layer according to another embodiment of the present invention.

[0027] Figure 8A This illustrates the threshold voltage (V) of a vertical FET device with a silicon marker layer according to an embodiment of the present invention.TH A schematic diagram of the function of the position of the marker layer.

[0028] Figure 8B This is a schematic diagram illustrating the maximum electric field (Emax) of a vertical FET device with a silicon marker layer according to an embodiment of the present invention as a function of the position of the marker layer.

[0029] Figure 9A This is a 2D cross-sectional drawing showing the magnitude of the electric field (|E|) of a vertical FET device without a marker layer for comparison.

[0030] Figures 9B to 9E This is a 2D cross-sectional drawing illustrating the amplitude of |E| of a vertical FET device having silicon marker layers located at different positions according to an embodiment of the present invention.

[0031] Figure 9F It shows how by, Figures 9A to 9E The overlapping of the cutting lines of the maximum electric field (Emax) shown.

[0032] Figure 10 This is a schematic diagram illustrating the on-state resistance of a vertical FET device having aluminum gallium nitride (AlGaN) marker layers located at different positions, according to an embodiment of the present invention.

[0033] Figure 11A This is a 2D cross-sectional drawing showing the total current density of a vertical FET device without a marker layer for comparison.

[0034] Figures 11B to 11E This is a 2D cross-sectional drawing illustrating the total current density of a vertical FET device with AlGaN marker layers located at different positions, according to an embodiment of the present invention.

[0035] Figures 12A to 12P This is a partial cross-sectional view showing an intermediate stage of a method for manufacturing a vertical FET device according to an embodiment of the present invention.

[0036] Figures 13A to 13C This is a simplified flowchart illustrating a method for manufacturing a vertical FET device according to an embodiment of the present invention.

[0037] Figures 14A to 14P This is a partial cross-sectional view showing an intermediate stage of a method for manufacturing a MOSFET device according to an embodiment of the present invention.

[0038] Figures 15A to 15C This is a simplified flowchart illustrating a method for manufacturing a MOSFET device according to an embodiment of the present invention.

[0039] Figures 16A to 16VThis is a partial cross-sectional view showing an intermediate stage of a method for manufacturing a MOSFET device according to an embodiment of the present invention.

[0040] Figures 17A to 17C This is a simplified flowchart illustrating a method for manufacturing a MOSFET device according to another embodiment of the present invention. Detailed Implementation

[0041] Embodiments of the present invention relate to methods and systems for improving etch depth variation control in semiconductor processing operations. The embodiments of the present invention are applicable to a variety of semiconductor manufacturing operations, including the fabrication of group III nitride semiconductor devices. By way of example only, the embodiments are applied to the fabrication of vertical fin-based FET devices, but the embodiments of the present invention are applicable to a variety of device structures.

[0042] Figure 1 A partial cross-sectional view of a vertical FET device 100 according to an embodiment of the present invention is shown. The vertical FET device 100 may include a semiconductor substrate 102, a first semiconductor layer 104 coupled to the semiconductor substrate 102, and a second semiconductor layer 106 coupled to the first semiconductor layer 104. In one embodiment, the semiconductor substrate 102 may include a group III nitride compound, such as gallium nitride (GaN). In one embodiment, the semiconductor substrate 102 may include heavily n-type doped GaN, which can be used as a drain contact. The doping concentration of the semiconductor substrate 102 may be appropriately varied depending on the specific application. In one embodiment, the doping concentration of the semiconductor substrate 102 may range from about 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 Within the range. In one embodiment, the semiconductor substrate 102 may have a density of less than 0.020 ohm-cm. 3 The resistivity. In one embodiment, the first semiconductor layer 104 may comprise a group III nitride compound, such as GaN. For example, the first semiconductor layer 104 may comprise n-type doped GaN. The doping concentration of the first semiconductor layer 104 may be appropriately varied depending on the specific application. In one embodiment, the doping concentration of the first semiconductor layer 104 may be approximately 1 × 10⁻⁶. 16 atoms / cm 3In one embodiment, the second semiconductor layer 106 may comprise a group III nitride compound, such as GaN. For example, the second semiconductor layer 106 may comprise n-type doped GaN. In one embodiment, the second semiconductor layer 106 is characterized by having a gradient doping concentration between a first side 106a and a second side 106b opposite to the first side 106a. This gradient doping concentration may be appropriately varied depending on the specific application. For example, the gradient doping concentration may be a linear increase from a lower doping concentration at the first side 106a adjacent to the first semiconductor layer 104 to a higher doping concentration at the second side 106b. In one embodiment, the lower doping concentration may be 1 × 10⁻⁶. 16 atoms / cm 3 This higher doping concentration can be 5.5 × 10⁻⁶. 16 atoms / cm 3 In one embodiment, the second semiconductor layer 106 may have a thickness of 0.2 μm.

[0043] The vertical FET device 100 may further include a marker layer 108 deposited on a second semiconductor layer 106, and a third semiconductor layer 110 coupled to the marker layer 108. In one embodiment, the third semiconductor layer 110 may include a group III nitride compound, such as GaN. In one embodiment, the third semiconductor layer 110 is characterized by having a gradient doping concentration between a first side 110a and a second side 110b opposite to the first side 110a. For example, the gradient doping concentration may be a linear increase from a lower doping concentration at the first side 110a adjacent to the marker layer 108 to a higher doping concentration at the second side 110b. In one embodiment, the lower doping concentration may be 5.5 × 10⁻⁶. 16 atoms / cm 3 This higher doping concentration can be 7.5 × 10⁻⁶. 16 atoms / cm 3 In one embodiment, the third semiconductor layer 110 may have a thickness of 0.1 μm. In another embodiment, the third semiconductor layer 110 is characterized by having a uniform doping concentration, for example, 7.5 × 10⁻⁶. 16 atoms / cm 3 In another embodiment, the third semiconductor layer 110 may be omitted from the vertical FET device 100.

[0044] The vertical FET device 100 may further include a plurality of semiconductor fins 112 coupled to a third semiconductor layer 110, and a semiconductor gate layer 114 coupled to a second semiconductor layer 106 and surrounding the semiconductor fins 112. In one embodiment, the semiconductor fins 112 are doped with a concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3Furthermore, it is an n-type doped GaN with a thickness of approximately 0.8 μm. Typically, the semiconductor substrate 102 is more heavily doped than the semiconductor fins 112, which in turn are more heavily doped than the first semiconductor layer 104, the second semiconductor layer 106, or the third semiconductor layer 110. These semiconductor fins 112 can be grouped together as drift layers in a vertical FET device 100. In one embodiment, the semiconductor gate layer 114 has a doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 p-type doped GaN.

[0045] The vertical FET device 100 may further include a source metal layer 116 formed on the plurality of semiconductor fins 112 and a gate metal layer 118 formed on the semiconductor gate layer 114. In some embodiments, the source metal layer 116 may include a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN). In some embodiments, the gate metal layer 118 may include nickel, gold, molybdenum, platinum, palladium, silver, or combinations thereof.

[0046] Figures 2A to 2B This is a simplified flowchart illustrating a method 200 for manufacturing a vertical FET device according to an embodiment of the present invention. (See reference) Figures 2A to 2B Method 200 may include providing a semiconductor substrate (202). In one embodiment, the semiconductor substrate comprises a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a density of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range and has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. Method 200 may include an epitaxially grown first semiconductor layer (204) coupled to a semiconductor substrate (e.g., deposited on a semiconductor substrate). In one embodiment, the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration. In one embodiment, the first semiconductor layer may include n-type doped GaN. The doping concentration of the first semiconductor layer may be about 1 × 10⁻⁶. 16 atoms / cm 3 In one embodiment, the thickness of the first semiconductor layer is between 5 μm and 12 μm.

[0047] Method 200 may further include epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having a first conductivity type (206). In one embodiment, the second semiconductor layer is further characterized by a first gradient doping concentration between a first side and a second side opposite to the first side. In one embodiment, the second semiconductor layer comprises n-type doped GaN, and the first gradient doping concentration begins at a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side adjacent to the first semiconductor layer. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side (e.g., 5.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the thickness of the second semiconductor layer is 0.2 μm.

[0048] Method 200 may further include forming a marker layer (208) coupled to a second semiconductor layer. In one embodiment, the marker layer may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marking layer may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marking layer may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The marking layer contains indium at a metallurgical concentration. In one embodiment, the marking layer may have a thickness ranging from 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer has a thickness of 5 nm.

[0049] Method 200 may further include epitaxially growing a third semiconductor layer coupled to the marker layer, wherein the third semiconductor layer is characterized by having a first conductivity type (210). In another embodiment, the third semiconductor layer is further characterized by a second gradient doping concentration between a first side and a second side opposite to the first side. In one embodiment, the third semiconductor layer may comprise n-type doped GaN, and the second gradient doping concentration begins at a lower doping concentration (e.g., 5.5 × 10⁻⁶) at the first side adjacent to the marker layer. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the thickness of the third semiconductor layer is 0.1 μm.

[0050] Method 200 may further include epitaxially growing a fourth semiconductor layer coupled to the third semiconductor layer, wherein the fourth semiconductor layer is characterized by having a first conductivity type and a second doping concentration (212). In one embodiment, the second doping concentration may be greater than the first doping concentration. In one embodiment, the fourth semiconductor layer may include a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 It is an n-type doped GaN with a thickness of approximately 12 μm.

[0051] Method 200 may further include forming a hard mask layer coupled to a fourth semiconductor layer, wherein the hard mask layer includes a set of openings (214) operable to expose an upper surface portion of the fourth semiconductor layer.

[0052] Method 200 may further include etching a fourth semiconductor layer and a third semiconductor layer using a hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions (216). In one embodiment, the depth of the recessed region 216 is between 0.6 μm and 1.0 μm. In one embodiment, the depth of the recessed region 216 is about 0.8 μm. In one embodiment, each of the plurality of fins may have a width of about 0.2 μm (between the recessed regions).

[0053] refer to Figures 2A to 2B Method 200 may further include etching at least a portion (218) of the marker layer and probing the etching of at least a portion of the marker layer (220). In one embodiment, the probing of the etching process can be performed by standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes in silicon dopant can be readily detected. In another embodiment using an AlGaN layer as the marker layer, the Al doping concentration can be readily detected. In another embodiment using an In-doped layer, the In dopant can be readily detected. In one embodiment, method 200 may stop the etching process when it is detected that the etching process has reached the marker layer. In another embodiment, method 200 may further include etching to penetrate the marker layer, and then continuing to etch a second semiconductor layer using a hard mask layer as a mask for a predetermined time period.

[0054] Method 200 may further include epitaxially growing a fifth semiconductor layer (222) within a plurality of recessed regions. In one embodiment, the fifth semiconductor layer may include a doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3The method then further includes forming a source metal layer (224) coupled to each of the plurality of fins and forming a gate metal layer (226) coupled to a fifth semiconductor layer. In some embodiments, the source metal layer may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN). In some embodiments, the gate metal layer may comprise nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0055] It should be understood that Figures 2A to 2B The specific steps shown provide a particular method for manufacturing a vertical FET device according to an embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, Figures 2A to 2B A single step shown may include multiple sub-steps, which may be executed in various orders suitable for that single step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0056] Return to reference Figures 2A to 2B and reference Figures 3A to 3G The present invention describes a method for manufacturing a vertical FET device 300 according to some embodiments thereof. Figure 3A This is a partial cross-sectional view showing a vertical FET device 300, which has an n+ type doped semiconductor substrate 302, an n-type doped first semiconductor layer 304 epitaxially grown on the semiconductor substrate 302, and an n-type doped second semiconductor layer 306 epitaxially grown on the first semiconductor layer 304. In one embodiment, the second semiconductor layer 306 has a first gradient doping concentration between a first side 306a and a second side 306b opposite to the first side 306a. In one embodiment, the first gradient doping concentration starts from a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side 306a adjacent to the first semiconductor layer 304. 16 atoms / cm 3 The doping concentration increases linearly to a higher concentration at the second side 306b (e.g., 5.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the second semiconductor layer 306 has a thickness of 0.2 μm. A marker layer 308 is deposited on the second semiconductor layer 306. In one embodiment, the marker layer 308 may include a GaN layer incorporating 1 × 10⁻⁶ μm of silicon. 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marker layer 308 may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3The aluminum has a metallurgical concentration. In another embodiment, the marker layer 308 may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The metallurgical concentration of indium. In one embodiment, the marking layer 308 may have a thickness in the range of 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer 308 has a thickness of 5 nm.

[0057] A third semiconductor layer 310 is epitaxially grown on the marker layer 308. In one embodiment, the third semiconductor layer 310 may comprise n-type doped GaN and has a first gradient doping concentration between a first side 310a and a second side 310b opposite to the first side 310a. In one embodiment, the second gradient doping concentration begins at a lower doping concentration (e.g., 5.5 × 10⁻⁶) at the first side 310a adjacent to the marker layer 308. 16 atoms / cm 3 The doping concentration increases linearly to a higher concentration at the second side 310b (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the third semiconductor layer 310 has a thickness of 0.1 μm. In one embodiment, the lower doping concentration within the second graded doping concentration range of the third semiconductor layer 310 (e.g., 5.5 × 10⁻⁶) 16 atoms / cm 3 The doping concentration can be equal to or greater than the higher doping concentration within the first graded doping concentration range of the second semiconductor layer 306 (e.g., 4.5 × 10⁻⁶). 16 atoms / cm 3 ).

[0058] A fourth semiconductor layer 312 is epitaxially grown on the third semiconductor layer 310, wherein the fourth semiconductor layer 312 is characterized by having a first conductivity type and a second doping concentration. In one embodiment, the third semiconductor layer 310 may be omitted from the vertical FET device 300. In such an embodiment, the fourth semiconductor layer 312 is epitaxially grown on the marker layer 308. In one embodiment, the fourth semiconductor layer 312 comprises a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 And it is an n-type doped GaN with a thickness of approximately 0.6 μm to 0.8 μm. In another embodiment, the second doping concentration of the fourth semiconductor layer 312 can be greater than the first doping concentration of the first semiconductor layer 304. In another embodiment, the second doping concentration of the fourth semiconductor layer 312 (e.g., 1.3 × 10⁻⁶) is... 17 atoms / cm 3The doping concentration can be greater than the higher doping concentration within the first graded doping concentration of the second semiconductor layer 306 (e.g., 4.5 × 10⁻⁶). 16 atoms / cm 3 In another embodiment, the second doping concentration of the fourth semiconductor layer 312 (e.g., 1.3 × 10⁻⁶) 17 atoms / cm 3 The doping concentration can be greater than the higher doping concentration within the second graded doping concentration of the third semiconductor layer 310 (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the second doping concentration of the fourth semiconductor layer 312 (e.g., 7.5 × 10⁻⁶) 16 atoms / cm 3 This can be equal to the higher doping concentration within the second graded doping concentration of the third semiconductor layer 310 (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 ).

[0059] refer to Figure 3B A hard mask layer 314 is formed on the fourth semiconductor layer 312. The hard mask layer 314 includes a set of openings 316 operable to expose the upper surface portion 318 of the fourth semiconductor layer 312. (See reference) Figure 3C A hard mask layer 314 is used as a mask to perform an etching process to form a plurality of fins 312a within a fourth semiconductor layer 312. Each fin 312a is separated by one of a plurality of recessed regions 320 formed by the etching process. Figure 3C As shown, the etching process is monitored to detect when the etching process reaches the marker layer 308. In one embodiment, the detection of the etching process reaching the marker layer can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be easily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be easily detected. In another embodiment using an In-doped layer, In dopant can be easily detected. Dopant can be detected when at least a portion of the marker layer 308 is etched. The detection of the etching of the marker layer will be described in detail below.

[0060] During the etching of at least a portion of the marker layer 308, a probing process can be used to detect when the etching process reaches the marker layer 308. In one embodiment, subsequent etching processes can be finely controlled to achieve a predetermined etching depth in the target doped layer. Alternatively, in one embodiment, the etching process can be stopped when the etching process reaches the marker layer 308 or a portion of the marker layer 308. (See reference...) Figure 3DThe subsequent etching process can be timed to achieve an etching depth of 0.1 μm in the second semiconductor layer 306. It should be noted that the etching depth within the second semiconductor layer 306 can be appropriately varied depending on the specific application.

[0061] exist Figure 3D In the embodiment shown, the bottom of fin 312a has an isosceles trapezoidal shape. However, it should be noted that after the etching process, the bottom of fin 312a may have a shape similar to... Figure 3D Different shapes are shown. In this document, embodiments of the invention are described with reference to cross-sectional views illustrating idealized embodiments (and intermediate structures). For clarity, the thicknesses of layers and regions in the figures may be exaggerated. Furthermore, variations in the shapes shown in the figures are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be considered limited to the specific shapes of the regions shown herein, but rather include shape deviations, for example, due to manufacturing processes.

[0062] In one embodiment, after the recessed region 320 is formed, a cleaning process is performed for approximately 30 minutes at a temperature of approximately 85°C using a tetramethylammonium hydroxide (TMAH) solution at a weight ratio of approximately 25%. In another embodiment, a pre-cleaning process may be performed before cleaning with the TMAH solution, which may be, for example, a two-minute piranha cleaning using a 2:1 volume ratio of H₂SO₄:H₂O₂.

[0063] refer to Figure 3E A fifth semiconductor layer 322 is epitaxially regrown inside and outside multiple recessed regions 320. In one embodiment, the upper surface of the fifth semiconductor layer 322 is substantially flush with the upper surface of the semiconductor fin 312a. Figure 3E As shown, the fifth semiconductor layer 322 is coupled to the second semiconductor layer 306. The fifth semiconductor layer 322 provides a gate layer for the vertical FET device 300. In one embodiment, the fifth semiconductor layer 322 may include a doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 p-type doped GaN. (Reference) Figure 3F Then, the hard mask layer 314 is removed from the semiconductor fin 312a.

[0064] refer to Figure 3GA source metal layer 324 is deposited on each fin 312a (i.e., the source metal layer 324 is deposited to couple to the fourth semiconductor layer 312). Then, a gate metal layer 326 is deposited on the fifth semiconductor layer 322. In some embodiments, the source metal layer 324 may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN). In some embodiments, the gate metal layer 326 may comprise nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0065] Figure 4 This is a partial cross-sectional view showing a vertical FET device 400 manufactured according to another embodiment of the present invention. The differences between the vertical FET device 100 and the vertical FET device 400 are indicated by the location of the marking layer. Specifically, the vertical FET device 400 may include a semiconductor substrate 402, a first semiconductor layer 404 coupled to the semiconductor substrate 402, and a second semiconductor layer 406 coupled to the first semiconductor layer 404. In one embodiment, the semiconductor substrate 402 may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate 402 may include heavily n-type doped GaN, which can be used as a drain contact. The doping concentration of the semiconductor substrate 402 may be appropriately varied depending on the specific application. In one embodiment, the doping concentration of the semiconductor substrate 402 may be from about 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 Within the range. In one embodiment, the semiconductor substrate 402 may have a density of less than 0.020 ohm-cm. 2 The resistivity. In one embodiment, the first semiconductor layer 404 may comprise a group III nitride compound, such as GaN. For example, the first semiconductor layer 404 may comprise n-type doped GaN. The doping concentration of the first semiconductor layer 404 may be appropriately varied depending on the specific application. In one embodiment, the doping concentration of the first semiconductor layer 404 may be approximately 1 × 10⁻⁶. 16 atoms / cm 3 In one embodiment, the first semiconductor layer 404 has a thickness of approximately 5 μm to 12 μm. In one embodiment, the second semiconductor layer 406 may comprise a group III nitride compound, such as GaN. For example, the second semiconductor layer 406 may comprise n-type doped GaN. In one embodiment, the second semiconductor layer 406 is characterized by a gradient doping concentration between a first side 406a and a second side 406b opposite to the first side 406a. For example, the gradient doping concentration linearly increases from a lower doping concentration at the first side 406a adjacent to the first semiconductor layer 404 to a higher doping concentration at the second side 406b. In one embodiment, the lower doping concentration may be 1 × 10⁻⁶.16 atoms / cm 3 This higher doping concentration can be 7.5 × 10⁻⁶. 16 atoms / cm 3 In one embodiment, the second semiconductor layer 406 may have a thickness of 0.3 μm.

[0066] The vertical FET device 400 may further include a third semiconductor layer 408 epitaxially grown on the second semiconductor layer 406 and a marker layer 410 formed on the third semiconductor layer 408. In one embodiment, the third semiconductor layer 408 may include a group III nitride compound, such as GaN. For example, the third semiconductor layer 408 may include n-type doped GaN. In one embodiment, the doping concentration of the third semiconductor layer 408 may be 7.5 × 10⁻⁶. 16 atoms / cm 3 In another embodiment, the third semiconductor layer 408 may be omitted from the vertical FET device 400. In such a case, the marker layer 410 is formed directly on the second semiconductor layer 406.

[0067] The vertical FET device 400 may further include a plurality of semiconductor fins 412 coupled to a marker layer 410, and a semiconductor gate layer 414 coupled to a second semiconductor layer 406 and surrounding the semiconductor fins 412. In one embodiment, the semiconductor fins 412 are n-type doped GaN with a doping concentration of 1.3 × 10¹⁷ atoms / cm³ and a thickness of about 0.6 μm to 0.8 μm. Typically, the semiconductor substrate 402 is more heavily doped than the semiconductor fins 412, and the semiconductor fins 412 are more heavily doped than the first semiconductor layer 404, the second semiconductor layer 406, or the third semiconductor layer 408. These semiconductor fins 412 may be grouped as drift layers in the vertical FET device 400. In one embodiment, the semiconductor gate layer 414 is doped with a doping concentration of 1 × 10¹⁷ atoms / cm³. 19 atoms / cm 3 p-type doped GaN.

[0068] The vertical FET device 400 may further include a source metal layer 416 formed on the plurality of semiconductor fins 412 and a gate metal layer 418 formed on the semiconductor gate layer 414. In some embodiments, the source metal layer 416 may include a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN). In some embodiments, the gate metal layer 418 may include nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0069] Figures 5A to 5B This is a simplified flowchart illustrating a method 500 for manufacturing a vertical FET device according to an embodiment of the present invention. (See reference) Figures 5A to 5BMethod 500 may include providing a semiconductor substrate (502). In one embodiment, the semiconductor substrate may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a density of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range and has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. The first semiconductor layer is epitaxially grown on or coupled to the semiconductor substrate (504). In one embodiment, the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration. In one embodiment, the first semiconductor layer may include a doping concentration of about 1 × 10⁻⁶. 16 atoms / cm 3 n-type doped GaN.

[0070] Method 500 may further include epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having a first conductivity type (506). In one embodiment, the second semiconductor layer is further characterized by a gradient doping concentration between a first side and a second side opposite to the first side. In one embodiment, the second semiconductor layer comprises n-type doped GaN, and the gradient doping concentration begins at a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side adjacent to the first semiconductor layer. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the thickness of the second semiconductor layer is 0.3 μm.

[0071] Method 500 may further include epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having a first conductivity type (508). In one embodiment, the third semiconductor layer may include a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 The third semiconductor layer is n-type doped GaN. In one embodiment, the doping concentration of the third semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In another embodiment, the doping concentration of the third semiconductor layer (e.g., 1.3 × 10⁻⁶) is... 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3In some embodiments, the thickness of the third semiconductor layer is between about 0.1 μm and 0.3 μm.

[0072] Method 500 may further include forming a marker layer (510) coupled to a third semiconductor layer. In one embodiment, the marker layer may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marking layer may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marking layer may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The marking layer contains indium at a metallurgical concentration. In one embodiment, the marking layer may have a thickness ranging from 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer has a thickness of 5 nm.

[0073] Method 500 may further include epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having a first conductivity type and a second doping concentration (512). In one embodiment, the second doping concentration of the fourth semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In one embodiment, the fourth semiconductor layer may include a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 And it is an n-type doped GaN with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the second doping concentration of the fourth semiconductor layer (e.g., 1.3 × 10⁻⁶) 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 ).

[0074] Method 500 may further include forming a hard mask layer coupled to a fourth semiconductor layer, wherein the hard mask layer includes a set of openings (514) operable to expose an upper surface portion of the fourth semiconductor layer.

[0075] Method 500 may further include etching a fourth semiconductor layer to form a plurality of fins by using a hard mask layer as a mask, wherein each of the plurality of fins is separated by one of a plurality of recessed regions (516). In one embodiment, the depth of the recessed region is between 0.6 μm and 1.0 μm. In one embodiment, the depth of the recessed region is about 0.8 μm. In one embodiment, each of the plurality of fins may have a width of about 0.2 μm (between the recessed regions).

[0076] refer to Figures 5A to 5B Method 500 may further include etching at least a portion (518) of the marker layer and probing the etching of at least a portion of the marker layer (520). In one embodiment, the probing process may be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be readily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be readily detected. In one embodiment, method 500 may stop etching when it is detected that the etching process has reached the marker layer. In another embodiment, method 500 may further include etching to penetrate the marker layer, and then using a hard mask layer as a mask to continue etching a third semiconductor layer and / or a second semiconductor layer for a predetermined time period.

[0077] Method 500 may further include epitaxially growing a fifth semiconductor layer (522) within a plurality of recessed regions. In one embodiment, the fifth semiconductor layer may include a doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 The method 500 may further include forming a source metal layer (524) coupled to each of the plurality of fins and forming a gate metal layer (526) coupled to a fifth semiconductor layer. In some embodiments, the source metal layer may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN). In some embodiments, the gate metal layer may comprise nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0078] It should be understood that Figures 5A to 5B The specific steps shown provide a particular method for manufacturing a vertical FET device according to an embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, Figures 5A to 5B A single step shown may include multiple sub-steps, which may be executed in various orders suitable for that single step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0079] Return to reference Figures 5A to 5B and reference Figures 6A to 6G A method for manufacturing a vertical FET device 600 according to an embodiment of the present invention is described. Figure 6A This is a partial cross-sectional view showing a vertical FET device 300, which has an n+ type doped semiconductor substrate 602, an n-type doped first semiconductor layer 604 epitaxially grown on the semiconductor substrate 602, and an n-type doped second semiconductor layer 606 epitaxially grown on the first semiconductor layer 604. In one embodiment, the first semiconductor layer 604 has a 1×10⁻⁶ Ω·cm². 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 606 has a gradient doping concentration between a first side 606a and a second side 606b opposite to the first side 606a. In one embodiment, the gradient doping concentration starts from a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side 606a adjacent to the first semiconductor layer 604. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side 606b (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the second semiconductor layer 606 has a thickness of 0.3 μm.

[0080] A third semiconductor layer 608 is epitaxially grown on the second semiconductor layer 606. The third semiconductor layer 608 is characterized by having a first conductivity type. In one embodiment, the doping concentration of the third semiconductor layer 608 is greater than the doping concentration of the first semiconductor layer 604. In one embodiment, the third semiconductor layer 608 comprises a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 n-type doped GaN.

[0081] A marker layer 610 is deposited on the third semiconductor layer 608. In one embodiment, the marker layer 610 may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marker layer 610 may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marker layer 610 may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3The metallurgical concentration of indium. In one embodiment, the marking layer 610 may have a thickness in the range of 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer 610 has a thickness of 5 nm. In one embodiment, the vertical FET device 600 may omit the third semiconductor layer 608. In such an embodiment, the marking layer 610 is deposited directly on the second semiconductor layer 606.

[0082] A fourth semiconductor layer 612 is epitaxially grown on the marker layer 610. In one embodiment, the fourth semiconductor layer 612 comprises a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 Furthermore, the GaN is an n-type doped layer with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the doping concentration of the fourth semiconductor layer 612 is greater than the doping concentration of the first semiconductor layer 604. In another embodiment, the doping concentration of the fourth semiconductor layer 612 is greater than the higher doping concentration within the gradient doping concentration range of the second semiconductor layer 606. In yet another embodiment, the doping concentration of the fourth semiconductor layer 612 is equal to or greater than the doping concentration of the third semiconductor layer 608.

[0083] refer to Figure 6B A hard mask layer 614 is formed on the fourth semiconductor layer 612. The hard mask layer 614 includes a set of openings 616 operable to expose the upper surface portion 618 of the fourth semiconductor layer 612. (See reference) Figure 6C A hard mask layer 614 is used as a mask to perform an etching process to form a plurality of fins 612a within a fourth semiconductor layer 612. Each fin 612a is separated by a recessed region 320 of a plurality of recessed regions 620 formed by the etching process. Figure 6C As shown, the etching process is monitored to detect when the etching process reaches the marker layer 610. In one embodiment, the detection process can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes in the silicon dopant can be easily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be easily detected. In another embodiment using an In-doped layer, In dopant can be easily detected. The detection of the etching process reaching the marker layer will be described in detail below.

[0084] During the etching of at least a portion of the marker layer 610, a probing process is used to detect when the etching process reaches the marker layer 610. In one embodiment, subsequent etching processes can be finely controlled to achieve a predetermined etching depth in the target doped layer. (Reference) Figure 6DSubsequent etching can be timed to achieve an etching depth of 0.1 μm in the second semiconductor layer 606. It should be noted that the etching depth within the second semiconductor layer 606 can be appropriately varied depending on the specific application. In another embodiment, subsequent etching can be timed to achieve an etching depth (e.g., 0.2 μm) in the third semiconductor layer 608. In another embodiment, the etching process can be stopped once it is detected that the etching process has reached the marker layer 610.

[0085] In one embodiment, after the depression area is formed, a cleaning process is performed for approximately 30 minutes at a temperature of approximately 85°C using a TMAH solution at a weight ratio of approximately 25%. In another embodiment, a pre-cleaning process may be performed before cleaning with the TMAH solution, which may be, for example, a two-minute peroxysulfuric acid cleaning using a 2:1 volume ratio of H2SO4:H2O2.

[0086] refer to Figure 6E A fifth semiconductor layer 622 is epitaxially grown inside and outside multiple recessed regions 620. In one embodiment, the upper surface of the fifth semiconductor layer 622 is substantially flush with the upper surface of the fourth semiconductor layer 612 (i.e., the upper surface of the fin 612a). Figure 6E As shown, the fifth semiconductor layer 622 is coupled to the second semiconductor layer 606. The fifth semiconductor layer 622 provides a gate layer for the vertical FET device 600. In one embodiment, the fifth semiconductor layer 622 may include a doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 p-type doped GaN. (Reference) Figure 6F Then the hard mask layer 614 is removed from fin 612a (i.e., from the fourth semiconductor layer 612).

[0087] refer to Figure 6G A source metal layer 624 is deposited on each fin 612a (i.e., on the fourth semiconductor layer 612). Then, a gate metal layer 626 is deposited on the fifth semiconductor layer 622. In some embodiments, the source metal layer 624 may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN). In some embodiments, the gate metal layer 626 may comprise nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0088] In the fabrication of vertical FET devices, controlling the etching depth can be crucial to meeting the electrical performance requirements of these devices. For example, etching multiple recessed areas (e.g., Figure 3C One objective of the recessed region 320 shown is in the target doped layer (e.g., Figure 3DThe etching process is completed within the second semiconductor layer 306 shown. Because the drift layer (e.g., the second semiconductor layer 306) with a low doping concentration is exposed to the gate layer (e.g., p-type doped), the etching process is performed within this layer. Figure 3G The depletion caused by the fifth semiconductor layer 322 shown, and over-etching will lead to a series of gate effects. Under-etching will cause fins with higher doping concentrations (e.g., Figure 3G The fin 312a shown extends into the drift layer (e.g., Figure 3G In the second semiconductor layer 306 shown, this results in the gate layer (e.g., Figure 3G The high electric field (|E|) at the interface between the fifth semiconductor layer 322 and the drift layer (e.g., the third semiconductor layer 310) shown.

[0089] Figure 7A This is a partial schematic diagram illustrating a vertical FET device 700 having hypothetical marker layers 708 located at different depths according to an embodiment of the present invention. Figure 7A As shown, the vertical FET device 700 includes an n+ type GaN substrate 702, a drift layer including an n-type GaN layer 704, and a doping concentration of approximately 1 × 10⁻⁶. 16 atoms / cm 3 To approximately 1×10 17 atoms / cm 3 A graded n-type GaN layer 706 with a doping concentration of approximately 1 × 10⁻⁶ within the range of [missing information]. 17 atoms / cm 3 The vertical FET device 700 includes an n-type GaN fin 712, a p-type GaN gate layer 722, a source metal layer 724, and a gate metal layer 727. The vertical FET device 700 includes a marker layer 708 located at different depths for varying degrees. In one embodiment, the marker layer 708 includes a doping concentration of approximately 1 × 10⁻⁶. 19 atoms / cm 3 The silicon layer.

[0090] exist Figure 7A In the embodiment shown, for simplicity of description, the bottom of fin 712 is rectangular. Figure 7A In the diagram, position "0" indicates the upper surface of fin 712; position "0.8" indicates that marker layer 708 is located at the bottom of gate layer 722, i.e., 0.8 μm below the upper surface of fin 712; position "0.7" indicates that marker layer 708 is located at the top of gradient n-type GaN layer 706, i.e., 0.7 μm below the upper surface of fin 712; positions "0.6" and "0.5" indicate that marker layer 708 is located 0.1 μm and 0.2 μm above gradient n-type GaN layer 706, respectively. It should be noted that, for clarity, the thickness of layers and regions in the figure may be exaggerated.

[0091] Figure 7B This is a schematic diagram showing the doping concentration detected during the etching of the recessed region for gate layer 722. Figure 7B In the example shown, the marker layer 708 is located at the "0.7" position (i.e., on top of the gradient n-type GaN layer 706). Figure 7B In the coordinate system shown, the horizontal axis represents the etching depth starting from the upper surface of fin 712, and the vertical axis represents the logarithm of the detected doping concentration (LogNd). Figure 7B As shown, LogNd remains at approximately 17 as the etching process proceeds until it reaches marker layer 708, where LogNd increases to approximately 19. Thereafter, LogNd decreases as the etching process continues within the gradient n-shaped GaN layer 706.

[0092] Figure 7C This is a schematic diagram illustrating the doping concentration detected during the etching of the recessed region for gate layer 722. Figure 7B Compared to the embodiments shown, in Figure 7C The marker layer 708 used in the illustrated embodiment comprises an Al doping concentration of 1.7 × 10⁻⁶. 17 atoms / cm 3 AlGaN. And in Figure 7B The coordinate system shown is similar, with the horizontal axis representing the etching depth starting from the upper surface of fin 712, and the vertical axis representing LogNd. (As shown...) Figure 7C As shown, LogNd remains low as the etching process proceeds until it reaches the marker layer 708, where LogNd increases to approximately 17. Thereafter, LogNd decreases to a low level as the etching process continues within the gradient n-shaped GaN layer 706.

[0093] Figure 8A This illustrates the threshold voltage (V) of a vertical FET device 700 with a silicon marker layer. TH A schematic diagram illustrating the function of the marker layer's position. Figure 8A In the coordinate system shown, the horizontal axis represents the position of the marker layer starting from the upper surface of fin 712 (represented by "0"), and the vertical axis represents the V-axis perpendicular to FET device 700. TH .exist Figure 8A In contrast, the V of the vertical FET device without a marker layer is compared. TH It is shown as the baseline (reference). Figure 8A As shown, the V of the vertical FET device 700 TH The number of marker layers increases gradually with their position. In some embodiments, references are used. Figures 2A to 2B The described detection process can detect the V of the vertical FET device 700.TH The predetermined threshold has been exceeded. For example, for the marker layer located at the "0.7" position, the V of the vertical FET device... TH It is 1.17. When V is detected TH When the value exceeds 1.17, it indicates that the etching process has reached the marker layer 708.

[0094] Figure 8B This is a schematic diagram illustrating the maximum electric field (Emax) of a vertical FET device 700 with a silicon marker layer as a function of the marker layer's location. Figure 8B In the coordinate system shown, the horizontal axis represents the position of the marking layer 708 starting from the upper surface of the fin 712 (represented by "0"), and the vertical axis represents the Emax measured at a voltage of 1200V. Figure 8B In the comparison, the Emax of the vertical FET device without a marker layer is shown as the baseline (reference). Figure 8B As shown, the Emax of the vertical FET device 700 gradually increases with the position of the marker layer. In some embodiments, when the Emax of the vertical FET device 700 exceeds a predetermined threshold, a reference... Figures 2A to 2B The described probing process is capable of detecting this. For example, for the marker layer located at the "0.7" position, the Emax of the vertical FET device 700 is 3.09. When an Emax exceeding 3.09 is detected, it indicates that the etching process has reached the marker layer 708.

[0095] Using embodiments of the present invention, a series of device fabrication runs can be performed to manufacture a series of FET devices with different etching process conditions. By analyzing and characterizing the V of the FET devices... TH And / or Emax, analysis can be performed to determine the V that causes the FET device to have a value less than a predetermined threshold. TH And / or the FET device has etching process conditions where the Emax is less than another predetermined threshold.

[0096] Figure 9A This is a 2D cross-sectional drawing showing the magnitude of |E| of a vertical FET device without a marker layer for comparison. Figures 9B to 9E This is a 2D cross-sectional drawing showing the magnitude of |E| of a vertical FET device 700 with silicon marker layers 708 located at different positions. The |E| of the vertical FET device and the |E| of the vertical FET device 700 are compared in V... DS =1200V and V GS Measured at 0V. Figure 9B The |E| of a vertical FET device 700 with a marker layer 708 located at the “0.5” position is shown; Figure 9C The |E| of a vertical FET device 700 with a marker layer 708 located at the “0.6” position is shown; Figure 9D The |E| of a vertical FET device 700 with a marker layer 708 located at the "0.7" position is shown; and, Figure 9E The |E| of a vertical FET device 700 with a marker layer 708 located at the "0.8" position is shown. Figures 9A to 9E In the middle, the upper left region represents the gate region (e.g., Figure 7A The gate layer 722 shown in the diagram, with the upper right region representing a fin (e.g., Figure 7A The fin shown is 712), while the bottom area represents the drift area (e.g., Figure 7A The gradient n-type GaN layer 706 shown in the figure. Figures 9A to 9E The Emax value appears near the boundary between the gate region and the drift region close to the fin, and is represented by ellipse 902. It can be seen that the Emax deteriorates as the marker layer moves closer to the drift region. Figure 9F It shows how by, Figures 9A to 9E The overlapping of the cut lines of Emax is shown. From Figure 9F It can be seen that the vertical FET device 700 with the marker layer located at the "0.8" position has the worst Emax.

[0097] Using embodiments of the present invention, a series of device fabrication runs can be performed to manufacture a series of FET devices with marker layers located at different depths. By analyzing the amplitude of |E| characterizing the FET devices, an analysis can be performed to evaluate the impact of the marker layers on the FET device performance. Based on this evaluation, the depth of the marker layers can be adjusted to retain the benefits provided by the marker layers while controlling the quality of the FET devices.

[0098] Figure 10 This is a schematic diagram illustrating the simulated on-state resistance of a vertical FET device 700 with AlGaN marker layers 708 located at different positions. Figure 10 In the coordinate system shown, the horizontal axis represents the position of the marking layer 708 starting from the upper surface of the fin 712 (represented by "0"), and the vertical axis represents the position of the marking layer 708 starting from the upper surface of the fin 712. D The on-state resistance of a vertical FET device 700 measured at 20A. Figure 10 In the comparison, the on-state resistance of a vertical FET device without a marker layer is shown as a baseline (reference). Figure 10 As shown, the on-state resistance of the vertical FET device 700 with the AlGaN marker layer 708 is typically greater than that of the comparative vertical FET device, and gradually decreases with increasing marker layer depth.

[0099] Using embodiments of the present invention, a series of device fabrication runs can be performed to manufacture a series of FET devices with different etching process conditions. By analyzing the on-state resistance characterizing the FET devices, analysis can be performed to determine the etching process conditions that cause the FET devices to have an on-state resistance greater than a predetermined threshold.

[0100] Figure 11A This is a 2D cross-sectional drawing showing the total current density of a vertical FET device without a marker layer for comparison. Figures 11B to 11E This is a 2D cross-sectional drawing showing the total current density of a vertical FET device 700 with AlGaN marker layers 708 located at different positions. The total current density of the vertical FET device and the total current density of the vertical FET device 700 are compared in I... D Measured at 2A. Figure 11B The total current density of a vertical FET device 700 with a marker layer 708 located at the “0.5” position is shown; Figure 11C The total current density of a vertical FET device 700 with a marker layer 708 located at the “0.6” position is shown; Figure 11D The total current density of a vertical FET device 700 with a marker layer 708 located at the "0.7" position is shown; and, Figure 11E The total current density of a vertical FET device 700 with a marker layer 708 located at the "0.8" position is shown. Figures 11A to 11E In the middle, the upper left region represents the gate region (e.g., Figure 7A The gate layer 722 shown in the diagram, with the upper right region representing a fin (e.g., Figure 7A The fin shown is 712), while the bottom area represents the drift area (e.g., Figure 7A The gradient n-type GaN layer 706 shown in the figure. Figures 11A to 11C and Figure 11E The maximum total current density occurs near the boundary between the fin and the drift region, and is represented by ellipse 1102. Figure 11D In the figure, the maximum total current density appears below the boundary between the fin and the drift region. It can be seen that the on-state resistance of the vertical FET device 700 with the marker layer 708 is significantly increased compared to the vertical FET device without the marker layer in the comparison.

[0101] Using embodiments of the present invention, a series of device fabrication runs can be performed to manufacture a series of FET devices with marker layers located at different depths. By analyzing and characterizing the total current density of the FET devices, analyses can be performed to evaluate the impact of the marker layers on the FET device performance. Based on this evaluation, the depth of the marker layers can be adjusted to retain the benefits provided by the marker layers while controlling the quality of the FET devices.

[0102] refer to Figures 12A to 12PThis paper describes a method for manufacturing a vertical junction field-effect transistor (JFET) device 1200 according to an embodiment of the present invention. Figure 12A This is a partial cross-sectional view of a vertical JFET device 1200 showing an n+ type doped semiconductor substrate 1202. In one embodiment, the semiconductor substrate may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a doped structure of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range specified. In one embodiment, the substrate has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. Reference Figure 12B An n-type doped first semiconductor layer 1204 is epitaxially grown on a semiconductor substrate 1202. In one embodiment, the first semiconductor layer 1204 is a GaN layer. (Reference) Figure 12C An n-type doped second semiconductor layer 1206 is epitaxially grown on the first semiconductor layer 1204. In one embodiment, the second semiconductor layer 1206 is a GaN layer. In one embodiment, the first semiconductor layer 1204 has a 1×10⁻⁶ diameter. 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 1206 has a doping concentration of 7.5 × 10⁻⁶. 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 1206 has a gradient doping concentration between a first side 1206a and a second side 1206b opposite to the first side 1206a. In one embodiment, the gradient doping concentration starts from a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side 1206a adjacent to the first semiconductor layer 1204. 16 atoms / cm 3 The doping concentration increases linearly to a higher concentration (e.g., 7.5 × 10⁻⁶) at the second side 1206b. 16 atoms / cm 3 In one embodiment, the second semiconductor layer 1206 has a thickness of 0.3 μm.

[0103] refer to Figure 12D A third semiconductor layer 1208 is epitaxially grown on the second semiconductor layer 1206. The third semiconductor layer 1208 is characterized by having a first conductivity type. In one embodiment, the doping concentration of the third semiconductor layer 1208 is greater than the doping concentration of the first semiconductor layer 1204. In one embodiment, the third semiconductor layer 1208 comprises a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm3 n-type doped GaN.

[0104] refer to Figure 12E The marker layer 1210 is coupled to the third semiconductor layer 1208 (e.g., deposited on the third semiconductor layer 1208). In one embodiment, the marker layer 1210 may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marker layer 1210 may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marker layer 1210 may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The metallurgical concentration of indium. In one embodiment, the marking layer 1210 may have a thickness in the range of 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer 1210 has a thickness of 5 nm. In one embodiment, the third semiconductor layer 1208 may be omitted from the vertical JFET device 1200. In such an embodiment, the marking layer 1210 may be deposited directly on the second semiconductor layer 1206.

[0105] refer to Figure 12F A fourth semiconductor layer 1212 is epitaxially grown on the marker layer 1210. In one embodiment, the fourth semiconductor layer 1212 comprises a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 The GaN is an n-type doped layer with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the doping concentration of the fourth semiconductor layer 1212 is greater than the doping concentration of the first semiconductor layer 1204. In another embodiment, the doping concentration of the fourth semiconductor layer 1212 is greater than the higher doping concentration within the gradient doping concentration range of the second semiconductor layer 1206. In yet another embodiment, the doping concentration of the fourth semiconductor layer 1212 is equal to or greater than the doping concentration of the third semiconductor layer 1208.

[0106] refer to Figure 12G A hard mask layer 1214 is formed on the fourth semiconductor layer 1212. The hard mask layer 1214 includes a set of openings 1215 operable to expose an upper surface portion 1217 of the fourth semiconductor layer 1212. (See reference) Figure 12HAn etching process is performed using a hard mask layer 1214 as a mask to form a plurality of fins 1212a within a fourth semiconductor layer 1212. Each fin 1212a is separated by a recessed region 320 of a plurality of recessed regions 1220 formed by the etching process. Figure 12H As shown, the etching process is monitored to detect when the etching process reaches the marker layer 1210. In one embodiment, the etching process is monitored to detect etching of at least a portion of the marker layer 1210. In one embodiment, the detection process can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be easily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be easily detected. In another embodiment using an In-doped layer, In dopant can be easily detected.

[0107] For clarity, in the following examples, the etching process can be stopped once it is detected that the etching process has reached the marker layer 1210. Those skilled in the art will understand that the invention is not limited to these examples. As referenced above... Figure 6D The etching process can be precisely controlled to achieve a predetermined etching depth in the target doped layer. For clarity of description and illustration, the following examples are described using a single recessed region 1220 or a single fin 1212a. Those skilled in the art will understand that, unless explicitly stated otherwise, the descriptions relating to a single recessed region 1220 or a single fin 1212a apply equally to all recessed regions 1220 or fins 1212a.

[0108] In one embodiment, after the depression area is formed, a cleaning process is performed for approximately 30 minutes at a temperature of approximately 85°C using a TMAH solution at a weight ratio of approximately 25%. In another embodiment, a pre-cleaning process may be performed before cleaning with the TMAH solution, which may be, for example, a two-minute peroxysulfuric acid cleaning using a 2:1 volume ratio of H2SO4:H2O2.

[0109] refer to Figure 12I A dielectric spacer layer 1216 is disposed on the hard mask layer 1214 and the plurality of recessed regions 1220. In one embodiment, the dielectric spacer layer 1216 is deposited as a conformal coating on the sidewalls of the hard mask layer 1214 and the fins 1212a. For example, as Figure 12IAs shown, the dielectric spacer layer 1216 may include a first portion 1216a on top of the hard mask layer 1214, a second portion 1216b conformally to the sidewalls of the plurality of fins 1212a, and a third portion 1216c coupled to the plurality of recessed regions 1220. In some embodiments, the dielectric spacer layer 1216 may include titanium oxide (TiOx). In some embodiments, the dielectric spacer layer 1216 may be deposited using a thermal atomic layer deposition (ALD) process. In some embodiments, the dielectric spacer layer 1216 may include silicon nitride, aluminum silicon nitride, or silicon dioxide.

[0110] In some embodiments, the dielectric spacer layer 1216 may have a thickness in the range of about 3 nm to 8 nm.

[0111] refer to Figure 12J A first photoresist layer 1218 is formed on the dielectric spacer layer 1216. In some embodiments, the photoresist layer 1218 is disposed on a first portion 1216a and a second portion 1216b of the dielectric spacer layer 1216. A third portion 1216c in the recessed region 1220 is exposed.

[0112] In some embodiments, the first photoresist layer 1218 protects the portion of the dielectric spacer layer 1216 disposed on the fin 1212a and the hard mask layer 1214 from subsequent processing.

[0113] refer to Figure 12K Using a first photoresist layer 1218 as a mask, an etching process is performed in the recessed region 1220 to remove the dielectric spacer layer 1216 within the recessed region 1220. The etching process then continues to remove a portion of the marker layer 1210 within the recessed region 1220 and stops in the third semiconductor layer 1208. In some embodiments, the etching process is monitored to detect when the etching process reaches the marker layer 1210, and subsequent etching processes can then be finely controlled to achieve a predetermined etching depth in the third semiconductor layer 1208. For example, subsequent etching can be timed to achieve an etching depth of 0.1 μm in the third semiconductor layer 1208. In some embodiments, subsequent etching processes can be finely controlled to stop at the upper surface of the third semiconductor layer 1208. In some embodiments, the photoresist layer 1218 is omitted and the etching process removes portions 1216a and 1216c of the dielectric spacer layer 1216, leaving only portion 1216b on the sidewall of the fin 1212a.

[0114] refer to Figure 12LAn ion implantation process is performed in multiple recessed regions 1220 to implant p-type dopant into a second semiconductor layer 1206 within the multiple recessed regions 1220. In some embodiments, the ion implantation process also implants p-type dopant into a third semiconductor layer 1208. In some embodiments, multiple tilt angles are used to perform ion implantation so that p-type dopant is also implanted into the sidewalls of the fin 1212a. In some embodiments, ion implantation is performed before etching the dielectric spacer layer 1216. In some embodiments, the ion implantation is annealed (e.g., by a rapid thermal annealing process) before etching the dielectric spacer layer 1216. After the ion implantation process, a gate region 1222 is formed in the third semiconductor layer 1208 and the second semiconductor layer 1206 within the recessed regions 1220. In some embodiments, the gate region 1222 extends upward to the sidewalls of the fin 1212a. In some embodiments, the p-type dopant may include boron, aluminum, or indium, etc. After the gate region 1222 is formed, the first photoresist layer 1218 is removed.

[0115] refer to Figure 12M A gate metal layer 1226 is formed on a gate region 1222 within a plurality of recessed regions 1220. In some embodiments, the gate metal layer 1226 may include nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0116] refer to Figure 12N A second photoresist layer 1228 is formed on the gate metal layer 1226 within a plurality of recessed regions 1220. In one embodiment, the second photoresist layer 1228 is formed conformally to the sidewall of the fin 1212a and exposes the upper portion of the dielectric spacer layer 1216 on the top of the fin 1212a. In some embodiments, the second photoresist layer 1228 can protect the gate metal layer 1226 from subsequent processing.

[0117] refer to Figure 12O An etching process is performed using a second photoresist layer 1228 as a mask to remove the dielectric spacer layer 1216 and the hard mask layer 1214, and the etching process stops on the fourth semiconductor layer 1212. In some embodiments, the etching process removes a portion 1216a of the first portion 1216a of the dielectric spacer layer 1216, a portion of the hard mask layer 1214, and a portion 1216b of the second portion 1216 of the dielectric spacer layer 1216 on top of the fin 1212a. After the etching process, the upper part of the fin 1212a is exposed. After the etching process, the second photoresist layer 1228 is removed.

[0118] refer to Figure 12PA source metal layer 1224 is formed on the fourth semiconductor layer 1212. Specifically, the source metal layer 1224 is formed on the upper part of the fin 1212a. In some embodiments, the source metal layer 1224 may include a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN).

[0119] Figures 13A to 13C This is a simplified flowchart illustrating a method 1300 for manufacturing a vertical JFET device according to an embodiment of the present invention. (See reference) Figures 13A to 13C Method 1300 may include providing a semiconductor substrate (1302). In one embodiment, the semiconductor substrate may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a density of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range and has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. The first semiconductor layer is epitaxially grown to be coupled to the semiconductor substrate (i.e., grown on the semiconductor substrate) (1304). In one embodiment, the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration. In one embodiment, the first semiconductor layer may include a doping concentration of about 1 × 10⁻⁶. 16 atoms / cm 3 n-type doped GaN.

[0120] Method 1300 may further include epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having a first conductivity type (1306). In one embodiment, the second semiconductor layer is further characterized by a gradient doping concentration between a first side and a second side opposite to the first side. In one embodiment, the second semiconductor layer comprises n-type doped GaN, and the gradient doping concentration begins at a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side adjacent to the first semiconductor layer. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the thickness of the second semiconductor layer is 0.3 μm.

[0121] Method 1300 may further include epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having a first conductivity type (1308). In one embodiment, the third semiconductor layer may include a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm3 The third semiconductor layer is n-type doped GaN. In one embodiment, the doping concentration of the third semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In another embodiment, the doping concentration of the third semiconductor layer (e.g., 1.3 × 10⁻⁶) is... 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 In some embodiments, the thickness of the third semiconductor layer is between about 0.1 μm and 0.3 μm.

[0122] Method 1300 may further include forming a marker layer (1310) coupled to a third semiconductor layer. In one embodiment, the marker layer may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marking layer may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marking layer may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The marking layer contains indium at a metallurgical concentration. In one embodiment, the marking layer may have a thickness ranging from 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer has a thickness of 5 nm.

[0123] Method 1300 may further include epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having a first conductivity type and a second doping concentration (1312). In one embodiment, the second doping concentration of the fourth semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In one embodiment, the fourth semiconductor layer may include a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 And it is an n-type doped GaN with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the second doping concentration of the fourth semiconductor layer (e.g., 1.3 × 10⁻⁶) 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 ).

[0124] Method 1300 may further include forming a hard mask layer coupled to a fourth semiconductor layer, wherein the hard mask layer includes a set of openings (1314) operable to expose an upper surface portion of the fourth semiconductor layer.

[0125] Method 1300 may further include etching a fourth semiconductor layer to form a plurality of fins by using a hard mask layer as a mask, wherein each of the plurality of fins is separated by one of a plurality of recessed regions (1316). In one embodiment, each of the plurality of fins may have a thickness of about 0.8 μm.

[0126] Method 1300 may further include etching at least a portion (1318) of the marker layer and probing the etching of at least a portion of the marker layer (1320). In one embodiment, the probing process may be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be readily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be readily detected. In one embodiment, method 1300 may stop etching when it is detected that the etching process has reached the marker layer. In another embodiment, method 1300 may further include etching to penetrate the marker layer, and then using a hard mask layer as a mask to continue etching the third semiconductor layer and the second semiconductor layer for a predetermined time period.

[0127] Method 1300 may further include depositing a dielectric spacer layer (1322) coupled to the hard mask layer and the plurality of recessed regions. In one embodiment, the dielectric spacer layer is formed conformally to the sidewalls of the plurality of fins and the upper surface of the hard mask layer.

[0128] Method 1300 may further include forming a first photoresist layer (1324) coupled to the dielectric spacer layer. In one embodiment, the first photoresist layer is patterned to cover a portion of the dielectric spacer layer on top of the plurality of fins and expose a plurality of recessed regions. In some embodiments, the photoresist layer is omitted.

[0129] Method 1300 may further include etching dielectric spacer layers and marker layers (1326) in multiple recessed regions. In some embodiments, the etching process stops in the third semiconductor layer. In some embodiments, the etching process is monitored to detect when the etching process reaches the marker layer, and subsequent etching processes can then be finely controlled to achieve a predetermined etching depth in the third semiconductor layer. In some embodiments, subsequent etching processes can be finely controlled to stop at the upper surface of the third semiconductor layer.

[0130] Method 1300 may further include ion implanting a dopant into a second semiconductor layer within a plurality of recessed regions to form a gate region (1328). In some embodiments, the dopant may be characterized by a second conductivity type opposite to the first conductivity type. In one embodiment, the dopant may include a p-type dopant. After the ion implantation process, the gate region is formed in a third semiconductor layer. In another embodiment, the dopant may be implanted into both the third and second semiconductor layers. In another embodiment, the implantation process is performed in such a manner (e.g., by implanting at an angle) that the dopant is implanted into the sidewalls of a plurality of fins. Thus, the gate region may be formed in both the third and second semiconductor layers. In some embodiments, the gate region is also formed in a fourth semiconductor layer. Method 1300 may then further include removing the first photoresist layer (1330).

[0131] Method 1300 may further include forming a gate metal layer (1332) coupled to the gate region within a plurality of recessed regions. In some embodiments, the gate metal layer may include nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0132] Method 1300 may further include forming a second photoresist layer (1334) on a gate metal layer in a plurality of recessed regions. In some embodiments, the second photoresist layer is formed conformally to the sidewalls of the plurality of fins and exposed above a dielectric spacer layer on the top of the plurality of fins.

[0133] Method 1300 may further include using a second photoresist layer as a mask to etch the dielectric spacer layer and the hard mask layer (1336). In some embodiments, the etching process stops on the fourth semiconductor layer, exposing the upper portions of the plurality of fins. After the etching process, the second photoresist layer (1338) is removed.

[0134] Method 1300 may further include forming a source metal layer (1340) coupled to a fourth semiconductor layer. In some embodiments, the source metal layer is coupled to the upper portion of a plurality of fins. In some embodiments, the source metal layer may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN).

[0135] It should be understood that Figures 13A to 13C The specific steps shown provide a particular method for manufacturing a vertical JFET device according to an embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the invention may perform the steps outlined above in a different order. Furthermore, Figures 13A to 13C A single step shown may include multiple sub-steps, which may be executed in various orders suitable for that single step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0136] refer to Figures 14A to 14P The present invention describes a method for manufacturing a MOSFET device 1400 according to an embodiment of the present invention. Figure 14A This is a partial cross-sectional view showing an n+ type doped semiconductor substrate 1402. (Reference) Figure 14B An n-type doped first semiconductor layer 1404 is epitaxially grown on a semiconductor substrate 1402. (Reference) Figure 14C An n-type doped second semiconductor layer 1406 is epitaxially grown on the first semiconductor layer 1404. In one embodiment, the first semiconductor layer 1404 has a 1×10⁻⁶ diameter. 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 1406 has a doping concentration of 7.5 × 10⁻⁶. 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 1406 has a gradient doping concentration between a first side 1406a and a second side 1406b opposite to the first side 1406a. In one embodiment, the gradient doping concentration starts from a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side 1406a adjacent to the first semiconductor layer 1404. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side 1406b (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the second semiconductor layer 1406 has a thickness of 0.3 μm.

[0137] refer to Figure 14D A third semiconductor layer 1408 is epitaxially grown on the second semiconductor layer 1406. The third semiconductor layer 1408 is characterized by having a first conductivity type. In one embodiment, the doping concentration of the third semiconductor layer 1408 is greater than the doping concentration of the first semiconductor layer 1404. In one embodiment, the third semiconductor layer 1408 comprises a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 n-type doped GaN.

[0138] refer to Figure 14E A marker layer 1410 is deposited on the third semiconductor layer 1408. In one embodiment, the marker layer 1410 may include a 1×10 19 atoms / cm 3 A GaN layer of silicon with a metallurgical concentration. In another embodiment, the marker layer 1410 may include a 1.3 × 10⁻⁶ silicon core. 17 atoms / cm 3An AlGaN layer of aluminum with a metallurgical concentration. In another embodiment, the marker layer 1410 may include a 1×10 17 Up to 1×10 19 atoms / cm 3 The InGaN layer has a metallurgical concentration of indium. In one embodiment, the marker layer 1410 may have a thickness in the range of 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marker layer 1410 has a thickness of 5 nm. In one embodiment, the vertical JFET device 1400 may omit the third semiconductor layer 1408. In such an embodiment, the marker layer 1410 is deposited directly on the second semiconductor layer 1406.

[0139] refer to Figure 14F A fourth semiconductor layer 1412 is epitaxially grown on the marker layer 1410. In one embodiment, the fourth semiconductor layer 1412 comprises a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 Furthermore, the GaN is an n-type doped layer with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the doping concentration of the fourth semiconductor layer 1412 is greater than the doping concentration of the first semiconductor layer 1404. In another embodiment, the doping concentration of the fourth semiconductor layer 1412 is greater than the higher doping concentration within the gradient doping concentration range of the second semiconductor layer 1406. In yet another embodiment, the doping concentration of the fourth semiconductor layer 1412 is equal to or greater than the doping concentration of the third semiconductor layer 1408.

[0140] refer to Figure 14G A hard mask layer 1414 is formed on the fourth semiconductor layer 1412. The hard mask layer 1414 includes a set of openings 1415 operable to expose an upper surface portion 1413 of the fourth semiconductor layer 1412. (See reference) Figure 14H An etching process is performed using a hard mask layer 1414 as a mask to form a plurality of fins 1412a within a fourth semiconductor layer 1412. Each fin 1412a is separated by a recessed region 320 of a plurality of recessed regions 1420 formed by the etching process. Figure 14H As shown, the etching process is monitored to detect when the etching process reaches the marker layer 1410. In one embodiment, the etching process is monitored to detect etching of at least a portion of the marker layer 1410. In one embodiment, the detection process can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be easily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be easily detected. In another embodiment using an In-doped layer, In dopant can be easily detected.

[0141] For clarity, in the following examples, the etching process can be stopped once it is detected that the etching process has reached the marker layer 1410. Those skilled in the art will understand that the invention is not limited to these examples. As referenced above... Figure 6D The etching process can be precisely controlled to achieve a predetermined etching depth in the target doped layer. For clarity of description and illustration, the following examples are described using a single recessed region 1420 or a single fin 1412a. Those skilled in the art will understand that, unless explicitly stated otherwise, the descriptions relating to one recessed region 1420 or one fin 1412a apply equally to all recessed regions 1420 or fins 1412a.

[0142] In one embodiment, after the depression area is formed, a cleaning process is performed for approximately 30 minutes at a temperature of approximately 85°C using a TMAH solution at a weight ratio of approximately 25%. In another embodiment, a pre-cleaning process may be performed before cleaning with the TMAH solution, which may be, for example, a two-minute peroxysulfuric acid cleaning using a 2:1 volume ratio of H2SO4:H2O2.

[0143] refer to Figure 14I A dielectric spacer layer 1416 is deposited on the hard mask layer 1414 and the plurality of recessed regions 1420. In one embodiment, the dielectric spacer layer 1416 is deposited conformally to the sidewalls of the hard mask layer 1414 and the fins 1412a. For example, as Figure 14I As shown, the dielectric spacer layer 1416 may include a first portion 1416a on top of the hard mask layer 1414, a second portion 1416b conformally to the sidewalls of the plurality of fins 1412a, and a third portion 1416c coupled to the plurality of recessed regions 1420. In some embodiments, the dielectric spacer layer 1416 may include TiOx. In some embodiments, the dielectric spacer layer 1416 may be deposited using a thermal ALD process. In some embodiments, the dielectric spacer layer 1416 may have a thickness in the range of about 3 nm to 8 nm.

[0144] refer to Figure 14J A first photoresist layer 1418 is formed on the dielectric spacer layer 1416. In some embodiments, the photoresist layer 1418 is disposed on a first portion 1416a and a second portion 1416b of the dielectric spacer layer 1416. A third portion 1416c in the recessed region 1420 is exposed. In some embodiments, the first photoresist layer 1418 protects portions of the dielectric spacer layer 1416 disposed on the fin 1412a and the hard mask layer 1414 from subsequent processing.

[0145] refer to Figure 14KUsing a first photoresist layer 1418 as a mask, an etching process is performed in the recessed region 1420 to remove the dielectric spacer layer 1416 within the recessed region 1420. The etching process then continues to remove a portion of the marker layer 1410 within the recessed region 1420 and stops in the third semiconductor layer 1408. In some embodiments, the etching process is monitored to detect when the etching process reaches the marker layer 1410, and subsequent etching processes can then be finely controlled to achieve a predetermined etching depth in the third semiconductor layer 1408. For example, subsequent etching can be timed to achieve an etching depth of 0.1 μm in the third semiconductor layer 1408. In some embodiments, subsequent etching processes can be finely controlled to stop at the upper surface of the third semiconductor layer 1408.

[0146] refer to Figure 14L A metal dielectric layer 1417 is formed on a third semiconductor layer 1408 within a plurality of recessed regions 1420. In some embodiments, the metal dielectric layer 1417 is also formed on top of a plurality of fins 1412a. Specifically, the metal dielectric layer 1417 is formed on a first photoresist layer 1418 retained on top of the plurality of fins 1412a. In some embodiments, the metal dielectric layer 1417 may comprise TiOx. In some embodiments, a thermal ALD process may be used to deposit the metal dielectric layer 1417. In some embodiments, the metal dielectric layer 1417 may have a thickness in the range of about 3 nm to 8 nm. The portion of the metal dielectric layer 1417 on the first photoresist layer 1418 is then removed together with the first photoresist layer 1418.

[0147] refer to Figure 14M A gate metal layer 1426 is formed on a metal dielectric layer 1417 within a plurality of recessed regions 1420. In some embodiments, the gate metal layer 1426 may include nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0148] refer to Figure 14N A second photoresist layer 1428 is formed on the gate metal layer 1426 within a plurality of recessed regions 1420. In one embodiment, the second photoresist layer 1428 is formed conformally to the sidewalls of the fins 1412a and exposes the upper portion of the dielectric spacer layer 1416 on the top of the plurality of fins 1412a. In some embodiments, the second photoresist layer 1428 can protect the gate metal layer 1426 from subsequent processing.

[0149] refer to Figure 14OAn etching process is performed using a second photoresist layer 1428 as a mask to remove the dielectric spacer layer 1416 and the hard mask layer 1414, and the etching process stops at the fourth semiconductor layer 1412. In some embodiments, the etching process removes a portion 1416a of the first portion 1416a of the dielectric spacer layer 1416, a portion of the hard mask layer 1414, and a portion 1416b of the second portion 1416 of the dielectric spacer layer 1416 from the top of the plurality of fins 1412a. After the etching process, the upper portion of the fins 1412a is exposed. After the etching process, the second photoresist layer 1428 is removed.

[0150] refer to Figure 14P A source metal layer 1424 is formed on the fourth semiconductor layer 1412. Specifically, the source metal layer 1424 is formed on the upper portion of the plurality of fins 1412a. In some embodiments, the source metal layer 1424 may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN).

[0151] Figures 15A to 15C This is a simplified flowchart illustrating a method 1500 for manufacturing a MOSFET device according to an embodiment of the present invention. (See reference) Figures 15A to 15C Method 1500 may include providing a semiconductor substrate (1502). In one embodiment, the semiconductor substrate may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a density of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range and has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. A first semiconductor layer (1504) is epitaxially grown on a semiconductor substrate. In one embodiment, the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration. In one embodiment, the first semiconductor layer may include a doping concentration of about 1 × 10⁻⁶. 16 atoms / cm 3 n-type doped GaN.

[0152] Method 1500 may further include epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having a first conductivity type (1506). In one embodiment, the second semiconductor layer is further characterized by a gradient doping concentration between a first side and a second side opposite to the first side. In one embodiment, the second semiconductor layer comprises n-type doped GaN, and the gradient doping concentration begins at a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side adjacent to the first semiconductor layer. 16 atoms / cm 3The doping concentration increases linearly to the higher doping concentration at the second side (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the thickness of the second semiconductor layer is 0.3 μm.

[0153] Method 1500 may further include epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having a first conductivity type (1508). In one embodiment, the third semiconductor layer may include a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 The third semiconductor layer is n-type doped GaN. In one embodiment, the doping concentration of the third semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In another embodiment, the doping concentration of the third semiconductor layer (e.g., 1.3 × 10⁻⁶) is... 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 In some embodiments, the thickness of the third semiconductor layer is between about 0.1 μm and 0.3 μm.

[0154] Method 1500 may further include forming a marker layer (1510) coupled to a third semiconductor layer. In one embodiment, the marker layer may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marking layer may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marking layer may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The marking layer contains indium at a metallurgical concentration. In one embodiment, the marking layer may have a thickness ranging from 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer has a thickness of 5 nm.

[0155] Method 1500 may further include epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having a first conductivity type and a second doping concentration (1512). In one embodiment, the second doping concentration of the fourth semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In one embodiment, the fourth semiconductor layer may include a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3And it is an n-type doped GaN with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the second doping concentration of the fourth semiconductor layer (e.g., 1.3 × 10⁻⁶) 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 ).

[0156] Method 1500 may further include forming a hard mask layer coupled to a fourth semiconductor layer, wherein the hard mask layer includes a set of openings (1514) operable to expose an upper surface portion of the fourth semiconductor layer.

[0157] Method 1500 may further include etching a fourth semiconductor layer to form a plurality of fins by using a hard mask layer as a mask, wherein each of the plurality of fins is separated by one of a plurality of recessed regions (1516). In one embodiment, each of the plurality of fins may have a thickness of about 0.8 μm.

[0158] Method 1500 may further include etching at least a portion of the marker layer (1518) and probing the etching of at least a portion of the marker layer (1520). In one embodiment, the probing process can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be readily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be readily detected. In one embodiment, method 1500 may stop etching when it is detected that the etching process has reached the marker layer. In another embodiment, method 1500 may further include etching to penetrate the marker layer, and then using a hard mask layer as a mask to continue etching a third semiconductor layer and a second semiconductor layer for a predetermined time period.

[0159] Method 1500 may further include depositing a dielectric spacer layer (1522) coupled to the hard mask layer and the plurality of recessed regions. In one embodiment, the dielectric spacer layer is formed conformally to the sidewalls of the plurality of fins and the upper surface of the hard mask layer.

[0160] Method 1500 may further include forming a first photoresist layer (1524) coupled to the dielectric spacer layer. In one embodiment, the first photoresist layer covers a portion of the dielectric spacer layer on top of the plurality of fins and exposes a plurality of recessed regions.

[0161] Method 1500 may further include etching dielectric spacer layers and marker layers (1526) in multiple recessed regions. In some embodiments, the etching process stops in the third semiconductor layer. In some embodiments, the etching process is monitored to detect when the etching process reaches the marker layer, and subsequent etching processes can then be finely controlled to achieve a predetermined etching depth in the third semiconductor layer. In some embodiments, subsequent etching processes can be finely controlled to stop at the upper surface of the third semiconductor layer.

[0162] Method 1500 may further include depositing a metal dielectric layer (1528) on a third semiconductor layer within a plurality of recessed regions. In some embodiments, the metal dielectric layer is also formed on top of the plurality of fins. Specifically, the metal dielectric layer is formed on a first photoresist layer retained on top of the plurality of fins. In some embodiments, the metal dielectric layer may include TiOx. In some embodiments, a thermal ALD process may be used to deposit the metal dielectric layer. After depositing the metal dielectric layer, the first photoresist layer (1530) is removed.

[0163] Method 1500 may further include forming a gate metal layer (1532) coupled to a metal dielectric layer in a plurality of recessed regions. In some embodiments, the gate metal layer may include nickel, gold, molybdenum, platinum, palladium, silver, and combinations thereof.

[0164] Method 1500 may further include forming a second photoresist layer (1534) on the gate metal layer in the plurality of recessed regions. In some embodiments, the second photoresist layer is formed to also conform to the sidewalls of the plurality of fins and to be exposed above the dielectric spacer layer on the top of the plurality of fins.

[0165] Method 1500 may further include using a second photoresist layer as a mask to etch the dielectric spacer layer and the hard mask layer (1536). In some embodiments, the etching process stops on the fourth semiconductor layer, exposing the upper portions of the plurality of fins. After the etching process, the second photoresist layer (1538) is removed.

[0166] Method 1500 may further include forming a source metal layer (1540) coupled to a fourth semiconductor layer. In some embodiments, the source metal layer is coupled to the upper portion of a plurality of fins. In some embodiments, the source metal layer may comprise a refractory metal, a refractory metal compound, or a refractory metal alloy (e.g., TiN).

[0167] It should be understood that Figures 15A to 15C The specific steps shown provide a particular method for manufacturing a MOSFET device according to an embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the invention may perform the steps outlined above in a different order. Furthermore, Figures 15A to 15CA single step shown may include multiple sub-steps, which may be executed in various orders suitable for that single step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0168] refer to Figures 16A to 16P The present invention describes a method for manufacturing a MOSFET device 1600 according to another embodiment of the present invention. Figure 16A This is a partial cross-sectional view showing an n+ type doped semiconductor substrate 1602. In one embodiment, the semiconductor substrate 1602 may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a density of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range specified. In one embodiment, the substrate has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. Reference Figure 16B An n-type doped first semiconductor layer 1604 is epitaxially grown on a semiconductor substrate 1602. In one embodiment, the first semiconductor layer 1604 is a GaN layer. (Reference) Figure 16C An n-type doped second semiconductor layer 1606 is epitaxially grown on the first semiconductor layer 1604. In one embodiment, the second semiconductor layer 1606 is a GaN layer. In one embodiment, the first semiconductor layer 1604 has a 1×10⁻⁶ layer. 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 1606 has a doping concentration of 7.5 × 10⁻⁶. 16 atoms / cm 3 The doping concentration. In one embodiment, the second semiconductor layer 1606 has a gradient doping concentration between a first side 1606a and a second side 1606b opposite to the first side 1606a. In one embodiment, the gradient doping concentration starts from a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side 1606a adjacent to the first semiconductor layer 1604. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side 1606b (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the second semiconductor layer 1606 has a thickness of 0.3 μm.

[0169] refer to Figure 16DA third semiconductor layer 1608 is epitaxially grown on the second semiconductor layer 1606. The third semiconductor layer 1608 is characterized by having a first conductivity type. In one embodiment, the doping concentration of the third semiconductor layer 1608 is greater than the doping concentration of the first semiconductor layer 1604. In one embodiment, the third semiconductor layer 1608 comprises a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 n-type doped GaN.

[0170] refer to Figure 16E A marker layer 1610 is deposited on the third semiconductor layer 1608. In one embodiment, the marker layer 1610 may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marker layer 1610 may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marker layer 1610 may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The metallurgical concentration of indium. In one embodiment, the marking layer 1610 may have a thickness in the range of 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer 1610 has a thickness of 5 nm. In one embodiment, the vertical JFET device 1600 may omit the third semiconductor layer 1608. In such an embodiment, the marking layer 1610 is deposited directly on the second semiconductor layer 1606.

[0171] refer to Figure 16F A fourth semiconductor layer 1612 is epitaxially grown on the marker layer 1610. In one embodiment, the fourth semiconductor layer 1612 comprises a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 Furthermore, the GaN is an n-type doped layer with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the doping concentration of the fourth semiconductor layer 1612 is greater than the doping concentration of the first semiconductor layer 1604. In another embodiment, the doping concentration of the fourth semiconductor layer 1612 is greater than the higher doping concentration within the gradient doping concentration range of the second semiconductor layer 1606. In yet another embodiment, the doping concentration of the fourth semiconductor layer 1612 is equal to or greater than the doping concentration of the third semiconductor layer 1608.

[0172] refer to Figure 16GA hard mask layer 1614 is formed on the fourth semiconductor layer 1612. The hard mask layer 1614 includes a set of openings 1615 operable to expose an upper surface portion 1617 of the fourth semiconductor layer 1612. (See reference) Figure 16H An etching process is performed using a hard mask layer 1614 as a mask to form a plurality of fins 1612a within a fourth semiconductor layer 1612. Each fin 1612a is separated by a recessed region 320 of a plurality of recessed regions 1620 formed by the etching process. Figure 16H As shown, the etching process is monitored to detect when the etching process reaches the marker layer 1610. In one embodiment, the etching process is monitored to detect etching of at least a portion of the marker layer 1610. In one embodiment, the detection process can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be easily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be easily detected. In another embodiment using an In-doped layer, In dopant can be easily detected.

[0173] For clarity, in the following examples, the etching process can be stopped once it is detected that the etching process has reached the marker layer 1610. Those skilled in the art will understand that the invention is not limited to these examples. As referenced above... Figure 6D The etching process can be precisely controlled to achieve a predetermined etching depth in the target doped layer. For clarity of description and illustration, the following examples are described using a single recessed region 1620 or a single fin 1612a. Those skilled in the art will understand that, unless explicitly stated otherwise, the descriptions relating to a single recessed region 1620 or a single fin 1612a apply equally to all recessed regions 1620 or fins 1612a.

[0174] In one embodiment, after the depression area is formed, a cleaning process is performed for approximately 30 minutes at a temperature of approximately 85°C using a TMAH solution at a weight ratio of approximately 25%. In another embodiment, a pre-cleaning process may be performed before cleaning with the TMAH solution, such as a two-minute piranha clean using H2SO4:H2O2 at a volume ratio of 2:1.

[0175] refer to Figure 16I A dielectric spacer layer 1616 is deposited on the hard mask layer 1614 and the plurality of recessed regions 1620. In one embodiment, the dielectric spacer layer 1616 is deposited conformally to the sidewalls of the hard mask layer 1614 and the fins 1612a. For example, as Figure 16IAs shown, the dielectric spacer layer 1616 may include a first portion 1616a on top of the hard mask layer 1614, a second portion 1616b conformally to the sidewalls of the plurality of fins 1612a, and a third portion 1616c coupled to the plurality of recessed regions 1620. In some embodiments, the dielectric spacer layer 1616 may include TiOx. In some embodiments, the dielectric spacer layer 1616 may be deposited using a thermal ALD process. In some embodiments, the dielectric spacer layer 1616 may have a thickness in the range of about 3 nm to 8 nm.

[0176] refer to Figure 16J A first photoresist layer 1618 is formed on the dielectric spacer layer 1616 to planarize the plurality of recessed regions 1620. In some embodiments, the first photoresist layer 1618 protects portions of the dielectric spacer layer 1616 disposed within the plurality of recessed regions 1620 from subsequent processing.

[0177] refer to Figure 16K An etching process is performed on the first photoresist layer 1618 to etch back the first photoresist layer 1618 to expose the dielectric spacer layer 1616 on top of the hard mask layer 1614. Specifically, a first portion 1616a and a portion of the second portion 1616b of the dielectric spacer layer 1616 are exposed.

[0178] refer to Figure 16L The portion of the dielectric spacer layer 1616 on top of the hard mask layer 1614 and the exposed portion of the dielectric spacer layer 1616 on the sidewalls are removed to expose the fourth semiconductor layer 1612. Specifically, a first portion 1616a of the dielectric spacer layer 1616 and a portion of the second portion 1616b of the dielectric spacer layer 1616 are removed. In one embodiment, a portion of the second portion 1616b of the dielectric spacer layer 1616 may be removed such that the remaining portion of the second portion 1616b is below the upper surface of the remaining portion of the first photoresist layer 1618.

[0179] refer to Figure 16M The first photoresist layer 1618 is peeled off from the dielectric spacer layer 1616. Then, refer to... Figure 16NA gate dielectric layer (not shown) and a gate metal layer 1626 are formed on a fourth semiconductor layer 1612 on the sidewalls. For clarity, the gate dielectric layer is omitted in the following description. In some embodiments, the gate dielectric may be formed of Al2O3. In some embodiments, the gate dielectric may be formed of SiO2. In some embodiments, the gate dielectric may be formed of silicon nitride. Specifically, the gate dielectric layer and the gate metal layer 1626 are formed conformally to the top of the hard mask layer 1614, the exposed portion of the sidewalls of the fin 1612a, the second portion 1616b of the dielectric spacer layer 1616, and the third portion 1616c of the dielectric spacer layer 1616 within the plurality of recessed regions 1620. In some embodiments, the fin 1612a is n-type GaN, and the gate metal layer 1626 has a work function such that the fin 1612a is depleted in the exposed region of the sidewalls after etching the dielectric spacers. In some embodiments, the gate metal layer is one of molybdenum, tungsten, or tantalum.

[0180] refer to Figure 16O The second photoresist layer 1628 is masked and patterned to expose a portion of the gate metal layer 1626. In some embodiments, the second photoresist layer 1628 is masked and patterned within a plurality of recessed regions 1620 to expose the portion of the gate metal layer 1626 on top of a plurality of fins 1612a. In some embodiments, the second photoresist layer 1628 may protect the gate metal layer 1626 within the plurality of recessed regions 1620 from subsequent processing.

[0181] refer to Figure 16P An etching process is performed using a second photoresist layer 1628 as a mask to etch the gate metal layer 1626, the gate dielectric layer (not shown), and the hard mask layer 1614. This etching process stops at the fourth semiconductor layer 1612. Specifically, the upper portions of a plurality of fins 1612a are exposed. In some embodiments, the etching process removes more material from the gate metal layer 1626 in the thickness direction than it removes from the fins 1612a.

[0182] refer to Figure 16Q A second dielectric layer 1630 is deposited on the exposed gate metal layer 1626 and the fourth semiconductor layer 1612. Specifically, the second dielectric layer 1630 is formed to cover the gate metal layer 1626 and the upper part of the plurality of fins 1612a within the plurality of recessed regions 1620.

[0183] refer to Figure 16R A third photoresist layer 1632 is formed on the second dielectric layer 1630. In some embodiments, the third photoresist layer 1632 is patterned to expose a portion of the second dielectric layer 1630 on top of the plurality of fins 1612a.

[0184] refer to Figure 16SAn etching process is performed using a third photoresist layer 1632 as a mask to etch back the second dielectric layer 1630 to expose the fourth semiconductor layer 1612. Specifically, an etching process is performed to etch back the portion of the second dielectric layer 1630 on top of the plurality of fins 1612a to expose the upper portion of the plurality of fins 1612a. In some embodiments, the etching process removes more material from the second dielectric layer 1630 in the thickness direction than the amount removed from the fins 1612a. The third photoresist layer 1632 is then removed.

[0185] refer to Figure 16T A source metal layer 1624 is formed on the fourth semiconductor layer 1612 and the second dielectric layer 1630 (which may be an oxide layer). Specifically, the source metal layer 1624 is formed on the upper portion of the plurality of fins 1612a and is also coupled to the second dielectric layer 1630. In some embodiments, the source metal layer 1624 may include a refractory metal, a refractory metal compound (e.g., TiN), or a refractory metal alloy (e.g., TiAlx).

[0186] refer to Figure 16U A fourth photoresist layer 1634 is formed on the source metal layer 1624. Specifically, the fourth photoresist layer 1634 is patterned to expose portions of the second dielectric layer 1630 within the plurality of recessed regions 1620.

[0187] refer to Figure 16V An etching process is performed using a fourth photoresist layer 1634 as a mask to etch the second dielectric layer 1630 to expose the gate metal layer 1626. Specifically, an etching process is performed to etch portions of the second dielectric layer 1630 within a plurality of recessed regions 1620 to expose the gate metal layer 1626 within the plurality of recessed regions 1620.

[0188] above Figures 16A to 16V A MOSFET with a gate controlling a portion of the fin 1612a is formed in such a way that the fin is initially completely depleted. For an n-type fin, as the gate voltage becomes more positive, the depletion of the fin decreases, and vertical conduction from the source metal layer 1624 to the substrate 1602 becomes possible. As the gate voltage increases further, an electron accumulation region is formed on the sidewalls of the fin 1612a to further increase the conductivity between the source metal layer 1624 and the substrate 1602. The resulting MOSFET operates in the normally off state, and the combination of bulk conduction and accumulation layer conduction is in the "on" state.

[0189] It will be recognized that the rearrangement of layers, particularly layer 1608, can produce a conventional enhancement-mode MOSFET. Specifically, if the upper portion of layer 1608 is n-type and the lower portion is p-type, the MOSFET is formed such that as the gate voltage increases, a conduction path is created through conduction on the sidewall surface of the "reverse" p-type region. The resulting surface electron layer can conduct between the source metal layer 1624 and the substrate 1602.

[0190] Figures 17A to 17C This is a simplified flowchart illustrating a method 1700 for manufacturing a MOSFET device according to another embodiment of the present invention. (See reference) Figures 17A to 17C Method 1700 may include providing a semiconductor substrate (1702). In one embodiment, the semiconductor substrate may include a group III nitride compound, such as GaN. In one embodiment, the semiconductor substrate is an n+ type doped GaN substrate having a density of approximately 5 × 10⁻⁶. 17 atoms / cm 3 To approximately 1×10 19 atoms / cm 3 The doping concentration is within the range and has a doping concentration of less than 0.020 ohm-cm. 2 The resistivity. A first semiconductor layer (1704) is epitaxially grown on a semiconductor substrate. In one embodiment, the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration. In one embodiment, the first semiconductor layer may include a doping concentration of about 1 × 10⁻⁶. 16 atoms / cm 3 n-type doped GaN.

[0191] Method 1700 may further include epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having a first conductivity type (1706). In one embodiment, the second semiconductor layer is further characterized by a gradient doping concentration between a first side and a second side opposite to the first side. In one embodiment, the second semiconductor layer comprises n-type doped GaN, and the gradient doping concentration begins at a lower doping concentration (e.g., 1 × 10⁻⁶) at the first side adjacent to the first semiconductor layer. 16 atoms / cm 3 The doping concentration increases linearly to the higher doping concentration at the second side (e.g., 7.5 × 10⁻⁶). 16 atoms / cm 3 In one embodiment, the thickness of the second semiconductor layer is 0.3 μm.

[0192] Method 1700 may further include epitaxially growing a third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having a first conductivity type (1708). In one embodiment, the third semiconductor layer may include a doping concentration of approximately 1.3 × 10⁻⁶. 17 atoms / cm 3 The third semiconductor layer is n-type doped GaN. In one embodiment, the doping concentration of the third semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In another embodiment, the doping concentration of the third semiconductor layer (e.g., 1.3 × 10⁻⁶) is... 17 atoms / cm 3 The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 In some embodiments, the thickness of the third semiconductor layer is between about 0.1 μm and 0.3 μm.

[0193] Method 1700 may further include forming a marker layer (1710) coupled to a third semiconductor layer. In one embodiment, the marker layer may include a GaN layer incorporating 1×10 19 atoms / cm 3 The silicon has a metallurgical concentration. In another embodiment, the marking layer may include an AlGaN layer incorporating 1.3 × 10⁻⁶ silicon. 17 atoms / cm 3 The aluminum has a metallurgical concentration. In another embodiment, the marking layer may include an InGaN layer, which incorporates 1×10 17 Up to 1×10 19 atoms / cm 3 The marking layer contains indium at a metallurgical concentration. In one embodiment, the marking layer may have a thickness ranging from 1 nm to 10 nm (preferably 3 nm to 8 nm). In an exemplary embodiment, the marking layer has a thickness of 5 nm.

[0194] Method 1700 may further include epitaxially growing a fourth semiconductor layer coupled to the marker layer, wherein the fourth semiconductor layer is characterized by having a first conductivity type and a second doping concentration (1712). In one embodiment, the second doping concentration of the fourth semiconductor layer is greater than the first doping concentration of the first semiconductor layer. In one embodiment, the fourth semiconductor layer may include a doping concentration of 1.3 × 10⁻⁶. 17 atoms / cm 3 And it is an n-type doped GaN with a thickness of approximately 0.3 μm to 0.7 μm. In one embodiment, the second doping concentration of the fourth semiconductor layer (e.g., 1.3 × 10⁻⁶) 17 atoms / cm 3The higher doping concentration within the gradient doping concentration range of the second semiconductor layer (e.g., 7.5 × 10⁻⁶) is greater than that of the higher doping concentration within the gradient doping concentration range of the second semiconductor layer. 16 atoms / cm 3 ).

[0195] Method 1700 may further include forming a hard mask layer coupled to a fourth semiconductor layer, wherein the hard mask layer includes a set of openings (1714) operable to expose an upper surface portion of the fourth semiconductor layer.

[0196] Method 1700 may further include etching a fourth semiconductor layer to form a plurality of fins by using a hard mask layer as a mask, wherein each of the plurality of fins is separated by one of a plurality of recessed regions (1716). In one embodiment, the depth of the recessed region 1716 is between 0.6 μm and 1.5 μm. In one embodiment, the depth of the recessed region 1716 is about 0.8 μm to 1.0 μm. In one embodiment, each of the plurality of fins may have a width of about 0.2 μm (between the recessed regions).

[0197] Method 1700 may further include etching at least a portion of the marker layer (1718) and probing the etching of at least a portion of the marker layer (1720). In one embodiment, the probing process can be performed using standard methods (e.g., an endpoint detector). In one embodiment using a silicon layer as the marker layer, spikes of silicon dopant can be readily detected. In another embodiment using an AlGaN layer as the marker layer, Al dopant can be readily detected. In one embodiment, method 1700 may stop etching when it is detected that the etching process has reached the marker layer. In another embodiment, method 1700 may further include etching to penetrate the marker layer, and then using a hard mask layer as a mask to continue etching the third semiconductor layer and the second semiconductor layer for a predetermined time period.

[0198] Method 1700 may further include depositing a dielectric spacer layer (1722) coupled to the hard mask layer and the plurality of recessed regions. In one embodiment, the dielectric spacer layer is formed conformally to the sidewalls of the plurality of fins and the upper surface of the hard mask layer.

[0199] Method 1700 may further include forming a first photoresist layer (1724) coupled to the dielectric spacer layer. In one embodiment, the first photoresist layer is formed on the dielectric spacer layer to planarize a plurality of recessed regions.

[0200] Method 1700 may also include etching back the first photoresist layer to expose a dielectric spacer layer on top of the hard mask layer (1726).

[0201] Method 1700 may further include removing dielectric spacers on the top and sidewalls of the hard mask layer to expose the fourth semiconductor layer (1728). In some embodiments, method 1700 may include removing portions of the dielectric spacer layer on the top of the hard mask layer and portions of the dielectric spacer layer on the sidewalls of the plurality of fins to expose at least a portion of the sidewalls of the plurality of fins. In some embodiments, the exposed portion of the sidewalls is between 0.4 μm and 0.8 μm.

[0202] Method 1700 may further include stripping the first photoresist layer from the dielectric spacer layer (1730).

[0203] Method 1700 may further include forming a gate dielectric layer and a gate metal layer (1732) coupled to a sidewall portion of a fourth semiconductor layer. In one embodiment, the gate metal is selected such that the work function of the gate metal layer causes the fin to completely deplete mobile carriers in the region where the gate dielectric layer contacts the fin sidewall. In some embodiments, the fin is n-type GaN, and the gate metal layer is one of molybdenum, tungsten, or tantalum.

[0204] Method 1700 may further include forming a second photoresist layer (1734) coupled to the gate metal layer. In some embodiments, the second photoresist layer is patterned in a plurality of recessed regions to expose portions of the gate metal layer on top of the plurality of fins.

[0205] Method 1700 may further include using a second photoresist layer as a mask to etch the gate metal layer, the gate dielectric layer, and the hard mask layer, the etching stopping at the fourth semiconductor layer (1736). The second photoresist layer is then removed.

[0206] Method 1700 may further include depositing a second dielectric layer (1738) coupled to the exposed gate metal layer and the fourth semiconductor layer. Specifically, the second dielectric layer is deposited to cover the gate metal layer in the plurality of recessed regions and the upper portion of the plurality of fins.

[0207] Method 1700 may further include forming a third photoresist layer (1740) coupled to the second dielectric layer. In some embodiments, the third photoresist layer is patterned to expose portions of the second dielectric layer on top of the plurality of fins.

[0208] Method 1700 may further include using a third photoresist layer as a mask to etch the second dielectric layer back and forth to expose the fourth semiconductor layer (1742). Specifically, an etching process is performed to etch back portions of the second dielectric layer on top of the plurality of fins to expose the upper portions of the plurality of fins. The third photoresist layer is then removed.

[0209] Method 1700 may further include forming a source metal layer (1744) coupled to a fourth semiconductor layer and a second dielectric layer. Specifically, the source metal layer is formed on the upper portion of the plurality of fins and is also coupled to the second dielectric layer.

[0210] Method 1700 may further include forming a fourth photoresist layer (1746) coupled to the source metal layer. Specifically, the fourth photoresist layer is patterned to expose portions of the second dielectric layer in multiple recessed regions.

[0211] Method 1700 may further include using a fourth photoresist layer as a mask to etch the second dielectric layer to expose the gate metal layer (1748). Specifically, an etching process is performed to etch portions of the second dielectric layer in multiple recessed regions to expose the gate metal layer in the multiple recessed regions.

[0212] It should be understood that Figures 17A to 17C The specific steps illustrated herein provide a particular method for manufacturing a MOSFET device according to another embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, Figures 17A to 17C A single step shown may include multiple sub-steps, which may be executed in various orders suitable for that single step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0213] Embodiments of the invention have been described herein with reference to the accompanying drawings. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and comprehensive, and fully express the scope of the invention to those skilled in the art. Features may not be drawn to scale, and some details may be exaggerated relative to other elements for clarity. Similar numerals always refer to similar elements.

[0214] It should be understood that the accompanying drawings are not drawn to scale, and similar reference numerals are used to represent similar elements. As used herein, the terms "exemplary embodiment," "exemplary model," and "this embodiment," while possible, do not necessarily refer to a single embodiment, and various exemplary embodiments can be readily combined and interchanged without departing from the scope or spirit of the invention. Furthermore, the terminology used herein is for the purpose of describing exemplary embodiments only and is not intended to be a limitation of the invention. In this regard, as used herein, the term "in" can include "in" and "on," and the terms "a," "an," and "the" can include both singular and plural references. Furthermore, as used herein, depending on the context, the term "by" may also mean "from." Furthermore, as used herein, depending on the context, the term "if" may also mean "when" or "in the case of." Furthermore, as used herein, the term "and / or" may refer to and cover any possible combination of one or more of the associated listed items.

[0215] It will be understood that while the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another region, layer, or portion. Therefore, without departing from the teachings of the invention, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion.

[0216] As used in this application, the term "horizontal" is defined as a plane parallel to a conventional plane or the surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term "vertical" refers to a direction perpendicular to the "horizontal" as defined above. Prepositions such as "above," "side" (e.g., "sidewall"), "below," "above," "higher," "lower," "directly above," and "directly below" are defined relative to a conventional plane or a surface on the top surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. It should be understood that these terms are intended to cover different orientations of the device in addition to those depicted in the figures.

[0217] It should be understood that the appended claims are not limited to the precise configuration illustrated in the figures. Those skilled in the art will recognize that various modifications, substitutions, and variations can be made to the arrangement and steps of the above methods and devices without departing from the scope of the invention.

Claims

1. A method for manufacturing a field-effect transistor (FET) device, the method comprising: A semiconductor substrate structure is provided, comprising: A first epitaxial semiconductor layer coupled to a semiconductor substrate, wherein the first epitaxial semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second epitaxial semiconductor layer is coupled to the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer is characterized by having the first conductivity type; A marking layer is located on top of the second epitaxial semiconductor layer; A third epitaxial semiconductor layer, situated above the marking layer, wherein the third epitaxial semiconductor layer is characterized by having the first conductivity type; and A fourth epitaxial semiconductor layer is disposed on the third epitaxial semiconductor layer, wherein the fourth epitaxial semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A hard mask layer is formed coupled to the fourth epitaxial semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth epitaxial semiconductor layer; Etch portions of the fourth epitaxial semiconductor layer and the third epitaxial semiconductor layer to form multiple fins; Etch at least a portion of the marking layer; Detect the etching of at least a portion of the marked layer; A semiconductor layer is epitaxially grown in the recessed region between adjacent fins disposed in the plurality of fins; A source metal layer is formed on each of the plurality of fins; and A gate metal layer is formed that is coupled to the semiconductor layer.

2. The method according to claim 1, characterized in that, Etching at least a portion of the marker layer includes etching to penetrate the marker layer and etching a portion of the second epitaxial semiconductor layer.

3. The method according to claim 1, wherein: Providing the semiconductor substrate structure includes providing the marker layer having a doping concentration of the marker layer; and Detecting the etching includes measuring the doping concentration of the marker layer.

4. The method according to claim 1, wherein: Detecting the etching includes measuring the threshold voltage of the FET device.

5. The method according to claim 1, characterized in that, The semiconductor layer includes a fifth epitaxial semiconductor layer, characterized in that it has a second conductivity type opposite to the first conductivity type.

6. The method according to claim 1, characterized in that, It also includes using the hard mask layer as a mask to etch the second epitaxial semiconductor layer for a predetermined time period.

7. The method according to claim 1, characterized in that, The second epitaxial semiconductor layer is characterized by having a first gradient doping concentration, which is a gradient that linearly increases from the first doping concentration to the third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

8. The method according to claim 1, characterized in that, The third epitaxial semiconductor layer is characterized by having a second gradient doping concentration, which is a gradient that increases linearly from a third doping concentration to the second doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

9. The method according to claim 1, characterized in that, The second doping concentration is greater than the first doping concentration.

10. The method according to claim 1, characterized in that, The marking layer comprises silicon and is characterized by having a marking layer doping concentration; and Detecting the etching includes measuring the doping concentration of the marker layer.

11. The method according to claim 1, characterized in that, The marking layer has a thickness in the range of 5 nm to 10 nm.

12. A method for manufacturing a field-effect transistor (FET) device, the method comprising: Provide semiconductor substrates; A first semiconductor layer is epitaxially grown and coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second semiconductor layer is epitaxially grown and coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; A third semiconductor layer is epitaxially grown and coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; A marking layer is formed that is coupled to the third semiconductor layer; A fourth semiconductor layer is epitaxially grown and coupled to the marking layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A hard mask layer is formed coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth semiconductor layer; The fourth semiconductor layer is etched using the hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions; Etch at least a portion of the marking layer; Detect the etching of at least a portion of the marked layer; A fifth semiconductor layer is epitaxially grown within the plurality of recessed regions, wherein the fifth semiconductor layer is characterized by having a second conductivity type opposite to the first conductivity type; a source metal layer is formed on each of the plurality of fins; and A gate metal layer is formed that is coupled to the fifth semiconductor layer.

13. The method according to claim 12, characterized in that, Etching at least a portion of the marker layer includes etching to penetrate the marker layer.

14. The method according to claim 12, characterized in that, It also includes using the hard mask layer as a mask to etch the third semiconductor layer and the second semiconductor layer for a predetermined time period.

15. The method according to claim 12, characterized in that, The second semiconductor layer is characterized by having a gradient doping concentration, which is a gradient that linearly increases from the first doping concentration to the third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

16. The method according to claim 12, characterized in that, The third semiconductor layer is characterized by having a fourth doping concentration that is greater than the first doping concentration.

17. The method according to claim 12, characterized in that, The second doping concentration is greater than the first doping concentration.

18. A field-effect transistor (FET) device, comprising: Semiconductor substrate; A first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized in that it has the first conductivity type; A plurality of fins coupled to the first semiconductor layer, each of the plurality of fins being separated by one of a plurality of recessed regions, wherein each of the plurality of fins includes: A labeling layer coupled to the second semiconductor layer; A third semiconductor layer, coupled to the marker layer, wherein the third semiconductor layer is characterized by having the first conductivity type; and A fourth semiconductor layer coupled to the third semiconductor layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A fifth semiconductor layer is epitaxially grown in the plurality of recessed regions, wherein the fifth semiconductor layer is characterized in that it has a second conductivity type opposite to the first conductivity type; A source metal layer coupled to each of the plurality of fins; and A gate metal layer, which is coupled to the fifth semiconductor layer.

19. The FET device according to claim 18, characterized in that, The second semiconductor layer is characterized by having a first gradient doping concentration, which is a gradient that linearly increases from the first doping concentration to the third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

20. The FET device according to claim 18, characterized in that, The third semiconductor layer is characterized by having a second gradient doping concentration, which is a gradient that increases linearly from a third doping concentration to the second doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

21. The FET device according to claim 18, characterized in that, The second doping concentration is greater than the first doping concentration.

22. The FET device according to claim 18, characterized in that, The marking layer comprises silicon or AlGaN.

23. The FET device according to claim 18, characterized in that, The marking layer has a thickness in the range of 5 nm to 10 nm.

24. A field-effect transistor (FET) device, comprising: Semiconductor substrate; A first semiconductor layer coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized in that it has the first conductivity type; A plurality of fins coupled to the second semiconductor layer, each of the plurality of fins being separated by one of a plurality of recessed regions, wherein each of the plurality of fins includes: A third semiconductor layer coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A marker layer, coupled to the third semiconductor layer; and A fourth semiconductor layer coupled to the marking layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and the third doping concentration; A fifth semiconductor layer is epitaxially grown in the plurality of recessed regions, wherein the fifth semiconductor layer is characterized in that it has a second conductivity type opposite to the first conductivity type; A source metal layer coupled to each of the plurality of fins; and A gate metal layer, which is coupled to the fifth semiconductor layer.

25. The FET device according to claim 24, characterized in that, The second semiconductor layer is characterized by having a gradient doping concentration, which is a gradient that increases linearly from the first doping concentration to the fourth doping concentration, wherein the fourth doping concentration is greater than the first doping concentration and less than the third doping concentration.

26. The FET device according to claim 24, characterized in that, The second doping concentration is greater than the first doping concentration.

27. The FET device according to claim 24, characterized in that, The third doping concentration is greater than the first doping concentration.

28. The FET device according to claim 24, characterized in that, The third doping concentration is greater than the second doping concentration.

29. The FET device according to claim 24, characterized in that, The marking layer comprises silicon or AlGaN.

30. The FET device according to claim 24, characterized in that, The marking layer has a thickness in the range of 5 nm to 10 nm.

31. A method for manufacturing a vertical JFET device, the method comprising: Provide semiconductor substrates; A first semiconductor layer is epitaxially grown and coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second semiconductor layer is epitaxially grown and coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; A third semiconductor layer is epitaxially grown and coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; A marking layer is formed that is coupled to the third semiconductor layer; A fourth semiconductor layer is epitaxially grown and coupled to the marking layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A hard mask layer is formed coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth semiconductor layer; The fourth semiconductor layer is etched using the hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions; Etch at least a portion of the marking layer; Detect the etching of at least a portion of the marked layer; A dielectric spacer layer is deposited and coupled to the hard mask layer and the plurality of recessed regions; A first photoresist layer is formed and coupled to the dielectric spacer layer; Etch the dielectric spacer layer and the marking layer within the plurality of recessed regions; Ion implantation of dopant is performed in the second semiconductor layer within the plurality of recessed regions to form a gate region; Remove the first photoresist layer; A gate metal layer coupled to the gate region is formed in the plurality of recessed regions; A second photoresist layer is formed on the gate metal layer in the plurality of recessed regions; The second photoresist layer is used as a mask to etch the dielectric spacer layer and the hard mask layer; Remove the second photoresist layer; and A source metal layer is formed that is coupled to the fourth semiconductor layer.

32. The method according to claim 31, characterized in that, Etching at least a portion of the marker layer includes etching to penetrate the marker layer.

33. The method according to claim 31, characterized in that, It also includes using the hard mask layer as a mask to etch the third semiconductor layer and the second semiconductor layer for a predetermined time period.

34. The method according to claim 31, characterized in that, The second semiconductor layer is characterized by having a gradient doping concentration, which is a gradient that linearly increases from the first doping concentration to the third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

35. The method according to claim 31, characterized in that, The third semiconductor layer is characterized by having a fourth doping concentration that is greater than the first doping concentration.

36. The method according to claim 31, characterized in that, The second doping concentration is greater than the first doping concentration.

37. A method for manufacturing a MOSFET device, the method comprising: Provide semiconductor substrates; A first semiconductor layer is epitaxially grown and coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second semiconductor layer is epitaxially grown and coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; A third semiconductor layer is epitaxially grown and coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; A marking layer is formed that is coupled to the third semiconductor layer; A fourth semiconductor layer is epitaxially grown and coupled to the marking layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A hard mask layer is formed coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth semiconductor layer; The fourth semiconductor layer is etched using the hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions; Etch at least a portion of the marking layer; Detect the etching of at least a portion of the marked layer; A dielectric spacer layer is deposited and coupled to the hard mask layer and the plurality of recessed regions; A first photoresist layer is formed and coupled to the dielectric spacer layer; Etch the dielectric spacer layer and the marking layer within the plurality of recessed regions; A metal dielectric layer is deposited on the third semiconductor layer within the plurality of recessed regions; Remove the first photoresist layer; A gate metal layer coupled to the metal dielectric layer is formed in the plurality of recessed regions; A second photoresist layer is formed on the gate metal layer in the plurality of recessed regions; The second photoresist layer is used as a mask to etch the dielectric spacer layer and the hard mask layer; Remove the second photoresist layer; and A source metal layer is formed that is coupled to the fourth semiconductor layer.

38. The method according to claim 37, characterized in that, Etching at least a portion of the marker layer includes etching to penetrate the marker layer.

39. The method according to claim 38, characterized in that, It also includes using the hard mask layer as a mask to etch the second semiconductor layer for a predetermined time period.

40. The method according to claim 38, characterized in that, The second semiconductor layer is characterized by having a first gradient doping concentration, which is a gradient that linearly increases from the first doping concentration to the third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

41. The method according to claim 38, characterized in that, The third semiconductor layer is characterized by having a second gradient doping concentration, which is a gradient that increases linearly from a third doping concentration to the second doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

42. The method according to claim 38, characterized in that, The second doping concentration is greater than the first doping concentration.

43. The method according to claim 37, characterized in that, The marking layer comprises silicon or AlGaN.

44. The method according to claim 37, characterized in that, The marking layer has a thickness in the range of 5 nm to 10 nm.

45. A method for manufacturing a MOSFET device, the method comprising: Provide semiconductor substrates; A first semiconductor layer is epitaxially grown and coupled to the semiconductor substrate, wherein the first semiconductor layer is characterized by having a first conductivity type and a first doping concentration; A second semiconductor layer is epitaxially grown and coupled to the first semiconductor layer, wherein the second semiconductor layer is characterized by having the first conductivity type; A third semiconductor layer is epitaxially grown and coupled to the second semiconductor layer, wherein the third semiconductor layer is characterized by having the first conductivity type; A marking layer is formed that is coupled to the third semiconductor layer; A fourth semiconductor layer is epitaxially grown and coupled to the marking layer, wherein the fourth semiconductor layer is characterized by having the first conductivity type and the second doping concentration; A hard mask layer is formed coupled to the fourth semiconductor layer, wherein the hard mask layer includes a set of openings operable to expose a portion of the upper surface of the fourth semiconductor layer; The fourth semiconductor layer is etched using the hard mask layer as a mask to form a plurality of fins, wherein each of the plurality of fins is separated by one of a plurality of recessed regions; Etch at least a portion of the marking layer; Detect the etching of at least a portion of the marked layer; A dielectric spacer layer is deposited and coupled to the hard mask layer and the plurality of recessed regions; A first photoresist layer is formed and coupled to the dielectric spacer layer; Etch back the first photoresist layer to expose the dielectric spacer layer on top of the hard mask layer; Remove a portion of the dielectric spacer layer on top of the hard mask layer and a portion of the dielectric spacer layer on the sidewalls of the plurality of fins to expose at least a portion of the sidewalls of the plurality of fins; The first photoresist layer is peeled off from the dielectric spacer layer; A metal dielectric layer and a gate metal layer are formed and coupled to the sidewall portion of the fourth semiconductor layer; A second photoresist layer is formed and coupled to the gate metal layer; The gate metal layer, the metal dielectric layer, and the hard mask layer are etched using the second photoresist layer as a mask. A second oxide layer is deposited and coupled to the gate metal layer and the fourth semiconductor layer; A third photoresist layer is formed and coupled to the second oxide layer; The second oxide layer is etched back and forth using the third photoresist layer as a mask to expose the fourth semiconductor layer; A source metal layer is formed that is coupled to the fourth semiconductor layer and the second oxide layer; A fourth photoresist layer is formed and coupled to the source metal layer; and The second oxide layer is etched using the fourth photoresist layer as a mask to expose the gate metal layer.

46. ​​The method according to claim 45, characterized in that, Etching at least a portion of the marker layer includes etching to penetrate the marker layer.

47. The method according to claim 46, characterized in that, It also includes using the hard mask layer as a mask to etch the second semiconductor layer for a predetermined time period.

48. The method according to claim 46, characterized in that, The second semiconductor layer is characterized by having a first gradient doping concentration, which is a gradient that linearly increases from the first doping concentration to the third doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

49. The method according to claim 46, characterized in that, The third semiconductor layer is characterized by having a second gradient doping concentration, which is a gradient that increases linearly from a third doping concentration to the second doping concentration, wherein the third doping concentration is greater than the first doping concentration and less than the second doping concentration.

50. The method according to claim 46, characterized in that, The second doping concentration is greater than the first doping concentration.

51. The method according to claim 45, characterized in that, The marking layer comprises silicon or AlGaN.

52. The method according to claim 45, characterized in that, The marking layer has a thickness in the range of 5 nm to 10 nm.

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