Method of providing trench isolation and semiconductor device
CN113851420BActive Publication Date: 2026-07-07TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
- Filing Date
- 2020-12-14
- Publication Date
- 2026-07-07
AI Technical Summary
Technical Problem
In existing CMOS processes, deep trench isolation may have defects and unreliability when not planarized, and additional chemical mechanical polishing processes will increase manufacturing time, complexity and cost.
Method used
Deep trenches are formed before shallow trenches are formed, and both deep and shallow trenches are polished in the same chemical mechanical polishing process. Annealing is then performed before material is deposited in the active region of the silicon wafer to repair damage.
Benefits of technology
By sealing the upper surface of deep trenches, defects are reduced, manufacturing costs are lowered, and manufacturing efficiency and cycle time are improved by simplifying process steps.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN113851420B_ABST
Abstract
A method of providing trench isolation includes the following steps. One or more semiconductor processing tools can form a deep trench within a silicon wafer. The one or more semiconductor processing tools can deposit a first insulating material within the deep trench. After forming the deep trench within the silicon wafer, the one or more semiconductor processing tools can form a shallow trench above the deep trench. The one or more semiconductor processing tools can deposit a second insulating material within the shallow trench. A semiconductor device having a deep trench and a shallow trench is also provided.
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