Method of forming a semiconductor element

Abstract

A method of forming a semiconductor device includes depositing a film on a dielectric layer. The dielectric layer is over a first fin and a second fin and within a trench between the first fin and the second fin. The method further includes etching a top portion of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portion of the film, and filling the trench on a remaining portion of the film. The treatment includes bombarding the dielectric layer with radicals.

Description

Technical Field

[0001] This disclosure pertains to semiconductor devices and their fabrication methods. Background Technology

[0002] Semiconductor components are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor components are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate, and then using photolithography to pattern each material layer to form circuit components and elements on these material layers.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0004] One embodiment of this disclosure provides a method for forming a semiconductor device, comprising: depositing a film on a dielectric layer, the dielectric layer being located on a first fin and a second fin, and within a trench between the first fin and the second fin; etching a top of the film; after etching the top of the film, performing a process on the dielectric layer to remove impurities, the process comprising bombarding the dielectric layer with free radicals; and filling a trench on a retained portion of the film.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor device, comprising: depositing a dielectric layer on a first fin and a second fin, the dielectric layer covering the sidewalls and bottom surface of a trench between the first fin and the second fin; forming a first film on the dielectric layer; etching the top of the first film; removing a first impurity from the surface of the dielectric layer by free radical bombardment, and forming a first oxide layer on a retained portion of the first film by bombardment; performing a chemical oxide removal process to remove the first oxide layer; and filling the trench after performing the chemical oxide removal process.

[0006] Another embodiment of this disclosure provides a method for forming a semiconductor device, comprising the following steps: forming a first fin and a second fin, the first fin and the second fin extending from a substrate; forming a dummy dielectric layer on exposed surfaces of the first fin, the second fin and the substrate; forming a dummy gate on the first fin and the second fin, the formation of the dummy gate comprising a first cycle including: depositing a first film on the dummy dielectric layer; etching the top of the first film; removing a first impurity from the surface of the dummy dielectric layer by bombardment with hydroxyl radicals or oxygen radicals; forming an interlayer dielectric on the first fin and the second fin; and removing the dummy gate. Attached Figure Description

[0007] The various features of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 An example of a FinFET perspective diagram according to some embodiments is shown;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 A cross-sectional view of an early intermediate stage of FinFET fabrication according to some embodiments;

[0010] Figure 13 , Figure 14 , Figure 15A , Figure 15B and Figure 16 A flowchart illustrating a method for filling gaps between fins according to some embodiments is shown;

[0011] Figure 17 , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 20C , Figure 20D , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 24A , Figure 24B , Figure 24C , Figure 25A , Figure 25B , Figure 26A and Figure 26B This is a cross-sectional view of a late intermediate stage of FinFET fabrication according to some embodiments.

[0012] [Symbol Explanation]

[0013] 50: Substrate

[0014] 50N: n-type region

[0015] 50P:p-type area

[0016] 51: Divider

[0017] 52: Fins

[0018] 54: Insulating materials

[0019] 55: Trench

[0020] 56: Isolation Area

[0021] 58: Dummy Dielectric Layer

[0022] 60: First membrane

[0023] 62: Dummy gate layer

[0024] 64: Masking layer

[0025] 66: Passage Area

[0026] 72: Dummy gate

[0027] 74: Mask

[0028] 80: Gate sealing spacer

[0029] 82: Source / Drain Region

[0030] 86: Gate spacer

[0031] 87: Contact Etching Termination Layer

[0032] 88: First interlayer dielectric

[0033] 89: Area

[0034] 90: concave part

[0035] 92: Gate dielectric layer

[0036] 94: Gate electrode

[0037] 94A: Padding layer

[0038] 94B: Power Function Tuning Layer

[0039] 94C: Filler material

[0040] 96: Gate mask

[0041] 108: Interlayer dielectric

[0042] 110: Gate contact

[0043] 112: Source / Drain Contact

[0044] 158: Oxide layer

[0045] 190: Residual impurities

[0046] 200: Processing

[0047] 300: Chemical Oxide Removal Process

[0048] 1000: Method

[0049] 1010: Steps

[0050] 1020: Steps

[0051] 1030: Steps

[0052] 1040: Steps

[0053] 1050: Steps

[0054] 2000: Method

[0055] 2010: Steps

[0056] 2020: Steps

[0057] 2030: Steps

[0058] 2040: Steps

[0059] 3000: Method

[0060] 3010: Steps

[0061] 3020: Steps

[0062] 3030: Steps

[0063] 3040: Steps

[0064] 3100: Method

[0065] 3110: Steps

[0066] 3120: Steps

[0067] 3130: Steps

[0068] 3140: Steps

[0069] 3150: Steps

[0070] 4000: Method

[0071] 4010: Steps

[0072] 4020: Steps

[0073] 4030: Steps

[0074] 4040: Steps

[0075] AA: Section

[0076] BB: Section

[0077] CC: Section

[0078] D1: Depth Detailed Implementation

[0079] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0080] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0081] Embodiments will now be described with reference to specific examples, wherein, in the manufacture of semiconductor devices, a process is used to remove impurities from a film as part of a gap-filling process. However, the described embodiments are not intended to be limited to those described herein, but can be used in a wide variety of embodiments.

[0082] Figure 1 An example of a three-dimensional view of a FinFET according to some embodiments is shown. The FinFET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and fins 52 protrude over and between adjacent isolation regions 56. Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" may be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Additionally, although fins 52 are shown as a single continuous material identical to the substrate 50, fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this document, fins 52 refer to the portion extending between adjacent isolation regions 56.

[0083] The gate dielectric layer 92 runs along the sidewalls and is above the top surface of the fin 52, while the gate electrode 94 is above the gate dielectric layer 92. The source / drain regions 82 are disposed on opposite sides of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 Reference cross sections used in the following figures are further illustrated. Cross section AA is along the longitudinal axis of the gate electrode 94 and in a direction, for example, perpendicular to the current flow direction between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 and in a direction, for example, between the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions of the FinFET. For clarity, subsequent figures refer to these reference cross sections.

[0084] Some embodiments discussed herein are presented in the context of FinFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments contemplate patterns used in planar devices, such as planar FETs, nanostructured field-effect transistors (NSFETs) (e.g., nanosheets, nanowires, all-around gate, etc.), etc.

[0085] Figures 2 to 12 and Figures 17 to 26B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET according to some embodiments. In addition to multiple fins / FinFETs, Figures 2 to 12 It shows Figure 1 The reference cross section AA is shown. In addition to multiple fins / FinFETs, Figure 17 , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A and Figure 26A along Figure 1 The reference section AA is shown, and Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 24C , Figure 25B and Figure 26B along Figure 1 A similar cross-section BB is shown. In addition to multiple fins / FinFETs, Figure 20C and Figure 20D along Figure 1The reference section CC is shown.

[0086] exist Figure 2 The substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, the SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide, and / or combinations thereof.

[0087] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, for example, an n-type FinFET. The p-type region 50P can be used to form p-type devices, such as PMOS transistors, for example, a p-type FinFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be provided between the n-type region 50N and the p-type region 50P.

[0088] exist Figure 3 In this embodiment, fins 52 are formed in the substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic.

[0089] The fins can be patterned using any suitable method. For example, one or more photolithography processes can be used to pattern the fins 52, including dual patterning or multiple patterning processes. Typically, dual or multiple patterning processes combine photolithography with self-aligned processes, allowing the creation of patterns with pitches, for example, smaller than those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer formed over a substrate is patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) may be retained on the fins 52.

[0090] exist Figure 4 In this embodiment, an insulating material 54 is formed over the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon oxide, nitrides, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system and post-curing to transform it into another material, such as an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In the embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surface of the substrate 50 and the fins 52. A filler material, such as the filler material described above, may then be formed on the liner.

[0091] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fin 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, or a combination thereof, may be used. The planarization process exposes the fin 52 such that, after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are horizontal. In embodiments where a mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the mask or the top surfaces of the fin 52 and the insulating material 54 are horizontal.

[0092] exist Figure 6In this process, the insulating material 54 is recessed to form shallow trench isolation (STI) regions (isolation regions 56). The insulating material 54 is recessed so that the upper portions of the fins 52 in the n-type region 50N and p-type region 50P protrude from between adjacent isolation regions 56. Furthermore, the top surface of the isolation region 56 may have a planar, convex, concave (e.g., bulging) surface, or a combination thereof, as shown. The top surface of the isolation region 56 can be formed as flat, convex, and / or concave by appropriate etching. The isolation region 56 can be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fins 52). For example, it can be removed using an oxide, such as that using dilute hydrofluoric acid (dHF).

[0093] like Figure 6 As shown, grooves 55 can be formed between adjacent fins 52. Each groove 55 may have a bottom surface on the top surface of the corresponding isolation region 56 and a side surface on the sidewall of the corresponding fin 52. In some embodiments, the groove 55 may have a depth-to-width ratio in the range of about 3 to about 9. The height of the groove 55 is equal to the height of the fin 52, and the width is equal to the width of the isolation region 56 disposed between adjacent fins 52.

[0094] Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed via an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepic epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepic epitaxial structure protrudes from the dielectric layer to form the fin. Additionally, in some embodiments, heteroepic epitaxial structures can be used for the fin 52. For example, a heteroepic epitaxial structure can be used. Figure 5 The fins 52 are recessed, and a different material from the fins 52 can be epitaxially grown on the recessed fins 52. In these embodiments, the fins 52 include a recessed material and an epitaxial growth material disposed above the recessed material. In another embodiment, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer. Heterogeneous epitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepigraphic structure protrudes from the dielectric layer to form the fins 52. In some embodiments of epitaxial growth of homoepigraphic or heteroepigraphic structures, although in-situ and implantation doping can be used together, the epitaxial growth material can be doped in-situ during growth, eliminating the need for prior and subsequent implantation.

[0095] Furthermore, it may be advantageous to epitaxially grow a different material in the n-type region 50N (e.g., an NMOS region) than in the p-type region 50P (e.g., a PMOS region). In various embodiments, the upper portion of the fin 52 may be made of silicon-germanium (Si... x Ge 1-x The semiconductor can be formed from materials such as silicon carbide, pure or substantially pure germanium, group III to group V compound semiconductors, and group II to group VI compound semiconductors. For example, materials that can be used to form group III to group V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, and gallium phosphide.

[0096] Further in Figure 6 In this process, suitable wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in the n-type region 50N and an N-well may be formed in the p-type region 50P. In some embodiments, either a P-well or an N-well may be formed in both the n-type region 50N and the p-type region 50P.

[0097] In embodiments with different trap types, photoresist and / or other masks (not shown) can be used to implement different implantation steps for the n-type region 50N and the p-type region 50P. For example, photoresist can be formed over the fins 52 and the isolation region 56 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P of the substrate 50. The photoresist can be formed using a spin coating technique and can be patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurities are implanted in the p-type region 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into the n-type region 50N. The n-type impurities can be phosphorus, arsenic, antimony, etc., implanted into the region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 With about 10 18 cm -3 Between. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0098] After implanting the p-type region 50P, a photoresist is formed over the fins 52 and isolation region 56 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist can be formed using spin coating technology, and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurities can be implanted in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., in the implanted region, with a concentration equal to or less than 10. 18 cm -3 For example, in about 10 16 cm -3 With about 10 18 cm -3 Between. After implantation, photoresist can be removed, for example, through an acceptable ashing process.

[0099] After the implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, although in-situ and implantation doping can be used together, the growth material of the epitaxial fins can be in-situ doped during growth, which can eliminate implantation.

[0100] exist Figure 7 In this embodiment, a dummy dielectric layer 58 is formed on the fins 52. The dummy dielectric layer 58 may be, for example, silicon oxide, silicon nitride, or a combination thereof, and may be deposited and / or chemically grown on the fins 52, or conformally deposited by means of plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any suitable deposition technique. It should be noted that the dummy dielectric layer 58 shown covering the fins 52 and the isolation region 56 is for illustrative purposes only. In some embodiments, the dummy dielectric layer 58 may be thermally grown according to acceptable techniques such that the dummy dielectric layer 58 covers only the fins 52 and does not extend between the fins 52 above the isolation region 56. In some embodiments, residual impurities (not shown) such as cleaning processes or etching processes may be present on the exposed surface of the dummy dielectric layer 58 before the formation of the first film 60, or as residues of halogen-containing precursors for forming the dummy dielectric layer 58, such as chlorosilanes or dichlorosilanes.

[0101] exist Figure 8 In this process, a first film 60 is formed on a dummy dielectric layer 58. The first film 60 may be formed as a seed layer to utilize, for example, a subsequently deposited dummy gate layer (such as dummy gate layer 62, hereinafter referred to). Figure 12(Discussion) to assist in filling the gaps in trench 55. The first film 60 can be selected based on the material of the dummy gate layer 62. In embodiments where the dummy gate layer 62 includes silicon (e.g., polycrystalline silicon, amorphous silicon (a-Si), etc.), the first film 60 may be a silicon-containing film. In some embodiments, the first film 60 may include polycrystalline silicon or amorphous silicon. The material of the first film 60 can be deposited by conformal deposition processes such as remote plasma CVD (RPCVD), low-pressure CVD (LPCVD), CVD, PECVD, ALD, plasma-enhanced ALD (PEALD), or any suitable deposition process that can be performed in a processing chamber. The first film 60 can be deposited to a thickness in the range of about 1 nm to about 100 nm.

[0102] In embodiments where the first film 60 is deposited by CVD (e.g., RPCVD), a silicon-containing precursor can be used in the deposition process to form the first film 60. Suitable silicon-containing precursors may include silanes, etc. Silanes may include silane (SiH4), silane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H6), etc. 10 Experimental Si x H (2x+2) Higher-order silanes (where x>3), including dimethylaminosilane (SiH3[N(CH3)2], DMAS), ethylmethylaminosilane (SiH3[N(CH3C2H5)], EMAS), diethylaminosilane (SiH3[N(C2H5)2], DEAS), ethylisopropylaminosilane (SiH3[N(C2H5C3H7)], EIPAS), di(isopropylamino)silane (SiH3[N(C3H7)2], DIPAS), dipropylaminosilane (SiH3[N(C3H7)2], DPAS), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and chlorosilane (SiH3Cl). Silicon-containing precursors can be provided at flow rates from about 10 sccm to about 5000 sccm.

[0103] During the deposition process of the first membrane 60, the processing chamber may be maintained at a temperature of about 100˚C to about 750˚C, for example, about 300˚C to about 700˚C. During the deposition of the first membrane 60, the processing chamber may be maintained at a pressure of about 0.1 Torr to about 0.5 Torr.

[0104] Then, in Figure 9In this process, the material of the first film 60 is etched using an appropriate etching process, which may leave residual impurities 190 on the exposed surface of the dummy dielectric layer 58. The etching process can be performed in situ in the same processing chamber as the deposition process or in a different processing chamber. The etching process can be performed using an etchant gas (e.g., a halogen-containing etchant gas), which may include chlorine (Cl2), hydrogen chloride (HCl), fluorine (F2), hydrogen bromide (HBr), bromine (Br), or combinations thereof. In some embodiments, the etchant gas can be supplied to the processing chamber at a rate of about 0.01 slm to about 5 slm.

[0105] The etchant gas can be mixed with an additional gas, such as a carrier gas, a reactive gas, or both. For example, the additional gas may include hydrogen (H2), nitrogen (N2), argon (Ar), or combinations thereof. The additional gas can be supplied at a flow rate of less than about 20 slm.

[0106] During the etching process, the processing chamber can be maintained in a temperature range of about 100˚C to about 700˚C. In embodiments where the etchant gas includes hydrogen chloride, the processing chamber can be maintained in a temperature range of about 500˚C to about 650˚C. In embodiments where the etchant gas includes chlorine, the processing chamber can be maintained in a temperature range of about 300˚C to about 450˚C. During the etching process, the processing chamber can be maintained at a pressure of about 0.1 Torr to about 200 Torr.

[0107] The etching process can remove portions of the first film 60 disposed on the top surface and upper sidewalls of the fin 52 at a rate greater than the etching process can remove portions of the first film 60 disposed at the bottom of the trench 55. For example, due to the aspect ratio of the trench 55, the etchant gas may not penetrate to the bottom of the trench 55 as easily as it penetrates to the top, resulting in a greater degree of etching at the top than at the bottom. After each deposition process, the etching process can continue for a period of time sufficient to completely remove the first film 60 from the top surface and upper sidewalls of the dummy dielectric layer 58. In various embodiments, the first film 60 can be removed from the dummy dielectric layer 58 to a depth D1 of approximately 1 nm to approximately 50 nm below the top surface of the dummy dielectric layer 58.

[0108] Residual impurities 190 may remain on the exposed surface of the dummy dielectric layer 58 above the etched film 160. In some embodiments, residual impurities 190 include halogens, such as chlorine, fluorine, bromine, or combinations thereof. As described above, residual impurities 190 may remain in the etching process that removes a portion of the first film 60.

[0109] exist Figure 10In this process, a treatment 200 (sometimes referred to as a seed enhancement treatment) is performed on the dummy dielectric layer 58 to remove residual impurities 190. In some embodiments, treatment 200 includes bombarding the dummy dielectric layer 58 with free radicals, any suitable free radicals being feasible, such as hydroxyl radicals (OH*) and / or oxygen radicals (O*). The free radicals can react with the residual impurities 190 to remove them from the surface of the dummy dielectric layer 58. Removing at least some of the residual impurities 190 can reduce the surface roughness of the subsequently formed film, which can help achieve better subsequent gap filling of the trench 55 by preventing or reducing voids formed in the gap-filling material in the trench 55.

[0110] Processing 200 can be performed by supplying a processing gas (such as a gas comprising oxygen (O2) and hydrogen (H2)) into the processing chamber. Free radicals can be generated through the chemical reaction of O2 and H2. The O2:H2 ratio can range from about 0.1% to about 99.9%. The processing gas can be supplied at a flow rate of about 10 sccm to about 5000 sccm, which is beneficial for removing residual impurities 190 and reducing the surface roughness of the subsequently formed film, thereby improving gap filling. Supplying the processing gas at a flow rate less than about 10 sccm may be disadvantageous because less residual impurities 190 can be removed, resulting in greater surface roughness and poorer gap filling ability in the subsequently formed film. Supplying the processing gas at a flow rate greater than about 5000 sccm may be disadvantageous because this may exceed the operating parameters of the tool used.

[0111] Treatment 200 can be performed in a temperature range of approximately 300˚C to approximately 900˚C. This is beneficial for removing residual impurities 190 and reducing the surface roughness of the subsequently formed film, thereby improving gap filling. Performing treatment 200 at temperatures below approximately 300˚C may be disadvantageous because it generates fewer OH* and / or O* free radicals and removes fewer residual impurities 190, resulting in greater surface roughness and poorer gap filling ability in the subsequently formed film. Performing treatment 200 at temperatures above approximately 900˚C may be disadvantageous because it may lead to excessively rapid oxidation rates and may exceed the operating parameters of the tools used.

[0112] Process 200 can be performed at pressures ranging from about 0.01 Torr to about 760 Torr. This is beneficial for removing residual impurities 190 and reducing the surface roughness of the subsequently formed membrane, thereby improving gap filling. Performing process 200 at pressures below about 0.01 Torr may be disadvantageous because it removes less residual impurities 190, resulting in greater surface roughness and poorer gap filling ability in the subsequently formed membrane. Performing process 200 at pressures above about 760 Torr may be disadvantageous because it may exceed the operating parameters of the tools used and create safety hazards.

[0113] The duration of process 200 can range from approximately 0.01 hours to approximately 10 hours. This facilitates the removal of residual impurities 190 and reduces the surface roughness of the subsequently formed film, thereby improving gap filling. Performing process 200 for less than approximately 0.01 hours may be disadvantageous, as it removes less residual impurities 190, resulting in greater surface roughness and poorer gap filling capability in the subsequently formed film. Performing process 200 for more than approximately 10 hours may be disadvantageous, as it may lead to low yield and high cost.

[0114] In some embodiments, process 200 may produce an oxide layer 158 on the first film 60. The oxide layer 158 may be formed by oxidizing OH* and / or O* free radicals on the surface of the first film 60 by process 200. In some embodiments where the first film 60 comprises silicon, the oxide layer 158 comprises silicon oxide (SiO) and / or silicon dioxide (SiO2). The oxide layer 158 may have a thickness in the range of about 0.5 nanometers to about 10 nanometers. See below for reference. Figure 11 The oxide layer 158 can be removed by a chemical oxide removal process 300.

[0115] exist Figure 11 In some embodiments where oxide layer 158 is formed, a chemical oxide removal process 300 is performed to remove oxide layer 158. In other embodiments, the chemical oxide removal process 300 may be omitted. Removing oxide layer 158 allows subsequent gap filling to fill trench 55 with a uniform material, as shown in the following references. Figure 12 The dummy gate layer 62 is described. This may be useful for the subsequent removal of the dummy gate layer 62. See the following reference... Figure 23A and Figure 23B This is beneficial for the subsequent removal of the dummy gate layer 62 through a selective etching process.

[0116] In some embodiments, the chemical oxide removal process 300 includes treatment with a gas comprising ammonia (NH3), hydrogen fluoride (HF), nitrogen trifluoride (NF3), or combinations thereof. The chemical oxide removal process 300 can be performed in a temperature range of about 10˚C to about 90˚C, which is beneficial for removing the oxide layer 158 and improving the uniformity of subsequent crevice filling. Performing the chemical oxide removal process 300 at temperatures below about 10˚C may be disadvantageous because this may exceed the operating parameters of the tools used. Performing the treatment 200 at temperatures above about 90˚C may be disadvantageous because this may result in an oxidation removal rate of almost zero.

[0117] The chemical oxide removal process 300 can be performed within a pressure range of approximately 0.1 Torr to approximately 5.0 Torr, which is beneficial for removing the oxide layer 158 and improving the uniformity of subsequent gap filling. Performing the chemical oxide removal process 300 at temperatures below approximately 0.1 Torr may be disadvantageous, as this may exceed the operating parameters of the tools used. Performing the treatment 200 at temperatures above approximately 5.0 Torr may be disadvantageous, as this may exceed the operating parameters of the tools used and pose a safety hazard.

[0118] The duration of the chemical oxide removal process 300 can range from about 0.1 minutes to about 60 minutes, which is beneficial for removing the oxide layer 158 and improving the uniformity of subsequent gap filling. A duration of less than about 0.1 minutes for the chemical oxide removal process 300 may be disadvantageous because it may not react completely with the oxide layer 158. A duration of more than about 60 minutes for the process 200 may be disadvantageous because the etching amount may be saturated due to byproducts of the process 200.

[0119] exist Figure 12 In this process, a dummy gate layer 62, including a first film 60, is formed over a dummy dielectric layer 58, thereby filling the trench 55. The dummy gate layer 62 may be a conductive or non-conductive material, and may be selected from the group consisting of: amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals.

[0120] In some embodiments, the lower portion of the dummy gate layer 62 can be formed by a cyclic fill process comprising multiple cycles of deposition, etching, processing, and chemical oxide removal steps to fill the trench 55 by the cyclic fill process comprising multiple cycles of deposition, etching, processing, and chemical oxide removal steps. The cyclic fill process can be performed in a processing chamber. For example, one cycle of the cyclic fill process may include a deposition step, an etching step, a processing step, and a chemical oxide removal step. The deposition step can be performed by a method similar to the deposition of the first film 60, as referred to above. Figure 8The etching step can be performed using a method similar to the etching of the first film 60, as described above. Figure 9 The processing steps described above can be performed in a similar manner to those for processing 200, as referred to above. Figure 10 The chemical oxide removal step can be performed using a method similar to that of the chemical oxide removal process 300, as described above. Figure 11 In some embodiments, the processing steps and / or chemical oxide removal steps may be omitted in one or more cycles.

[0121] The cyclic filling process can be performed for 1 to 10 cycles, in which more material is deposited along the sidewalls and bottom of the trench 55 in each cycle. In some embodiments, each cycle deposits a layer with a thickness ranging from about 1 nanometer to about 100 nanometers. The cyclic filling process can continue until material is deposited to a depth ranging from about 1 nanometer to about 100 nanometers in the trench 55, such that the aspect ratio of the remaining unfilled portion of the trench 55 is less than about 1.5.

[0122] Once the cycle-fill process is complete, the upper portion of the dummy gate layer 62 can be deposited using a separate deposition process, such as physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. After the dummy gate layer 62 is deposited over the dummy dielectric layer 58, it can be planarized, for example, by CMP.

[0123] Figure 13 An embodiment of method 1000 is shown, which is used to fill gaps (e.g., trenches 55) between fins (e.g., fins 52) covered by a dielectric layer (e.g., a dummy dielectric layer 58), such as... Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 As shown. In step 1010, a first film 60 is deposited on the dummy dielectric layer 58, as described above. Figure 8 As described above. In step 1020, the top of the first film 60 is removed by an etching process, as referred to above. Figure 9 As described above. In step 1030, process 200 is performed to remove residual impurities 190 on the dummy dielectric layer 58. Figure 10 As described above. In step 1040, the oxide (e.g., oxide layer 158) formed by treatment 200 is removed by a chemical oxide removal (COR) process 300, as referred to above. Figure 11As described above. In step 1050, the retained portion of the first film 60 is used as a seed layer to fill the trench 55, such as by a cyclic deposition-etch-process-chemical oxide deposition (COR)-deposition process including repeated steps 1010, 1020, 1030, and 1040, until the aspect ratio of the trench 55 is less than about 1.5, as referred to above. Figure 12 However, any suitable gap-filling process can be used.

[0124] Figure 14 An embodiment of another method 2000 is shown, which is used to fill gaps (e.g., trenches 55) between fins (e.g., fin 52) covered by a dielectric layer (e.g., dummy dielectric layer 58). Method 2000 is similar to the above reference. Figure 13 The method 1000 omits the step of removing the oxides formed during the chemical oxide removal process. In step 2010, a first film 60 is deposited on the dummy dielectric layer 58, as described above. Figure 8 As described above. In step 2020, the top of the first film 60 is removed by an etching process, as referred to above. Figure 9 As described above. In step 2030, process 200 is performed to remove residual impurities 190 on the dummy dielectric layer 58. Figure 10 As described above. In step 2040, the retained portion of the first membrane 60 is used as a seed layer to fill the trench 55.

[0125] Figure 15A An embodiment of yet another method 3000 is shown, which is used to fill gaps (e.g., trenches 55) between fins (e.g., fin 52) covered by a dielectric layer (e.g., dummy dielectric layer 58), such as Figure 8 , Figure 9 and Figure 10 As shown. Method 3000 is similar to the above reference. Figure 13 The method 1000 omits the steps of removing the oxides formed by the chemical oxide removal process and filling the trenches 55 in step 3040. In step 3010, a first film 60 is deposited on the dummy dielectric layer 58, as described above. Figure 8 As described above. In step 3020, the top of the first film 60 is removed by an etching process. Figure 9 As described above. In step 3030, process 200 is performed to remove residual impurities 190 on the dummy dielectric layer 58. Figure 10As described above. In step 3040, trench 55 is filled by a cyclic deposition-etch-processing-deposition process including repeating steps 3010, 3020 and 3030 until trench 55 is fully filled, such as when material has been deposited in trench 55 to a depth in the range of about 1 nanometer to about 50 nanometers.

[0126] Figure 15B An embodiment of another method 3100 is shown, which is used to fill gaps (e.g., trenches 55) between fins (e.g., fin 52) covered by a dielectric layer (e.g., dummy dielectric layer 58). Method 3100 is similar to the above reference. Figure 15A The method 3000, in addition to including the step of removing the oxides formed during the process by a chemical oxide removal process, involves depositing a first film 60 on a dummy dielectric layer 58 in step 3110, as described above. Figure 8 As described above. In step 3120, the top of the first film 60 is removed by an etching process, as referred to above. Figure 9 As described above. In step 3130, process 200 is performed to remove residual impurities 190 on the dummy dielectric layer 58. Figure 10 As described above. In step 3140, the oxide (e.g., oxide layer 158) formed in treatment 200 is removed by a chemical oxide removal (COR) process 300, as referred to above. Figure 11 As described above. In step 3150, trench 55 is filled by a cyclic deposition-etch-processing-deposition process including repeating steps 3110, 3120, 3130 and 3140 until trench 55 is fully filled, such as when material has been deposited in trench 55 to a depth in the range of about 1 nanometer to about 50 nanometers.

[0127] Figure 16 An embodiment of another method 4000 is shown, which is used to fill gaps (e.g., trenches 55) between fins (e.g., fins 52) covered by a dielectric layer (e.g., a dummy dielectric layer 58). Except for the step of performing a process for removing impurities, which is performed before the steps of depositing and etching the film, method 4000 is similar to the above-described reference. Figure 14 The method described in 2000. Impurities may be present on the exposed surface of the dielectric layer, generated by existing processes such as cleaning processes, etching processes, or as residues of halogen-containing precursors for forming the dielectric layer, such as chlorosilanes or dichlorosilanes, as referred to above. Figure 7 As described above. In step 4010, process 200 is performed to remove impurities remaining on the dummy dielectric layer 58 from the previous process, as referred to above. Figure 10 As described above. In step 4020, the first film 60 is deposited on the dummy dielectric layer 58, as referred to above. Figure 8 As described above. In step 4030, the top of the first film 60 is removed by an etching process. Figure 9 As described above. In step 4040, the retained portion of the first membrane 60 is used as a seed layer to fill the trench 55.

[0128] exist Figure 17 In this process, a masking layer 64 is deposited on the dummy gate layer 62. The masking layer 64 may include one or more layers, such as silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 62 and a single masking layer 64 are formed on the n-type region 50N and the p-type region 50P. Figure 17 In the example shown, a single dummy gate layer 62 and a single mask layer 64 are formed on the n-type region 50N and the p-type region 50P. However, in other embodiments, different dummy gate layers and mask layers, each having one or more layers, can be formed in the n-type region 50N and the p-type region 50P. Figures 18A to 26B Various additional steps for manufacturing the components of the embodiments are shown. Figures 18A to 26B Features of either the n-type region 50N or the p-type region 50P are shown. For example, Figures 18A to 26B The structure shown is applicable to both n-type region 50N and p-type region 50P. The structural differences between n-type region 50N and p-type region 50P (if any) are described in the accompanying text to each figure.

[0129] exist Figure 18A and Figure 18B In this process, acceptable photolithography and etching techniques can be used to process the mask layer 64 (see...). Figure 17 The mask 74 is patterned to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 58 to form the dummy gate 72 using an acceptable etching technique. The dummy gate 72 covers the respective channel regions 66 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The length direction of the dummy gate 72 can also be substantially perpendicular to the length direction of the respective epitaxial fin 52.

[0130] Furthermore, in Figure 18A and Figure 18B In this process, a gate sealing spacer 80 can be formed on the exposed surfaces of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacer 80 can be formed by thermal oxidation or deposition following anisotropic etching. The gate sealing spacer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc.

[0131] After forming the gate sealing spacer 80, placement for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different element types, this is similar to the above. Figure 6 The implantation discussed earlier can involve forming a mask (e.g., photoresist) over the n-type region 50N while exposing the p-type region 50P, and implanting an appropriate type (e.g., p-type) impurity into the exposed fin 52 in the p-type region 50P. The mask can then be removed. Subsequently, while exposing the n-type region 50N, a mask such as photoresist can be formed over the p-type region 50P, and an appropriate type (e.g., n-type) impurity can be implanted into the exposed fin 52 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The impurity concentration of the lightly doped source / drain regions can be approximately 10. 15 cm -3 To about 10 19 cm -3 Annealing can be used to repair damaged fabric and activate impurities in the fabric.

[0132] exist Figure 19A and Figure 19B In this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the shield 74. The gate spacer 86 can be formed by conformally depositing an insulating material and anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof.

[0133] Note that the above description generally outlines the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and different step sequences can be employed (e.g., the gate seal spacer 80 can be left unetched before forming the gate spacer 86, creating an "L-shaped" gate seal spacer; spacers can be formed and removed, etc.). Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device can be formed before forming the gate seal spacer 80, and the LDD region for a p-type device can be formed after forming the gate seal spacer 80.

[0134] exist Figure 20A and Figure 20BIn this process, epitaxial source / drain regions 82 are formed in fin 52. The epitaxial source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is disposed between adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend within and through fin 52. In some embodiments, gate spacers 86 are used to space the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short-circuit the gate of the subsequently formed FinFET. The material of the epitaxial source / drain regions 82 can be selected to apply stress in the respective channel regions 66, thereby improving performance.

[0135] Epitaxial source / drain regions 82 can be formed in the n-type region 50N by masking the p-type region 50P and etching the source / drain regions of the fin 52 in the n-type region 50N, thereby forming a recess in the fin 52. The epitaxial source / drain regions 82 in the n-type region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can comprise any acceptable material, such as materials suitable for n-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the n-type region 50N can comprise a material for applying tensile strain in the channel region 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain regions 82 in the n-type region 50N may have a surface higher than the corresponding surface of the fin 52 and may have facets.

[0136] The source / drain regions of the fin 52 in the n-type region 50N can be masked and etched in the p-type region 50P to form an epitaxial source / drain region 82 in the p-type region 50P, thereby forming a recess in the fin 52. The epitaxial source / drain region 82 in the p-type region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 82 can comprise any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain region 82 in the p-type region 50P can comprise a material to which compressive strain is applied in the channel region 66, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 82 in the p-type region 50P can have a surface higher than the corresponding surface of the fin 52 and can have facets.

[0137] The epitaxial source / drain regions 82 and / or fins 52 can be doped to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The impurity concentration of the source / drain regions can be around 10. 19 cm -3 With about 10 21 cm -3Between. The n-type and / or p-type impurities used for the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0138] Due to the epitaxial process used to form the epitaxial source / drain regions 82 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 82 has facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, the facets combine adjacent source / drain regions 82 of the same FinFET, such as... Figure 20C As shown. In other embodiments, after the epitaxial process is completed, adjacent source / drain regions 82 remain separated, as shown. Figure 20D As shown. In Figure 20C and Figure 20D In the illustrated embodiment, gate spacers 86 are formed as part of the sidewalls of fins 52 that extend over isolation regions 56, thereby blocking epitaxial growth. In some other embodiments, the spacer etchant used to form the gate spacers 86 may be adjusted to remove spacer material, allowing the area for epitaxial growth to extend to the surface of the isolation regions 56.

[0139] exist Figure 21A and Figure 21B In the middle, the first interlayer dielectric (ILD) 88 is deposited on Figure 20A and Figure 20B The structure shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped-silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain regions 82, between the mask 74, and between the gate spacers 86. The CESL 87 may include a dielectric material with a lower etch rate than the material covering the first ILD 88, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0140] exist Figure 22A and Figure 22BIn this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, as well as a portion of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surface of the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the first ILD 88 are flush. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0141] exist Figure 23A and Figure 23B In the etching step, the dummy gate 72 and the mask 74 (if present) are removed, thereby forming the recess 90. A portion of the dummy dielectric layer 58 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, leaving the dummy dielectric layer 58 exposed by the recess 90. In some embodiments, the dummy dielectric layer 58 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and remains in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 while little or no etching of the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or covers the channel region 66 of each fin 52. Each channel region 66 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 58 can be used as an etch stop layer when the dummy gate 72 is formed. Then, after removing the dummy gate 72, the dummy dielectric layer 58 can optionally be removed.

[0142] exist Figure 24A and Figure 24B In the process, a gate dielectric layer 92 and a gate electrode 94 are formed to replace the gate. Figure 24C It shows Figure 24BA detailed view of region 89. One or more gate dielectric layers 92 are deposited in the recess 90, such as on the top surface and sidewalls of the fin 52 and on the sidewalls of the gate sealing spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. In some embodiments, the gate dielectric layer 92 includes one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, etc. For example, in some embodiments, the gate dielectric layer 92 includes a silicon oxide interface layer formed by thermal or chemical oxidation and a high-k dielectric material covered thereon, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof. The gate dielectric layer 92 may include a dielectric layer having a k value greater than about 7.0. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, etc. In embodiments where a portion of the dummy gate dielectric layer 58 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy gate dielectric layer 58 (e.g., SiO2).

[0143] Gate electrodes 94 are deposited over the gate dielectric layer 92 and fill the reserved portion of the recess 90. Gate electrodes 94 may comprise metal-containing materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, and combinations thereof or multiple layers. For example, although in Figure 24B The diagram shows a single-layer gate electrode 94, but the gate electrode 94 may include any number of pad layers 94A, any number of work function tuning layers 94B, and filler material 94C, such as... Figure 24C As shown. After filling the recess 90, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 92 and the material of the gate electrode 94, which are located above the top surface of the first ILD 88. The remaining portions of the material of the gate electrode 94 and the gate dielectric layer 92 thus form the replacement gate of the resulting FinFET. The gate electrode 94 and the gate dielectric layer 92 can be collectively referred to as the “gate stack”. The gate and the gate stack can extend along the sidewalls of the channel region 66 of the fin 52.

[0144] Gate dielectric layers 92 can be formed simultaneously in both the n-type region 50N and the p-type region 50P, such that the gate dielectric layers 92 in each region are formed of the same material, and the formation of gate electrodes 94 can occur simultaneously, such that the gate electrodes 94 in each region are formed of the same material. In some embodiments, the gate dielectric layers 92 in each region can be formed using different processes, such that the gate dielectric layers 92 can be formed of different materials, and / or the gate electrodes 94 in each region can be formed using different processes, such that the gate electrodes 94 can be formed of different materials. When using different processes, various masking steps can be used to mask and expose appropriate areas.

[0145] exist Figure 25A and Figure 25B In this configuration, a gate mask 96 is formed on the gate stack (including a gate dielectric layer 92 and a corresponding gate electrode 94), and the gate mask 96 may be disposed between opposing portions of the gate spacers 86. In some embodiments, forming the gate mask 96 includes recessing the gate stack to directly form a recess over the gate stack and between opposing portions of the gate spacers 86. The gate mask 96, comprising one or more layers of dielectric material (such as silicon nitride, silicon oxynitride, etc.), fills the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 88.

[0146] Just like Figure 25A and Figure 25B As shown, a second interlayer dielectric layer (second ILD) 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flow film formed by a flow CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method such as CVD and PECVD. The gate contact 110 is subsequently formed... Figure 26A and Figure 26B It passes through the second ILD 108 and the gate shield 96 to contact the top surface of the recessed gate electrode 94.

[0147] exist Figure 26A and Figure 26BIn some embodiments, gate contacts 110 and source / drain contacts 112 are formed through a second ILD 108 and a first ILD 88. Openings for the source / drain contacts 112 are formed through the first ILD 88 and the second ILD 108, and openings for the gate contacts 110 are formed through the second ILD 108 and a gate mask 96. Acceptable photolithography and etching techniques can be used to form the openings. Pads (not shown), such as diffusion barrier layers and adhesion layers, and conductive material are formed within the openings. Pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. Conductive materials may be copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the surface of the second ILD 108. The remaining pads and conductive material form the source / drain contacts 112 and the gate contacts 110 within the openings. An annealing process can be performed to form silicide at the interface between the epitaxial source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically and electrically coupled to the epitaxial source / drain region 82, and the gate contact 110 is physically and electrically coupled to the gate electrode 94. The source / drain contact 112 and the gate contact 110 can be formed using different processes or the same process. Although shown as having the same cross-section, it should be understood that each of the source / drain contact 112 and the gate contact 110 can be formed with a different cross-section to avoid short circuits at the contacts.

[0148] The disclosed FinFET embodiments can also be applied to nanostructured devices, such as nanostructured (e.g., nanosheets, nanowires, all-around gates, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning alternating layers of patterned channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to the embodiments described above. After removing the dummy gate stacks, the sacrificial layers can be partially or completely removed in the channel regions. Replacement gate structures are formed in a manner similar to the embodiments described above, whereby the replacement gate structures can partially or completely fill the openings left by the removal of the sacrificial layers, and the replacement gate structures can partially or completely surround the channel layers in the channel regions of the NSFET device. ILDs and contacts with the replacement gate structures and source / drain regions can be formed sequentially in a manner similar to the embodiments described above. Nanostructured devices can be formed in the manner disclosed in U.S. Patent Application Publication No. 2016 / 0365414, the entire contents of which are incorporated herein by reference.

[0149] The embodiments offer the following advantages. Treatment of the dielectric layer in the gaps between fins with free radicals such as hydroxyl (OH*) and / or oxygen (O*) radicals can be useful for removing residual impurities (such as halogens) from the dielectric layer. This helps reduce the roughness of the subsequently formed film or seed layer, which can increase gap-filling capability. Through this treatment, the oxide layer formed on the dielectric layer can be removed by a chemical oxide removal process. This facilitates subsequent gap filling with dummy gates comprising a uniform material, allowing for more efficient removal of the dummy gates by subsequent selective etching processes.

[0150] According to one embodiment, a method of forming a semiconductor device includes: depositing a film on a dielectric layer, the dielectric layer being located on a first fin and a second fin, and within a trench between the first fin and the second fin; etching a top of the film; after etching the top of the film, performing a process on the dielectric layer to remove impurities, the process including bombarding the dielectric layer with free radicals; and filling trenches on a remaining portion of the film. In one embodiment, the film deposition includes the step of using a silane as a precursor. In one embodiment, the film deposition is performed in a temperature range of 100˚C to 750˚C. In one embodiment, the film deposition is performed at a pressure range of 0.1 Torr to 0.5 Torr. In one embodiment, the free radicals include OH* or O*. In one embodiment, the etching of the top of the film is performed in a temperature range of 100˚C to 700˚C. In one embodiment, the process is performed in a temperature range of 300˚C to 900˚C. In one embodiment, the process is performed at a pressure range of 0.01 Torr to 760 Torr.

[0151] According to another embodiment, a method of forming a semiconductor device includes: depositing a dielectric layer on a first fin and a second fin, the dielectric layer covering the sidewalls and bottom surface of a trench between the first fin and the second fin; forming a first film on the dielectric layer; etching the top of the first film; removing a first impurity from the surface of the dielectric layer by free radical bombardment, and forming a first oxide layer on a retained portion of the first film by bombardment; performing a chemical oxide removal process to remove the first oxide layer; and filling the trench after performing the chemical oxide removal process. In one embodiment, the free radicals include hydroxyl or oxygen free radicals. In one embodiment, filling the trench includes one or more additional cycles, each of the one or more additional cycles including the steps of: forming an additional film on the dielectric layer; etching the top of the additional film; and removing additional impurities from the surface of the dielectric layer by free radical bombardment. In an embodiment, each of the one or more additional cycles further includes performing an additional chemical oxide removal process to remove the additional oxide layer. In one embodiment, the trench filling step further includes the step of depositing an upper portion of a dummy gate layer on a retained portion of the one or more additional films. In one embodiment, the chemical oxide removal process is performed at a temperature range of 10˚C to 90˚C. In another embodiment, the chemical oxide removal process is performed at a pressure range of 0.1 Torr to 5.0 Torr.

[0152] According to another embodiment, a method of forming a semiconductor device includes the following steps: forming a first fin and a second fin, the first fin and the second fin extending from a substrate; forming a dummy dielectric layer on exposed surfaces of the first fin, the second fin and the substrate; forming a dummy gate on the first fin and the second fin, the formation of the dummy gate including a first cycle including: depositing a first film on the dummy dielectric layer; etching the top of the first film; and removing a first impurity from the surface of the dummy dielectric layer by bombardment with hydroxyl radicals or oxygen radicals; forming an interlayer dielectric on the first fin and the second fin; and removing the dummy gate. In one embodiment, forming the dummy gate includes an additional cycle, each cycle including: depositing an additional film on the dummy dielectric layer; etching the top of the additional film; and removing a second impurity from the surface of the dummy dielectric layer by another bombardment with hydroxyl radicals or oxygen radicals. In one embodiment, the removal of the first impurity is performed before forming the first film. In one embodiment, the first impurity is formed by etching the top of the first film and the removal of the first impurity is performed after forming the first film. In one embodiment, the aforementioned method further includes performing a chemical oxide removal process after removing the first impurity to remove the oxide layer.

[0153] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: A film is deposited on a dielectric layer located on a first fin and a second fin, and in a trench between the first fin and the second fin; Etch multiple tops of the film; After etching the plurality of tops of the film, a process is performed on the dielectric layer to remove a plurality of impurities, the process including bombarding the dielectric layer with a plurality of free radicals, the process forming an oxide layer on the film; After removing these impurities, a chemical oxide removal process is performed to remove the oxide layer, wherein the chemical oxide removal process includes treatment with a gas containing ammonia, hydrogen fluoride, nitrogen trifluoride, or a combination thereof; and The groove is filled in the retained portion of the membrane.

2. The method according to claim 1, characterized in that, The deposition of this film involves using silane as a precursor.

3. The method according to claim 1, characterized in that, The deposition of this film was carried out in a temperature range of 100˚C to 750˚C.

4. The method according to claim 1, characterized in that, The deposition of the film was carried out at a pressure range of 0.1 Torr to 0.5 Torr.

5. The method according to claim 1, characterized in that, The plurality of free radicals include OH* or O*.

6. The method according to claim 1, characterized in that, The etching of these tops of the film is carried out in a temperature range of 100˚C to 700˚C.

7. The method according to claim 1, characterized in that, The treatment is carried out in a temperature range of 300˚C to 900˚C.

8. The method according to claim 1, characterized in that, The treatment was carried out at pressures ranging from 0.01 Torr to 760 Torr.

9. A method for forming a semiconductor device, characterized in that, The method includes: A dielectric layer is deposited on a first fin and a second fin, the dielectric layer covering multiple sidewalls and a bottom surface of a trench between the first fin and the second fin; A first film is formed on the dielectric layer; Etch multiple tops of the first film; Multiple first impurities are removed from a surface of the dielectric layer by bombardment with multiple free radicals, and the bombardment forms a first oxide layer on the retained portion of the first film. After removing the first impurities, a chemical oxide removal process is performed to remove the first oxide layer, wherein the chemical oxide removal process includes treatment with a gas containing ammonia, hydrogen fluoride, nitrogen trifluoride, or a combination thereof; and After the chemical oxide removal process is performed, the trench is filled.

10. The method according to claim 9, characterized in that, These free radicals include hydroxyl or oxygen free radicals.

11. The method according to claim 9, characterized in that, The filling of the trench includes one or more additional loops, each of which includes: An additional film is formed on the dielectric layer; Etching multiple tops of the additional film; and Multiple additional impurities are removed from the surface of the dielectric layer by bombardment with free radicals.

12. The method according to claim 11, characterized in that, Each of the additional cycles further includes performing an additional chemical oxide removal process to remove an additional oxide layer.

13. The method according to claim 11, characterized in that, The filling of the trench further includes depositing multiple upper portions of a dummy gate layer on the retained portions of the additional films.

14. The method according to claim 9, characterized in that, The chemical oxide removal process is carried out in a temperature range of 10˚C to 90˚C.

15. The method according to claim 9, characterized in that, The chemical oxide removal process is carried out at pressures ranging from 0.1 Torr to 5.0 Torr.

16. A method for forming a semiconductor device, characterized in that, The method includes: A first fin and a second fin are formed, the first fin and the second fin extending from a substrate; A dummy dielectric layer is formed on multiple exposed surfaces of the first fin, the second fin, and the substrate; A dummy gate is formed on the first fin and the second fin. The formation of the dummy gate includes a first cycle, comprising: A first film is deposited on the dummy dielectric layer; Etching multiple tops of the first film; and Multiple first impurities are removed from a surface of the dummy dielectric layer by bombardment with hydroxyl radicals or oxygen radicals, and the hydroxyl radicals or oxygen radicals form an oxide layer on the first film. After removing these first impurities, a chemical oxide removal process is performed to remove the oxide layer, wherein the chemical oxide removal process includes treatment with a gas containing ammonia, hydrogen fluoride, nitrogen trifluoride or a combination thereof. A layer of inter-dielectric material is formed on the first fin and the second fin; and Remove the dummy gate.

17. The method according to claim 16, characterized in that, The formation of the dummy gate includes multiple additional cycles, each cycle including: An additional film is deposited on the dummy dielectric layer; Etch multiple tops of the additional film; and Multiple second impurities are removed from the surface of the dummy dielectric layer by another bombardment with hydroxyl radicals or oxygen radicals.

18. The method according to claim 16, characterized in that, The plurality of first impurities are removed before the formation of the first membrane.

19. The method according to claim 16, characterized in that, The first impurities are formed by etching the tops of the first film, and the removal of the first impurities is performed after the formation of the first film.

20. The method according to claim 16, characterized in that, The duration of this chemical oxide removal process ranges from 0.1 minutes to 60 minutes.

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