Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device and a method of manufacturing the same are disclosed. The semiconductor memory device includes a gate stack, an insulating layer overlapping the gate stack, a first source layer including a horizontal portion between the gate stack and the insulating layer and a protrusion extending from the horizontal portion to penetrate the insulating layer, a channel layer penetrating the gate stack and extending into the horizontal portion of the first source layer, a first memory pattern between the channel layer and the gate stack, and a second source layer disposed between the gate stack and the first source layer and in contact with the channel layer.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to semiconductor memory devices and methods of manufacturing such semiconductor memory devices, and more specifically, to a three-dimensional (3D) semiconductor memory device and a method of manufacturing such a 3D semiconductor memory device. Background Technology

[0002] Semiconductor memory devices include memory cells that can store data. Three-dimensional (3D) semiconductor memory devices include memory cells arranged in three dimensions, thus reducing the two-dimensional (2D) area occupied by the memory cells on the substrate.

[0003] To improve the integration density in 3D semiconductor memory devices, the number of stacked memory cells can be increased. Summary of the Invention

[0004] A semiconductor memory device according to embodiments of the present disclosure may include: a gate stack; an insulating layer overlapping the gate stack; a first source layer including a horizontal portion between the gate stack and the insulating layer and a protrusion extending from the horizontal portion to penetrate the insulating layer; a channel layer penetrating the gate stack and extending into the horizontal portion of the first source layer; a first memory pattern between the channel layer and the gate stack; and a second source layer disposed between the gate stack and the first source layer and in contact with the channel layer.

[0005] Another semiconductor memory device according to an embodiment of the present disclosure may include: a first gate stack surrounding a first channel structure; a second gate stack adjacent to the first gate stack and surrounding a second channel structure; a vertical insulating structure between the first gate stack and the second gate stack; and a first source layer. The first source layer includes: a protrusion overlapping the vertical insulating structure and having a groove facing the vertical insulating structure; a first horizontal portion extending from a first side of the protrusion to overlap with the first channel structure and the first gate stack; and a second horizontal portion extending from a second side of the protrusion to overlap with the second channel structure and the second gate stack. The semiconductor memory device further includes a second source layer surrounding the first channel structure between the first source layer and the first gate stack, and surrounding the second channel structure between the first source layer and the second gate stack.

[0006] A method for manufacturing a semiconductor memory device according to embodiments of the present disclosure may include the following steps: forming an insulating layer on a sacrificial substrate; forming a first opening through the insulating layer; forming a first source layer that contacts the sacrificial substrate through the first opening and extends over the insulating layer; forming a sacrificial source layer on the first source layer; forming a gate stack on the sacrificial source layer, the gate stack surrounding a channel structure; and replacing the sacrificial source layer with a second source layer that contacts the channel structure. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a diagram showing the vertical arrangement of a semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 3 This is a circuit diagram illustrating a unit string according to an embodiment of the present disclosure.

[0010] Figure 4A and Figure 4B This is a cross-sectional view showing a memory cell array according to an embodiment of the present disclosure.

[0011] Figure 5 This is a cross-sectional view showing the upper lead wire according to an embodiment of the present disclosure.

[0012] Figure 6 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0013] Figures 7A to 7C , Figures 8A to 8G , Figure 9A and Figure 9B It is shown Figure 6 The diagram shows an implementation of step S1.

[0014] Figure 10A and Figure 10B It is shown Figure 6 Cross-sectional view of the implementation of steps S5 and S7 shown.

[0015] Figure 11 It is shown in Figure 6 A cross-sectional view of an embodiment of the subsequent process performed after step S7.

[0016] Figure 12 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0017] Figure 13 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0018] The specific structural or functional descriptions disclosed herein are merely illustrative and intended to describe implementations based on the concepts of this disclosure. Implementations based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific implementations set forth herein.

[0019] Hereinafter, the terms "first" and "second" will be used to distinguish one component from another. For example, without departing from the scope of the concepts according to this disclosure, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

[0020] Embodiments of this disclosure relate to a semiconductor memory device capable of improving the stability of the manufacturing process and a method for manufacturing the semiconductor memory device.

[0021] Figure 1 This is a block diagram illustrating a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0022] Reference Figure 1 The semiconductor memory device 10 may include peripheral circuitry PC and memory cell array 20.

[0023] The peripheral circuit PC can control programming operations that store data in the memory cell array 20, reading operations that output data stored in the memory cell array 20, and erasing operations that erase data stored in the memory cell array 20.

[0024] In an implementation, the peripheral circuit PC may include a voltage generator 31, a line decoder 33, a control circuit 35, and a page buffer group 37.

[0025] The memory cell array 20 may include multiple memory blocks. The memory cell array 20 can be connected to the row decoder 33 via word line WL and to the page buffer group 37 via bit line BL.

[0026] Control circuit 35 can control peripheral circuit PC in response to command CMD and address ADD.

[0027] The voltage generator 31 can generate various operating voltages under the control of the control circuit 35, such as pre-erase voltage, erase voltage, ground voltage, programming voltage, verification voltage, pass voltage and read voltage for programming operation, read operation and erase operation.

[0028] The line decoder 33 can select a memory block under the control of the control circuit 35. The line decoder 33 can apply an operating voltage to the word line WL connected to the selected memory block.

[0029] Page buffer group 37 can be connected to memory cell array 20 via bit line BL. During programming operations, page buffer group 37 can temporarily store data received from input / output circuitry (not shown) under the control of control circuitry 35. During read or verification operations, page buffer group 37 can sense the voltage or current of bit line BL under the control of control circuitry 35. Page buffer group 37 can select bit line BL under the control of control circuitry 35.

[0030] Each memory block in memory cell array 20 may include multiple cell strings. Each cell string may include memory cells connected to word lines.

[0031] Figure 2 This is a diagram showing the vertical arrangement of a semiconductor memory device according to an embodiment of the present disclosure.

[0032] Reference Figure 2 The semiconductor memory device may include a first structure ST1 and a second structure ST2 bonded together. The bonding surface 50 between the first structure ST1 and the second structure ST2 may include a bonding surface between insulating layers and a bonding surface between metal layers.

[0033] The first structure ST1 may include a source structure SL, a bit line array BLA, a gate stack GST disposed between the source structure SL and the bit line array BLA, and a first interconnect array ICA1 disposed between the bonding surface 50 and the bit line array BLA. The source structure SL may include a source layer formed of different materials. The bit line array BLA may include multiple bit lines. The gate stack GST may include at least one source select line, at least one drain select line, and word lines stacked between the source select line and the drain select line in a spaced-apart state. The first interconnect array ICA1 may include multiple conductive pads, multiple conductive vias, multiple conductive leads, and multiple bonding patterns.

[0034] The second structure ST2 may include peripheral circuitry PC and a second interconnect array ICA2 disposed between the mating surface 50 and the peripheral circuitry PC. The peripheral circuitry PC may include... Figure 1 The voltage generator 31, line decoder 33, control circuitry 35, and page buffer group 37 are shown. The second interconnect array ICA2 may include multiple conductive pads, multiple conductive vias, multiple conductive leads, and multiple bonding patterns.

[0035] The bonding pattern of the first interconnect array ICA1 can be bonded to the bonding pattern of the second interconnect array ICA2. Therefore, the first interconnect array ICA1 can be electrically connected to the second interconnect array ICA2. The peripheral circuit PC can be electrically connected via the first interconnect array ICA1 and the second interconnect array ICA2 to at least one of the bit line array BLA, the gate stack GST, and the source structure SL.

[0036] Figure 3 This is a circuit diagram illustrating a cell string CS according to an embodiment of the present disclosure.

[0037] Reference Figure 3 The cell string CS can be connected to the source structure SL and the bit line BL. The cell string CS may include multiple memory cells MC1 to MCn, at least one source selection transistor SST, and at least one drain selection transistor DST.

[0038] Multiple memory cells MC1 to MCn can be connected in series. The gates of the multiple memory cells MC1 to MCn can be connected to the corresponding word lines of multiple word lines WL1 to WLn stacked in a spaced-apart state.

[0039] At least one source select transistor SST controls the electrical connection between the unit string CS and the source structure SL. According to one embodiment, the unit string CS may include a single source select transistor SST disposed between the source structure SL and a plurality of memory cells MC1 to MCn. This disclosure is not limited thereto. According to another embodiment, the unit string CS may include two or more source select transistors disposed between the source structure SL and the plurality of memory cells MC1 to MCn and connected in series with each other. The gate of the source select transistor SST may be connected to the source select line SSL.

[0040] At least one drain-select transistor (DST) controls the electrical connection between the unit string CS and the bit line BL. According to one embodiment, the unit string CS may include a single drain-select transistor (DST) disposed between the bit line BL and a plurality of memory cells MC1 to MCn. This disclosure is not limited thereto. According to another embodiment, the unit string CS may include two or more drain-select transistors disposed between the bit line BL and the plurality of memory cells MC1 to MCn and connected in series with each other. The gate of the drain-select transistor (DST) may be connected to the drain-select line DSL.

[0041] The source select line SSL, multiple word lines WL1 to WLn, and drain select line DSL can be implemented by conductive patterns stacked in a spaced-apart state. The source select transistor SST, multiple memory cells MC1 to MCn, and drain select transistor DST can be connected in series through the channel layer of the channel structure. The source structure SL can be connected to the channel layer of the channel structure.

[0042] Figure 4A and Figure 4B This is a cross-sectional view showing a memory cell array according to an embodiment of the present disclosure. Figure 4A This is a cross-sectional view showing the source structure SL of the memory cell array that are adjacent to each other, as well as the first gate stack GST1 and the second gate stack GST2 of the memory cell array. Figure 4B yes Figure 4A An enlarged cross-sectional view of region A shown.

[0043] Reference Figure 4A and Figure 4B Each of the first gate stack GST1 and the second gate stack GST2 may include an interlayer insulating layer (ILD) and a conductive pattern (CP) alternately disposed in the stacking direction. The conductive pattern (CP) can be used as... Figure 3 The source selection line SSL, multiple word lines WL1 to WLn, and drain selection line DSL are shown.

[0044] The first gate stack GST1 can be penetrated by the first channel structure CH1, and the second gate stack GST2 can be penetrated by the second channel structure CH2. The first channel structure CH1 can be surrounded by the interlayer insulating layer ILD and the conductive pattern CP of the first gate stack GST1, and the second channel structure CH2 can be surrounded by the interlayer insulating layer ILD and the conductive pattern CP of the second gate stack GST2. The first channel structure CH1 and the second channel structure CH2 can extend in the direction in which the interlayer insulating layer ILD and the conductive pattern CP are stacked.

[0045] The gap between the first gate stack GST1 and the second gate stack GST2 can be filled by the vertical insulating structure VI.

[0046] The source structure SL may extend to overlap with the first gate stack GST1, the vertical insulating structure VI, and the second gate stack GST2. The insulating layer ILL may extend to cover the portion of the source structure SL that overlaps with the first gate stack GST1 and the second gate stack GST2. In other words, a portion of the source structure SL may be disposed between the first gate stack GST1 and the insulating layer ILL, and between the second gate stack GST2 and the insulating layer ILL. The portion of the source structure SL that overlaps with the vertical insulating structure VI may extend to penetrate the insulating layer ILL.

[0047] The source structure SL may include a first source layer SL1 and a second source layer SL2. The first source layer SL1 may include a material different from the material included in the second source layer SL2.

[0048] The first source layer SL1 may overlap with the first gate stack GST1, the vertical insulating structure VI, and the second gate stack GST2, and may penetrate the insulating layer ILL. The first source layer SL1 may include a first surface SU1 in contact with the insulating layer ILL and a second surface SU2 opposite to the first surface SU1. A groove GV may be formed on the second surface SU2 of the first source layer SL1.

[0049] A second source layer SL2 may be disposed between the first source layer SL1 and each of the first gate stack GST1 and the second gate stack GST2. The second source layer SL2 may extend to surround each of the first channel structure CH1 and the second channel structure CH2. In other words, the first channel structure CH1 and the second channel structure CH2 may extend to penetrate the second source layer SL2.

[0050] Each of the first channel structure CH1 and the second channel structure CH2 may extend into the first source layer SL1. Each of the first channel structure CH1 and the second channel structure CH2 may include a core insulating layer CO, a channel layer CL, and a doped semiconductor pattern DP.

[0051] The core insulating layer CO can extend in the direction of the interlayer insulating layer ILD and the conductive pattern CP to penetrate the interlayer insulating layer ILD and the conductive pattern CP. The core insulating layer CO can overlap with the doped semiconductor pattern DP.

[0052] The channel layer CL may surround the sidewalls of the core insulating layer CO. The channel layer CL may extend between the core insulating layer CO and the first source layer SL1 to close the end of the core insulating layer CO facing the first source layer SL1. The channel layer CL may extend to surround the sidewalls of the doped semiconductor pattern DP. The channel layer CL may be in direct contact with the second source layer SL2 protruding toward the sidewalls of the channel layer CL.

[0053] According to one embodiment, the channel layer CL may include undoped silicon, and the doped semiconductor pattern DP may include n-type doped silicon. According to another embodiment, the portion of the channel layer CL surrounding the doped semiconductor pattern DP may include the same dopant as the dopant in the doped semiconductor pattern DP.

[0054] The sidewalls of the first channel structure CH1 and the second channel structure CH2 can be surrounded by a first memory pattern ML1. The first memory pattern ML1 can be disposed between the first channel structure CH1 and the first gate stack GST1 and between the second channel structure CH2 and the second gate stack GST2, respectively.

[0055] The ends of the first channel structure CH1 and the second channel structure CH2 facing the first source layer SL1 can be covered by a second memory pattern ML2. The second memory pattern ML2 can be disposed between the first source layer SL1 and the first channel structure CH1, and between the first source layer SL1 and the second channel structure CH2. The second memory pattern ML2 can be spaced apart from the first memory pattern ML1 by the second source layer SL2.

[0056] A vertical insulating structure VI may be disposed between a first gate stack GST1 and a second gate stack GST2, and may extend in the direction of the interlayer insulating layer ILD and the conductive pattern CP stack. The vertical insulating structure VI may include a spacer insulating layer SP and a gap-filling insulating layer FI. The spacer insulating layer SP may extend to cover the sidewalls of each of the first gate stack GST1 and the second gate stack GST2.

[0057] Reference Figure 4B The first source layer SL1 may include a first horizontal portion P1, a second horizontal portion P2, and a protrusion P3. The first horizontal portion P1 may extend to overlap with the first channel structure CH1 and the first gate stack GST1. The protrusion P3 may extend from the first horizontal portion P1 and may overlap with the vertical insulating structure VI. The protrusion P3 may have a curved shape to have a groove GV facing the vertical insulating structure VI. The protrusion P3 may extend to penetrate the insulating layer ILL. The second horizontal portion P2 may extend from the protrusion P3 and may extend to overlap with the second channel structure CH2 and the second gate stack GST2. According to an embodiment of the present disclosure, the first horizontal portion P1 may extend from a first side of the protrusion P3, and the second horizontal portion P2 may extend from a second side of the protrusion P3.

[0058] The first source layer SL1 may have a lower resistivity than the second source layer SL2. The first source layer SL1 may comprise a conductive material whose electrical properties remain unchanged or only slightly altered at the high temperatures resulting from the manufacturing process of the semiconductor memory device. According to an embodiment, the first source layer SL1 may comprise at least one of a tungsten silicide layer and a cobalt silicide layer. The second source layer SL2 may comprise a doped semiconductor layer. According to an embodiment, the second source layer SL2 may comprise n-type doped silicon.

[0059] The sidewall 63 of the interlayer insulating layer ILD may protrude toward the gap-filling insulating layer FI relative to the surface 61 between the protrusion P3 of the first source layer SL1 and the insulating layer ILL. In an embodiment, the interlayer insulating layer ILD may extend to overlap a portion of the protrusion P3 of the first source layer SL1.

[0060] The gap-filling insulating layer FI of the vertical insulating structure VI may extend into the second source layer SL2 overlapping with the groove GV. According to an embodiment, the gap-filling insulating layer FI may penetrate the second source layer SL2 to contact the first source layer SL1. Embodiments of this disclosure are not limited thereto. Although not shown in the figures, according to an embodiment, the surface of the gap-filling insulating layer FI facing the first source layer SL1 may be spaced apart from the first source layer SL1 and covered by the second source layer SL2.

[0061] The channel layer CL of the first channel structure CH1 can extend into the first horizontal portion P1 of the first source layer SL1, and the channel layer CL of the second channel structure CH2 can extend into the second horizontal portion P2 of the first source layer SL1.

[0062] Each of the first memory pattern ML1 and the second memory pattern ML2 may include a tunnel insulation layer TI, a data storage layer DS, and a first barrier insulation layer BI1.

[0063] The tunnel insulation layer TI may extend along the surface of the channel layer CL. The tunnel insulation layer TI may include an insulating material that allows charge tunneling. According to an embodiment, the tunnel insulation layer TI may include a silicon oxide layer.

[0064] The data storage layer DS may extend along the surface of the tunnel insulation layer TI. The data storage layer DS may include a material layer capable of storing data. According to one embodiment, the data storage layer DS may include a nitride layer capable of storing data altered by the Fowler-Nordheim tunneling.

[0065] The first barrier insulating layer BI1 may extend along the surface of the data storage layer DS. The first barrier insulating layer BI1 may include an oxide layer.

[0066] A conductive pattern CP may surround a first memory pattern ML1 between interlayer insulating layers ILDs adjacent to each other in the direction of stacking of the conductive pattern CP and the interlayer insulating layer ILD. A second barrier insulating layer BI2 may be formed between each conductive pattern CP and the first barrier insulating layer BI1. The second barrier insulating layer BI2 may include an insulating material having a dielectric constant higher than that of the first barrier insulating layer BI1. According to an embodiment, the second barrier insulating layer BI2 may include a metal oxide. According to an embodiment, the metal oxide may include an aluminum oxide layer. The second barrier insulating layer BI2 may extend between the conductive pattern CP and the interlayer insulating layer ILD. The second barrier insulating layer BI2 may extend between the spacer insulating layer SP and the interlayer insulating layer ILD.

[0067] Figure 5 This is a cross-sectional view showing the upper leads L1 and L2 according to an embodiment of the present disclosure.

[0068] Reference Figure 5 The upper leads L1 and L2 can overlap with the source structure SL. The insulating layer ILL and the upper insulating layer UIL can be inserted between the upper leads L1 and L2 and the source structure SL.

[0069] The upper insulating layer UIL can be extended to cover the source structure SL and the insulating layer ILL.

[0070] The upper insulating layer UIL can be penetrated by the contact plug CT. The contact plug CT can make contact with the protrusion of the first source layer SL1 and can extend in a direction opposite to the direction in which the vertical insulating structure VI extends. The first source layer SL1 can be used as an ohmic contact layer between the contact plug CT and the second source layer SL2.

[0071] The top leads L1 and L2 may include a metal source line L1 and a power line L2 spaced apart from the metal source line L1. The metal source line L1 may be electrically connected to the first source layer SL1 via a contact plug CT. According to embodiments of the present disclosure, the resistance of the source structure SL can be reduced by using the first source layer SL1, which has a lower resistivity than the second source layer SL2. Therefore, the layer or process for reducing the resistance of the metal source line L1 connected to the source structure SL to compensate for the resistance value of the source structure SL can be omitted. The resistance value of the metal source line L1 is set according to its area. As the area of ​​the metal source line L1 increases, the resistance of the metal source line L1 decreases, but the space required to provide the power line L2 decreases. According to embodiments of the present disclosure, the reduction in the resistance of the source structure SL reduces the area required for the metal source line L1, thereby ensuring the area for providing the power line L2. Therefore, embodiments of the present disclosure can facilitate the reduction of the size of the semiconductor memory device. According to the embodiment, the power line L2 may overlap with the first gate stack GST1 and the second gate stack GST2, and the upper insulating layer UIL is inserted between the power line L2 and each of the first gate stack GST1 and the second gate stack GST2.

[0072] Power line L2 can supply the internal voltage generated by receiving external voltage to... Figure 1 and Figure 2 The peripheral circuit PC is shown. According to an embodiment, the internal voltage supplied by the power line L2 may include the internal power supply voltage and the internal ground voltage.

[0073] Figure 6 This is a flowchart schematically illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0074] Reference Figure 6 A method for manufacturing a semiconductor memory device may include: forming a first structure including a memory cell array on a sacrificial substrate in step S1; forming a second structure including peripheral circuitry in step S3; bonding the first and second structures together in step S5; and removing the sacrificial substrate in step S7. Although not shown in the figures, subsequent processes (e.g., forming top leads, etc.) may be performed after the sacrificial substrate is removed.

[0075] Figures 7A to 7C , Figures 8A to 8G , Figure 9A and Figure 9B It is shown Figure 6 The diagram illustrates an embodiment of step S1. Although not shown in the diagram, step S1 can be performed on a support of a semiconductor manufacturing apparatus.

[0076] Figures 7A to 7C This is a three-dimensional view showing some of the processes in step S1.

[0077] Reference Figure 7A Step S1 may include forming a first insulating layer 103 on the sacrificial substrate 101. The sacrificial substrate 101 may extend in a first direction I and a second direction II that are different from each other. In an embodiment, the axis toward the first direction I and the axis toward the second direction II intersect each other. According to an embodiment, in the XYZ Cartesian coordinate system, the first direction I and the second direction II may be the X-axis direction and the Y-axis direction, respectively. Hereinafter, the direction perpendicular to the plane extending in the first direction I and the second direction II is defined as the third direction III. In the XYZ Cartesian coordinate system, the third direction III may be the Z-axis direction.

[0078] The sacrificial substrate 101 may contact a support member (not shown) of the manufacturing equipment. According to an embodiment, the sacrificial substrate 101 may be a silicon substrate.

[0079] The first insulating layer 103 may include a material capable of serving as a stop layer in subsequent processes that remove the sacrificial substrate 101. According to an embodiment, the first insulating layer 103 may include a nitride layer.

[0080] Step S1 may include forming a mask pattern 105 on the first insulating layer 103 and using the mask pattern 105 as an etching barrier to etch the first insulating layer 103. Therefore, a first opening 107 may be formed through the first insulating layer 103. The first opening 107 may extend linearly. According to an embodiment, the first opening 107 may extend in a second direction II. A portion of the sacrificial substrate 101 may be exposed through the first opening 107. The first opening 107 may be formed with a first width W1.

[0081] Reference Figure 7B It can remove Figure 7A The mask pattern 105 shown exposes the first insulating layer 103.

[0082] Subsequently, step S1 may include forming a first source layer 111 covering the surface of the first insulating layer 103 and the first opening 107, and forming a sacrificial source layer 113 on the first source layer 111. The first source layer 111 may contact the sacrificial substrate 101 through the first opening 107 and may extend over the first insulating layer 103.

[0083] The first source layer 111 may include a groove overlapping the first opening 107. The deposition thickness T1 of the first source layer 111 can be controlled such that the groove is defined on the surface of the first source layer 111. According to an embodiment, the deposition thickness T1 of the first source layer 111 can be controlled to be less than half a value corresponding to the first width W1. The portion of the first source layer 111 that overlaps with the first opening 107 may have a curved shape to define the groove.

[0084] The sacrificial source layer 113 may be formed to fill the groove of the first source layer 111, and its surface may be planarized. The sacrificial source layer 113 may include a first portion Pa overlapping the first insulating layer 103 and a second portion Pb extending from the first portion Pa and filling the groove of the first source layer 111. The first portion Pa may be formed with a first thickness Ta, and the second portion Pb may be formed with a second thickness Tb. According to an embodiment, the first thickness Ta may be controlled to be less than a first width W1. The second thickness Tb may be formed to be greater than the first thickness Ta. According to an embodiment of the present disclosure, the planarized sacrificial source layer 113 is retained to fill the first opening 107 and the groove of the first source layer 111 overlapping the first opening 107. Therefore, the second thickness Tb of the second portion Pb of the sacrificial source layer 113 filling the groove defined on the surface of the first source layer 111 may be defined to be greater than the first thickness Ta of the first portion Pa of the sacrificial source layer 113 overlapping the first insulating layer 103.

[0085] The first source layer 111 may include a conductive material. According to an embodiment, the first source layer 111 may include a conductive material with a resistivity lower than that of silicon. The conductive material included in the first source layer 111 can serve as an ohmic contact layer and can resist the high temperatures generated during the manufacturing process of a semiconductor memory device. Additionally, in Figure 10B When the sacrificial substrate 101 is removed in the subsequent process shown, the conductive material included in the first source layer 111 may be lost little or no. According to an embodiment, the first source layer 111 may include at least one of a tungsten silicide layer and a cobalt silicide layer.

[0086] The sacrificial source layer 113 may include the ability to Figure 7C The material shown is used as a stop layer in subsequent processes to form the second opening 153. The sacrificial source layer 113 may include a material that can be selectively removed in subsequent processes. According to an embodiment, the sacrificial source layer 113 may include undoped silicon.

[0087] Subsequently, step S1 may include forming a preliminary laminate 120 on the sacrificial source layer 113 and forming a hole 127 through the preliminary laminate 120 and a first portion Pa of the sacrificial source layer 113.

[0088] The initial stack 120 can be formed by alternately stacking interlayer insulating layers 121 and sacrificial layers 123 on the sacrificial source layer 113. The sacrificial layer 123 may include a material that can be selectively removed in subsequent processes. According to an embodiment, each interlayer insulating layer 121 may include silicon oxide, and the sacrificial layer 123 may include silicon nitride.

[0089] Forming the via 127 may include forming a mask pattern 125 on the initial stack 120 and etching the initial stack 120 and the sacrificial source layer 113 by using the mask pattern 125 as an etching barrier. The via 127 may extend into the first source layer 111.

[0090] While the initial laminate 120 is being etched, a ground voltage can be applied to the sacrificial substrate 101 from the support member (not shown) of the manufacturing equipment. Therefore, while the initial laminate 120 is being etched, the charge accumulated in the first source layer 111 and the sacrificial source layer 113 can be discharged through the sacrificial substrate 101 via the first source layer 111.

[0091] To improve the integration density in a semiconductor memory device, the number of interlayer insulating layers 121 and sacrificial layers 123 stacked in the preliminary stack 120 can be increased. In this case, higher power can be applied to the manufacturing equipment to perform the etching process of the preliminary stack 120. According to embodiments of the present disclosure, even when high power is applied during the etching process of the preliminary stack 120, the charge accumulated by the high power can be discharged through the first source layer 111 in contact with the sacrificial substrate 101, thereby preventing arcing. In other words, embodiments of the present disclosure allow the charge generated while the preliminary stack 120 is being etched to be discharged through the first source layer 111. Therefore, the present disclosure omits additional structures for discharge, thereby simplifying the process of manufacturing the semiconductor memory device.

[0092] Subsequently, step S1 may include forming a memory layer 130 on the surface of the hole 127 and forming a channel structure 140 on the memory layer 130 to fill the hole 127.

[0093] Memory layer 130 may include Figure 8A The first barrier insulation layer 131, data storage layer 133, and tunnel insulation layer 135 are shown. The first barrier insulation layer 131, data storage layer 133, and tunnel insulation layer 135 may include, with... Figure 4B The first barrier insulation layer BI1, the data storage layer DS, and the tunnel insulation layer TI shown are made of the same material.

[0094] Forming the channel structure 140 may include forming a channel layer 141 on the surface of the memory layer 130 and filling the central region of the via 127 opened through the channel layer 141 using a core insulating layer 143 and a doped semiconductor pattern 145. The channel layer 141 may include a semiconductor layer. According to one embodiment, the channel layer 141 may include undoped silicon. According to one embodiment, the portion of the channel layer 141 surrounding the doped semiconductor pattern 145 may include the same dopant as the dopant in the doped semiconductor pattern 145. According to one embodiment, the doped semiconductor pattern 145 may include n-type doped silicon.

[0095] Reference Figure 7C ,exist Figure 7B After the mask pattern 125 shown is removed, a second insulating layer 151 covering the channel structure 140 can be formed.

[0096] Subsequently, step S1 may include forming a second opening 153 through the second insulating layer 151 and the preliminary laminate 120. The second opening 153 may extend linearly. According to an embodiment, the second opening 153 may extend in a second direction II.

[0097] The second opening 153 may overlap with the second portion of Pb in the sacrificial source layer 113. According to embodiments of this disclosure, since the second portion of Pb in the sacrificial source layer 113 is formed to be relatively thicker than the other portion, complete penetration of the second portion of Pb can be prevented when performing the etching process for forming the second opening 153. Therefore, this disclosure prevents damage to the first source layer 111 during the formation of the second opening 153.

[0098] The second width W2 of the second opening 153 can be set taking into account the alignment margin between the second opening 153 and the second portion of Pb, as well as the thickness of the material layer deposited on the sidewall of the second opening 153 in subsequent processes. According to an embodiment, the second opening 153 may be formed with a second width W2, which is smaller than the first width W1 of the first opening 107.

[0099] According to an embodiment, the second width W2 of the second opening 153 can be formed to be greater than the first thickness Ta corresponding to the gap distance between the initial laminate 120 and the first source layer 111. Therefore, in subsequent processes where the second source layer replaces the sacrificial source layer 113, voids can be prevented from forming in the second source layer.

[0100] Figures 8A to 8G yes Figure 7C The enlarged cross-sectional view of region B shown is illustrated, and it also shows that... Figure 7C The implementation method of the process following the process shown.

[0101] Reference Figure 8A Step S1 may include selectively removing through the second opening 153 Figure 7C The sacrificial layer 123 is shown. Therefore, the third opening 157 can be defined between interlayer insulating layers 121 that are adjacent to each other along the third direction III.

[0102] Reference Figure 8B Step S1 may include filling the third opening 157 with conductive patterns 163. Filling the third opening 157 with conductive patterns 163 may include forming a conductive material through the second opening 153 to fill the third opening 157 and etching the conductive material to separate the conductive material into a plurality of conductive patterns 163. Each conductive pattern 163 may be formed of a variety of conductive materials by including a metal barrier layer and a metal layer, including a silicon layer and a metal silicide layer, or including at least one of a metal layer, a silicon layer and a metal silicide layer. The conductive patterns 163 may extend to surround the sidewalls of the channel structure 140, and the memory layer 130 is interposed between them.

[0103] According to an embodiment, step S1 may include forming a preliminary second barrier insulating layer 161L before filling the third opening 157 with the conductive pattern 163. The conductive pattern 163 may fill the third opening 157 on the preliminary second barrier insulating layer 161L.

[0104] The initial second barrier insulating layer 161L may extend above the surface of the sacrificial source layer 113, which is coplanar with the bottom surface of the second opening 153. The initial second barrier insulating layer 161L may comprise an insulating material with a dielectric constant higher than that of the first barrier insulating layer 131. The initial second barrier insulating layer 161L may extend to surround the sidewalls of the channel structure 140, and the memory layer 130 is interposed between the initial second barrier insulating layer 161L and the channel structure 140.

[0105] Based on the above reference Figure 8A and Figure 8B The described process utilizes conductive pattern 163 to replace Figure 7C The sacrificial layer 123 shown defines the gate stack 160. The gate stack 160 may include conductive patterns 163 and interlayer insulating layers 121 alternately disposed around the channel structure 140.

[0106] Subsequently, a preliminary spacer insulating layer 165L and a protective layer 167L can be sequentially formed along the surface of the second opening 153 to cover the sidewalls of the gate stack 160. The preliminary spacer insulating layer 165L and the protective layer 167L can extend to cover Figure 7C The sidewalls of the second insulating layer 151 are shown. The preliminary spacer insulating layer 165L may include a material different from the material included in the protective layer 167L. According to an embodiment, the preliminary spacer insulating layer 165L may include a nitride layer, and the protective layer 167L may include an oxide layer.

[0107] Reference Figure 8C Etching processes such as back etching can be used to etch. Figure 8B A portion of each of the protective layer 167L, the preliminary spacer insulation layer 165L, and the preliminary second barrier insulation layer 161L shown. Therefore, the sacrificial source layer 113 can be exposed through the bottom surface of the second opening 153. Hereinafter, the remaining portions of the protective layer 167L, the preliminary spacer insulation layer 165L, and the preliminary second barrier insulation layer 161L are referred to as the protective pattern 167, the spacer insulation layer 165, and the second barrier insulation layer 161, respectively.

[0108] Reference Figure 8D Step S1 may include selectively removing through the second opening 153 Figure 8C The sacrificial source layer 113 shown exposes the memory layer 130. A fourth opening 171 can be defined between the gate stack 160 and the first source layer 111 by removing the sacrificial source layer 113.

[0109] Reference Figure 8E Step S1 may include removing a portion of the memory layer exposed through the fourth opening 171, thereby exposing the channel layer 141 of the channel structure. Thus, the memory layer can be separated into a first memory pattern 130P1 and a second memory pattern 130P2.

[0110] Removing a portion of the memory layer may include etching a portion of the first barrier insulating layer 131 using an anisotropic etching method, etching a portion of the data storage layer 133 using a wet etching method, and etching a portion of the tunnel insulating layer 135 using anisotropic etching. While a portion of the first barrier insulating layer 131 is being etched, Figure 8D A portion of the protective pattern 167 shown can be etched. While a portion of the data storage layer 133 is being etched, a portion of the spacer insulating layer 165 and a portion of the second barrier insulating layer 161 can also be etched. Figure 8D The protective pattern 167 shown can be used as an etching barrier. While a portion of the tunnel insulation layer 135 is being etched, Figure 8D The protective pattern 167 shown can be removed. The spacer insulation layer 165 can act as an etching barrier while a portion of the tunnel insulation layer 135 is being etched.

[0111] Reference Figure 8F Step S1 may include forming a preliminary source layer 173L. The preliminary source layer 173L may be filled with... Figure 8EThe fourth opening 171 shown will contact the channel layer 141 of the channel structure. The initial source layer 173L may include a doped semiconductor layer. According to an embodiment, the initial source layer 173L may include n-type doped silicon. The dopant within the initial source layer 173L may be activated by heat treatment. According to an embodiment, the heat treatment causes the dopant to diffuse from the initial source layer 173L into a portion of the channel layer 141 surrounded by the initial source layer 173L, whereby that portion of the channel layer 141 may be doped.

[0112] The initial source layer 173L can be replaced by the first portion Pa of the relatively thin sacrificial source layer 113 (as referred above). Figure 7B (As described). Therefore, embodiments of this disclosure can prevent the formation of voids in the initial source layer 173L between the gate stack 160 and the first source layer 111.

[0113] According to the implementation method, the initial source layer 173L can be formed by repeatedly depositing the doped semiconductor layer and etching the doped semiconductor layer at least once.

[0114] Reference Figure 8G Step S1 may include etching. Figure 8F The preliminary source layer 173L shown makes Figure 8F The initial source layer 173L shown is retained as a second source layer 173 between the gate stack 160 and the first source layer 111. Therefore, a fifth opening 175 can be defined. The fifth opening 175 can be connected to the second opening 153 and can extend into the second source layer 173.

[0115] According to one embodiment, the initial source layer 173L may be etched to expose the spacer insulating layer 165. According to one embodiment, the fifth opening 175 may expose the first source layer 111. Embodiments of this disclosure are not limited thereto. According to one embodiment, the second source layer 173 may extend along the bottom surface of the fifth opening 175, and the fifth opening 175 may be spaced apart from the first source layer 111 by the second source layer 173.

[0116] Based on the above reference Figures 8C to 8G The described process allows the sacrificial source layer to be replaced by a second source layer 173 that is in contact with the channel layer 141 of the channel structure.

[0117] Figure 9A and Figure 9B It is shown in Figure 8G A cross-sectional view of an implementation of a subsequent process following the shown process.

[0118] Reference Figure 9A The third insulating layer 181 can be used to fill it. Figure 8GThe second opening 153 and the fifth opening 175 are shown. A third insulating layer 181 may extend over the second insulating layer 151. The third insulating layer 181 may include an oxide layer. According to an embodiment, a spacer insulating layer 165 may be retained between the third insulating layer 181 and the gate stack 160. The spacer insulating layer 165 may extend between the sidewall of the second insulating layer 151 and the third insulating layer 181.

[0119] Reference Figure 9B Step S1 may include: forming a drain contact plug 183 that penetrates the second insulating layer 151 and the third insulating layer 181; forming a bit line 185 connected to the drain contact plug 183; and forming a first interconnect structure 190 on the bit line 185.

[0120] Drain contact plug 183 may extend to contact channel structure 140. Drain contact plug 183 may contact at least one of channel layer 141 and doped semiconductor pattern 145 of channel structure 140. The contact structure between drain contact plug 183 and channel structure 140 may vary and is not limited to that shown in the figures. The structure of drain contact plug 183 may vary and is not limited to that shown in the figures.

[0121] Bit line 185 can be connected to channel structure 140 via drain contact plug 183. The contact structure between bit line 185 and drain contact plug 183 can be various and is not limited to that shown in the figure.

[0122] The first interconnect structure 190 may be embedded in a first insulating structure 187 formed on the bit line 185. The first insulating structure 187 may include two or more insulating layers. The first interconnect structure 190 may be implemented in various ways, and is not limited to those shown in the figures. The first interconnect structure 190 may include a first connection structure 191 overlapping the bit line 185 and a first bonding pattern 193 connected to the first connection structure 191.

[0123] Figure 10A and Figure 10B It is shown Figure 6 Cross-sectional view of the implementation of steps S5 and S7 shown.

[0124] Reference Figure 10A Step S5 may include the arrangement of a first structure 100 formed on one surface of the sacrificial substrate 101 via... Figure 6 After the second structure 200 provided in step S3 is shown, the first bonding pattern 193 of the first structure 100 is bonded to the second bonding pattern 233 of the second structure 200.

[0125] The first structure 100 can be referenced above. Figures 7A to 7C , Figures 8A to 8G , Figure 9A and Figure 9B The process described is used to form it.

[0126] The second structure 200 may include a peripheral circuit substrate and a second interconnect structure 230 on the peripheral circuit substrate. The peripheral circuit substrate may include a substrate 201 having a well region, an isolation insulating layer 203 for the active region of the isolation substrate 201, and transistors 210 insulated from each other by the isolation insulating layer 203. Each transistor 210 may include a junction 211 formed in the active region of the substrate 201, a gate insulating layer 213 stacked on the active region of the substrate 201, and a gate electrode 215 stacked on the gate insulating layer 213. The junction 211 may be defined by implanting at least one of an n-type dopant and a p-type dopant into the active region opposite to the gate electrode 215.

[0127] The peripheral circuit board may be covered by a second insulating structure 221. The second insulating structure 221 may include two or more insulating layers.

[0128] The second interconnect structure 230 may be embedded in the second insulating structure 221. The second interconnect structure 230 may include a second connection structure 231 electrically connected to a peripheral circuit board and a second bonding pattern 233.

[0129] The first bonding pattern 193 and the second bonding pattern 233 may include metals capable of being combined with each other by an intermetallic bonding process. According to an embodiment, each of the first bonding pattern 193 and the second bonding pattern 233 may include copper.

[0130] According to embodiments of this disclosure, after the dopant inside the second source layer 173 is activated, the first bonding pattern 193 bonds to the second bonding pattern 233. Therefore, even if the process temperature is limited after the first bonding pattern 193 bonds to the second bonding pattern 233, the heat treatment for activating the dopant can be omitted, thereby ensuring the reliable operation of the semiconductor memory device.

[0131] Reference Figure 10B Removed through step S7 Figure 10A The sacrificial substrate 101 shown exposes the first source layer 111 and the first insulating layer 103. According to an embodiment, at least one of a chemical mechanical polishing (CMP) method and a wet etching method can be used to remove the sacrificial substrate 101.

[0132] When removing Figure 10A When the sacrificial substrate 101 is shown, the first insulating layer 103 can be used as an etch stop layer. Therefore, when the sacrificial substrate 101 is being removed, excessive damage to the first source layer 111 can be prevented.

[0133] Figure 11 It is shown in Figure 6 A cross-sectional view of an embodiment of the subsequent process performed after step S7.

[0134] Reference Figure 11 After the sacrificial substrate is removed, an upper insulating layer 301 can be formed. The upper insulating layer 301 can overlap with the second structure 200 and the gate stack 160, and the first source layer 111 and the first insulating layer 103 are inserted between the upper insulating layer 301 and the second structure 200.

[0135] Subsequently, a contact plug 311 may be formed. The contact plug 311 may penetrate the upper insulating layer 301 to contact the first source layer 111. The contact plug 311 may comprise various types of metal.

[0136] According to embodiments of the present disclosure, the first source layer 111 may have a lower resistivity than the second source layer 173 and may provide an ohmic contact layer. Therefore, the present disclosure may compensate for the resistance of the second source layer 173 by means of the first source layer 111, and the first source layer 111 may be used as an ohmic contact layer between the second source layer 173 and the contact plug 311.

[0137] The first source layer 111 for the ohmic contact layer can be formed by a silicide process performed at a temperature range higher than the process temperature limited after the bonding process. According to this disclosure, the first source layer 111, serving as the ohmic contact layer, is formed before the first bonding pattern 193 is bonded to the second bonding pattern 233. Therefore, the first source layer 111 can be stably formed without being limited by the process temperature.

[0138] Subsequently, the steps of forming a metal source line 321 in contact with the contact plug 311 and forming a power line 323 spaced apart from the metal source line 321 and overlapping the gate stack 160 can be performed. An upper insulating layer 301 and a first insulating layer 103 may be disposed between the power line 323 and the gate stack 160. Although not shown in the figures, the power line 323 may be disposed on the insulating layer after additionally forming an insulating layer extending to cover the metal source line 321.

[0139] Figure 12 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0140] Reference Figure 12 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0141] The memory device 1120 may include a gate stack surrounding a channel structure, a first source layer overlapping the gate stack and having protrusions, and a second source layer disposed between the gate stack and the first source layer and in contact with the channel layer of the channel structure.

[0142] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0143] The storage controller 1110 is configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 has a data exchange protocol connected to a host connected to the memory system 1100. Additionally, the error correction block 1114 detects and corrects errors included in the data read from the memory device 1120, and the memory interface 1115 performs interfacing with the memory device 1120. Furthermore, the storage controller 1110 may also include a read-only memory (ROM) configured to store code data, etc., for interfacing with the host.

[0144] Figure 13 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure.

[0145] Reference Figure 13 The computing system 1200 according to embodiments of the present disclosure may include a CPU 1220, random access memory (RAM) 1230, user interface 1240, modem 1250, and memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0146] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a gate stack surrounding a channel structure, a first source layer overlapping the gate stack and having protrusions, and a second source layer disposed between the gate stack and the first source layer and in contact with the channel layer of the channel structure.

[0147] According to this disclosure, charges generated during the manufacturing process of a semiconductor memory device can be discharged through a protrusion in the first source layer, thereby preventing arcing. Therefore, this disclosure improves the stability of the manufacturing process for semiconductor memory devices.

[0148] According to this disclosure, the first source layer can be used as an ohmic contact layer, thereby ensuring the reliability of the operation of the semiconductor memory device.

[0149] Cross-references to related applications

[0150] This application claims priority to Korean Patent Application No. 10-2020-0077985, filed with the Korean Intellectual Property Office on June 25, 2020, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Gate stack; An insulating layer that overlaps with the gate stack; A first source layer includes a horizontal portion between the gate stack and the insulating layer and a protrusion extending from the horizontal portion, wherein an upper surface of the protrusion protrudes toward the insulating layer and a lower surface of the protrusion protrudes toward the insulating layer to form a groove on the lower surface of the protrusion. A channel layer that penetrates the gate stack and extends into the horizontal portion of the first source layer; A first memory pattern is formed between the channel layer and the gate layer stack; and A second source layer is disposed between the gate stack and the first source layer and in contact with the channel layer.

2. The semiconductor memory device according to claim 1, wherein, The first source layer comprises a conductive material, and The first source layer has a lower resistivity than the second source layer.

3. The semiconductor memory device according to claim 1, wherein, The first source layer includes at least one of a tungsten silicide layer and a cobalt silicide layer, and The second source layer includes a doped semiconductor layer.

4. The semiconductor memory device of claim 1, further comprising a second memory pattern disposed between the first source layer and the channel layer.

5. The semiconductor memory device according to claim 1, wherein, The gate stack includes a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked around the channel layer.

6. The semiconductor memory device according to claim 5, wherein, The interlayer insulating layer extends to overlap with a portion of the protrusion of the first source layer.

7. The semiconductor memory device according to claim 1, wherein, The first source layer includes a first surface that contacts the insulating layer and a second surface opposite to the first surface, and The second surface of the first source layer includes the groove defined by the protrusion of the first source layer.

8. The semiconductor memory device of claim 1, further comprising a core insulating layer penetrating the gate stack, wherein, The channel layer surrounds the sidewalls of the core insulation layer, and The channel layer extends between the core insulating layer and the first source layer to close the end of the core insulating layer facing the first source layer.

9. The semiconductor memory device of claim 1, further comprising: An upper insulating layer that covers the insulating layer and the protrusion; A contact plug that penetrates the upper insulating layer and contacts the protrusion; A metal source line, which is electrically connected to the first source layer via the contact plug; as well as A power line, which is spaced apart from the metal source line and overlaps with the gate stack, wherein the insulating layer and the upper insulating layer are inserted between the power line and the gate stack.

10. A semiconductor memory device, the semiconductor memory device comprising: A first gate stack, the first gate stack surrounding a first channel structure; A second gate stack is adjacent to the first gate stack and surrounds the second channel structure; A vertical insulating structure is provided between the first gate stack and the second gate stack; The first source layer includes: A protrusion that overlaps with the vertical insulating structure and has a groove facing the vertical insulating structure; A first horizontal portion, extending from a first side of the protrusion to overlap with the first channel structure and the first gate stack; and A second horizontal portion extends from a second side of the protrusion to overlap with the second channel structure and the second gate stack; and A second source layer surrounds the first channel structure between the first source layer and the first gate layer stack, and surrounds the second channel structure between the first source layer and the second gate layer stack. The upper surface of the protrusion protrudes in a direction away from the vertical insulating structure, and the lower surface of the protrusion protrudes in the same direction to form the groove on the lower surface of the protrusion.

11. The semiconductor memory device of claim 10, wherein, The first source layer comprises a conductive material, and The first source layer has a lower resistivity than the second source layer.

12. The semiconductor memory device according to claim 10, wherein, The first source layer includes at least one of a tungsten silicide layer and a cobalt silicide layer, and The second source layer includes a doped semiconductor layer.

13. The semiconductor memory device of claim 10, further comprising: Multiple first memory patterns are respectively disposed between the first gate stack and the first channel structure and between the second gate stack and the second channel structure; as well as Multiple second memory patterns are respectively disposed between the first channel structure and the first source layer and between the second channel structure and the first source layer, and are spaced apart from the first memory pattern by the second source layer.

14. The semiconductor memory device of claim 10, wherein, The groove of the protrusion is defined by a curved shape.

15. The semiconductor memory device according to claim 10, wherein, The vertical insulating structure extends into the second source layer.

16. The semiconductor memory device of claim 10, further comprising: A contact plug that contacts the protrusion and extends in a direction opposite to that facing the vertical insulating structure; A metal source line, which is electrically connected to the first source layer via the contact plug; as well as The power line is spaced apart from the metal source line and overlaps with the first gate stack and the second gate stack.

17. The semiconductor memory device of claim 10, wherein, Each of the first gate stack and the second gate stack includes alternatingly stacked multiple interlayer insulating layers and multiple conductive patterns, and Each of the first channel structure and the second channel structure includes: A core insulating layer that penetrates the interlayer insulating layer and the conductive pattern; and A channel layer surrounds the sidewall of the core insulating layer and extends between the core insulating layer and the first source layer to close the end of the core insulating layer facing the first source layer.

18. A method for manufacturing a semiconductor memory device, the method comprising the following steps: An insulating layer is formed on the sacrificial substrate; Forming a first opening through the insulating layer; A first source layer is formed that contacts the sacrificial substrate through the first opening and extends over the insulating layer; A sacrificial source layer is formed on the first source layer; A gate stack is formed on the sacrificial source layer, wherein the gate stack surrounds the channel structure; as well as The sacrificial source layer is replaced by a second source layer that is in contact with the channel structure.

19. The method according to claim 18, wherein, The sacrificial substrate includes a silicon substrate; and The insulating layer includes a nitride layer.

20. The method according to claim 18, wherein, A groove is defined on the surface of the first source layer that overlaps with the first opening.

21. The method according to claim 18, wherein, The deposition thickness of the first source layer is controlled to be less than half the width of the first opening.

22. The method according to claim 20, wherein, The sacrificial source layer includes: A first portion, which overlaps with the insulating layer and has a first thickness; and The second part fills the groove and has a second thickness greater than the first thickness.

23. The method according to claim 22, wherein, The first thickness is controlled to be less than the width of the first opening.

24. The method according to claim 22, wherein, The step of forming the gate stack surrounding the channel structure includes the following steps: A preliminary laminate is formed by alternately stacking multiple interlayer insulating layers and multiple sacrificial layers on the sacrificial source layer; A hole is formed through the first portion of the initial stack and the sacrificial source layer; A memory layer is formed on the surface of the hole; The channel structure is formed on the memory layer, and the channel structure fills the holes; Forming a second opening that passes through the initial stack and overlaps with the second portion of the sacrificial source layer; and The sacrificial layer is replaced by a conductive pattern through the second opening.

25. The method according to claim 24, wherein, The step of replacing the sacrificial source layer with the second source layer in contact with the channel structure includes the following steps: The memory layer is exposed by selectively removing the sacrificial source layer through the second opening; Remove the exposed portion of the memory layer to expose the channel structure; and The second source layer is used to fill the space between the gate stack and the first source layer to contact the exposed portion of the channel structure and the first source layer.

26. The method according to claim 24, wherein, The second opening is formed as follows: Narrower than the first opening; and It is wider than the gap between the initial stack and the first source layer.

27. The method according to claim 18, wherein, The first source layer comprises a conductive material with a resistivity lower than that of silicon.

28. The method according to claim 18, wherein, The first source layer includes at least one of a tungsten silicide layer and a cobalt silicide layer. The sacrificial source layer includes an undoped silicon layer, and The second source layer includes a doped semiconductor layer.

29. The method of claim 18, further comprising the step of: A bit line is formed on the gate stack, wherein the bit line is connected to the channel structure; A first bonding pattern is formed on the bit line; Forming a structure including a peripheral circuit board and a second bonding pattern on the peripheral circuit board; and The first bonding pattern is bonded to the second bonding pattern.

30. The method of claim 18, further comprising the step of: Remove the sacrificial substrate to expose the first source layer and the insulating layer; An upper insulating layer is formed overlapping the gate stack, wherein the first source layer and the insulating layer are interposed between the upper insulating layer and the gate stack; A contact plug is formed by penetrating the upper insulating layer to contact the first source layer; and A metal source line is formed that contacts the contact plug.

31. The method of claim 30, further comprising the step of: A power line is formed that is spaced apart from the metal source line and overlaps with the gate stack, wherein the upper insulating layer and the insulating layer are inserted between the power line and the gate stack.

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