A single photon avalanche diode image sensor pixel device, method of manufacture

Abstract

The application discloses a kind of single-photon avalanche diode image sensor pixel devices, preparation method, above-mentioned pixel device, comprising: substrate;First P-type silicon doped region is arranged inside substrate;N-type epitaxial layer is arranged on substrate;Second P-type silicon doped region, third P-type silicon doped region, fourth P-type silicon doped region, N-type silicon doped region are arranged inside N-type epitaxial region;The upper surface of first P-type silicon doped region is sequentially arranged second P-type silicon doped region, fourth P-type silicon doped region, third P-type silicon doped region from left to right;N-type silicon doped region is arranged on fourth P-type silicon doped region, for forming PN junction;First isolation region is arranged between second P-type silicon doped region and N-type silicon doped region, between third P-type silicon doped region and N-type silicon doped region;Second isolation region is arranged on the side of second P-type silicon doped region away from first isolation region, on the side of third P-type silicon doped region away from first isolation region.

Description

Technical Field

[0001] This invention relates to the field of diode technology, and in particular to a single-photon avalanche diode image sensor pixel device and its fabrication method. Background Technology

[0002] D-ToF imaging technology, short for Direct Time Of Flight, works on the principle that a pulsed light source emits laser pulses into a scene. These pulses are reflected from objects, and the reflected laser echoes are imaged onto a photosensitive sensor through a lens. By calculating the time difference between the laser emission and the received echo, the distance to the object can be calculated. Through the use of mechanical structures or photosensitive sensors with a certain resolution, 3D imaging within a specific field of view can be achieved. D-ToF imaging technology was first proposed in Western countries and has been commercially deployed, playing an increasingly important role in 3D graphics acquisition.

[0003] A typical application of D-ToF imaging technology is automotive LiDAR, which can currently be mainly divided into three types: mechanical, hybrid solid-state, and pure solid-state. Currently, commercially available LiDAR products are predominantly mechanical and hybrid solid-state, and suffer from drawbacks such as high cost, short lifespan, and insufficient resolution, greatly limiting their widespread application and becoming a pressing issue. Pure solid-state LiDAR, on the other hand, has a natural advantage in reliability due to the absence of mechanical moving parts within the device; however, it is technically challenging and complex to implement, and is currently still in the research stage. The most critical component is the design of the area array sensor chip that receives the laser echo.

[0004] Currently available area array sensor chips use single-photon avalanche diodes (SPADs) as their pixels. These diodes operate at a voltage higher than their breakdown voltage. When an over-bias voltage higher than the breakdown voltage is applied to the diode, incident light generates photogenerated carriers in the depletion region. These carriers are accelerated by the strong electric field in the depletion region, and after collisional ionization, an avalanche occurs. The statistically significant collisional ionization process determines the probability of an avalanche signal occurring, and this probability depends on factors such as the electric field of the avalanche diode, the materials used, and environmental conditions. If the electric field strength is high enough, electrons and holes can produce a significant ionization effect, and the avalanche process will automatically continue. In this case, the avalanche diode operates in Geiger mode.

[0005] However, single-photon avalanche diodes in related technologies suffer from limitations in device size and electronic crosstalk between adjacent pixel devices. Summary of the Invention

[0006] In view of this, embodiments of the present invention provide a single-photon avalanche diode image sensor pixel device and a fabrication method, in order to at least partially solve the above-mentioned technical problems.

[0007] As one aspect of the present invention, an embodiment of the present invention provides a single-photon avalanche diode image sensor pixel device, comprising: a substrate; a first P-type silicon doped region disposed within the substrate; an N-type epitaxial layer disposed on the substrate; a second P-type silicon doped region, a third P-type silicon doped region, a fourth P-type silicon doped region, and an N-type silicon doped region disposed within the N-type epitaxial region; wherein, the second P-type silicon doped region, the fourth P-type silicon doped region, and the third P-type silicon doped region are disposed sequentially from left to right on the upper surface of the first P-type silicon doped region; the N-type silicon doped region is disposed on the fourth P-type silicon doped region, for use... To form a PN junction; a first isolation region is provided between the second P-type silicon doped region and the N-type silicon doped region, and between the third P-type silicon doped region and the N-type silicon doped region. The first isolation region includes a first isolation trench and the N-type epitaxial layer disposed between the second P-type silicon doped region and the fourth P-type silicon doped region, for isolating the cathode and anode of the pixel device; a second isolation region is provided on the side of the second P-type silicon doped region away from the first isolation region and on the side of the third P-type silicon doped region away from the first isolation region, for isolating the pixel devices.

[0008] According to embodiments of the present invention, the specific ion concentration range of the above-mentioned N-type silicon doped region, the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region includes 1E14 to 1E20 cm⁻¹. -3 .

[0009] According to an embodiment of the present invention, the width of the first isolation region is 0.05 to 2 μm.

[0010] According to an embodiment of the present invention, the width of the first isolation groove is 0.1 to 1 μm, and the depth is 0.1 to 1 μm.

[0011] According to an embodiment of the present invention, the second isolation region includes a second isolation trench, the second isolation trench penetrates the N-type epitaxial layer and extends into the interior of the substrate, the width of the second isolation trench includes 0.1 to 5 μm, and the depth includes 10 to 70 μm.

[0012] According to an embodiment of the present invention, the thickness of the above-mentioned N-type epitaxial layer includes 1 to 7 μm.

[0013] As another aspect of the present invention, embodiments of the present invention also provide a method for fabricating the above-mentioned device, characterized in that: a substrate is provided; a first P-type silicon doped region is formed on the substrate by ion implantation; an N-type epitaxial layer is grown on the substrate; a first isolation region and a second isolation region are defined on the N-type epitaxial layer; a first isolation trench is formed on the first isolation region by etching; a second isolation trench is formed on the second isolation region by etching, the second isolation trench penetrating the N-type epitaxial layer to the interior of the substrate; a second P-type silicon doped region and a third P-type silicon doped region are formed between the first isolation region and the second isolation region by ion implantation; a fourth P-type silicon doped region is formed between the first isolation region by ion implantation; an N-type silicon doped region is then formed between the first isolation region by ion implantation, a PN junction is formed between the N-type silicon doped region and the fourth P-type silicon doped region; a cathode is formed in the N-type silicon doped region by etching; and an anode is formed in both the second P-type silicon doped region and the third P-type silicon doped region by etching to obtain a pixel device.

[0014] According to an embodiment of the present invention, the first P-type silicon doped region includes: forming the first P-type silicon doped region on the substrate by implantation of P-type silicon doped ions.

[0015] According to an embodiment of the present invention, the dopant ions in the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region all include boron.

[0016] According to an embodiment of the present invention, the dopant ions in the above-mentioned N-type silicon doped region include phosphorus.

[0017] This invention provides a single-photon avalanche diode image sensor pixel device. By forming a single-photon avalanche diode structure in an N-type epitaxial layer, and by setting a first isolation region between the cathode and anode, and the first isolation region including a first isolation trench and the N-type epitaxial layer between the cathode and anode, the size of the photosensitive PN junction can be further reduced, which is beneficial for high-density array integration of sensor pixel devices. By using a second isolation trench that penetrates the N-type epitaxial layer and extends into the substrate for isolation between pixel devices, electronic crosstalk between pixels can be reduced, and sensor noise can be effectively reduced. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a single-photon avalanche diode pixel device in related technologies.

[0019] Figure 2 A schematic cross-sectional view of a pixel device in an embodiment of the present invention is shown.

[0020] Figure 3 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which P-type silicon doped ion implantation is performed in a specific region of the substrate.

[0021] Figure 4 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, wherein an N-type epitaxial layer is grown on a substrate.

[0022] Figure 5 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, wherein a first isolation trench is formed by ion etching in a specific region of the epitaxial layer.

[0023] Figure 6 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, wherein a second isolation trench is formed by ion etching in a specific region of the epitaxial layer.

[0024] Figure 7 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which P-type silicon doped ions of appropriate depth are implanted in a specific region of the epitaxial layer.

[0025] Figure 8 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which shallow P-type silicon doped ion implantation is performed in a specific region of the epitaxial layer.

[0026] Figure 9 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which N-type silicon doped ion implantation is performed in a specific region of the epitaxial layer.

[0027] Figure 10 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, including electrode connection and back-end metal interconnection after the front-end process is completed, followed by wafer thinning.

[0028] Reference numerals in the figures: 1. Substrate; 2. First P-type silicon doped region; 3. N-type epitaxial layer; 4. Second P-type silicon doped region; 5. Third P-type silicon doped region; 6. Fourth P-type silicon doped region; 7. N-type silicon doped region; 8. Anode; 9. Cathode; 10. First isolation region; 101. First isolation trench; 11. Second isolation region; 111. Second isolation trench; 12. Barrier layer. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0030] Figure 1 This schematically illustrates a single-photon avalanche diode pixel device structure in the related art.

[0031] like Figure 1 As shown, the single-photon avalanche diode pixel device structure in the related technology includes: a device anode formed by a P+ type substrate, a device cathode formed by an N-well / Deep N-well / N+, a P-well to isolate the device cathode and anode, and a shallow trench (STI) to isolate pixels from each other.

[0032] and Figure 1 The manufactured SPAD avalanche diode image sensor pixel device has at least the following drawbacks:

[0033] First, since the P-well and the central photosensitive area N-well form a PN junction, a depletion region will also be generated in the N-well from the side. When the size of the photosensitive area, that is, the central N-well area of ​​the device, shrinks, the entire central area may become a depletion region, thus limiting the continuous shrinkage of the pixel device size.

[0034] Secondly, the shallow trench isolation (STI) used for pixel-to-pixel isolation cannot effectively block electronic crosstalk between pixels. Carriers generated in one pixel may be transferred to adjacent pixels through the substrate, causing interference between adjacent pixels and increasing sensor noise.

[0035] Finally, because the front illumination method is used, the depletion region generated between the PN junctions of the photosensitive layer is relatively short from the silicon surface, while the near-infrared laser, which is relatively safe for the human eye, penetrates deeper into the silicon, resulting in a lower detection efficiency of the near-infrared laser in the sensor.

[0036] Therefore, a novel pixel structure is needed to improve the performance of single-photon avalanche diode image sensors.

[0037] This invention provides a single-photon avalanche diode image sensor pixel device, comprising: a substrate; a first P-type silicon doped region disposed within the substrate; an N-type epitaxial layer disposed on the substrate; a second P-type silicon doped region, a third P-type silicon doped region, a fourth P-type silicon doped region, and an N-type silicon doped region disposed within the N-type epitaxial layer; wherein, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region are disposed sequentially from left to right on the upper surface of the first P-type silicon doped region; and the N-type silicon doped region is disposed on the fourth P-type silicon doped region for forming a PN junction. The first isolation region is provided between the second P-type silicon doped region and the N-type silicon doped region, and between the third P-type silicon doped region and the N-type silicon doped region. The first isolation region includes a first isolation trench and the N-type epitaxial layer disposed between the second P-type silicon doped region and the fourth P-type silicon doped region, for isolating the cathode and anode of the pixel device. A second isolation region is provided on the side of the second P-type silicon doped region away from the first isolation region and on the side of the third P-type silicon doped region away from the first isolation region, for isolating the pixel devices.

[0038] Figure 2 A schematic cross-sectional view of a pixel device in an embodiment of the present invention is shown.

[0039] like Figure 2 As shown, the single-photon avalanche diode image sensor pixel device includes: a substrate 1, a first P-type silicon doped region 2, an N-type epitaxial layer 3, a second P-type silicon doped region 4, a third P-type silicon doped region 5, a fourth P-type silicon doped region 6, an N-type silicon doped region 7, an anode 8, a cathode 9, a first isolation region 10, a first isolation trench 101, a second isolation region 11, and a second isolation trench 111.

[0040] A first P-type silicon doped region 2 is disposed inside the substrate 1, and an N-type epitaxial layer 3 is disposed on the upper surface of the substrate 1. A second P-type silicon doped region 4, a third P-type silicon doped region 5, a fourth P-type silicon doped region 6, and an N-type silicon doped region 7 are disposed inside the N-type epitaxial layer 3.

[0041] Specifically, from left to right, a second P-type silicon doped region 4, a fourth P-type silicon doped region 6, and a third P-type silicon doped region 5 are sequentially disposed on the upper surface of the first P-type silicon doped region 2; an N-type silicon doped region 7 is disposed on the fourth P-type silicon doped region 6 to form a PN junction; an anode 8 is disposed on both the second P-type silicon doped region 4 and the third P-type silicon doped region 5; a cathode 9 is disposed on the N-type silicon doped region; and a first isolation region 10 is disposed between the second P-type silicon doped region 4 and the N-type silicon doped region 7, and between the third P-type silicon doped region 5 and the N-type silicon doped region 7, to isolate the cathode 9 and the anode 8 of the pixel device.

[0042] The first isolation region 10 includes a first isolation trench 101 and an N-type epitaxial layer 3 disposed between the second P-type silicon doped region 4 and the fourth P-type silicon doped region 6. The first isolation trench 101 is disposed in the first isolation region 10 near the anode 8.

[0043] A second isolation region 11 is provided on the side of the second P-type silicon doped region 4 away from the first isolation region 2 and on the side of the third P-type silicon doped region 5 away from the first isolation region 2, for isolation between pixel devices.

[0044] A second isolation trench 111 is provided on the second isolation region 11. The second isolation trench 111 penetrates the N-type epitaxial layer 3 and extends into the interior of the substrate 1.

[0045] This invention provides a single-photon avalanche diode image sensor pixel device. By forming a single-photon avalanche diode structure in an N-type epitaxial layer and setting a first isolation region between the cathode and anode, the size of the photosensitive PN junction can be further reduced, thereby further reducing the size of the single-photon avalanche diode image sensor. This is beneficial for high-density array integration of pixel devices. By using a second isolation region that penetrates the N-type epitaxial layer and extends into the substrate for isolation between pixel devices, electronic crosstalk between pixels can be reduced, effectively reducing sensor noise.

[0046] According to an embodiment of the present invention, the ion concentrations of the N-type silicon doped region, the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region are the same, and their ion concentrations are greater than the ion concentrations of the N-type epitaxial layer.

[0047] According to embodiments of the present invention, the specific ion concentration range of the above-mentioned N-type silicon doped region, the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region includes 1E14 to 1E20 cm⁻¹. -3 For example, 1E14cm -3 1E16cm -3 1E18cm -3 1E20cm -3 .

[0048] According to an embodiment of the present invention, the first isolation region includes a first isolation trench and an N-type epitaxial layer disposed between the second P-type silicon doped region and the fourth P-type silicon doped region. The width of the first isolation region includes 0.05 to 2 μm, for example, 0.05 μm, 0.1 μm, 0.5 μm, 1 μm, 1.5 μm, and 2 μm.

[0049] According to an embodiment of the present invention, the width of the first isolation groove includes 0.1 to 1 μm, for example, 0.1 μm, 0.3 μm, 0.5 μm, 1 μm; and the depth includes 0.1 to 1 μm, for example, 0.1 μm, 0.5 μm, 0.8 μm, 1 μm.

[0050] In the embodiments of the present invention, the first isolation region includes an N-type epitaxial layer disposed between the second P-type silicon doped region and the fourth P-type silicon doped region. The distance of the first isolation region can be achieved by adjusting the size of the N-type epitaxial layer. Therefore, the size of the depletion region in the N-type epitaxial layer located in the first isolation region can be adjusted, thereby enabling the size of the photosensitive PN junction to be proportionally reduced. This achieves a proportional reduction in the size of the single-photon avalanche diode formed in the N-type epitaxial layer for the pixel device, which is beneficial for the high-density array integration of sensor pixel devices.

[0051] According to an embodiment of the present invention, the second isolation region includes a second isolation trench, the second isolation trench penetrates the N-type epitaxial layer and extends into the interior of the substrate, the width of the second isolation trench includes 0.1 to 5 μm, and the depth includes 10 to 70 μm.

[0052] In this embodiment of the invention, the width of the second isolation groove includes 0.1 to 5 μm, for example, 0.1 μm, 2 μm, 3 μm, 5 μm; the depth of the second isolation groove includes 10 to 70 μm, for example, 10 μm, 30 μm, 50 μm, 70 μm.

[0053] According to an embodiment of the present invention, the thickness of the above-mentioned N-type epitaxial layer includes 1 to 7 μm.

[0054] In this embodiment of the invention, the thickness of the N-type epitaxial layer includes 1 to 7 μm, for example, 1 μm, 3 μm, 5 μm, 7 μm.

[0055] As another aspect of the present invention, embodiments of the present invention also provide a method for preparing the above-mentioned device, comprising:

[0056] A substrate is provided; a first P-type silicon doped region is formed on the substrate by ion implantation; an N-type epitaxial layer is grown on the substrate; a first isolation region and a second isolation region are defined on the N-type epitaxial layer; a first isolation trench is formed on the first isolation region by etching; a second isolation trench is formed on the second isolation region by etching, the second isolation trench penetrating the N-type epitaxial layer and extending into the substrate; a second P-type silicon doped region and a third P-type silicon doped region are formed between the first and second isolation regions by ion implantation; a fourth P-type silicon doped region is formed between the first isolation regions by ion implantation; an N-type silicon doped region is then formed between the first isolation regions by ion implantation, and a PN junction is formed between the N-type silicon doped region and the fourth P-type silicon doped region; a cathode is formed in the N-type silicon doped region by etching; and an anode is formed in both the second and third P-type silicon doped regions by etching; thus, a pixel device is obtained.

[0057] According to an embodiment of the present invention, the first P-type silicon doped region includes: forming the first P-type silicon doped region on the substrate by implantation of P-type silicon doped ions.

[0058] According to an embodiment of the present invention, the dopant ions in the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region are all boron.

[0059] According to an embodiment of the present invention, the dopant ions in the above-mentioned N-type silicon doped region include phosphorus.

[0060] In this embodiment of the invention, a pixel device with a single-photon avalanche diode photosensitive area diameter of 5µm and an overall size of 13µm is used as an example to further illustrate the invention in detail.

[0061] In embodiments of the present invention, the fabrication process of the pixel device of the single-photon avalanche diode image sensor includes steps S1 to S9.

[0062] Figure 3 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which P-type silicon doped ion implantation is performed in a specific region of the substrate.

[0063] like Figure 3 As shown, step S1: A substrate is provided, and P-type silicon doped ion implantation is performed in the upper surface region of the substrate.

[0064] In this embodiment of the invention, the substrate is a silicon substrate. After cleaning the surface of the silicon substrate by wet etching, photoresist is laid on the entire wafer surface. Then, the wafer is exposed through a mask to develop and open the cathode 9 and anode 8 regions of the diode, with a diameter of 5-10 μm. P-type silicon doped ions are then implanted through the defined region of the barrier layer 12 in the silicon substrate 1 to form the first P-type silicon doped region 2. The type of P-type silicon doped ion implanted is boron, and the implantation depth is 0.1-2 μm, preferably 1.5 μm. Finally, the photoresist is removed by wet etching.

[0065] Figure 4 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which an N-type epitaxial layer is grown on a whole substrate.

[0066] like Figure 4 As shown, step S2: Based on the structure obtained in step S1, an N-type epitaxial layer is grown on the entire substrate. The N-type epitaxial layer is a doped N-type silicon material with a growth thickness of 1 to 7 μm, preferably 5 μm.

[0067] Figure 5 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, wherein a first isolation trench is formed by ion etching in a specific region of the epitaxial layer.

[0068] like Figure 5 As shown, in step S3, based on the structure obtained in step S2, silicon nitride chemical vapor deposition is performed on the entire wafer surface. Then, photoresist is laid as a barrier layer 12. Then, exposure is performed through a mask to develop and open the first isolation region 10 between the cathode 9 and the anode 8. The width is 0.1~1um, preferably 0.8um. ​​Then, the first isolation trench 101 is etched by dry etching. The depth is 0.1~1um, preferably 0.5um. Then, silicon oxide is filled in the first isolation trench 101 as an electrical isolator. Finally, chemical mechanical planarization is performed to grind down to the wafer surface to remove the silicon oxide and silicon nitride on the wafer.

[0069] Figure 6 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, wherein a second isolation trench is formed by ion etching in a specific region of the epitaxial layer.

[0070] like Figure 6As shown, in step S4, based on the structure obtained in step S3, silicon nitride chemical vapor deposition is performed on the entire wafer. Then, photoresist is laid as a barrier layer 12. After that, photoresist is laid, and then the wafer is exposed through a mask. The development opens a second isolation trench 111 for isolation between pixels, with a width of 0.5 to 3 μm, preferably 2 μm. Then, the second isolation trench 111 is etched by dry etching. The depth of the second isolation trench 11 is 10 to 40 μm, preferably 35 μm. The second isolation trench 111 will penetrate the N-type epitaxial layer 3 to the interior of the silicon substrate 1. Then, silicon oxide is filled in the second isolation trench 11 as an electrical isolator. Finally, the wafer surface is polished by chemical mechanical planarization to remove the silicon oxide and silicon nitride on the wafer.

[0071] Figure 7 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which P-type silicon doped ions of appropriate depth are implanted in a specific region of the epitaxial layer.

[0072] like Figure 7 As shown, in step S5, based on the structure obtained in step S4, after cleaning the surface of the N-type epitaxial layer 3 of the structure obtained in step S5 by wet etching, photoresist is laid on the entire wafer, and then exposed through a mask. Then, the diode cathode 9 and anode 8 regions are opened by development, while the first isolation region 10 between the cathode 9 and anode 8 is not opened. Then, P-type silicon doped ion implantation is performed to form a fourth P-type silicon doped region 6 in the middle region of the N-type epitaxial layer 3. The type of P-type silicon doped ion implanted is boron, and the implantation depth is 0.5~7um, preferably 6um. Finally, the photoresist is removed by wet etching.

[0073] Figure 8 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which shallow P-type silicon doped ion implantation is performed in a specific region of the epitaxial layer.

[0074] like Figure 8 As shown, in step S6, based on the structure obtained in step S5, after cleaning the surface of the N-type epitaxial layer 3 by wet etching, photoresist is laid on the entire wafer, and then exposed through a mask. Then, the diode anode 8 region is opened by development, while the cathode 9 and the first isolation region 10 are not opened. Then, P-type silicon doped ion implantation is performed to form the second P-type silicon doped region 4 and the third P-type silicon doped region 5. The type of P-type silicon doped ion is boron, and the implantation depth is 0-3 μm, preferably 2 μm. Finally, the photoresist is removed by wet etching.

[0075] Figure 9 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, in which N-type silicon doped ion implantation is performed in a specific region of the epitaxial layer.

[0076] like Figure 9 As shown, in step S7, based on the structure obtained in step S6, after cleaning the surface of the N-type epitaxial layer 3 by wet etching, photoresist is laid on the entire wafer. Then, it is exposed through a mask to develop and open the diode cathode 9 region, while the anode 8 and the first isolation region 10 are not opened. Then, N-type silicon doped ion implantation is performed to form the N-type silicon doped region 7. The type of N-type silicon doped ion is phosphorus, and the implantation depth is 0-5 μm, preferably 5 μm. Finally, the photoresist is removed by wet etching.

[0077] Figure 10 The illustration schematically shows the fabrication process steps of the pixel device in an embodiment of the present invention, including electrode connection and back-end metal interconnection after the front-end process is completed, followed by wafer thinning.

[0078] like Figure 10 As shown, in step S8, based on the structure obtained in step S7, ion implantation growth is performed on the upper surfaces of the second P-type silicon doped region 4 and the third P-type silicon doped region 5 to form an anode 8; ion implantation growth is performed on the upper surface of the N-type silicon doped region 7 to form a cathode 9. After the above front-end process is completed, electrode connection and back-end metal interconnection processes in standard CMOS process are used to complete the back-end metal interconnection of cathode 9 and anode 8. Finally, the wafer is thinned by chemical mechanical polishing to achieve a wafer thickness of 20-100 μm.

[0079] In this embodiment of the invention, the wafer is thinned, and the standard for thinning the wafer thickness is: the distance from the depletion region of the photosensitive PN junction to the silicon surface in the direction of incident light is equal to the penetration depth of the near-infrared laser wavelength used in silicon, so as to maximize the detection efficiency of the laser.

[0080] In this embodiment of the invention, after the wafer is thinned, the wafer thickness reaches 20 to 100 μm, for example, 20 μm, 40 μm, 80 μm, 100 μm.

[0081] Through the embodiments of the present invention, wafer thinning technology is adopted, and incident light is irradiated from the back of the wafer. Compared with the front illumination method, the depth of the PN junction depletion region in silicon is increased, so that the depletion region of the photosensitive area is deeper than the silicon surface, thereby matching the deeper silicon penetration depth of the near-infrared laser and improving the detection efficiency of the near-infrared laser of the sensor. At the same time, the present invention proposes specific process steps for realizing this pixel structure, which can smoothly realize the large-scale mass production of sensor chips.

[0082] The present embodiment has been described in detail above with reference to the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the single-photon avalanche diode image sensor pixel device and its fabrication method according to the present invention. The pixel device structure provided by the present invention can be mass-produced under the above-described process flow. This pixel device is a single-photon avalanche diode formed in a lightly doped N-type epitaxial layer, and its size can be proportionally reduced, which is beneficial for high-density sensor pixel array integration. Furthermore, the isolation between pixels through a second isolation trench effectively reduces electronic crosstalk between pixels and lowers sensor noise. Moreover, after wafer thinning, the incident light enters from the back side, which increases the depth of the PN junction depletion region in silicon compared to the front-illuminated type, significantly improving the near-infrared laser detection efficiency of the sensor.

[0083] It should be noted that implementations not illustrated or described in the accompanying drawings or the main text of the specification are all forms known to those skilled in the art and are not described in detail. Furthermore, the definitions of the various components and methods described above are not limited to the specific structures, shapes, or methods mentioned in the embodiments. Those skilled in the art can easily modify or substitute them. For example, the size of the photosensitive area of ​​the single-photon avalanche diode, the type of silicon-doped ion implantation, and the concentration of each ion implantation can be varied according to actual conditions.

[0084] It should also be noted that this document provides examples of parameters containing specific values, but these parameters need not be exactly equal to the corresponding values, but can approximate the corresponding values ​​within acceptable error tolerances or design constraints. Directional terms mentioned in the embodiments, such as "up," "down," "front," "back," "left," and "right," are only for reference to the accompanying drawings and are not intended to limit the scope of protection of this invention.

[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A single-photon avalanche diode image sensor pixel device, comprising: Substrate; A first P-type silicon doped region is provided inside the substrate; An N-type epitaxial layer is disposed on the substrate; The N-type epitaxial layer contains a second P-type silicon doped region, a third P-type silicon doped region, a fourth P-type silicon doped region, and an N-type silicon doped region. The upper surface of the first P-type silicon doped region is provided with a second P-type silicon doped region, a third P-type silicon doped region, and a fourth P-type silicon doped region from left to right. The N-type silicon doped region is disposed on the fourth P-type silicon doped region to form a PN junction; A first isolation region is provided between the second P-type silicon doped region and the N-type silicon doped region, and between the third P-type silicon doped region and the N-type silicon doped region. The first isolation region includes a first isolation trench and an N-type epitaxial layer disposed between the second P-type silicon doped region and the fourth P-type silicon doped region, for isolating the cathode and anode of the pixel device. A second isolation region is provided on the side of the second P-type silicon doped region away from the first isolation region and on the side of the third P-type silicon doped region away from the first isolation region, for isolation between the pixel devices.

2. The device according to claim 1, wherein, The specific ion concentration range of the N-type silicon doped region, the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region includes 1E14~1E20 cm⁻¹. -3 .

3. The device according to claim 1, wherein, The width of the first isolation region ranges from 0.05 to 2 μm.

4. The device according to claim 3, wherein, The width of the first isolation groove is 0.1~1µm, and the depth is 0.1~1µm.

5. The device according to claim 1, wherein, The second isolation region includes a second isolation trench that penetrates the N-type epitaxial layer and extends into the substrate. The width of the second isolation trench is 0.1~5 μm and the depth is 10~70 μm.

6. The device according to claim 1, wherein, The thickness of the N-type epitaxial layer ranges from 1 to 7 μm.

7. A method for preparing the device according to any one of claims 1 to 6, characterized in that, Provide a substrate; A first P-type silicon doped region is formed on the substrate; An N-type epitaxial layer is grown on the substrate; A first isolation region and a second isolation region are defined in the N-type epitaxial layer; A first isolation trench is formed on the first isolation region by etching. A second isolation trench is formed by etching on the second isolation region. The second isolation trench penetrates the N-type epitaxial layer and extends into the interior of the substrate. A second P-type silicon doped region and a third P-type silicon doped region are formed by ion implantation between the first isolation region and the second isolation region; A fourth P-type silicon doped region is formed between the first isolation regions by ion implantation; An N-type silicon doped region is formed between the first isolation regions by ion implantation, and a PN junction is formed between the N-type silicon doped region and the fourth P-type silicon doped region; A cathode is formed by etching in the N-type silicon doped region; In both the second and third P-type silicon doped regions, an anode is formed by etching to obtain a pixel device.

8. The method according to claim 7, wherein, The step of forming a first P-type silicon doped region on the substrate includes: forming the first P-type silicon doped region on the substrate by ion implantation.

9. The method according to claim 7, wherein, The dopant ions in the first P-type silicon doped region, the second P-type silicon doped region, the third P-type silicon doped region, and the fourth P-type silicon doped region all include boron.

10. The method according to claim 7, wherein, The doping ions in the N-type silicon doped region include phosphorus.

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