Display device

Abstract

A display device includes a display area configured to display an image, a first non-display area arranged adjacent to the display area, a second non-display area arranged adjacent to the first non-display area, and a first driving voltage line arranged in the first non-display area and the second non-display area, the first driving voltage line configured to be applied with a first driving voltage and including a first sub-driving voltage line including a first hole and a second sub-driving voltage line arranged on the first sub-driving voltage line and including a second hole, wherein the second hole includes a first sub-hole and a second sub-hole having a size different from the first sub-hole.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate generally to display devices, and more specifically, to display devices with high reliability. Background Technology

[0002] With the development of the information society, increasing demands are being placed on display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and light-emitting displays. Light-emitting displays include organic light-emitting displays containing organic light-emitting elements, inorganic light-emitting displays containing inorganic light-emitting elements such as inorganic semiconductors, and micro-light-emitting displays containing micro-light-emitting elements.

[0003] Organic light-emitting display devices can be manufactured by forming thin-film transistors on a substrate, forming a planarization layer on the thin-film transistors, and forming light-emitting elements, each having an anode electrode, a light-emitting layer, and a cathode electrode, on the planarization layer. To protect the light-emitting layer and cathode electrode from oxygen and moisture, an encapsulation layer comprising multiple organic and inorganic layers can be further formed on the light-emitting element.

[0004] The planarization layer can be formed from organic layers such as photopolymer acrylic and polyimide. Due to the moisture-absorbing nature of the planarization layer when exposed to air, moisture must be removed from the vacuum deposition equipment before placing the substrate on which the thin-film transistors will be formed into the vacuum deposition equipment during the planarization layer deposition process. However, some moisture may still remain on the planarization layer. In this case, the exhaust gas generated from the planarization layer may damage the light-emitting layer of the light-emitting element, which may cause sub-pixels, including those with damaged light-emitting layers, to appear as black spots.

[0005] The information disclosed above in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] The display device constructed according to an exemplary embodiment of the present invention can reduce or prevent damage to the light-emitting layer of the light-emitting element caused by exhaust gas generated by the organic layer.

[0007] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the inventive concept.

[0008] A display device according to an exemplary embodiment includes: a display area configured to display an image; a first non-display area arranged adjacent to the display area; a second non-display area arranged adjacent to the first non-display area; and a first driving voltage line arranged in the first and second non-display areas, the first driving voltage line being configured to be applied a first driving voltage and including: a first sub-driving voltage line including a first hole; and a second sub-driving voltage line arranged on the first sub-driving voltage line and including a second hole, wherein the second hole includes a first sub-hole and a second sub-hole, and the size of the second sub-hole is different from the size of the first sub-hole.

[0009] The first sub-hole can be arranged in the first non-display area and the second non-display area, and the second sub-hole can be arranged in the first non-display area.

[0010] The length of the second sub-hole in the first direction can be greater than the length of the first sub-hole in the first direction.

[0011] The first hole, the first sub-hole, and the second sub-hole can be non-overlapping.

[0012] The second sub-driving voltage line can be connected to the first sub-driving voltage line through the first connection hole in the first non-display area and the second non-display area, and the first connection hole may not overlap with the first hole and the second hole.

[0013] In the first non-display area, one of the first connecting holes may be arranged in a first direction between one of the first holes and one of the first sub-holes.

[0014] In the first non-display area, one of the first connecting holes and one of the first holes can be arranged between adjacent second sub-holes in a second direction that intersects the first direction.

[0015] In the second non-display area, the first hole and the first sub-hole can be alternately set in the first direction.

[0016] In the second non-display area, the first hole and the first sub-hole can be alternately arranged in a second direction that intersects the first direction.

[0017] In the second non-display area, one of the first connecting holes can be arranged in the first direction between one of the first holes and one of the first sub-holes.

[0018] The display device may further include: a pixel electrode and a light-emitting layer disposed in the display area; and a common electrode disposed on the light-emitting layer and connected to a second sub-driving voltage line through a second connection hole in the second non-display area.

[0019] One of the second connecting holes can overlap with one of the first holes.

[0020] A display device according to another exemplary embodiment includes: a display area configured to display an image; a first non-display area arranged adjacent to the display area; a second non-display area arranged adjacent to the first non-display area; and a first sub-driving voltage line arranged in the first and second non-display areas, the first sub-driving voltage line being configured to be applied a first driving voltage and including a first aperture, wherein the first aperture includes a first sub-aperture and a second sub-aperture, the size of the second sub-aperture being different from the size of the first sub-aperture.

[0021] The first sub-hole can be arranged in the first non-display area and the second non-display area, and the second sub-hole can be arranged in the first non-display area.

[0022] The length of the second sub-hole in the first direction can be greater than the length of the first sub-hole in the first direction.

[0023] The display device may further include: a second sub-driving voltage line, disposed on the first sub-driving voltage line and including a second hole, wherein the second hole, the first sub-hole and the second sub-hole may not overlap each other.

[0024] The second sub-driving voltage line can be connected to the first sub-driving voltage line through the first connection hole in the first non-display area and the second non-display area, and the first connection hole may not overlap with the first hole and the second hole.

[0025] A display device according to yet another exemplary embodiment includes: a display area configured to display an image; a first non-display area arranged adjacent to the display area; a second non-display area arranged adjacent to the first non-display area; and a first driving voltage line arranged in the first and second non-display areas, the first driving voltage line being configured to be applied a first driving voltage and including: a first sub-driving voltage line including a first hole; and a second sub-driving voltage line arranged on the first sub-driving voltage line and including a second hole, wherein the size of one of the second holes in the first non-display area is different from the size of one of the second holes in the second non-display area.

[0026] In the first non-display area, the size of one of the first holes may be different from the size of one of the second holes.

[0027] The length of the second hole in the first non-display area in the first direction can be greater than the length of the second hole in the second non-display area in the first direction.

[0028] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept.

[0030] Figure 1 This is a perspective view illustrating a display device according to an exemplary embodiment.

[0031] Figure 2 and Figure 3 This is a plan view illustrating a display device according to an exemplary embodiment.

[0032] Figure 4 This is a side view illustrating a display device according to an exemplary embodiment.

[0033] Figure 5 This is a layout diagram illustrating the scan driver, scan fan-out line, data fan-out line, and first drive voltage line of a display panel according to an exemplary embodiment.

[0034] Figure 6 This is according to an exemplary embodiment. Figure 5 The layout diagram of the display area.

[0035] Figure 7 This is a layout diagram illustrating a display area, a first non-display area, a second non-display area, a first driving voltage line, and a common electrode according to an exemplary embodiment.

[0036] Figure 8 This is according to an exemplary embodiment. Figure 7 The layout diagram of the first non-display area.

[0037] Figure 9 This is according to an exemplary embodiment. Figure 7 The layout diagram of the second non-display area.

[0038] Figure 10 According to an exemplary embodiment, along Figure 6 A cross-sectional view of the display panel taken from line I-I'.

[0039] Figure 11 According to an exemplary embodiment, along Figure 8 A cross-sectional view of the display panel taken from line II-II'.

[0040] Figure 12 According to an exemplary embodiment, along Figure 8 The cross-sectional view of the display panel taken from line III-III'.

[0041] Figure 13 According to an exemplary embodiment, along Figure 9 A cross-sectional view of the display panel taken from line IV-IV'.

[0042] Figure 14 According to an exemplary embodiment, along Figure 9 A cross-sectional view of the display panel taken from line V-V'.

[0043] Figure 15 According to another exemplary embodiment Figure 7 The layout diagram of the first non-display area.

[0044] Figure 16 According to another exemplary embodiment Figure 7 The layout diagram of the second non-display area.

[0045] Figure 17 According to an exemplary embodiment, along Figure 15 A cross-sectional view of the display panel taken from line VII-VII'.

[0046] Figure 18 This is according to yet another exemplary embodiment. Figure 7 The layout diagram of the first non-display area.

[0047] Figure 19 This is according to yet another exemplary embodiment. Figure 7 The layout diagram of the second non-display area.

[0048] Figure 20 According to an exemplary embodiment, along Figure 18 A cross-sectional view of the display panel taken from line IX-IX'. Detailed Implementation

[0049] In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more inventive concepts disclosed herein. However, it will be apparent, however, that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are illustrated in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but are not necessarily exclusive. For example, a particular shape, configuration, and feature of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0050] Unless otherwise stated, the illustrated exemplary embodiments should be understood as providing exemplary features detailing variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged, and / or rearranged in other ways without departing from the inventive concept.

[0051] Crosshairs and / or shading are typically used in accompanying drawings to clarify boundaries between adjacent elements. Therefore, unless explicitly stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between illustrated elements, and / or any other characteristics, properties, or characteristics of the elements. Furthermore, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, specific processes may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Additionally, the same reference numerals denote the same elements.

[0052] When a component or layer is referred to as being "on," "connected to," or "coupled to" another component or layer, it can be directly on, connected to, or coupled to the other component or layer, or an intermediary component or layer may be present. However, when a component or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another component or layer, an intermediary component or layer is not present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection with or without an intermediary component. Furthermore, the D1, D2, and D3 axes are not limited to the three axes of a Cartesian coordinate system (such as the x, y, and z axes) and can be interpreted in a broader sense. For example, the D1, D2, and D3 axes can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0054] Spatial relative terms, such as “below,” “under,” “lower,” “lower part,” “above,” “upper part,” “above,” “higher,” “side” (e.g., in “sidewall”), etc., are used herein for descriptive purposes and thus to describe the relationship of one element to another(s) as illustrated in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture other than those depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features would then be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0055] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the (described)” are intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, when the terms “comprising” and / or “including” are used in this specification, they specify the presence of stated features, integrals, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof. It should also be noted that, as used herein, the terms “basically,” “about,” and other similar terms are used as approximate terms rather than degree terms, and are therefore utilized to explain the inherent biases in measured, calculated, and / or provided values ​​that would be recognized by one of ordinary skill in the art.

[0056] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views, which are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the shape of the illustrations are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the exemplary embodiments disclosed herein should not necessarily be interpreted as limited to the specific illustrated shapes of the regions, but should include, for example, deviations in shape due to manufacturing processes. In this way, the regions illustrated in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore are not necessarily intended to be limiting.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in commonly used dictionaries, shall be interpreted as having the same meaning as they have in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly stated otherwise.

[0058] Figure 1 This is a perspective view illustrating a display device according to an exemplary embodiment.

[0059] Reference Figure 1 The display device 10 is a device for displaying moving or still images. The display device 10 can be used as a display screen for various devices such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs).

[0060] Display device 10 may be a light-emitting display device, such as an organic light-emitting display using organic light-emitting diodes, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including inorganic semiconductors, and a micro light-emitting display using micro light-emitting diodes (LEDs) or nano light-emitting diodes (LEDs). Hereinafter, display device 10 will be exemplarily described as an organic light-emitting display device, but the inventive concept is not limited thereto.

[0061] The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0062] In a planar view, the display panel 100 can be formed as a basic rectangular shape having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The corners where the short side in the first direction (X-axis direction) and the long side in the second direction (Y-axis direction) intersect can be rounded to have a predetermined curvature or can be right angles. The planar shape of the display panel 100 is not limited to a rectangular shape and can be formed as other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 can be formed as flat, but is not limited to this. For example, the display panel 100 may include curved portions formed at the left and / or right ends and having a predetermined curvature or a varying curvature. Additionally, the display panel 100 can be flexible so that it can be bent, folded, or rolled up.

[0063] Display panel 100 may include a main area MA and a sub-area SBA.

[0064] The main region MA may include the display area DA that displays the image and the non-display area NDA that is the outer region of the display area DA. The display area DA may include sub-pixels of the displayed image. The sub-region SBA may protrude from one side of the main region MA in a second direction (Y-axis direction).

[0065] Despite Figure 1 The diagram exemplarily illustrates a sub-region SBA unfolded, but the sub-region SBA can be bent to be placed on the bottom surface of the display panel 100. When the sub-region SBA is bent, it can be placed on the substrate SUB (see [reference]). Figure 4 The thickness direction (Z-axis direction) of the sub-region SBA overlaps with the main region MA. The sub-region SBA may include display driving circuitry 200 formed thereon.

[0066] The display driving circuit 200 can generate signals and voltages for driving the display panel 100. The display driving circuit 200 can be formed as an integrated circuit (IC) and attached to the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method, but the inventive concept is not limited thereto. For example, in some exemplary embodiments, the display driving circuit 200 can be attached to the circuit board 300 by a chip-on-film (COF) method.

[0067] The circuit board 300 can be attached to one end of a sub-area SBA of the display panel 100. Therefore, the circuit board 300 can be electrically connected to the display panel 100 and the display driving circuit 200. The display panel 100 and the display driving circuit 200 can receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 can be a flexible film, a printed circuit board, or a chip-on-film, such as a flexible printed circuit board.

[0068] Figure 2 and Figure 3 This is a plan view of a display device according to an embodiment. Figure 4 This is a side view illustrating a display device according to an exemplary embodiment.

[0069] Figure 2 The example shows that the subregion SBA is expanded without bending, and Figure 3 An example is shown where the subregion SBA is bent.

[0070] Reference Figure 2 and Figure 3 The display panel 100 may include a main area MA and a sub-area SBA.

[0071] The main area MA may include the display area DA for displaying the image and the non-display area NDA that is the outer perimeter of the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be located at the center of the main area MA.

[0072] The display area DA may include scan lines extending in a first direction (X-axis direction), data lines extending in a second direction (Y-axis direction), and sub-pixels connected to the scan lines and data lines. Each sub-pixel may be connected to at least one scan line and at least one data line. When a scan signal is applied to at least one scan line, a data voltage corresponding to the data line may be supplied to each sub-pixel. Each sub-pixel may emit light with a predetermined brightness according to the data voltage.

[0073] The non-display area NDA can be arranged adjacent to the display area DA. The non-display area NDA can be an area outside the display area DA. The non-display area NDA can be arranged around the display area DA, but is not limited thereto. The non-display area NDA can be an edge area of ​​the display area DA.

[0074] The sub-region SBA can protrude from one side of the main region MA in the second direction (Y-axis direction). The length of the sub-region SBA in the second direction (Y-axis direction) can be less than the length of the main region MA in the second direction (Y-axis direction). The length of the sub-region SBA in the first direction (X-axis direction) can be substantially equal to or less than the length of the main region MA in the first direction (X-axis direction). The sub-region SBA can be bent to be placed on the bottom surface of the display panel 100. In this case, the sub-region SBA can overlap with the main region MA in the third direction (Z-axis direction).

[0075] The sub-region SBA can include the protruding region PA, the pad region PDA, and the bent region BA.

[0076] The protruding area PA is the area that protrudes from one side of the main area MA in the second direction (Y-axis direction). One side of the protruding area PA can be connected to the non-display area NDA, and the other side of the protruding area PA can be connected to the curved area BA.

[0077] The pad area PDA is the region on which pads PD and display driving circuitry 200 are arranged. The display driving circuitry 200 can be attached to the driving pads of the pad area PDA using a low-resistance, high-reliability material such as self-assembly anisotropic conductive adhesive (SAP) or anisotropic conductive film. The circuit board 300 can be attached to the pads PD of the pad area PDA using a low-resistance, high-reliability material such as SAP or anisotropic conductive film. One side of the pad area PDA can be connected to the curved area BA.

[0078] The curved region BA is a region that can be bent. When bent, the curved region BA can be positioned below the protruding region PA and the main region MA. The curved region BA can be positioned between the protruding region PA and the pad region PDA. One end of the curved region BA can be connected to the protruding region PA, and the other end of the curved region BA can be connected to the pad region PDA.

[0079] Furthermore, the display panel 100 may include a first scan driver 410 and a second scan driver 420. The first scan driver 410 and the second scan driver 420 may be connected to the scan lines of the display area DA. Both the first scan driver 410 and the second scan driver 420 may be connected via scan fan-out lines (…). Figure 5 The first scan driver 410 and the second scan driver 420 can both generate scan signals according to the scan timing signals and output the scan signals to the scan lines of the display area DA.

[0080] The first scan driver 410 and the second scan driver 420 can be disposed in the non-display area NDA. The first scan driver 410 can be arranged outside the left side of the display area DA, and the second scan driver 420 can be arranged outside the right side of the display area DA.

[0081] Despite Figure 2 and Figure 3 The diagram shows a display panel 100 including two scan drivers 410 and 420; however, the inventive concept is not limited thereto. In some exemplary embodiments, the display panel 100 may include a single scan driver, and in this case, one of the first scan driver 410 and the second scan driver 420 may be omitted.

[0082] Figure 4 This is a side view illustrating a display device according to an exemplary embodiment.

[0083] More specifically, Figure 4 It is along Figure 3 A cross-sectional view taken from line A-A' of the display device 10.

[0084] Reference Figure 4 The display panel 100 may include a substrate SUB, a thin film transistor layer TFTL, a light-emitting element layer EML, a thin film encapsulation layer TFEL, and a sensor electrode layer SENL.

[0085] A thin-film transistor layer (TFTL) can be disposed on a substrate SUB. The TFTL can be located in a main region (MA) and a sub-region (SBA). The TFTL can include thin-film transistors (TFTs). Figure 10TFT, scan lines, data lines, scan fan-out lines (in the image) Figure 5 SFL in the middle), data fan-out line ( Figure 5 DFL in the middle), first drive voltage line ( Figure 5 The VSL, the first scan driver 410, and the second scan driver 420 are included.

[0086] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The EML can be disposed in the display area (DA) of the main area (MA). The EML may include light-emitting elements disposed in the emission area.

[0087] A thin-film encapsulation layer (TFEL) can be disposed on the light-emitting element layer (EML). The TFEL can be located in the display area (DA) and non-display area (NDA) of the main area (MA). The TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light-emitting element layer (EML).

[0088] The sensor electrode layer SENL can be disposed on the thin-film encapsulation layer TFEL. The sensor electrode layer SENL can be located in the main region MA and the protruding region PA of the sub-region SBA. The sensor electrode layer SENL may not be located in the curved region BA of the sub-region SBA or the pad region PDA. The sensor electrode layer SENL can detect touch from a human body or object via sensor electrodes.

[0089] A polarizing film can be disposed on the sensor electrode layer SENL to prevent external light reflected by the lines and electrodes of the display panel 100 from reducing the user's visual perception of the display panel 100. The polarizing film may include a first substrate material, a linear polarizer, a phase retardation film such as a λ / 4 (quarter-wave) plate and / or a λ / 2 (half-wave) plate, and a second substrate material. For example, the first substrate material, the linear polarizer, the λ / 4 plate, the λ / 2 plate, and the second substrate material may be sequentially stacked on the sensor electrode layer SENL.

[0090] To protect the upper portion of the display panel 100, a cover window can be arranged on a polarizing film. The cover window can be attached to the polarizing film using a transparent adhesive material such as optically transparent resin (OCR) or optically transparent adhesive (OCA) film. The cover window can be made of inorganic materials such as glass or organic materials such as plastics or polymers.

[0091] Figure 5 This is a layout diagram of the scan driver, scan fan-out line, data fan-out line, and first drive voltage line of a display panel according to an exemplary embodiment. Specifically, Figure 5 Detailed illustrations according to exemplary embodiments Figure 2 The layout diagram of area A.

[0092] To simplify the illustration, Figure 5 The first scan driver 410, the scan fan-out line SFL connecting the first scan driver 410 to the display driver circuit 200, the data line of the display area DA connecting the data fan-out line DFL of the display driver circuit 200, and the first drive voltage line VSL are shown only by way of example.

[0093] The scan fan-out line SFL can be connected to the first scan driver 410. The first scan driver 410 can be connected to the display driver circuit 200 via the scan fan-out line SFL. The first scan driver 410 can receive scan timing signals from the display driver circuit 200 via the scan fan-out line SFL. The first scan driver 410 can generate scan signals according to the scan timing signals. The first scan driver 410 can output scan signals to the scan lines of the display area DA.

[0094] Scan fan-out line (SFL), data fan-out line (DFL), and first drive voltage line (VSL) can be set in the non-display area (NDA) and the protruding area (PA), curved area (BA), and pad area (PDA) of the sub-area (SBA).

[0095] Each scan fan-out line (SFL) can include a first sub-scan fan-out line (SFL1), a scan connection line (SCL), and a second sub-scan fan-out line (SFL2).

[0096] The first sub-scan fan-out line SFL1 can be set in the non-display area NDA and the protruding area PA. The first sub-scan fan-out line SFL1 can be arranged between the first scan driver 410 and the scan connection line SCL. One end of the first sub-scan fan-out line SFL1 can be connected to the first scan driver 410, and the other end of the first sub-scan fan-out line SFL1 can be connected to the scan connection line SCL.

[0097] The scan connection line SCL can be positioned within the protruding region PA, the curved region BA, and the pad region PDA. The scan connection line SCL can be positioned between the first sub-scan fan-out line SFL1 and the second sub-scan fan-out line SFL2. One end of the scan connection line SCL can be connected to the first sub-scan fan-out line SFL1 via the first scan connection hole SCT1 in the protruding region PA, and the other end of the scan connection line SCL can be connected to the second sub-scan fan-out line SFL2 via the second scan connection hole SCT2 in the pad region PDA.

[0098] The second sub-scan fan-out line SFL2 can be set in the pad area of ​​the PDA. The second sub-scan fan-out line SFL2 can be arranged between the scan connection line SCL and the display driver circuit. Figure 2Between 200 and 200. One end of the second sub-scan fan-out line SFL2 can be connected to the scan connection line SCL, and the other end of the second sub-scan fan-out line SFL2 can be connected to the display driver circuit ( Figure 2 (200 in the middle).

[0099] Each data fan-out line (DFL) may include a first sub-data fan-out line (DFL1), a data connection line (DCL), and a second sub-data fan-out line (DFL2).

[0100] The first sub-data fan-out line DFL1 can be located in the non-display area NDA and the protruding area PA. The first sub-data fan-out line DFL1 can be positioned between the data line and the data connection line DCL. One end of the first sub-data fan-out line DFL1 can be connected to the data line via a data contact hole, and the other end of the first sub-data fan-out line DFL1 can be connected to the data connection line DCL via a first data connection hole DCT1.

[0101] Data connection lines (DCLs) can be positioned within the protruding region PA, the curved region BA, and the pad region PDA. The DCLs can be positioned between a first sub-data fan-out line DFL1 and a second sub-data fan-out line DFL2. One end of the DCL can be connected to the first sub-data fan-out line DFL1 via a first data connection hole DCT1 in the protruding region PA, and the other end of the DCL can be connected to the second sub-data fan-out line DFL2 via a second data connection hole DCT2 in the pad region PDA.

[0102] The second sub-data fan-out line DFL2 can be set in the pad area of ​​the PDA. The second sub-data fan-out line DFL2 can be arranged between the data connection line DCL and the display driver circuit (…). Figure 2 Between 200 in the middle). One end of the second sub-data fan-out line DFL2 can be connected to the data connection line DCL, and the other end of the second sub-data fan-out line DFL2 can be connected to the display driver circuit ( Figure 2 (200 in the middle).

[0103] In the following text, the scan fan-out line (SFL) and the data fan-out line (DFL) can be collectively referred to as fan-out lines.

[0104] The first driving voltage line VSL can be disposed in the non-display area NDA, the protruding area PA, and the curved area BA. The first driving voltage line VSL can be arranged between the first scan driver 410 in the display area DA and the non-display area NDA. The first driving voltage line VSL can overlap with the scan fan-out line SFL and the data fan-out line DFL in the non-display area NDA. The width of the first driving voltage line VSL in the non-display area NDA on the lower outer side of the display area DA can be greater than the width of the first driving voltage line VSL in the non-display area NDA on the left outer side of the display area DA. The first driving voltage line VSL can be connected to the voltage fan-out line VFL via the voltage connection hole VCT in the pad area PDA.

[0105] The voltage fan-out line VFL can be set in the pad area of ​​the PDA. The voltage fan-out line VFL can be arranged between the first drive voltage line VSL and the display drive circuit. Figure 2 Between 200 and 200. One end of the voltage fan-out line VFL can be connected to the first drive voltage line VSL, and the other end of the voltage fan-out line VFL can be connected to the display drive circuit ( Figure 2 (200 in the middle).

[0106] Figure 6 This is according to an exemplary embodiment. Figure 5 The layout diagram of the display area.

[0107] Figure 6 A light-emitting element layer according to an exemplary embodiment is shown. Figure 4 The first to fourth emission regions EA1, EA2, EA3 and EA4 of the EML and the sensor electrode layer ( Figure 4 The driving electrode TE and sensing electrode RE in SENL). Figure 6 An exemplary illustration shows a mutual capacitance type touch electrode comprising two sensor electrodes (i.e., a driving electrode TE and a sensing electrode RE) for detecting a user's touch. For simplicity of illustration, Figure 6 Only two sensing electrodes RE adjacent in the first direction (X-axis direction) and two driving electrodes TE adjacent in the second direction (Y-axis direction) are shown in the figure.

[0108] Reference Figure 6 The driving electrode TE and the sensing electrode RE can be electrically isolated from each other. The driving electrode TE and the sensing electrode RE can be configured to be separated from each other on the same layer. A gap can exist between the driving electrode TE and the sensing electrode RE.

[0109] The sensing electrode RE can be electrically connected in a first direction (X-axis direction). The driving electrode TE can be electrically connected in a second direction (Y-axis direction). In order to electrically decouple the sensing electrode RE and the driving electrode TE at their intersection, the driving electrode TE adjacent in the second direction (Y-axis direction) can be connected via the connecting electrode BE1.

[0110] The connecting electrode BE1 can be formed on a different layer than the layer on which the driving electrode TE and the sensing electrode RE are formed, and can be connected to the driving electrode TE via the first sensor contact hole TCNT1. One end of the connecting electrode BE1 can be connected via the first sensor contact hole TCNT1 to one of the driving electrodes TE adjacent in the second direction (Y-axis direction). The other end of the connecting electrode BE1 can be connected via the first sensor contact hole TCNT1 to the other driving electrode TE adjacent in the second direction (Y-axis direction). The connecting electrode BE1 can overlap with the sensing electrode RE in the third direction (Z-axis direction). Because the connecting electrode BE1 can be formed on a different layer than the layer on which the driving electrode TE and the sensing electrode RE are formed, the connecting electrode BE1 can be electrically decoupled from the sensing electrode RE even when it overlaps with the sensing electrode RE in the third direction (Z-axis direction).

[0111] The connecting electrode BE1 can be bent at least once. Figure 6 Exemplarily shown is the connecting electrode BE1 bent to have a basic bracket (staple) shape ("<" or ">"), and the inventive concept is not limited to a specific shape of the connecting electrode BE1. Since the drive electrodes TE adjacent in the second direction (Y-axis direction) are connected via a plurality of connecting electrodes BE1, the drive electrodes TE adjacent in the second direction (Y-axis direction) can still be electrically connected to each other even when one of the connecting electrodes BE1 is disconnected.

[0112] Each of the driving electrode TE and the sensing electrode RE can have a grid or mesh shape in the planar view. This is because the driving electrode TE and the sensing electrode RE are formed in a thin-film encapsulation layer ( Figure 4 On the TFEL in the middle, therefore the light-emitting element ( Figure 10 The common electrode of LEL in ( Figure 10 The distance between 173 and the driving electrode TE or sensing electrode RE can be small. This may be in the light-emitting element ( Figure 10 The common electrode of LEL in ( Figure 10 Parasitic capacitance is generated between the light-emitting element (173) and the driving electrode TE or sensing electrode RE. This parasitic capacitance is related to the light-emitting element (...). Figure 10 The common electrode of LEL in ( Figure 10The size of the overlapping area between the driving electrode TE and the sensing electrode RE is proportional to the size of 173 in the diagram. Therefore, in order to reduce parasitic capacitance, the driving electrode TE and the sensing electrode RE can have a grid or mesh shape in the planar diagram.

[0113] The display area DA may include multiple sub-pixels for displaying images. Each sub-pixel may include a light-emitting element for emitting a specific type of light. Figure 10 The thin-film transistor (TFTL) consists of an LEL (Light Emitting Layer) and a TFTL (Thin Film Transistor Layer). Each of the emission regions EA1, EA2, EA3, and EA4 represents a light-emitting element (LED) used to emit a specific light. Figure 10 The LEL (Lowest Least Least) emission area.

[0114] For example, when the display area DA includes the first to fourth sub-pixels, the first emission area EA1 can be a light-emitting element of the first sub-pixel for emitting the first light. Figure 10 The second emission region EA2 can be the light-emitting element of the second sub-pixel for emitting the second light. Figure 10 The third emission region EA3 can be the light-emitting element (LEL) of the third sub-pixel for emitting the third light. Figure 10 The fourth emission region EA4 can be the light-emitting element of the fourth sub-pixel for emitting the fourth light. Figure 10 The emission region of the LEL (Leadership Level) in the image. The first to fourth sub-pixels can be defined as a single pixel used to represent white grayscale.

[0115] The first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 can emit light of different colors. In some exemplary embodiments, at least two of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 can emit light of the same color. For example, the first emission region EA1 can emit red light, the second emission regions EA2 and the fourth emission region EA4 can emit green light, and the third emission region EA3 can emit blue light.

[0116] Although each of the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 is exemplarily shown as having a basic quadrilateral shape (such as a rhombus in a plan view), the inventive concept is not limited thereto. For example, in some exemplary embodiments, the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 may all have a polygonal shape other than a quadrilateral, a circle, or an ellipse in a plan view. Furthermore, although the third emission region EA3 is exemplarily shown as the largest, the first emission region EA1 as the second largest, and the second emission region EA2 and the fourth emission region EA4 as the smallest among the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4, the inventive concept is not limited thereto.

[0117] Because the driving electrode TE, sensing electrode RE, and connecting electrode BE1 are arranged in a grid structure or mesh structure in the plan view, the emission region EA can be designed not to overlap with the driving electrode TE, sensing electrode RE, and connecting electrode BE1 in the third direction (Z-axis direction). In this way, the reduction in brightness of light emitted from each of the emission regions EA can be avoided or mitigated, which could otherwise be caused by the driving electrode TE, sensing electrode RE, and connecting electrode BE1 blocking the light.

[0118] Figure 7 This is a layout diagram illustrating a display area, a first non-display area, a second non-display area, a first driving voltage line, and a common electrode according to an exemplary embodiment. Specifically, Figure 7 This is a detailed illustration based on exemplary embodiments. Figure 5 The layout diagram of area B.

[0119] Reference Figure 7 The non-display area NDA may include a first non-display area NDA1 located near the display area DA and a second non-display area NDA2 located near the first non-display area NDA1. The first non-display area NDA1 may be arranged between the display area DA and the second non-display area NDA2. The second non-display area NDA2 may be arranged at the edge of the display panel 100.

[0120] A first driving voltage line VSL can be disposed in a first non-display area NDA1 and a second non-display area NDA2. The first driving voltage line VSL includes a first sub-driving voltage line SVSL1 and a second sub-driving voltage line SVSL2 that overlap each other in the third direction (Z-axis direction). The second sub-driving voltage line SVSL2 can be disposed on the first sub-driving voltage line SVSL1.

[0121] The second sub-driving voltage line SVSL2 can be accessed via multiple first connection holes in the first non-display area NDA1 and the second non-display area NDA2. Figure 8 and Figure 9 CCT1 in the first sub-drive voltage line SVSL1 is connected to the first sub-drive voltage line SVSL1. In this case, a first drive voltage can be applied to the first sub-drive voltage line SVSL1 and the second sub-drive voltage line SVSL2.

[0122] Despite Figure 7 The illustration exemplarily shows that the width W1 of the first sub-driving voltage line SVSL1 is greater than the width W2 of the second sub-driving voltage line SVSL2, but the inventive concept is not limited thereto. In some exemplary embodiments, the width of the first sub-driving voltage line SVSL1 may be smaller than the width of the second sub-driving voltage line SVSL2, or the first sub-driving voltage line SVSL1 and the second sub-driving voltage line SVSL2 may have substantially the same width as each other.

[0123] A common electrode 173 can be disposed in the display area DA and the first non-display area NDA1 and the second non-display area NDA2. The common electrode 173 can overlap with the first sub-driving voltage line SVSL1 and the second sub-driving voltage line SVSL2 in the third direction (Z-axis direction). The common electrode 173 can be arranged on the second sub-driving voltage line SVSL2.

[0124] The common electrode 173 can be connected via multiple second connection holes in the second non-display area NDA2. Figure 9 The CCT2 in the middle is connected to the second sub-drive voltage line SVSL2. In this way, a first drive voltage can be applied to the common electrode 173.

[0125] The end of the first sub-driving voltage line SVSL1 can be arranged closer to the edge of the substrate SUB than the end of the common electrode 173. Specifically, the end of the second sub-driving voltage line SVSL2 can be arranged closer to the edge of the substrate SUB than the end of the common electrode 173.

[0126] Figure 8 This is according to an exemplary embodiment. Figure 7 Detailed layout diagram of the first non-display area. Figure 9 Detailed illustrations according to exemplary embodiments Figure 7 The layout diagram of the second non-display area.

[0127] Figure 8 yes Figure 7 A detailed layout diagram of area C, and Figure 9 yes Figure 7 Detailed layout diagram of area D.

[0128] Reference Figure 8and Figure 9 The first sub-driving voltage line SVSL1 may include a first hole SH1 disposed in the first non-display area NDA1 and the second non-display area NDA2. The second sub-driving voltage line SVSL2 may include a second hole SH2 disposed in the first non-display area NDA1 and the second non-display area NDA2. The first hole SH1 and the second hole SH2 may form an exhaust channel for the organic layer. The exhaust channel formed by the first hole SH1 and the second hole SH2 will be referred to later. Figure 11 and Figure 12 To describe in more detail.

[0129] The first hole SH1 and the second hole SH2 can be alternately set on a directional DRA. For example, the first hole SH1 and the second hole SH2 can be set on a directional DRA in the order of first hole SH1, second hole SH2, first hole SH1 and second hole SH2.

[0130] The first hole SH1 and the second hole SH2 can be alternately set on the DRB in another direction. For example, the first hole SH1 and the second hole SH2 can be set on the DRB in another direction in the order of first hole SH1, second hole SH2, first hole SH1 and second hole SH2.

[0131] The second sub-driving voltage line SVSL2 can be connected to the first sub-driving voltage line SVSL1 via a first connecting hole CCT1 disposed in the first non-display area NDA1 and the second non-display area NDA2. The first hole SH1, the second hole SH2, and the first connecting hole CCT1 can be non-overlapping with each other in the third direction (Z-axis direction). The first connecting hole CCT1 can be disposed between the first hole SH1 and the second hole SH2 in an odd-numbered column on the opposite direction DRB, and can also be disposed between the first hole SH1 and the second hole SH2 in an even-numbered column on the opposite direction DRB.

[0132] The common electrode 173 can be connected to the second sub-drive voltage line SVSL2 via the second connection hole CCT2 located in the second non-display area NDA2. The second connection hole CCT2 can overlap with the first hole SH1 in the third direction (Z-axis direction).

[0133] Despite Figure 8 and Figure 9 The illustration exemplarily shows that the size of the second connecting hole CCT2 is smaller than the size of the first hole SH1, but the inventive concept is not limited thereto. In some exemplary embodiments, the size of the second connecting hole CCT2 may be larger than the size of the first hole SH1, or the size of the second connecting hole CCT2 may be substantially equal to the size of the first hole SH1.

[0134] Despite Figure 8 and Figure 9 The illustration exemplarily shows that the size of each of the first holes SH1 is smaller than the size of each of the second holes SH2, but the inventive concept is not limited thereto. In some exemplary embodiments, the size of each of the first holes SH1 may be larger than the size of each of the second holes SH2, or the size of each of the first holes SH1 may be substantially equal to the size of each of the second holes SH2.

[0135] Figure 10 According to an exemplary embodiment, along Figure 6 A cross-sectional view of the display panel taken from line I-I'.

[0136] Reference Figure 10 The substrate SUB can be made of an insulating material such as polymer resin or glass. For example, the substrate SUB may include polyimide. In this case, the substrate SUB can be a flexible substrate that can be bent, folded, or rolled up.

[0137] A thin-film transistor layer (TFTL), including a thin-film transistor (TFT), can be disposed on a substrate (SUB). The TFTL may include a thin-film transistor (TFT), a first anode connection electrode (ANDE1), a second anode connection electrode (ANDE2), a buffer layer (BF), a gate insulating layer (130), a first interlayer insulating layer (141), a second interlayer insulating layer (142), a first organic layer (160), and a second organic layer (161).

[0138] The buffer layer (BF) can be disposed on the substrate (SUB). The buffer layer (BF) can be formed of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0139] Thin-film transistors (TFTs) can be disposed on a buffer layer (BF). A thin-film transistor (TFT) may include an active layer (ACT), a gate electrode (G), a source electrode (S), and a drain electrode (D).

[0140] The active layer ACT, source electrode S, and drain electrode D of a thin-film transistor (TFT) can be disposed on a buffer layer BF. The active layer ACT can comprise a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. The source electrode S and drain electrode D can be formed by doping the silicon semiconductor with ions or impurities to make it conductive. The active layer ACT may overlap with the gate electrode G in the third direction (Z-axis direction) of the thickness direction of the substrate SUB, and the source electrode S and drain electrode D may not overlap with the gate electrode G in the third direction (Z-axis direction).

[0141] The gate insulating layer 130 can be disposed on the active layer ACT, the source electrode S, and the drain electrode D of the thin-film transistor TFT. The gate insulating layer 130 can be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0142] The gate electrode G and the first capacitor electrode CAE1 of the thin-film transistor (TFT) can be disposed on the gate insulating layer 130. The gate electrode G may overlap with the active layer ACT in the third direction (Z-axis direction). The first capacitor electrode CAE1 may overlap with the second capacitor electrode CAE2 in the third direction (Z-axis direction). The gate electrode G may be formed as a single layer or multiple layers, and may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0143] The first interlayer insulating layer 141 can be disposed on the gate electrode G and the first capacitor electrode CAE1. The first interlayer insulating layer 141 can be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0144] The second capacitor electrode CAE2 can be disposed on the first interlayer insulating layer 141. The first interlayer insulating layer 141 has a predetermined dielectric constant, and therefore, the capacitor can be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the first interlayer insulating layer 141 disposed between the first capacitor electrode CAE1 and the second capacitor electrode CAE2. The second capacitor electrode CAE2 can be formed as a single layer or multiple layers, and can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0145] The second interlayer insulating layer 142 can be disposed on the second capacitor electrode CAE2. The second interlayer insulating layer 142 can be formed of an inorganic layer (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The second interlayer insulating layer 142 may include multiple inorganic layers and may be thicker than the first interlayer insulating layer 141 in the third direction (Z-axis direction).

[0146] The first anode connection electrode ANDE1 can be disposed on the second interlayer insulating layer 142. The first anode connection electrode ANDE1 can be connected to the drain electrode D via a first anode contact hole ANCT1, which penetrates the first interlayer insulating layer 141 and the second interlayer insulating layer 142 to expose the drain electrode D of the thin-film transistor TFT. The first anode connection electrode ANDE1 can be formed as a single layer or multiple layers, and can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0147] The first organic layer 160 for planarization can be disposed on the first anode connection electrode ANDE1. The first organic layer 160 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0148] The second anode connection electrode ANDE2 can be disposed on the first organic layer 160. The second anode connection electrode ANDE2 can be connected to the first anode connection electrode ANDE1 via a second anode contact hole ANCT2, which penetrates the first organic layer 160 to expose the first anode connection electrode ANDE1. The second anode connection electrode ANDE2 can be formed as a single layer or multiple layers, and can include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0149] The second organic layer 161 can be disposed on the second anode connection electrode ANDE2. The second organic layer 161 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0150] although Figure 10 The exemplary diagram illustrates a thin-film transistor (TFT) having a top-gate structure in which the gate electrode is located above the active layer, but the inventive concept is not limited thereto. In some exemplary embodiments, the thin-film transistor TFT may be formed as a bottom-gate structure in which the gate electrode is located below the active layer, or as a dual-gate structure in which the gate electrodes are located above and below the active layer.

[0151] The light-emitting element layer (EML) can be disposed on the second organic layer 161. The EML may include light-emitting elements (LELs) and a barrier 180. Each of the light-emitting elements (LELs) includes a pixel electrode 171, a light-emitting layer 172, and a common electrode 173. The common electrode 173 may be commonly connected to multiple light-emitting elements (LELs).

[0152] Pixel electrode 171 may be formed on the second organic layer 161. Pixel electrode 171 may be connected to the second anode connection electrode ANDE2 via a third anode contact hole ANCT3, which penetrates the second organic layer 161 to expose the second anode connection electrode ANDE2.

[0153] In the top emission structure in which light is emitted towards the common electrode 173 when viewed relative to the light-emitting layer 172, the pixel electrode 171 can be formed of a metallic material with high reflectivity, having a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0154] The dam 180 can be formed to define the pixel electrode 171 on the second organic layer 161 to define an emission region EA (such as a third emission region EA3). The dam 180 can be formed to cover the edge of the pixel electrode 171. The dam 180 can be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0155] The emission region EA (such as the third emission region EA3) is a region in which the pixel electrode 171, the light-emitting layer 172 and the common electrode 173 are stacked sequentially, such that holes from the pixel electrode 171 and electrons from the common electrode 173 recombine with each other to emit light.

[0156] A light-emitting layer 172 is formed on the pixel electrode 171. The light-emitting layer 172 may include organic materials to emit light of a predetermined color. For example, the light-emitting layer 172 includes a hole transport layer, an organic material layer, and an electron transport layer.

[0157] A common electrode 173 is formed on the light-emitting layer 172 and the embankment 180. The common electrode 173 may be formed to cover the light-emitting layer 172. The common electrode 173 may be a common layer formed on each of the emission regions EA (such as the third emission region EA3). In some exemplary embodiments, a capping layer may be formed on the common electrode 173.

[0158] In the top-emitting structure, the common electrode 173 can be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) and indium zinc oxide (IZO) that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode 173 is formed of a semi-transmissive conductive material, the luminous efficiency can be improved due to the microcavity effect.

[0159] A thin-film encapsulation layer TFEL can be disposed on the common electrode 173. The thin-film encapsulation layer TFEL includes at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. In addition, the thin-film encapsulation layer TFEL includes at least one organic layer to protect the light-emitting element layer EML from foreign matter such as dust. For example, the thin-film encapsulation layer TFEL may include a first inorganic layer TFE1, an organic layer TFE2, and a second inorganic layer TFE3.

[0160] A first inorganic layer TFE1 can be disposed on the common electrode 173, an organic layer TFE2 can be disposed on the first inorganic layer TFE1, and a second inorganic layer TFE3 can be disposed on the organic layer TFE2. The first inorganic layer TFE1 and the second inorganic layer TFE3 can be formed by a multilayer of alternating stacked inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer TFE2 can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, etc.

[0161] The sensor electrode layer SENL can be disposed on the thin-film encapsulation layer TFEL. The sensor electrode layer SENL may include a first sensor insulating layer TINS1, a second sensor insulating layer TINS2, a third sensor insulating layer TINS3, a driving electrode TE, a sensing electrode RE, and a connection electrode BE1.

[0162] The first sensor insulating layer TINS1 can be disposed on the second inorganic layer TFE3. The first sensor insulating layer TINS1 can be formed by multiple layers of one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and aluminum oxide layers, which are stacked alternately.

[0163] The connecting electrode BE1 can be disposed on the first sensor insulating layer TINS1. The connecting electrode BE1 may not overlap with the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4 in the third direction (Z-axis direction). The connecting electrode BE1 may overlap with the dam 180 in the third direction (Z-axis direction). The connecting electrode BE1 may be formed from a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0164] The second sensor insulating layer TINS2 can be disposed on the connecting electrode BE1. The second sensor insulating layer TINS2 can be formed by multiple layers of one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide, which are stacked alternately.

[0165] The driving electrode TE and the sensing electrode RE can be arranged on the second sensor insulating layer TINS2. The driving electrode TE and the sensing electrode RE can be arranged in the third direction (Z-axis direction) without overlapping with the first emission region EA1, the second emission region EA2, the third emission region EA3, and the fourth emission region EA4. The driving electrode TE and the sensing electrode RE can overlap with the dam 180 in the third direction (Z-axis direction). The driving electrode TE can be connected to the first connecting electrode BE1 via the first sensor contact hole TCNT1 penetrating the second sensor insulating layer TINS2. The driving electrode TE and the sensing electrode RE can be formed from a single layer including molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or can be formed as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an Ag-Pd-Cu (APC) alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO).

[0166] The third sensor insulating layer TINS3 can be disposed on the driving electrode TE and the sensing electrode RE. The third sensor insulating layer TINS3 can be formed by multiple layers of one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and aluminum oxide layers, which are stacked alternately.

[0167] Figure 11 According to an exemplary embodiment, along Figure 8 A cross-sectional view of the display panel taken from line II-II'. Figure 12 According to an exemplary embodiment, along Figure 8 The cross-sectional view of the display panel taken from line III-III'. Figure 13 According to an exemplary embodiment, along Figure 9 A cross-sectional view of the display panel taken from line IV-IV'. Figure 14 According to an exemplary embodiment, along Figure 9 A cross-sectional view of the display panel taken from line V-V'.

[0168] Reference Figures 11 to 14The scanning fan-out line (SFL) can be disposed in the first non-display area NDA1 and the second non-display area NDA2. The scanning fan-out line (SFL) can include a first sub-scanning fan-out line (SFL1) disposed on the gate insulating layer 130 and a second sub-scanning fan-out line (SFL2) disposed on the first interlayer insulating layer 141. The first sub-scanning fan-out line (SFL1) can be disposed on the same layer as the gate electrode G and the first capacitor electrode CAE1 of the thin-film transistor (TFT), and can be made of substantially the same material as the gate electrode G and the first capacitor electrode CAE1 of the thin-film transistor (TFT). The second sub-scanning fan-out line (SFL2) can be disposed on the same layer as the second capacitor electrode CAE2, and can be made of substantially the same material as the second capacitor electrode CAE2.

[0169] Data fan-out lines (DFLs) can be disposed in the first non-display area NDA1 and the second non-display area NDA2. The data fan-out lines (DFLs) can include a first data fan-out line disposed on the gate insulating layer 130 and a second data fan-out line disposed on the first interlayer insulating layer 141. The first data fan-out line can be disposed on the same layer as the gate electrode G and the first capacitor electrode CAE1 of the thin-film transistor TFT, and can be made of substantially the same material as the gate electrode G and the first capacitor electrode CAE1 of the thin-film transistor TFT. The second data fan-out line can be disposed on the same layer as the second capacitor electrode CAE2, and can be made of substantially the same material as the second capacitor electrode CAE2.

[0170] The first sub-driving voltage line SVSL1 can be disposed on the first organic layer 160. The first sub-driving voltage line SVSL1 can be disposed on the same layer as the second anode connection electrode ANDE2, and can be made of substantially the same material as the second anode connection electrode ANDE2.

[0171] The second sub-driving voltage line SVSL2 can be disposed on the second organic layer 161. The second sub-driving voltage line SVSL2 can be disposed on the same layer as the pixel electrode 171, and can be made of substantially the same material as the pixel electrode 171.

[0172] The second sub-driving voltage line SVSL2 can be connected to the first sub-driving voltage line SVSL1 via the first connection hole CCT1 penetrating the second organic layer 161. The common electrode 173 can be connected to the second sub-driving voltage line SVSL2 via the second connection hole CCT2 penetrating the dike 180.

[0173] The drive line TL can be arranged on the first sensor insulating layer TINS1. The drive line TL can be arranged on the same layer as the connecting electrode BE1 and can be made of substantially the same material as the connecting electrode BE1. The drive line TL can be connected to the drive electrode TE disposed in the display area DA.

[0174] When the first hole SH1 of the first sub-drive voltage line SVSL1 and the second hole SH2 of the second sub-drive voltage line SVSL2 overlap each other in the third direction (Z-axis direction), the first sub-scan fan-out line SFL1 or the second sub-scan fan-out line SFL2 may overlap with the drive line TL. This may cause parasitic capacitance between the first sub-scan fan-out line SFL1 or the second sub-scan fan-out line SFL2 and the drive line TL. Parasitic capacitance may cause the scan timing signal of the first sub-scan fan-out line SFL1 or the second sub-scan fan-out line SFL2 to interfere with the touch drive signal of the drive line TL. To prevent parasitic capacitance from affecting the scan timing signal of the first sub-scan fan-out line SFL1 or the second sub-scan fan-out line SFL2 and the touch drive signal of the drive line TL, the first hole SH1 and the second hole SH2 can be set to not overlap each other in the third direction (Z-axis direction).

[0175] like Figure 12 As shown, exhaust gas generated by moisture remaining on the first organic layer 160 can be discharged through the first hole SH1 of the first sub-driving voltage line SVSL1 and the second hole SH2 of the second sub-driving voltage line SVSL2. When the first hole SH1 and the second hole SH2 do not overlap in the third direction (Z-axis direction), the exhaust gas discharge channel can be enlarged, and the exhaust gas discharge is delayed. In this case, the exhaust gas remaining inside may damage the light-emitting layer 172 of the light-emitting element LEL, and the sub-pixels including the damaged light-emitting layer 172 may not emit light.

[0176] Figure 15 According to another exemplary embodiment Figure 7 Detailed layout diagram of the first non-display area. Figure 16 According to another exemplary embodiment Figure 7 Detailed layout diagram of the second non-display area. Figure 17 According to an exemplary embodiment, along Figure 15 A cross-sectional view of the display panel taken from line VII-VII'.

[0177] Figures 15 to 17 The display panel and Figures 9 to 11 The display panels shown are substantially the same, but the second hole SH2 according to the illustrated exemplary embodiment includes a first sub-hole SSH1 and a second sub-hole SSH2 of different sizes. Therefore, repeated descriptions of the elements forming the display panel already described above will be omitted or simplified, and the differences will be described primarily below. Along Figure 15 The cross-sectional view of line VI-VI' of the display panel and Figure 11 They are essentially the same, and therefore their repeated detailed descriptions will be omitted.

[0178] Reference Figures 15 to 17 The second hole SH2 may include a first sub-hole SSH1 and a second sub-hole SSH2. The first sub-hole SSH1 may be set in the first non-display area NDA1 and the second non-display area NDA2, and the second sub-hole SSH2 may be set in the first non-display area NDA1.

[0179] The dimensions of each of the first sub-holes SSH1 can be smaller than the dimensions of each of the second sub-holes SSH2. The length LA1 of each of the first sub-holes SSH1 in one direction DRA can be approximately equal to the length LA2 of each of the second sub-holes SSH2 in one direction DRA. The length LB1 of each of the first sub-holes SSH1 in the other direction DRB can be smaller than the length LB2 of each of the second sub-holes SSH2 in the other direction DRB.

[0180] The first hole SH1 and the first sub-hole SSH1 can be set in odd-numbered rows, and the first hole SH1 and the second sub-hole SSH2 can be set in even-numbered rows.

[0181] The first hole SH1 and the first sub-hole SSH1 can be set alternately on a directional DRA. For example, the first hole SH1 and the first sub-hole SSH1 can be set on a directional DRA in the order of first sub-hole SSH1, first hole SH1, first sub-hole SSH1, and first hole SH1.

[0182] The first hole SH1 and the second sub-hole SSH2 can be alternately set on a directional DRA. For example, the first hole SH1 and the second sub-hole SSH2 can be set on a directional DRA in the order of first hole SH1, second sub-hole SSH2, and first hole SH1 and second sub-hole SSH2.

[0183] The first hole SH1 and the first sub-hole SSH1 can be set in odd-numbered columns, and the first hole SH1 and the second sub-hole SSH2 can be set in even-numbered columns.

[0184] The first hole SH1 and the first sub-hole SSH1 can be alternately set on the DRB in another direction. For example, the first hole SH1 and the first sub-hole SSH1 can be set on the DRB in another direction in the order of first sub-hole SSH1, first hole SH1, first sub-hole SSH1, and first hole SH1.

[0185] The first hole SH1 and the second sub-hole SSH2 can be alternately set on the DRB in another direction. For example, the first hole SH1 and the second sub-hole SSH2 can be set on the DRB in another direction in the order of first hole SH1, second sub-hole SSH2, first hole SH1 and second sub-hole SSH2.

[0186] The first hole SH1, the first sub-hole SSH1, the second sub-hole SSH2, and the first connecting hole CCT1 can be non-overlapping in the third direction (Z-axis direction). The first connecting hole CCT1 can be located in an odd-numbered column in another direction DRB between the first hole SH1 and the first sub-hole SSH1. The first connecting hole CCT1 can be located between adjacent second sub-holes SSH2 in one direction DRA. The first hole SH1 can be located between adjacent second holes SSH2 in one direction DRA.

[0187] like Figure 17 As shown, exhaust gas generated from moisture remaining on the first organic layer 160 can be discharged through the first hole SH1 of the first sub-driving voltage line SVSL1 and the second sub-hole SSH2 of the second sub-driving voltage line SVSL2. When the first connection hole CCT1 is not arranged between the first hole SH1 and the second sub-hole SSH2, the length of the second sub-hole SSH2 in the other direction DRB can be increased to be longer than the length of the second sub-hole SSH2 in the one direction DRA. In this way, the size of the second sub-hole SSH2 can be increased to be larger than the size of the first sub-hole SSH1. Therefore, the exhaust channel through the second sub-hole SSH2 can be increased to facilitate the discharge of exhaust gas. Therefore, damage to the light-emitting layer 172 of the light-emitting element LEL that may occur when exhaust gas is not discharged can be prevented or at least suppressed.

[0188] Figure 16 The display panel and Figure 9 The difference in the display panel is that, in the second non-display area NDA2, the second hole SH2 is replaced by the first sub-hole SSH1. Therefore, references will be omitted. Figure 16 The second non-display area NDA2 is described repeatedly.

[0189] Figure 18 It is based on yet another exemplary embodiment. Figure 7 Detailed layout diagram of the first non-display area. Figure 19 This is according to yet another exemplary embodiment. Figure 7 Detailed layout diagram of the second non-display area. Figure 20 According to an exemplary embodiment, along Figure 18 A cross-sectional view of the display panel taken from line IX-IX'.

[0190] Figures 18 to 20 The display panel and Figures 9 to 11The display panels shown are substantially similar, but according to the exemplary embodiment illustrated, the first hole SH1 includes a first sub-hole SSH1' and a second sub-hole SSH2' of different sizes. Therefore, repeated descriptions of the elements forming the display panels already described above will be omitted or simplified, and the differences will be primarily described. Along Figure 18 The cross-sectional view of line VIII-VIII' of the display panel and Figure 13 They are essentially the same, and therefore repeated descriptions will be omitted.

[0191] Reference Figures 18 to 20 The first hole SH1 may include a first sub-hole SSH1' and a second sub-hole SSH2'. The first sub-hole SSH1' may be set in the first non-display area NDA1 and the second non-display area NDA2, and the second sub-hole SSH2' may be set in the first non-display area NDA1.

[0192] The dimensions of each of the first sub-holes SSH1' may be smaller than the dimensions of each of the second sub-holes SSH2'. The length LA1' of each of the first sub-holes SSH1' in one direction DRA may be substantially equal to the length LA2' of each of the second sub-holes SSH2' in one direction DRA. The length LB1' of each of the first sub-holes SSH1' in the other direction DRB may be smaller than the length LB2' of each of the second sub-holes SSH2' in the other direction DRB.

[0193] The second hole SH2 and the first sub-hole SSH1' can be set in even-numbered rows, and the second hole SH2 and the second sub-hole SSH2' can be set in odd-numbered rows.

[0194] The second hole SH2 and the first sub-hole SSH1' can be set alternately on a directional DRA. For example, the second hole SH2 and the first sub-hole SSH1' can be set on a directional DRA in the order of first sub-hole SSH1', second hole SH2, first sub-hole SSH1' and second hole SH2.

[0195] The second hole SH2 and the second sub-hole SSH2' can be alternately set on a directional DRA. For example, the second hole SH2 and the second sub-hole SSH2' can be set on a directional DRA in the order of second hole SH2, second sub-hole SSH2', second hole SH2 and second sub-hole SSH2'.

[0196] The second hole SH2 and the first sub-hole SSH1' can be set in odd-numbered columns, and the second hole SH2 and the second sub-hole SSH2' can be set in even-numbered columns.

[0197] The second hole SH2 and the first sub-hole SSH1' can be alternately set on the DRB in another direction. For example, the second hole SH2 and the first sub-hole SSH1' can be set on the DRB in another direction in the order of second hole SH2, first sub-hole SSH1', second hole SH2 and first sub-hole SSH1'.

[0198] The second hole SH2 and the second sub-hole SSH2' can be alternately set on the DRB in another direction. For example, the second hole SH2 and the second sub-hole SSH2' can be set on the DRB in another direction in the order of second sub-hole SSH2', second hole SH2, second sub-hole SSH2' and second hole SH2.

[0199] The second hole SH2, the first sub-hole SSH1', the second sub-hole SSH2', and the first connecting hole CCT1 can be arranged without overlapping each other in a third direction (Z-axis direction). The first connecting hole CCT1 can be arranged in an odd-numbered column in another direction DRB between the second hole SH2 and the first sub-hole SSH1'. The first connecting hole CCT1 can also be arranged in one direction DRA between adjacent second sub-holes SSH2'.

[0200] like Figure 20 As shown, exhaust gas generated from moisture remaining on the first organic layer 160 can be discharged through the second sub-hole SSH2' of the first sub-driving voltage line SVSL1 and the second hole SH2 of the second sub-driving voltage line SVSL2. When the first connection hole CCT1 is not arranged between the second sub-hole SSH2' and the second hole SH2, the length of the second sub-hole SSH2' in the other direction DRB can be formed to be longer than the length of the second sub-hole SSH2' in the other direction DRA. In this way, the size of the second sub-hole SSH2' can be increased to be larger than the size of the first sub-hole SSH1'. Therefore, the channel for exhaust gas discharge via the second sub-hole SSH2' can be increased to facilitate exhaust gas discharge. Therefore, damage to the light-emitting layer 172 of the light-emitting element LEL that may occur when exhaust gas is not discharged can be prevented or at least suppressed.

[0201] at the same time, Figure 19 The display panel and Figure 9 The difference in the display panel is that, in the second non-display area NDA2, the first hole SH1 is replaced by the first sub-hole SSH1'. Therefore, references will be omitted. Figure 19 The second non-display area NDA2 is described repeatedly.

[0202] In a display device constructed according to the principles and some exemplary embodiments of the present invention, exhaust gas generated by moisture remaining on the organic layer can be discharged through a first hole of the first sub-driving voltage line and a second hole of the second sub-driving voltage line. When the first connecting hole for connecting the first and second sub-driving voltage lines is not arranged between the first and second holes in one direction, the length of the first or second hole in one direction can be increased to be longer than the length of the first or second hole in the other direction. In this way, the size of the first or second hole can be increased to increase the exhaust channel through the first or second hole, thereby promoting the discharge of exhaust gas. Therefore, damage to the light-emitting layer of the light-emitting element, which might otherwise be damaged when exhaust gas is not discharged, can be reduced.

[0203] Although some exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from that description. Therefore, the inventive concept is not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalents that will be apparent to those skilled in the art.

Claims

1. A display device, comprising: The display area is configured to display an image; A first non-display area is arranged adjacent to the display area; The second non-display area is arranged adjacent to the first non-display area; as well as A first driving voltage line is disposed in the first non-display area and the second non-display area, the first driving voltage line is configured to be applied a first driving voltage and includes: The first sub-driving voltage line includes the first hole; and The second sub-driving voltage line is arranged on the first sub-driving voltage line and includes a second hole. The second hole includes a first sub-hole and a second sub-hole, the size of the second sub-hole being different from the size of the first sub-hole, and In the second non-display area, the first hole and the first sub-hole are alternately arranged in a first direction.

2. The display device according to claim 1, wherein: The first sub-hole is arranged in the first non-display area and the second non-display area; and The second sub-hole is arranged in the first non-display area.

3. The display device according to claim 1, wherein, The length of the second sub-hole in the first direction is greater than the length of the first sub-hole in the first direction.

4. The display device according to claim 1, wherein, The first hole, the first sub-hole, and the second sub-hole do not overlap with each other.

5. The display device according to any one of claims 1 to 4, wherein, The second sub-driving voltage line is connected to the first sub-driving voltage line through the first connection hole in the first non-display area and the second non-display area; and The first connecting hole does not overlap with the first hole and the second hole.

6. The display device according to claim 5, wherein, In the first non-display area, one of the first connecting holes is arranged in a first direction between one of the first holes and one of the first sub-holes.

7. The display device according to claim 6, wherein, In the first non-display area, one of the first connecting holes and one of the first holes are arranged between adjacent second sub-holes in a second direction that intersects the first direction.

8. The display device according to claim 5, wherein, In the second non-display area, the first hole and the first sub-hole are alternately arranged in a second direction that intersects the first direction.

9. The display device according to claim 5, wherein, In the second non-display area, one of the first connecting holes is arranged in the first direction between one of the first holes and one of the first sub-holes.

10. The display device according to claim 5, further comprising: Pixel electrodes and a light-emitting layer are arranged in the display area; as well as A common electrode is disposed on the light-emitting layer and connected to the second sub-driving voltage line through a second connection hole in the second non-display area.

11. The display device according to claim 10, wherein, One of the second connecting holes overlaps with one of the first holes.

12. A display device, comprising: The display area is configured to display an image; A first non-display area is arranged adjacent to the display area; The second non-display area is arranged adjacent to the first non-display area; A first sub-driving voltage line is disposed in the first non-display area and the second non-display area, the first sub-driving voltage line is configured to be applied a first driving voltage and includes a first aperture; and The second sub-driving voltage line is arranged on the first sub-driving voltage line and includes a second hole. The first hole includes a first sub-hole and a second sub-hole, wherein the size of the second sub-hole is different from the size of the first sub-hole, and The second hole, the first sub-hole, and the second sub-hole do not overlap with each other.

13. The display device according to claim 12, wherein: The first sub-hole is arranged in the first non-display area and the second non-display area; and The second sub-hole is arranged in the first non-display area.

14. The display device according to claim 12, wherein, The length of the second sub-hole in the first direction is greater than the length of the first sub-hole in the first direction.

15. The display device according to any one of claims 12 to 14, wherein: The second sub-driving voltage line is connected to the first sub-driving voltage line through the first connection hole in the first non-display area and the second non-display area; and The first connecting hole does not overlap with the first hole and the second hole.

16. A display device, comprising: The display area is configured to display an image; A first non-display area is arranged adjacent to the display area; The second non-display area is arranged adjacent to the first non-display area; as well as A first driving voltage line is disposed in the first non-display area and the second non-display area, the first driving voltage line is configured to be applied a first driving voltage and includes: The first sub-driving voltage line includes the first hole; and The second sub-driving voltage line is arranged on the first sub-driving voltage line and includes a second hole. Wherein, the size of one of the second holes in the first non-display area is different from the size of one of the second holes in the second non-display area, and In the first non-display area, the size of one of the first holes is different from the size of one of the second holes.

17. The display device according to claim 16, wherein, The length of the second hole in the first non-display area in the first direction is greater than the length of the second hole in the second non-display area in the first direction.

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