Field effect transistor and method of making the same, semiconductor structure

Abstract

A field effect transistor and a preparation method thereof and a semiconductor structure, the field effect transistor comprising: a substrate structure, a source electrode, a drain electrode and a gate electrode; the source electrode and the drain electrode are arranged on the substrate structure along a first direction, and a channel region is formed between the source electrode and the drain electrode; a channel layer is formed in the channel region, and N carbon nanotubes extending along the first direction are embedded in the channel layer, N being an integer greater than or equal to 1; two ends of the N carbon nanotubes are connected with the source electrode and the drain electrode respectively to form a conductive path; and the gate electrode is formed on the channel layer. The channel region between the source electrode and the drain electrode realizes electronic conduction between the source electrode and the drain electrode through the carbon nanotubes arranged in the channel layer, and the excellent conductive performance of the carbon nanotubes can make the field effect transistor have a wider channel, which is equivalent to the field effect transistor having a greater driving current with stronger performance; and the carbon nanotubes are small cylindrical bodies formed by carbon atoms, which is conducive to realizing device miniaturization.

Description

[0001] This application claims priority to Chinese Patent Application No. 202010599782.0, filed on June 28, 2020, entitled "A Transistor", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductors, and in particular to a field-effect transistor and its fabrication method and semiconductor structure. Background Technology

[0003] The transistors used in existing integrated circuits are typically FETs (field effect transistors). Figure 1 Taking the FET shown as an example, its structure includes a silicon substrate 1', a source 2', a drain 3', and a gate 4'. A channel region 5' is formed between the source 2' and the drain 3'. The current flowing through the channel region 5' between the source 2' and the drain 3' is the source-drain current. The source-drain current here is controlled by the voltage of the gate 4'. The width of the channel region 5' will affect the flow of the source-drain current and the performance of the FET.

[0004] Currently, the development trend of electronic devices is miniaturization and thinning. However, traditional transistors are difficult to develop beyond 1nm due to limitations in silicon technology. Therefore, it is necessary to seek new transistor structures to achieve miniaturization while meeting performance requirements. Summary of the Invention

[0005] This application provides a field-effect transistor, its fabrication method, and semiconductor structure, which is beneficial for achieving device miniaturization.

[0006] In a first aspect, this application provides a field-effect transistor, specifically including a substrate structure, a source, a drain, and a gate. The substrate structure is located at the bottom of the entire transistor structure, providing support and protection for the entire structure. The source and drain are arranged along a first direction on the substrate structure, forming a gap between the source and drain, which is a channel region. A channel layer is formed in the channel region, and N carbon nanotubes extending along the first direction are embedded in the channel layer, where N is an integer greater than or equal to 1. Since the carbon nanotubes all extend along the first direction, when N is greater than 1, it indicates that the carbon nanotubes are parallel to each other. The two ends of the N carbon nanotubes are respectively connected to the source and drain to form a conductive path, realizing the current conduction between the source and drain. The extension direction of the carbon nanotubes is the direction of their axis, which minimizes the current conduction distance between the source and drain. The gate is formed on the channel layer and is used to control the degree of electron flow between the source and drain.

[0007] In the aforementioned field-effect transistor, the channel region between the source and drain is achieved by carbon nanotubes disposed in the channel layer to enable electron conduction between the source and drain. The excellent conductivity of the carbon nanotubes themselves allows the field-effect transistor to have a wider channel, which is equivalent to the field-effect transistor having a stronger performance and a larger drive current. Furthermore, the carbon nanotubes themselves are tiny cylinders composed of carbon atoms, which is beneficial for achieving device miniaturization.

[0008] Specifically, along the direction from the gate to the channel layer, a capacitor layer and a gate dielectric layer are stacked between the gate and the channel layer. The aforementioned substrate structure may include a silicon substrate and a well region formed on the silicon substrate. This well region can be a P-well or an N-well. In specific implementations, the polarities of the source and gate need to correspond to the polarities of the well region. In addition, to prevent leakage, the substrate structure also includes an insulating layer disposed on the side of the well region away from the silicon substrate, with the source and drain located on the insulating layer.

[0009] When the number of carbon nanotubes is greater than 2, N carbon nanotubes can be distributed in an array within the channel layer, which is beneficial for the mass production of carbon nanotubes.

[0010] In one possible implementation, considering the distribution of carbon nanotubes within the channel layer, the channel layer structure may include at least one channel interlayer. Each channel interlayer includes a first oxide layer and a second oxide layer stacked along the direction from the substrate structure toward the channel layer, with at least one carbon nanotube embedded between the first oxide layer and the second oxide layer. Dividing the channel layer into upper and lower parts is beneficial for the fabrication of carbon nanotubes.

[0011] To improve the yield of carbon nanotubes, a metal silicate compound can be formed on the surface of the first oxide layer that is used to contact the carbon nanotubes, or a metal oxide can be formed on the surface of the first oxide layer that is used to contact the carbon nanotubes; both metal silicate compounds and metal oxides are beneficial to the formation of carbon nanotubes.

[0012] Considering that the contact between carbon nanotubes and the source and drain electrodes affects conductivity, one possible implementation involves a first contact layer on the side of the source electrode facing the channel layer and a second contact layer on the side of the drain electrode facing the channel layer. The two ends of the carbon nanotube are connected to the first and second contact layers, respectively. The carbon nanotubes can connect to the first and second contact layers through surface contact or insertion. The conductivity of the first contact layer is higher than that of the source electrode, and the conductivity of the second contact layer is higher than that of the drain electrode. This improves the conductivity of the connection between the carbon nanotubes and the source and drain electrodes, thus enhancing electron conduction between them. The first contact layer can be made of gold or a gold alloy, and the second contact layer can also be made of gold or a gold alloy.

[0013] Secondly, based on the structure of the above-mentioned field-effect transistor, this application also provides a semiconductor structure, which includes two of the above-mentioned field-effect transistors, and the two field-effect transistors are isolated from each other by an isolator.

[0014] Thirdly, based on the above-described structure of the field-effect transistor, this application also provides a method for fabricating a field-effect transistor, comprising the following steps: Preparation of substrate structure; A channel layer is prepared on the substrate structure, wherein N channels extending along a first direction are embedded in the channel layer and both ends of the carbon nanotubes are exposed in the channel layer, wherein N is an integer greater than or equal to 1. A gate is formed on the channel layer; A source and a drain are formed on both sides of the channel layer, and the source and the drain are respectively connected to the two ends of the carbon nanotube to form a conductive path.

[0015] The fabrication of the channel layer on the substrate structure includes at least one of the following steps: A first oxide layer is formed on a substrate, wherein the substrate is a structure used to form one side of the channel layer; At least one carbon nanotube is formed on the first oxide layer; A second oxide layer is formed on the surface of the carbon nanotubes to cover them.

[0016] Forming at least one carbon nanotube on the first oxide layer can be achieved in at least two ways: In one possible implementation, after forming the first oxide layer on the substrate and before forming at least one carbon nanotube on the first oxide layer, the following steps are further included: A metal oxide is prepared on the first oxide layer, such that the metal oxide reacts with the first oxide layer to form a metal silicate compound.

[0017] The step of forming at least one carbon nanotube on the first oxide layer includes the following steps: The carbon nanotubes are synthesized on the metal silicate compound by vapor deposition in the presence of a catalyst. The catalyst used here can be tungsten-based alloy nanocrystals.

[0018] In another possible implementation, after forming the first oxide layer on the substrate and before forming at least one carbon nanotube on the first oxide layer, the following steps are further included: A metal is added to the first oxide layer to form a metal oxide, and then carbon nanotubes are formed on the metal oxide.

[0019] In one possible implementation, a first contact layer is provided on the side of the source electrode facing the channel layer, and a second contact layer is provided on the side of the drain electrode facing the channel layer. One end of the carbon nanotube is connected to the source electrode through the first contact layer, and the other end of the carbon nanotube is connected to the drain electrode through the second contact layer. The conductivity of the first contact layer is higher than that of the source electrode, and the conductivity of the second contact layer is higher than that of the drain electrode. Before fabricating a channel layer on the substrate structure in which at least one carbon nanotube is embedded, and before forming a gate on the channel layer, the method further includes the following steps: A highly conductive metal is deposited on both sides of the channel layer to form a first contact layer and a second contact layer on both sides of the channel layer, and the two ends of the carbon nanotube are respectively connected to the first contact layer and the second contact layer. The deposition of the highly conductive metal on both sides of the channel layer can be performed using electron beam printing.

[0020] When the source and drain are fabricated after this step, the first contact layer is connected to the source and the second contact layer is connected to the drain.

[0021] In one possible implementation, along the direction from the gate to the channel layer, a gate dielectric layer and a capacitor layer are stacked between the gate and the channel layer. Forming the gate on the channel layer includes the following steps: A gate dielectric layer is fabricated on the channel layer; A capacitor layer is fabricated on the gate dielectric layer; The gate is fabricated on the capacitor layer.

[0022] In one possible implementation, the substrate structure includes a silicon substrate and a well region formed on the silicon substrate, and the fabrication of the substrate structure includes the following steps: Impurities are doped into a silicon substrate to form a well region.

[0023] When the substrate structure also includes an insulating layer formed on the side of the well region facing away from the silicon substrate, after doping the silicon substrate with impurities to form the well region, the following steps are also included: An insulating layer is formed on the side of the well region away from the silicon substrate. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a field-effect transistor in the prior art; Figures 2a to 2f This is a schematic diagram of the structure of a field-effect transistor provided in an embodiment of this application; Figures 3a to 3d A schematic diagram illustrating the distribution of carbon nanotubes in the channel layer of a field-effect transistor, provided as an embodiment of this application; Figure 4This application provides a schematic diagram of the channel layer structure in a field-effect transistor. Figure 5 A schematic diagram of the channel sandwich structure in a field-effect transistor provided in this application embodiment; Figure 6a and Figure 6b This is a schematic diagram of the structure of the first interlayer in a field-effect transistor provided in an embodiment of this application; Figure 7 This is a schematic diagram of a semiconductor structure provided in an embodiment of this application; Figure 8 A schematic flowchart illustrating a method for fabricating a field-effect transistor according to an embodiment of this application; Figure 9 This is a schematic flowchart of a method for fabricating a substrate structure in a field-effect transistor, provided in an embodiment of this application. Figure 10 A schematic flowchart illustrating a method for fabricating a channel sandwich layer in a field-effect transistor, as provided in this application embodiment; Figure 11 A schematic flowchart illustrating a method for fabricating a field-effect transistor according to an embodiment of this application; Figure 12 A schematic flowchart illustrating a method for fabricating a field-effect transistor according to an embodiment of this application; Figure 13 A schematic flowchart illustrating a method for fabricating a field-effect transistor according to an embodiment of this application; Figure 14 This is a schematic flowchart of a method for fabricating the gate of a field-effect transistor, provided in an embodiment of this application. Detailed Implementation

[0025] First, let's introduce the application scenario of this application. Currently, the size of traditional transistors is limited by manufacturing processes and cannot meet the development trend of miniaturization and thinning of electronic devices. Therefore, embodiments of this application provide a field-effect transistor, its fabrication method, and semiconductor structure. This field-effect transistor has stronger performance and larger drive current, which can meet the development needs of miniaturization of electronic devices.

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0027] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more” unless the context clearly indicates otherwise.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] Please refer to Figure 2a The schematic diagram of a field-effect transistor provided in this application embodiment shows that it includes a substrate structure 1, a source 2, a drain 3, and a gate 4; along Figure 2a In the Y direction shown, the substrate structure 1 is located at the bottom of the entire transistor structure. The top of the substrate structure 1 is divided into a first region A1 and a second region A2, with a gap between the first region A1 and the second region A2. The source 2 is disposed in the first region A1, and the drain 3 is disposed in the second region A2. A space is formed between the source 2 and the drain 3, which is designated as the channel region B. The gate 4 is located above the channel region B. A channel layer 5 is formed within the channel region B, and multiple carbon nanotubes 6 are embedded within the channel layer 5. The structure of the channel layer 5 and the carbon nanotubes 6 is shown in a partial cross-section here; the multiple carbon nanotubes 6 are distributed in a parallel manner. Figure 2a As shown, each carbon nanotube 6 is along the first direction (i.e. Figure 2a Extending along the X-direction (which is perpendicular to the Y-direction), the centerline of any carbon nanotube 6 is parallel to the X-direction, and both ends of each carbon nanotube 6 are connected to the source electrode 2 and drain electrode 3 respectively, enabling current conduction between the source electrode 2 and drain electrode 3. It should be understood that the number of carbon nanotubes 6 here is N, where N is an integer greater than or equal to 1. Figure 2aThe carbon nanotubes are shown in multiple quantities. When there is only one carbon nanotube 6, it can also achieve the effect of conducting the source 2 and the drain 3. However, multiple carbon nanotubes 6 will enhance the electron flow efficiency between the source 2 and the drain 3. The connection between the carbon nanotube 6 and the source 2 and the drain 3 is to achieve circuit conduction by direct contact connection. Of course, contact medium can also be added to achieve circuit conduction by indirect connection.

[0030] One possible way to achieve this is, such as Figure 2b The structure of the field-effect transistor shown has a first contact layer 21 on the side of the source electrode 2 facing the channel region B. This is equivalent to setting the first contact layer 21 between the source electrode 2 and the channel layer 5, so that the source electrode 2 and the channel layer 5 are connected through the first contact layer 21. The end of the carbon nanotube 6 buried in the channel layer 5 facing the source electrode 2 can contact or extend into the first contact layer 21. Correspondingly, a second contact layer 31 is set on the side of the drain electrode 3 facing the channel region B. This is equivalent to setting the drain electrode 3 and the channel layer 5 through the second contact layer 31. The end of the carbon nanotube 6 buried in the channel layer 5 facing the drain electrode 3 can contact or extend into the second contact layer 31.

[0031] The first contact layer 21 and the second contact layer 31 here are equivalent to the contact medium between the source electrode 2, the drain electrode 3 and the carbon nanotube 6. The conductivity of the first contact layer 21 is higher than that of the source electrode 2, and the conductivity of the second contact layer 31 is higher than that of the drain electrode 3. Therefore, the presence of the first contact layer 21 and the second contact layer 31 can improve the conductivity between the source electrode 2 and the carbon nanotube 6, and between the drain electrode 3 and the carbon nanotube 6.

[0032] Specifically, the material of the first contact layer 21 can be gold or a gold alloy, and the gold alloy can be an alloy doped with copper or cobalt. This material is chosen because gold or gold alloys have high conductivity in terms of electrical contact, and at the same time, gold or gold alloys have good ductility in terms of manufacturability, which facilitates the process preparation, and also has good contact properties. Similarly, the material of the second contact layer 31 can also be gold or a gold alloy.

[0033] by Figure 2b Taking the structure of the field-effect transistor shown as an example, the substrate structure 1 can be specifically as follows: Figure 2c As shown, the substrate structure 1 includes a silicon substrate 11 and a well region 12 formed on the silicon substrate 11. The silicon substrate 11 is located at the bottom layer of the entire field-effect transistor structure, providing support and carrying capacity for the entire field-effect transistor, and also playing a structural protection role. The well region 12 can be a P-well or an N-well; it should be understood that when the well region 12 is a P-well, the source 2 and drain 3 should be N-type doped; when the well region 12 is an N-well, the source 2 and drain 3 should be P-type doped. Figure 2bThe example illustrates a structure where well region 12 is a P-well, and source 2 and drain 3 are N-type doped.

[0034] exist Figure 2c Based on the structure of the field-effect transistor shown, Figure 2d This illustrates another field-effect transistor structure, which is similar to... Figure 2c The difference in the field-effect transistor structure shown is that an insulating layer 13 is formed on the surface of the well region 12 away from the silicon substrate 11 using SOI (silicon-on-insulator). The insulating layer 13 can be SiO2. The source 2 and drain 3 are both disposed on the insulating layer 13. The presence of the insulating layer 13 can reduce the parasitic capacitance between the source 2, drain 3 and well region 12, thereby achieving the effect of preventing leakage current.

[0035] Figure 2e In the field-effect transistor shown, a capacitor layer 41 and a gate dielectric layer 42 are stacked between the gate 4 and the channel layer 5 along the direction from the gate 4 to the channel layer 5. The capacitor layer 41 is in contact with the gate 4, and the gate dielectric layer 42 is in contact with the channel layer 5.

[0036] exist Figure 2e Based on the structure of the exemplified field-effect transistor, embodiments of this application also provide a field-effect transistor, such as... Figure 2f As shown, a first protective layer 43 is covered on the surface of the structure composed of gate 4, capacitor layer 41 and gate dielectric layer 42. The first protective layer 43 can be a nitride.

[0037] It should be noted that, in Figures 2a to 2f In the field-effect transistor shown, the silicon substrate 11, well region 12, and insulating layer 13 are referred to as a single structure as substrate structure 1. This designation is based solely on the position of this portion of the structure within the field-effect transistor structure. The concept of substrate structure 1 is only used to describe the placement of the silicon substrate 11, well region 12, and insulating layer 13, and is not intended to limit the specific function of these three layers. It should be understood that, based on this understanding of substrate structure 1, substrate structure 1 may also include other structures located within the substrate structure 1 portion of the field-effect transistor, which are not shown in the embodiments of this application.

[0038] Among them, multiple carbon nanotubes 6 Figure 3a Taking one distribution form as an example, in Figure 3aIn this diagram, there are 6 carbon nanotubes (66), arranged in two layers along the Y-axis, with a distance of C1 between the two layers (referenced to the axis of the carbon nanotubes). Along the Z-axis, the upper layer has 3 carbon nanotubes arranged side-by-side, with a distance of C2 between any two adjacent nanotubes (referenced to the axis of the carbon nanotubes). The lower layer also has 3 carbon nanotubes arranged side-by-side, with a distance of C2 between any two adjacent nanotubes (referenced to the axis of the carbon nanotubes). C1 can be equal to C2, or they can be different. In this distribution, the Y-axis is defined as the column direction, and the Z-axis as the row direction. Figure 3a The carbon nanotubes 6 are arranged horizontally in the row direction and vertically in the column direction, and the distance between any two carbon nanotubes 6 in the row direction is equal.

[0039] like Figure 3b Another possible distribution of carbon nanotubes 6 is shown, with 5 carbon nanotubes 6 arranged in two layers along the Y direction, the distance between the two layers being D1 (with the axis of the carbon nanotubes 6 as a reference). Along the Z direction, the upper layer has 3 carbon nanotubes 6 arranged side-by-side, the distance between any two adjacent carbon nanotubes 6 being D2 (with the axis of the carbon nanotubes 6 as a reference), and the lower layer has 2 carbon nanotubes 6 arranged side-by-side, the distance between two carbon nanotubes 6 also being D2 (with the axis of the carbon nanotubes 6 as a reference). Here, D1 can be equal to D2, or D1 can be different from D2. In this distribution, the Y direction is defined as the column direction, and Z as the row direction. Figure 3a The medium carbon nanotubes 6 are arranged in a way that they are aligned horizontally in the row direction and staggered in the column direction, and the distance between any two carbon nanotubes 6 in the row direction is equal.

[0040] like Figure 3c Another possible distribution of carbon nanotubes 6 is shown, with five carbon nanotubes 6 arranged in two layers along the Y direction, with a distance of E1 between the two layers (referenced to the axis of the carbon nanotubes 6). Along the Z direction, the upper layer has three carbon nanotubes 6 arranged side-by-side, with a distance of E2 between the first and second carbon nanotubes 6 from the left (referenced to the axis of the carbon nanotubes 6), and a distance of E3 between the second and third carbon nanotubes 6 from the left (referenced to the axis of the carbon nanotubes 6). The lower layer has two carbon nanotubes 6 arranged side-by-side, with a distance of E4 between them (referenced to the axis of the carbon nanotubes 6). In this distribution, the Y direction is defined as the column direction, and the Z direction as the row direction. Figure 3a The medium carbon nanotubes 6 are arranged in a way that is aligned horizontally in the row direction and staggered in the column direction, but the distance between any two carbon nanotubes 6 in the row direction is not equal.

[0041] like Figure 3d This illustrates another possible distribution of carbon nanotubes 6, with five nanotubes 6 arranged along either the Y or Z direction, with the axis of the carbon nanotubes 6 as a reference. Except for the carbon nanotubes 6 themselves, there is no specific arrangement pattern. In this distribution, the Y direction is defined as the column direction, and the Z direction as the row direction. Figure 3a The medium carbon nanotubes 6 are distributed in a staggered manner.

[0042] It should be understood that Figures 3a to 3d Several possible distribution patterns of carbon nanotubes 6 in the channel layer 5 are shown. The common feature is that in each pattern, the multiple carbon nanotubes 6 are parallel to each other, meaning the axis of all carbon nanotubes 6 is parallel to the X-direction (the direction from source 2 to drain 3 or from drain 3 to source 2). However, it should be noted that... Figure 3a and Figure 3b The carbon nanotubes 6 shown are distributed in an array. In the preparation of carbon nanotubes 6, batch processing can be used, reducing the complexity of the preparation process. Figure 3c and Figure 3d The distribution pattern of carbon nanotubes 6 shown is irregular, and a relatively complex preparation process may be required in the preparation of carbon nanotubes 6.

[0043] In the above field-effect transistor structure, electron conduction is achieved between the source 2 and the drain 3 through carbon nanotubes 6, which makes the field-effect transistor have a wider channel, which is equivalent to the field-effect transistor having stronger performance and a larger drive current; here, the carbon nanotubes 6 themselves are tiny cylinders arranged by carbon atoms, which is beneficial to the miniaturization of the device.

[0044] by Figure 3a Taking the distribution of carbon nanotubes 6 within the channel layer 5 as an example, the specific structure of the channel layer 5 can be as follows: Figure 4 As shown, the channel layer 5 includes at least one channel interlayer 51, for Figure 3a The carbon nanotubes 6 are distributed in an array. Along the X direction, one layer of channel interlayer 51 corresponds to one layer of carbon nanotubes 6. That is, within one layer of channel interlayer 51, a layer of carbon nanotubes 6 is formed that are distributed side by side.

[0045] For each channel interlayer 51, its structure can be referred to Figure 5Along the direction from the substrate structure 1 to the channel layer 5, each channel interlayer 51 includes a first oxide layer 511 and a second oxide layer 512 disposed opposite to each other. Here, the first oxide layer 511 is closer to the substrate structure 1, and the second oxide layer 512 is closer to the gate 4. At least one first recess a1 can be formed on the surface of the first oxide layer 511 facing the second oxide layer 512. Correspondingly, a second recess a2 is formed on the surface of the second oxide layer 512 facing the first oxide layer 511, corresponding to the first recess a1. Each set of corresponding first recesses a1 and second recesses a2 matches to clamp a carbon nanotube 6. Figure 5 In this process, a row of parallel carbon nanotubes 6 is embedded in the interlayer 51 of the channel. Therefore, the number of the first depression a1 and the second depression a2 is matched with the number of carbon nanotubes 6.

[0046] It should be understood that, Figure 5 The structural states shown in the first oxide layer 511 and the second oxide layer 512 are the final state of the field-effect transistor and are not used to limit the structural state of the channel layer 5 during the manufacturing process. That is to say, the first recess a1 and the second recess a2 may not exist during the manufacturing process, but only appear after the carbon nanotube 6 is sandwiched between the first oxide layer 511 and the second oxide layer 512.

[0047] In one possible implementation, the first oxide layer 511 and the second oxide layer 512 can be made of SiO2. In actual production, carbon nanotubes 6 can be formed at the first recess a1 position on the first oxide layer 511, and then the second oxide layer 512 is set on the side of the carbon nanotubes 6 away from the first oxide layer 511, so that the second oxide layer 512 covers the carbon nanotubes 6, and the first oxide layer 511 and the second oxide layer 512 surround the carbon nanotubes 6, resulting in... Figure 5 The structure in.

[0048] It should also be noted that, Figure 5 In the diagram, the first oxide layer 511 and the second oxide layer 512 are shown in a relatively regular structure (similar to a cube). In the actual production process, the first oxide layer 511 and the second oxide layer 512 may appear in an irregular state. Their structure is related to a layer of carbon nanotubes 6 with the axis on the same plane. It is only necessary that the structure of the final channel layer 5 matches the structure of the channel region B between the source electrode 2 and the drain electrode 3.

[0049] In a specific structure, such as Figure 6aAs shown, a metal silicate compound 71 is formed on the surface of the first recess a1 on the first oxide layer 511 facing the carbon nanotube 6. This metal silicate compound 71 can be distributed in the form of a film on the surface of the first recess a1, and the carbon nanotube 6 is formed on the metal silicate compound 71. The carbon nanotube 6 is essentially surrounded by the metal silicate compound 71 and the second oxide layer 512. In another specific structure, such as... Figure 6b As shown, a metal oxide 72 is formed on the surface of the first recess a1 on the first base layer 512 facing the carbon nanotube 6. The metal oxide 72 can be distributed in the form of a film on the surface of the first recess a1, and the carbon nanotube 6 is formed on the metal oxide 72. The carbon nanotube 6 is essentially surrounded by the metal oxide 72 and the second oxide layer 512. Both the metal silicate compound 71 and the metal oxide 72 here are conducive to the formation of the carbon nanotube 6.

[0050] It is understandable that when metal silicate compound 71, such as Figure 6a As shown or metal oxide 72 Figure 6b As shown, when the first depression a1 is covered and faces the surface of the carbon nanotube 6, it is more conducive to the formation of the carbon nanotube 6.

[0051] based on Figure 2d The present application also provides a semiconductor structure, such as the field-effect transistor structure shown. Figure 7 As shown, it includes two of the aforementioned field-effect transistors (shown as field-effect transistor M1 and field-effect transistor M2, respectively). The two field-effect transistors share a single silicon substrate 11, while other structures are separately configured. Specifically, as... Figure 7 As shown, the field-effect transistor M1 includes a P-well 12a formed on a silicon substrate 11. An insulating layer 13a is formed on the side of the P-well 12a facing away from the silicon substrate 11. An N-type source 2a and an N-type drain 3a are disposed on the insulating layer 13a. A trench layer 5a is disposed between the source 2a and the drain 3a. N parallel carbon nanotubes 6a (N is an integer greater than or equal to 1) are embedded in the trench layer 5a. Figure 7 In the case where N is greater than 1), a first contact layer 21a is provided between the channel layer 5a and the source 2a, and a second contact layer 31a is provided between the channel layer 5a and the drain 3a. The two ends of the carbon nanotube 6a are connected to the first contact layer 21a and the second contact layer 31a respectively, realizing the electron flow between the source 2a and the drain 3a. Correspondingly, the field-effect transistor M2 includes an N-well 12b formed on the silicon substrate 11. An insulating layer 13b is formed on the side of the N-well 12b away from the silicon substrate 11. Its P-type source 2b and P-type drain 3b are disposed on the insulating layer 13b. A trench layer 5b is provided between the source 2b and the drain 3b. N parallelly distributed carbon nanotubes 6b (N is an integer greater than or equal to 1) are embedded in the channel layer 5b. Figure 7(where N is greater than 1), a first contact layer 21b is provided between the channel layer 5b and the source electrode 2b, and a second contact layer 31b is provided between the channel layer 5b and the drain electrode 3b. The two ends of the carbon nanotube 6b are connected to the first contact layer 21b and the second contact layer 31b respectively, so as to realize the electron flow between the source electrode 2b and the drain electrode 3b.

[0052] Please continue to refer to Figure 7 The two field-effect transistors are isolated by shallow trench isolation (STI), that is, a spacer trench is formed between the two field-effect transistors, and the trench is filled with deposited isolation material to form an isolation part 8. A second protective layer 9 is also formed on the isolation part 8.

[0053] by Figure 2a Taking the structure of the field-effect transistor shown as an example, this application also provides a method for fabricating a field-effect transistor. For the specific fabrication process, please refer to [link / reference needed]. Figure 8 This includes the following steps: S1: Prepare substrate structure 1; it should be understood that substrate structure 1 here is only an example of the bottom structure of a field-effect transistor.

[0054] S2: A channel layer 5 is prepared on the substrate structure 1. N carbon nanotubes 6 extending along a first direction are embedded in the channel layer 5, where N is an integer greater than or equal to 1. The two ends of the carbon nanotubes 6 are exposed in the channel layer 5. It should be understood that the two ends of the carbon nanotubes 6 being exposed in the channel layer 5 means that the ends of the carbon nanotubes 6 are at least not covered by the channel layer 5. The ends of the carbon nanotubes 6 can be flush with the surface of the channel layer 5, or the carbon nanotubes 6 can protrude from the surface of the channel layer 5.

[0055] S3: A gate 4 is formed on the channel layer 5; S4: A source electrode 2 and a drain electrode 3 are formed on both sides of the channel layer 5 along the first direction. The source electrode 2 and the drain electrode 3 are connected to both ends of the carbon nanotube 6 to form a conductive path, thereby realizing the current conduction between the source electrode 2 and the drain electrode 3.

[0056] When the substrate structure 1 here includes a silicon substrate 11 and a well region 12, and the well region 12 is formed by doping the silicon substrate 11 with impurities, then step S1 is specifically as follows: Figure 9 As shown, it includes the following steps: S11: Doping impurities into silicon substrate 11 to form a well region 12. When the well region 12 is a P-well, a trivalent element (e.g., boron) is doped into silicon substrate 11 to form a P-well; when the well region 12 is an N-well, a pentavalent element (e.g., phosphorus) is doped into silicon substrate 11 to form an N-well.

[0057] When the substrate structure 1 further includes an insulating layer 13 formed on the side of the well region 12 facing away from the silicon substrate 11, the following steps are included after step S11: S12: An insulating layer 13 is formed on the side of the well region 12 away from the silicon substrate 11.

[0058] according to Figures 3a to 3d The distribution of carbon nanotubes 6 in the channel layer 5 can be illustrated by dividing the structure of the channel layer 5 and carbon nanotubes 6 into layers, with each layer of channel interlayer 51 serving as a unit. Each channel interlayer 51 contains at least one carbon nanotube 6. When the number of carbon nanotubes 6 is greater than or equal to two, all carbon nanotubes 6 are parallel, and their centerlines are all located in the same plane.

[0059] Based on this, Figure 4 For example, please refer to the structure shown below. Figure 10 As shown, the fabrication of the channel layer 5 on the substrate structure 1 in step S2 above includes at least one of the following steps: S21: A first oxide layer 511 is formed on a substrate, where the substrate is the structure of the base structure 1 used to form one side of the trench layer 5; when the trench interlayer 51 is the first trench interlayer 51 in contact with the base structure 1, the substrate here refers to the base structure 1; when the trench interlayer 51 refers to the trench interlayer 51 above other trench interlayers 51, the substrate here refers to the previously formed trench interlayer 51.

[0060] S22: At least one carbon nanotube 6 is formed on the first oxide layer 511; when the number of carbon nanotubes 6 is greater than or equal to two, the carbon nanotubes 6 are parallel to each other. It should be understood that forming on the first oxide layer 511... Figure 5 As shown in the first depression a1, carbon nanotubes 6 will be formed at the location of the first depression a1.

[0061] S23: A second oxide layer 512 is formed on the surface of carbon nanotube 6 to cover carbon nanotube 6, ultimately resulting in... Figure 5 The layer shown contains a channel interlayer 51 with carbon nanotubes 6 embedded in the same plane.

[0062] It is understandable that the first oxide layer 511 and the second oxide layer 512 here can be implemented in at least the following ways.

[0063] Method 1: The first oxide layer 511 can be SiO2 and the second oxide layer 512 can also be SiO2. The carbon nanotubes 6 can be directly formed on the first oxide layer 511.

[0064] Method 2: The first oxide layer 511 can be SiO2. A metal silicate compound 71 is formed at the location on the first oxide layer 511 where carbon nanotubes 6 will form. The carbon nanotubes 6 will be generated on the metal silicate compound 71. Based on this, such as... Figure 11 As shown, the steps following S21 and before S22 may also include the following steps: S211: A metal oxide is prepared on the first oxide layer 511, such that the metal oxide reacts with the first oxide layer 511 to form a metal silicate compound 71. When the first oxide layer 511 is SiO2, the metal oxide can be Al2O3. Specifically, Al2O3 can be implanted into SiO2 by sputtering. The reaction of Al2O3 with SiO2 can form a metal silicate compound Al2SiO5 or Al2O3 with a thickness at the nm level. SiO2.

[0065] Based on this, such as Figure 11 As shown, the above step S22, which forms at least one carbon nanotube 6 on the first oxide layer 511, can be implemented in the following steps: S221: Carbon nanotubes 6 are synthesized on metal silicate compound 71 by chemical vapor deposition under the action of a catalyst. The catalyst here can be tungsten-based alloy nanocrystals. The specific process is equivalent to preparing tungsten-based alloy nanocrystal catalysts on metal silicate compound 71 with clusters of carbonophilic metals (such as tungsten-containing metals) and other transition metal elements as starting materials under relatively mild conditions, and then synthesizing carbon nanotubes 6 by ethanol chemical vapor deposition.

[0066] Method 3: The first oxide layer 511 can be SiO2. A metal oxide 72 is formed at the locations on the first oxide layer 511 where carbon nanotubes 6 will be formed. The carbon nanotubes 6 will then be generated on the metal oxide 72. Based on this, such as... Figure 12 As shown, the steps following S21 and before S22 may also include the following steps: S212: Add metal to the first oxide layer 511 to form metal oxide 72. Here, the process of adding metal can be evaporation and photolithography. When the metal is Al, Al is added to the first oxide layer 511 by evaporation and photolithography. Al can be naturally oxidized in air to form metal oxide 72 (Al2O3) with a thickness of nm.

[0067] Based on this, such as Figure 12 As shown, step S23, which involves forming at least one carbon nanotube 6 on the first oxide layer 511, can be specifically implemented in step S222: S222: The above-mentioned carbon nanotubes 6 were prepared by laser ablation.

[0068] based on Figure 2b The structure of the field-effect transistor shown, after step S2 and before step S3, is as follows: Figure 13 As shown, it also includes the following steps: S2': Highly conductive metal is deposited on both sides of the channel layer 5 to form a first contact layer 21 and a second contact layer 31 on both sides of the channel layer 5. One end of the carbon nanotube 6 is electrically connected to the source electrode 2 through the first contact layer 21, and the other end of the carbon nanotube 6 is electrically connected to the drain electrode 3 through the second contact layer 31. Here, the process of depositing highly conductive metal on both sides of the channel layer 5 (referring to both sides along the first direction) can be carried out by electron beam printing. It should be understood that the first contact layer 21 and the second contact layer 31 can be prepared separately or simultaneously, depending on the specific process in production.

[0069] Based on step S2', Figure 13 In step S4, specifically, the source electrode 2 is connected to one end of the carbon nanotube 6 through the first contact layer 21, and the drain electrode 3 is connected to the other end of the carbon nanotube 6 through the second contact layer 31, thereby realizing the circuit connection between the source electrode 2, the carbon nanotube 6, and the drain electrode 3 to form a conductive path.

[0070] When a capacitor layer 41 and a gate dielectric layer 42 are stacked between the gate 4 and the channel layer 5 of a field-effect transistor, such as Figure 14 As shown, step S3 above includes the following steps: S31: Prepare gate dielectric layer 42 on the channel layer; S32: Prepare a capacitor layer 41 on the gate dielectric layer 42; S31: The gate 4 is fabricated on the capacitor layer 41.

[0071] It should be understood that a first protective layer 43 can also be added to cover the surface of the structure composed of gate 4, capacitor layer 41 and gate dielectric layer 42 to provide protection.

[0072] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A field-effect transistor, characterized in that, include: Substrate structure, source, drain, and gate; The source and the drain are arranged along a first direction on the substrate structure, and a channel region is formed between the source and the drain; A channel layer is formed within the channel region, and N carbon nanotubes extending along the first direction are embedded within the channel layer. The channel layer encloses the outer peripheral surface of each carbon nanotube. The carbon nanotubes are grown at the interface between the channel layer and the carbon nanotubes, and N is an integer greater than or equal to 1. The two ends of the N carbon nanotubes are respectively connected to the source and the drain to form a conductive path. The gate is formed on the channel layer.

2. The field-effect transistor as described in claim 1, characterized in that, The N is greater than or equal to 3, and the N carbon nanotubes are distributed in an array.

3. The field-effect transistor as described in claim 1, characterized in that, The channel layer includes at least one channel interlayer, and each channel interlayer includes a first oxide layer and a second oxide layer stacked along the direction of the substrate structure toward the channel layer, and at least one carbon nanotube is embedded between the first oxide layer and the second oxide layer.

4. The field-effect transistor as described in claim 3, characterized in that, The first oxide layer is used to contact the surface of the carbon nanotubes, where a metal silicate compound is formed.

5. The field-effect transistor as described in claim 3, characterized in that, The first oxide layer is used to contact the surface of the carbon nanotubes, where metal oxides are formed.

6. The field-effect transistor as claimed in claim 1, characterized in that, A first contact layer is provided on the side of the source electrode facing the channel layer, and a second contact layer is provided on the side of the drain electrode facing the channel layer. One end of the carbon nanotube is connected to the source electrode through the first contact layer, and the other end of the carbon nanotube is connected to the drain electrode through the second contact layer. The conductivity of the first contact layer is higher than that of the source electrode, and the conductivity of the second contact layer is higher than that of the drain electrode.

7. The field-effect transistor as claimed in claim 6, characterized in that, The first contact layer is made of gold or a gold alloy, and the second contact layer is made of gold or a gold alloy.

8. The field-effect transistor as claimed in claim 1, characterized in that, Along the direction from the gate to the channel layer, a capacitor layer and a gate dielectric layer are also stacked between the gate and the channel layer.

9. The field-effect transistor as described in any one of claims 1-8, characterized in that, The substrate structure includes a silicon substrate and a well region formed on the silicon substrate.

10. The field-effect transistor as claimed in claim 9, characterized in that, The substrate structure further includes an insulating layer disposed on the side of the well region away from the silicon substrate, and the source and the drain are located on the insulating layer.

11. A semiconductor structure, characterized in that, It includes two field-effect transistors as described in any one of claims 1-10, wherein the two field-effect transistors are isolated from each other by an isolator.

12. A method for fabricating a field-effect transistor, characterized in that, Includes the following steps: Preparation of substrate structure; A channel layer is prepared on the substrate structure, and N carbon nanotubes extending along a first direction are embedded in the channel layer with both ends of the carbon nanotubes exposed in the channel layer. The channel layer wraps around the outer peripheral surface of each carbon nanotube. The carbon nanotubes are grown at the interface between the channel layer and the carbon nanotubes, and N is an integer greater than or equal to 1. A gate is formed on the channel layer; A source and a drain are formed on both sides of the channel layer, and the source and the drain are respectively connected to the two ends of the carbon nanotube to form a conductive path.

13. The preparation method according to claim 12, characterized in that, The fabrication of the channel layer on the substrate structure includes at least one of the following steps: A first oxide layer is formed on a substrate, wherein the substrate is a structure used to form one side of the channel layer; At least one carbon nanotube is formed on the first oxide layer; A second oxide layer is formed on the surface of the carbon nanotubes to cover them.

14. The preparation method according to claim 13, characterized in that, After forming the first oxide layer on the substrate and before forming at least one carbon nanotube on the first oxide layer, the method further includes the following steps: A metal oxide is prepared on the first oxide layer, such that the metal oxide reacts with the first oxide layer to form a metal silicate compound.

15. The preparation method according to claim 14, characterized in that, The formation of at least one carbon nanotube on the first oxide layer includes the following steps: The carbon nanotubes were synthesized on the metal silicate compound by vapor deposition under the action of a catalyst.

16. The preparation method according to claim 15, characterized in that, The catalyst is a tungsten-based alloy nanocrystal.

17. The preparation method according to claim 13, characterized in that, After forming the first oxide layer on the substrate and before forming at least one carbon nanotube on the first oxide layer, the method further includes the following steps: A metal is added to the first oxide layer to form a metal oxide.

18. The preparation method according to claim 12, characterized in that, A first contact layer is provided on the side of the source electrode facing the channel layer, and a second contact layer is provided on the side of the drain electrode facing the channel layer. One end of the carbon nanotube is connected to the source electrode through the first contact layer, and the other end of the carbon nanotube is connected to the drain electrode through the second contact layer. The conductivity of the first contact layer is higher than that of the source electrode, and the conductivity of the second contact layer is higher than that of the drain electrode. Before fabricating a channel layer on the substrate structure in which at least one carbon nanotube is embedded, and before forming a gate on the channel layer, the method further includes the following steps: Highly conductive metal is deposited on both sides of the channel layer to form a first contact layer and a second contact layer on both sides of the channel layer, and the two ends of the carbon nanotube are respectively connected to the first contact layer and the second contact layer.

19. The preparation method according to claim 18, characterized in that, The process of depositing highly conductive metal on both sides of the channel layer is electron beam printing.

20. The preparation method according to any one of claims 12-19, characterized in that, Along the direction from the gate to the channel layer, a capacitor layer and a gate dielectric layer are further stacked between the gate and the channel layer. Forming the gate on the channel layer includes the following steps: A gate dielectric layer is fabricated on the channel layer; A capacitor layer is fabricated on the gate dielectric layer; The gate is fabricated on the capacitor layer.

21. The preparation method according to any one of claims 12-19, wherein the preparation method is characterized in that, The substrate structure includes a silicon substrate and a well region formed on the silicon substrate. The fabrication of the substrate structure includes the following steps: Impurities are doped into a silicon substrate to form a well region.

22. The preparation method according to claim 21, wherein the preparation method is characterized in that, The substrate structure further includes an insulating layer formed on the side of the well region facing away from the silicon substrate. After doping the silicon substrate with impurities to form the well region, the following steps are also included: An insulating layer is formed on the side of the well region away from the silicon substrate.

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