Bidirectional voltage converter for smart cards and smart cards including bidirectional voltage converters

Abstract

The bidirectional voltage converter for a smart card includes: a switching element connected between the input and output nodes; and a startup transistor whose channel width to channel length ratio is less than that of the switching element. During boost operation, the bidirectional voltage converter stores the drive voltage applied to the output node in a storage capacitor and provides the voltage stored in the storage capacitor to the input node. The bidirectional voltage converter can progressively boost another drive voltage at the input node and can perform bidirectional voltage conversion with a reduced footprint and high efficiency.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2020-0077866 filed on June 25, 2020 and Korean Patent Application No. 10-2020-0108035 filed on August 26, 2020, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of this disclosure relate to smart cards. Specifically, this disclosure relates to a bidirectional voltage converter for a smart card performing fingerprint authentication and a smart card including the bidirectional voltage converter. Background Technology

[0004] Depending on how the device is used, smart cards (also known as chip cards or integrated circuit (IC) cards) can be categorized into contact cards, contactless cards, and combination cards (or hybrid cards). Contact cards include contact terminals on their surface that are supplied with external power. Contactless cards include contactless terminals (such as antennas) that receive radio frequency signals to generate a power supply voltage. Combination cards can operate as contact cards in contact mode and as contactless cards in contactless mode. Summary of the Invention

[0005] An example embodiment provides a bidirectional voltage converter for a smart card that performs fingerprint authentication, which can efficiently perform a boost operation without a charge pump.

[0006] An example embodiment provides a smart card including a bidirectional voltage converter that can efficiently perform boost operation without a charge pump.

[0007] According to some example embodiments, a bidirectional voltage converter for a smart card performing fingerprint authentication includes a gate drive circuit, a switching circuit, and a startup circuit. The gate drive circuit generates a first clock signal to a fourth clock signal based on a first output signal, a second output signal, a first sub-power-down signal, and a second sub-power-down signal. The first and second output signals have non-overlapping activation intervals, and at least some of the first to fourth clock signals have non-overlapping activation intervals. The switching circuit includes a first to a fourth switching element connected in series between an input node and ground. The first to fourth switching elements switch in response to a corresponding one of the first to fourth clock signals, and in boost operation, store the output voltage applied to the output node in a storage capacitor coupled between the first and second nodes. The startup circuit includes a first startup transistor and a second startup transistor connected in series between the input and output nodes. The first and second startup transistors switch in response to a first delayed clock signal and a second delayed clock signal in boost operation to provide the output voltage stored in the storage capacitor to the input node. The first delayed clock signal and the second delayed clock signal have non-overlapping activation intervals.

[0008] According to some example embodiments, a smart card performing fingerprint authentication includes a matching circuit and a smart card chip. The matching circuit receives voltage from an external card reader without contact to provide the received voltage as a contactless voltage. The smart card chip is coupled to the matching circuit via a first power terminal and a second power terminal. The smart card chip includes a connection terminal, an internal voltage generation circuit, a fingerprint sensor, and a processor. The connection terminal receives voltage when in contact with a card reader to provide a contact voltage. The internal voltage generation circuit generates a first driving voltage and a second driving voltage based on the contactless voltage in contactless mode, and generates the first driving voltage and the second driving voltage based on a category of contact voltage levels in contact mode. The fingerprint sensor operates based on the first driving voltage and generates a fingerprint image signal based on an input fingerprint. The internal voltage generation circuit includes a bidirectional voltage converter. The bidirectional voltage converter is connected between an input node and an output node, and progressively boosts the first driving voltage by storing a second driving voltage applied to the output node in a storage capacitor therein and by providing the second driving voltage stored in the storage capacitor to the input node during a boost operation.

[0009] According to some example embodiments, a bidirectional voltage converter for a smart card performing fingerprint authentication includes an idle time generator, a gate drive circuit, a switching circuit, a startup circuit, and a delayed clock signal generation circuit. The idle time generator generates a first output signal and a second output signal having non-overlapping activation intervals based on a reference clock signal. The gate drive circuit generates a first clock signal to a fourth clock signal based on the first output signal, the second output signal, a first sub-power-down signal, and a second sub-power-down signal. At least some of the first clock signals to the fourth clock signal have non-overlapping activation intervals. The switching circuit includes a first switching element to a fourth switching element connected in series between an input node and ground voltage. The first switching element to the fourth switching element switches in response to a corresponding clock signal among the first clock signals to the fourth clock signal during boost operation and stores the output voltage applied to the output node in a storage capacitor coupled between the first node and the second node. The startup circuit includes a first startup transistor and a second startup transistor connected in series between the input node and the output node. The first and second startup transistors switch in response to a first delayed clock signal and a second delayed clock signal during boost operation to provide the output voltage stored in the storage capacitor to the input node. The first delayed clock signal and the second delayed clock signal have an activation interval that does not overlap with each other. The delayed clock generation circuit generates the first delayed clock signal and the second delayed clock signal based on the first output signal, the second output signal, and the second power-down signal.

[0010] Therefore, a bidirectional voltage converter for a smart card performing fingerprint authentication includes: a switching element connected between an input node and an output node; and a start-up transistor whose channel width to channel length ratio is less than that of the switching element. The bidirectional voltage converter does not include a charge pump. During boost operation, the bidirectional voltage converter stores a second drive voltage applied to the output node in a storage capacitor and provides the voltage stored in the storage capacitor to the input node. Therefore, the bidirectional switched-capacitor converter can progressively boost the first drive voltage at the input node and can perform bidirectional voltage conversion with a reduced footprint and high efficiency. Attached Figure Description

[0011] The above and other features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0012] Figure 1 This is a diagram illustrating a smart card system according to some example embodiments.

[0013] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram illustrating an example of a smart card in a smart card system.

[0014] Figure 3 An example embodiment is shown. Figure 2 An example of a rectifier in a smart card chip.

[0015] Figure 4 This illustrates an example embodiment. Figure 2 A block diagram of an example of the internal voltage generation circuit in a smart card chip.

[0016] Figure 5 This illustrates an example embodiment. Figure 4 A circuit diagram of an example switched capacitor converter in the internal voltage generation circuit.

[0017] Figure 6 This illustrates an example embodiment. Figure 4 A circuit diagram of another example of a switched capacitor converter in the internal voltage generation circuit.

[0018] Figure 7 It shows Figure 5 Example operation of the switched capacitor converter.

[0019] Figure 8 It shows Figure 5 Example operation of the switched capacitor converter.

[0020] Figure 9 This illustrates an example embodiment. Figure 4 A block diagram of an example mode selector in the internal voltage generation circuit.

[0021] Figure 10 The contactless mode is shown. Figure 4 It is part of the internal voltage generation circuit.

[0022] Figures 11 to 13 Each of them shows the contact mode. Figure 4 It is part of the internal voltage generation circuit.

[0023] Figure 14 This illustrates an example embodiment. Figure 4 A block diagram of an example bidirectional voltage converter in the internal voltage generation circuit.

[0024] Figure 15 This illustrates an example embodiment. Figure 14 A circuit diagram of an example of an idle time generator in a bidirectional voltage converter.

[0025] Figure 16 This illustrates an example embodiment. Figure 14 A circuit diagram of an example of a gate drive circuit.

[0026] Figure 17 This illustrates an example embodiment. Figure 14 A circuit diagram of an example clock generation circuit with a delay in the circuit.

[0027] Figure 18 It is shown Figure 14 Timing diagrams of various signals in a bidirectional voltage converter.

[0028] Figure 19 and Figure 20 They are shown respectively Figure 14 The operation of the switching circuit and the start-up circuit in the bidirectional voltage converter during the first and second stages of the step-down operation.

[0029] Figure 21 It shows Figure 14 Various signals in the step-down operation of the bidirectional voltage converter.

[0030] Figure 22 and Figure 23 They are shown respectively Figure 14 The operation of the switching circuit and the startup circuit in the bidirectional voltage converter during the first and second phases of the first interval of the boost operation.

[0031] Figure 24 The output and input voltages are shown during the first interval of the boost operation of the bidirectional voltage converter.

[0032] Figure 25 and Figure 26 They are shown respectively Figure 14 The operation of the switching circuit and the startup circuit in the bidirectional voltage converter during the first and second phases of the second interval of the boost operation.

[0033] Figure 27 The output and input voltages are shown during the second interval of the boost operation of the bidirectional voltage converter.

[0034] Figure 28 and Figure 29 They are shown respectively Figure 14 The operation of the switching circuit and the start-up circuit in the bidirectional voltage converter during the first and second phases of the third interval of the boost operation.

[0035] Figure 30 The output and input voltages are shown during the third interval of the boost operation of the bidirectional voltage converter.

[0036] Figure 31 It is shown Figure 14 Timing diagram of various signals of a bidirectional voltage converter during boost operation.

[0037] Figure 32 It shows that based on Figure 14 A table showing the logic levels of the first and second sub-power-down signals of the input and output voltages in a bidirectional voltage converter.

[0038] Figure 33 An example embodiment is shown. Figure 2 An example of a fingerprint recognition sensor in a smart card chip.

[0039] Figure 34 An example of a smart card according to an example embodiment is shown.

[0040] Figure 35 This is a block diagram illustrating an electronic device according to an example embodiment. Detailed Implementation

[0041] Exemplary embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings. The same reference numerals may denote the same elements throughout the drawings.

[0042] Figure 1 This is a diagram illustrating a smart card system according to some example embodiments.

[0043] Reference Figure 1 The smart card system 10 may include a card reader 20 and a smart card 50.

[0044] The card reader 20 may include a reader chip 30 and an antenna 21. The reader chip 30 may include a card socket 31. When the smart card 50 is in contact with the card socket 31, the card socket 31 provides voltage to the smart card 50 and exchanges data with the smart card 50. When the smart card 50 is inserted into the card socket 31, the reader chip 30 provides operating voltage to the smart card 50, identifies the smart card 50, and exchanges payment data with the smart card 50.

[0045] The smart card 50 may include an antenna 61 and a smart card chip 100. The smart card chip 100 may include contact terminals 63.

[0046] The smart card 50 can communicate with the card reader 20 in a contactless manner via the antenna 61, receive operating voltage from the card reader 20, and exchange payment data with the card reader 20. When the smart card 50 is inserted into the card slot 31, the smart card 50 can receive operating voltage through the contact terminal 63 and exchange payment data with the card reader 20 through the contact terminal 63.

[0047] When the smart card 50 communicates with the card reader 20 in a contactless manner, the smart card 50 can receive operating voltage and exchange payment data with the card reader 20 in electromagnetic form through antennas 21 and 61.

[0048] When making a payment in a contactless manner, the smart card 50 may include a fingerprint sensor (FRS) 270, and the fingerprint sensor 270 may be used to perform user authentication on the payment data.

[0049] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram illustrating an example of a smart card in a smart card system.

[0050] Reference Figure 2 The smart card 50 may include a matching circuit 70 and a smart card chip 100. The smart card chip 100 can be connected to the matching circuit 70 via a first power terminal L1 and a second power terminal L2.

[0051] Matching circuit 70 may include resonant circuit 71 and filter 73. Resonant circuit 71 may include antenna L and first capacitor C1. Filter 73 includes second capacitor C2 and third capacitor C3 to provide an induced voltage in response to electromagnetic wave EMW to first power terminal L1 and second power terminal L2. When smart card 50 is contactlessly coupled to card reader 20, matching circuit 70 can supply the induced voltage in response to electromagnetic wave EMW to smart card chip 100 as input voltage VIN.

[0052] The smart card chip 100 can receive an input voltage VIN from the matching circuit 70 via the first power terminal L1 and the second power terminal L2 in contactless mode, and the smart card chip 100 can receive a voltage supplied via the contact terminal 63 in contact mode.

[0053] The smart card chip 100 may include a rectifier 210, an internal voltage generation circuit (IVGC) 300, a processor 240, a memory 250, a demodulator 251, a modulator 253, a fingerprint sensor 270, LEDs 290, and a logic block (LCB) 295.

[0054] The rectifier 210 can generate a contactless voltage VDDU as a direct current (DC) voltage by rectifying the input voltage VIN.

[0055] The internal voltage generation circuit 300 can receive a contactless voltage VDDU in contactless mode and a contact voltage VDD5PX in contact mode. In contactless mode, the internal voltage generation circuit 300 can generate a first driving voltage VDD5P and a second driving voltage VDD3P with a level lower than the first driving voltage VDD5P based on the contactless voltage VDDU. In contact mode, it can generate the first driving voltage VDD5P and the second driving voltage VDD3P based on the level of the contact voltage VDD5PX and the type of the card reader 20.

[0056] The internal voltage generation circuit 300 can provide a second driving voltage VDD3P to the processor 240 and logic block 295, and can provide a first driving voltage VDD5P to the fingerprint sensor 270 and LED 290. Because the internal voltage generation circuit 300 provides the second driving voltage VDD3P to the more power-consuming processor 240 and logic block 295, the power consumption of the smart card chip 100 can be reduced.

[0057] The processor 240 can control the overall operation of the smart card chip 100.

[0058] When performing a signal receiving operation, demodulator 251 generates received data RND by demodulating the signal supplied from matching circuit 70 via first power terminal L1 and second power terminal L2, and provides the received data RND to processor 240. Processor 240 can decode the received data RND and can store at least a portion of the received data RND in memory 250.

[0059] When performing a signal transmission operation, processor 240 reads output data from memory 250 and encodes the output data to provide transmission data TNM to modulator 253. Modulator 253 can modulate transmission data TNM to provide a modulated signal to first power terminal L1 and second power terminal L2. For example, modulator 253 can generate a modulated signal by performing load modulation relative to transmission data TNM.

[0060] The processor 240 can provide the switch control signal SCS to the internal voltage generation circuit 300.

[0061] The memory 250 can store the original fingerprint of a user registered through preprocessing. The fingerprint sensor 270 can generate a fingerprint image signal based on the user's input fingerprint during payment operations in contactless mode, and can provide the fingerprint image signal to the processor 240. The processor 240 can compare the fingerprint image signal with the user's original fingerprint and can determine whether the user's input fingerprint is forged based on the comparison result. When the processor 240 determines that the user's input fingerprint matches the user's original fingerprint, the processor 240 can indicate successful user authentication by controlling LED 295 to emit light while performing user authentication on payment data associated with the payment operation. When the processor 240 determines that the user's input fingerprint does not match the user's original fingerprint, the processor 240 can indicate the mismatch via LED 295.

[0062] Figure 3 An example embodiment is shown. Figure 2 An example of a rectifier in a smart card chip.

[0063] Reference Figure 3 The rectifier 210 may include a first diode 211 and a second diode 212.

[0064] The first diode 211 is connected to the first power terminal L1, and the second diode 212 is connected to the second power terminal L2. The first diode 211 and the second diode 212 can rectify the induced voltage VDDUA generated in response to the electromagnetic wave EMW to provide the contactless voltage VDDU to the internal voltage generation circuit 300 in contactless mode.

[0065] Figure 4 This illustrates an example embodiment. Figure 2 A block diagram of an example of the internal voltage generation circuit in a smart card chip.

[0066] Reference Figure 4 The internal voltage generation circuit 300 may include a first switched capacitor (SC) converter 310, a second switched capacitor (SC) converter 400, a mode selector 330, a control signal generator 350, a first contact switch 360, and a second contact switch 370. The first switched capacitor converter 310 may be referred to as a switched capacitor converter, and the second switched capacitor converter 400 may be referred to as a bidirectional switched capacitor converter.

[0067] The first contact switch 360 can be connected to the first node ND1 and can selectively switch to the first node ND1 in contact mode based on the contact voltage VDD5PX received from the (external) card reader 20 based on the first switch enable signal SW_EN1.

[0068] The second contact switch 370 can be connected to the second node ND2, and can selectively switch to the second node ND2 in contact mode based on the contact voltage VDD5PX received from the card reader 20 based on the second switch enable signal SW_EN2.

[0069] The switched capacitor converter 310 can be connected to the first node ND1 and can reduce (gradually reduce) the contactless voltage VDDU received from the card reader 20 to provide a first (reduced) voltage to the first node ND1 in contactless mode.

[0070] The bidirectional switched capacitor converter 400 can be connected to a first node ND1 and a second node ND2. It can reduce the first drive voltage VDD5P of the first node ND1 to provide a second (reduced) voltage to the second node ND2 in contactless mode. It can also reduce the first drive voltage VDD5PX or boost the second drive voltage VDD3P of the second node ND2 based on the level of the contact voltage to provide the boosted voltage to the first node ND1.

[0071] The mode selector 330 can receive contact voltage VDD5PX, contactless voltage VDDU, and a first drive voltage VDD5P. It can output a first mode signal MDS1 specifying one of the contact mode and contactless mode, and a second mode signal MDS2 specifying one of the sub-modes of the contact mode based on the levels of contact voltage VDD5PX, contactless voltage VDDU, and the first drive voltage VDD5P. Furthermore, it can select one of the contact voltage VDD5PX, contactless voltage VDDU, and the first drive voltage VDD5P to output the selected one as the control voltage VDMAX. The selected one has the highest voltage level among the contact voltage VDD5PX, contactless voltage VDDU, and the first drive voltage VDD5P.

[0072] The mode selector 330 can provide a first mode signal MDS1 and a second mode signal MDS2 to the control signal generator 350. The second mode signal MDS2 may include multiple bits and can specify a sub-mode of the contact mode.

[0073] The control signal generator 350 can generate a first power-down signal PD1, a second power-down signal PD2, a first switch enable signal SW_EN1, and a second switch enable signal SW_EN2 based on the first mode signal MDS1 and the second mode signal MDS2. The second power-down signal PD2 may include the first sub-power-down signal and the second sub-power-down signal.

[0074] The first power-down signal PD1 can be associated with enabling the switched capacitor converter 310, the second power-down signal PD2 can be associated with enabling the bidirectional switched capacitor converter 400, the first switch enable signal SW_EN1 can be associated with enabling the first contact switch 360, and the second switch enable signal SW_EN2 can be associated with enabling the second contact switch 370.

[0075] Figure 5 This illustrates an example embodiment. Figure 4 A circuit diagram of an example switched capacitor converter in the internal voltage generation circuit.

[0076] Reference Figure 5The switched capacitor converter 310a may include a first switch 311, a second switch 312, a third switch 313, a fourth switch 314, and a capacitor 315.

[0077] The first switch 311 is connected between the first node N11, which receives the contactless voltage VDDU, and the second node N12, and switches in response to the first switch control signal SCS1. A capacitor 315 is coupled between the second node N12 and the third node N13. The second switch 312 is connected between the second node N12 and the fourth node N14, which provides the first drive voltage VDD5P, and switches in response to the second switch control signal SCS2.

[0078] The third switch 313 is connected between the third node N13 and the ground voltage VSS, and is switched in response to the second switch control signal SCS2. The fourth switch 314 is connected between the third node N13 and the fourth node N14, and is switched in response to the first switch control signal SCS1.

[0079] The first switch control signal SCS1 and the second switch control signal SCS2 can have the same logic level. The first switch 311 and the fourth switch 314 can be turned on in response to the first switch control signal SCS1 being low, and can be turned off in response to the first switch control signal SCS1 being high. The second switch 312 and the third switch 313 can be turned off in response to the second switch control signal SCS2 being low, and can be turned on in response to the second switch control signal SCS2 being high.

[0080] Figure 6 This illustrates an example embodiment. Figure 4 A circuit diagram of another example of a switched capacitor converter in the internal voltage generation circuit.

[0081] Reference Figure 6 The switched capacitor converter 310b may include p-channel metal-oxide-semiconductor (PMOS) transistors 316 and 319, n-channel metal-oxide-semiconductor (NMOS) transistors 317 and 318, and capacitor 315.

[0082] PMOS transistor 316 is connected between first node N11 and second node N12, which receive the contactless voltage VDDU, and is turned on / off in response to the first switch control signal SCS1. NMOS transistor 317 is connected between second node N12 and fourth node N14, which provides the first drive voltage VDD5P, and is turned on / off in response to the second switch control signal SCS2. Capacitor 315 is coupled between second node N12 and third node N13.

[0083] NMOS transistor 318 is connected between the third node N13 and ground voltage VSS, and is turned on / off in response to the second switch control signal SCS2. PMOS transistor 319 is connected between the third node N13 and the fourth node N14, and is turned on / off in response to the first switch control signal SCS1.

[0084] Figure 7 It shows Figure 5 Example operation of the switched capacitor converter.

[0085] Figure 6 The operation of the switched capacitor converter 310b in the middle can be with Figure 5 The operation is the same as that of the switched capacitor converter 310a.

[0086] Reference Figure 7 When the first switch 311 and the fourth switch 314 are turned on and the second switch 312 and the third switch 313 are turned off during the first phase, the voltage VCAP is stored in the capacitor 315 based on the contactless voltage VDDU, and the first drive voltage VDD5P is provided at the fourth node N14 based on the voltage VCAP stored in the capacitor 315.

[0087] Figure 8 It shows Figure 5 Example operation of the switched capacitor converter.

[0088] Figure 6 The operation of the switched capacitor converter 310b in the middle can be with Figure 5 The operation is the same as that of the switched capacitor converter 310a.

[0089] Reference Figure 8 When the first switch 311 and the fourth switch 314 are turned off and the second switch 312 and the third switch 313 are turned on during the second phase, the voltage VCAP stored in the capacitor 315 during the first phase decreases linearly, and a first drive voltage VDD5P is provided at the fourth node N14 based on the voltage VCAP stored in the capacitor 315.

[0090] Figure 9 This illustrates an example embodiment. Figure 4 A block diagram of an example mode selector in the internal voltage generation circuit.

[0091] Reference Figure 9 The mode selector 330 may include a comparator 331, a contact detector 333, a mode signal generator 335, a category detector 337, a level comparator 341, and a multiplexer (MUX) 343.

[0092] Comparator 331 can compare the contactless voltage VDDU and the contact voltage VDD5PX to output a comparison signal CS indicating the comparison result. When the smart card 50 is connected to the card reader 20 in contact mode, the contact detector 333 can output a detection signal DS associated with the detection of the external reset signal ERST based on the external reset signal ERST received from the card reader 20 in contact mode.

[0093] The pattern signal generator 335 can generate a first pattern signal MDS1 specifying one of a contact mode and a contactless mode, and can generate a contact mode signal CMS specifying a contact mode based on a comparison signal CS and a detection signal DS. Since the comparison signal CS indicates the comparison result of the contactless voltage VDDU and the contact voltage VDD5PX, and the detection signal DS indicates whether an external reset signal ERST has been applied, the pattern signal generator 335 can determine the logic levels of the first pattern signal MDS1 and the contact mode signal CMS.

[0094] The category detector 337 can be enabled in response to a contact mode signal CMS for a specified contact mode, and can compare the contact voltage VDD5PX with a first reference voltage VREF1 and a second reference voltage VREF2 to generate a second mode signal MDS2 indicating the category of the reader 20 associated with the sub-mode.

[0095] The category detector 337 can determine the logic level of the second mode signal MDS2 based on comparing the contact voltage VDD5PX with a first reference voltage VREF1 and a second reference voltage VREF2. The second reference voltage VREF2 can be less than the first reference voltage VREF1.

[0096] In an embodiment, the first reference voltage VREF1 can be set to approximately 4 [V], and the second reference voltage VREF2 can be set to approximately 2.4 [V].

[0097] For example, when the contact voltage VDD5PX is greater than the first reference voltage VREF1, the second mode signal MDS2 can specify the first sub-mode of the contact mode. For example, when the contact voltage VDD5PX is less than the first reference voltage VREF1 but greater than the second reference voltage VREF2, the second mode signal MDS2 can specify the second sub-mode of the contact mode. For example, when the contact voltage VDD5PX is less than the second reference voltage VREF2, the second mode signal MDS2 can specify the third sub-mode of the contact mode.

[0098] The first sub-mode can indicate that the card reader 20 corresponds to the first category and can provide a contact voltage VDD5PX with approximately 5 [V], the second sub-mode can indicate that the card reader 20 corresponds to the second category and can provide a contact voltage VDD5PX with approximately 3 [V], and the third sub-mode can indicate that the card reader 20 corresponds to the third category and can provide a contact voltage VDD5PX with approximately 1.8 [V].

[0099] The level comparator 341 can compare the contact voltage VDD5PX, the no-contact voltage VDDU, and the first drive voltage VDD5P to output a selection signal SS to the multiplexer 343. The selection signal SS indicates the one with the highest voltage level among the contact voltage VDD5PX, the no-contact voltage VDDU, and the first drive voltage VDD5P.

[0100] The multiplexer 343 can respond to the selection signal SS by outputting the contact voltage VDD5PX, the no-contact voltage VDDU, and the first drive voltage VDD5P, with the largest voltage level as the control voltage VDMAX.

[0101] Figure 10 The contactless mode is shown. Figure 4 Part of the internal voltage generation circuit, Figures 11 to 13 Each of them shows the contact mode. Figure 4 It is part of the internal voltage generation circuit.

[0102] exist Figures 10 to 13 For ease of explanation, the following is shown: Figure 4 The internal voltage generation circuit 300 includes a switched capacitor converter 310, a bidirectional switched capacitor converter 400, a first contact switch 360, and a second contact switch 370.

[0103] Reference Figure 4 and Figure 10 In contactless mode, the control signal generator 350 can respond to the first mode signal MDS1 by using the first switch enable signal SW_EN1 and the second switch enable signal SW_EN2 to disable the first contact switch 360 and the second contact switch 370 respectively.

[0104] The switched capacitor converter 310 can be enabled in response to a first power-down signal PD1 and can reduce the contactless voltage VDDU having a first voltage level (approximately 6 [V]) to output a first drive voltage VDD5P having a second voltage level (approximately 3 [V]) to the first node ND1. The second voltage level is less than the first voltage level.

[0105] The bidirectional switched capacitor converter 400 can receive a first drive voltage VDD5P through the first path PTH1, and can reduce the first drive voltage VDD5P to output a second drive voltage VDD3P with a third voltage level (approximately 1.5 [V]) to the second node ND2. The third voltage level is lower than the second voltage level.

[0106] Reference Figure 4 and Figure 11 In the first sub-mode of the contact mode, the control signal generator 350 can disable the switched capacitor converter 310 and the second contact switch 370 in response to the first mode signal and the second mode signal MDS2 by using the first power-down signal PD1 and the second switch enable signal SW_EN2, respectively.

[0107] The first contact switch 360 can switch the contact voltage VDD5PX, having a first voltage level (approximately 5 [V]), to the first node ND1 as the first drive voltage VDD5P. The bidirectional switched capacitor converter 400 can be enabled in response to a second power-down signal PD2, receive the first drive voltage VDD5P via path PTH2, and reduce the first drive voltage VDD5P, having a first level (approximately 5 [V]), to output a second drive voltage VDD3P, having a second voltage level (approximately 2.5 [V]), to the second node ND2. The second voltage level is lower than the first voltage level.

[0108] The internal voltage generation circuit 300 can generate a first drive voltage VDD5P with a first level (approximately 5 [V]) and a second drive voltage VDD3P with a second voltage level (approximately 2.5 [V]) in the first sub-mode of the contact mode.

[0109] Reference Figure 4 and Figure 12 In the second sub-mode of the contact mode, the control signal generator 350 can disable the switched capacitor converter 310 and the bidirectional switched capacitor converter 400 in response to the first mode signal MDS1 and the second mode signal MDS2 by using the first power-down signal PD1 and the second power-down signal PD2, respectively.

[0110] The first contact switch 360 can switch the contact voltage VDD5PX, which has a first voltage level (approximately 3 [V]), to the first node ND1 as the first drive voltage VDD5P. The second contact switch 370 can switch the contact voltage VDD5PX, which has a first voltage level (approximately 3 [V]), to the second node ND2 as the second drive voltage VDD3P.

[0111] The internal voltage generation circuit 300 can generate a first drive voltage VDD5P with approximately 3 [V] and a second drive voltage VDD3P with approximately 3 [V] in the second sub-mode of the contact mode.

[0112] Reference Figure 4 and Figure 13 In the third sub-mode of the contact mode, the control signal generator 350 can disable the switched capacitor converter 310 and the first contact switch 360 in response to the first mode signal MDS1 and the second mode signal MDS2 by using the first power-down signal PD1 and the first switch enable signal SW_EN1, respectively.

[0113] The second contact switch 370 can switch the contact voltage VDD5PX, which has a first voltage level (approximately 1.8 [V]), to the second node ND2 as the second drive voltage VDD3P.

[0114] The bidirectional switched capacitor converter 400 can be enabled in response to a second power-down signal PD2, which can boost a second drive voltage VDD3P having a first voltage level (approximately 1.8 [V]) to output a first drive voltage VDD5P having a second voltage level (approximately 3.6 [V]) to a first node ND1 via path PTH3, the second voltage level being greater than the first voltage level.

[0115] That is, the internal voltage generation circuit 300 can generate a first drive voltage VDD5P with approximately 3.6 [V] and a second drive voltage VDD3P with approximately 1.8 [V] in the third sub-mode of the contact mode.

[0116] The internal voltage generation circuit 300 according to the example embodiment includes a first contact switch 360, a second contact switch 370, and a bidirectional switched capacitor converter 400, and can generate a second drive voltage VDD3P for operating the logic circuit block 295 and a first drive voltage VDD5P for operating the fingerprint sensor 270 and the LED 295, even if the level of the contact voltage VDD5PX changes based on the type of the card reader 20.

[0117] Figure 14 This illustrates an example embodiment. Figure 4 A block diagram of an example bidirectional voltage converter in the internal voltage generation circuit.

[0118] Reference Figure 14 The bidirectional voltage converter 400 may include an oscillator OSC 405, an idle time generator DTG 410, an operating voltage generator 407, a gate drive circuit 420, a switching circuit 450, a startup circuit 455, a delayed clock generation circuit 460, and a storage capacitor CF.

[0119] The bidirectional voltage converter 400 may also include an input capacitor CIN and an output capacitor COUT. The input capacitor CIN may be coupled between the input node NI and the ground voltage VSS, and the output capacitor COUT may be coupled between the output node NO and the ground voltage VSS. The input node NI may correspond to the first node ND1, and the output node NO may correspond to the second node ND2.

[0120] Oscillator 405 can generate a reference clock signal CLK and provide the reference clock signal CLK to idle time generator 410. The reference clock signal CLK can be referred to as the default clock signal.

[0121] The idle time generator 410 can generate a first output signal OUT1 and a second output signal OUT2 with non-overlapping activation intervals based on the reference clock signal CLK, and can provide the first output signal OUT1 and the second output signal OUT2 to the gate drive circuit 420.

[0122] The operating voltage generator 407 can compare the levels of the input voltage VIN and the output voltage VOUT, and can provide the idle time generator 410 with the voltage level of the larger of the input voltage VIN and the output voltage VOUT as the operating voltage. The idle time generator 410 can operate based on the operating voltage from the operating voltage generator 407, and can generate a first output signal OUT1 and a second output signal OUT2.

[0123] The gate driving circuit 420 can generate first clock signals to fourth clock signals CLK0, CLK1, CLK2, and CLK3 based on the first output signal OUT1, the second output signal OUT2, the first sub-power-down signal PDH, and the second sub-power-down signal PDL. At least some of the first clock signals to fourth clock signals CLK0, CLK1, CLK2, and CLK3 have activation intervals that do not overlap with each other. The gate driving circuit 420 can provide the first clock signals to fourth clock signals CLK0, CLK1, CLK2, and CLK3 to the switching circuit 450.

[0124] The gate drive circuit 420 may include a first gate driver HSPD 430, a second gate driver HSND 440, a third gate driver LSPD 430a, and a fourth gate driver LSND440a connected between the input voltage VIN and the ground voltage VSS.

[0125] The first gate driver 430 can be selectively enabled in response to the first sub-power-down signal PDH, and can delay the first output signal OUT1 to output the first clock signal CLK0. The second gate driver 440 can be selectively enabled in response to the first sub-power-down signal PDH, and can delay the second output signal OUT2 to output the second clock signal CLK1.

[0126] The third gate driver 430a can be selectively enabled in response to the second sub-power-down signal PDL, and can delay the first output signal OUT1 to output the third clock signal CLK2. The fourth gate driver 440a can be selectively enabled in response to the second sub-power-down signal PDL, and can delay the second output signal OUT2 to output the fourth clock signal CLK3.

[0127] The switching circuit 450 may include a first p-channel metal-oxide-semiconductor (PMOS) transistor MP0, a first n-channel metal-oxide-semiconductor (NMOS) transistor MN0, a second PMOS transistor MP1, and a second NMOS transistor MN1 connected in series between the input node NI and the ground voltage VSS. Each of the first PMOS transistor MP0, the first NMOS transistor MN0, the second PMOS transistor MP1, and the second NMOS transistor MN1 can be switched in response to a corresponding clock signal among the first clock signal to the fourth clock signal CLK0, CLK1, CLK2, and CLK3. The first PMOS transistor MP0, the first NMOS transistor MN0, the second PMOS transistor MP1, and the second NMOS transistor MN1 can respectively indicate the first switching element, the second switching element, the third switching element, and the fourth switching element. During boost operation, the switching circuit 450 can store the output voltage VOUT applied to the output node NO in a storage capacitor CF coupled between the first node N21 and the second node N22.

[0128] The first PMOS transistor MP0 has a source coupled to the input node N1, a gate receiving the first clock signal CLK0, and a drain coupled to the first node N21. The first NMOS transistor MN0 has a drain coupled to the first node N21, a gate receiving the second clock signal CLK1, and a source coupled to the output node NO. The second PMOS transistor MP1 has a source coupled to the output node NO, a gate receiving the third clock signal CLK2, and a drain coupled to the second node N22. The second NMOS transistor MN1 has a drain coupled to the second node N22, a gate receiving the fourth clock signal CLK3, and a source coupled to ground voltage VSS.

[0129] In this embodiment, the channel width to channel length ratio of each of the first PMOS transistor MP0 and the second PMOS transistor MP1 is M, where M is an integer greater than one. The channel width to channel length ratio of each of the first NMOS transistor MN0 and the second NMOS transistor MN1 is N, where N is an integer greater than one.

[0130] The startup circuit 455 may include a third PMOS transistor MP2 and a fourth PMOS transistor MP3 connected in series between the input node NI and the output node NO. The third PMOS transistor MP2 and the fourth PMOS transistor MP3 can be switched in response to a first delayed clock signal CLK0F and a second delayed clock signal CLK1F with non-overlapping activation intervals, and can provide the output voltage VOUT stored in the storage capacitor CF to the input node NI during boost operation. The third PMOS transistor MP2 may be referred to as the first startup transistor, and the fourth PMOS transistor MP3 may be referred to as the second startup transistor.

[0131] The third PMOS transistor MP2 has a source coupled to the input node N1, a gate that receives the first delayed clock signal CLK0F, and a drain coupled to the first node N21, and is connected in parallel with the first PMOS transistor MP0. The fourth PMOS transistor MP3 has a source coupled to the first node N21, a gate that receives the second delayed clock signal CLK1F, and a drain coupled to the output node NO.

[0132] In this embodiment, the channel width to channel length ratio of the third PMOS transistor MP2 is M / K, where K is an integer greater than nine. The channel width to channel length ratio of the fourth PMOS transistor MP3 is N / K. The channel width to channel length ratio of the third PMOS transistor MP2 is 1 / K of the channel width to channel length ratio of the first PMOS transistor MP0, and the channel width to channel length ratio of the fourth PMOS transistor MP3 is 1 / K of the channel width to channel length ratio of the first NMOS transistor MN0. Therefore, the switching timings of the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are faster than the switching timings of the first PMOS transistor MP0, the first NMOS transistor MN0, the second PMOS transistor MP1, and the second NMOS transistor MN1.

[0133] The delayed clock generation circuit 460 can be connected between the input voltage VIN and the ground voltage VSS, and can include a first delayed clock generator (FDG1) 470 and a second delayed clock generator (FDG2) 480.

[0134] The first delayed clock generator is configured to be selectively enabled in response to a second power-down signal and is configured to delay a first output signal to generate a first delayed clock signal. The first delayed clock generator 470 includes a plurality of first delayed units connected in cascades. Each of the first delayed units is connected between an input voltage VIN and a ground voltage VSS.

[0135] The first delayed clock generator 470 can be selectively enabled in response to the second power-down signal PDL, and can delay the first output signal OUT1 to generate a first delayed clock signal CLK0F. The second delayed clock generator 480 can be selectively enabled in response to the second power-down signal PDL, and can delay the second output signal OUT2 to generate a second delayed clock signal CLK1F.

[0136] In an embodiment, the first delayed clock signal CLK0F may have a first falling delay relative to the second clock signal CLK1, and the second delayed clock signal CLK1F may have a second falling delay relative to the first clock signal CLK0.

[0137] Figure 15 This illustrates an example embodiment. Figure 14 A circuit diagram of an example of an idle time generator in a bidirectional voltage converter.

[0138] Reference Figure 15 The idle time generator 410 may include an inverter 411, NAND gates 412 and 413, and an inverter 414.

[0139] Inverter 411 inverts the reference clock signal CLK, and NAND gate 412 performs a NAND operation on the output of inverter 411 and the output of NAND gate 413 to provide the first output signal OUT1.

[0140] NAND gate 413 performs a NAND operation on the reference clock signal CLK and the output of NAND gate 412. Inverter 414 inverts the output of NAND gate 413 to provide a second output signal OUT2. Inverters 411, NAND gates 412 and 413, and inverter 414 can operate based on a voltage provided from operating voltage generator 407.

[0141] Figure 16 This illustrates an example embodiment. Figure 14 A circuit diagram of an example of a gate drive circuit.

[0142] Reference Figure 16The first gate driver 430 may include a plurality of first delay units 431-435 connected in tiers. Each of the first delay units 431-435 may be connected between the input voltage VIN and a half-input voltage VIN / 2 corresponding to half of the input voltage VIN. Each of the first delay units 431-435 may include an inverter. The first delay units 431-435 may delay a first output signal OUT1 to output a first clock signal CLK0. Therefore, the first clock signal CLK0 may oscillate between the input voltage VIN and the half-input voltage VIN / 2.

[0143] The second gate driver 440 may include a plurality of second delay units 441-445 connected in tiers, and each of the second delay units 441-445 may be connected between the input voltage VIN and half of the input voltage VIN / 2. Each of the second delay units 441-445 may include an inverter, and the second delay units 441-445 may delay the second output signal OUT2 to output a second clock signal CLK1. Therefore, the second clock signal CLK1 can swing between the input voltage VIN and half of the input voltage VIN / 2.

[0144] The third gate driver 430a may include a plurality of third delay units 431a to 435a connected in tiers, and each of the third delay units 431a to 435a may be connected between the half-input voltage VIN / 2 and the ground voltage VSS. Each of the third delay units 431a to 435a may include an inverter, and the third delay units 431a to 435a may delay the first output signal OUT1 to output a third clock signal CLK2. Therefore, the third clock signal CLK2 may oscillate between the half-input voltage VIN / 2 and the ground voltage VSS.

[0145] The fourth gate driver 440a may include a plurality of fourth delay units 441a to 445a connected in tiers. Each of the fourth delay units 441a to 445a may be connected between the half-input voltage VIN / 2 and the ground voltage VSS. Each of the fourth delay units 441a to 445a may include an inverter. The fourth delay units 441a to 445a may delay the second output signal OUT2 to output a fourth clock signal CLK3. Therefore, the fourth clock signal CLK3 can swing between the half-input voltage VIN / 2 and the ground voltage VSS.

[0146] Figure 17 This is an illustration based on an example embodiment. Figure 14 A circuit diagram of an example clock generation circuit with a delay in the circuit.

[0147] Reference Figure 14The first-delay clock generator 470 may include a plurality of first-delay units 471-475 connected in tiers. Each of the first-delay units 471-475 may be connected between the input voltage VIN and the ground voltage VSS. Each of the first-delay units 471-475 may include an inverter. The first-delay units 471-475 may delay the first output signal OUT1 to output a first-delayed clock signal CLK0F. Therefore, the first-delayed clock signal CLK0F can oscillate between the input voltage VIN and the ground voltage VSS.

[0148] The second-delay clock generator 480 may include a plurality of second-delay units 481-485 connected in tiers. Each of the second-delay units 481-485 may be connected between the input voltage VIN and the ground voltage VSS. Each of the second-delay units 481-485 may include an inverter. The second-delay units 481-485 may delay the second output signal OUT2 to output a second-delayed clock signal CLK1F. Therefore, the second-delayed clock signal CLK1F can oscillate between the input voltage VIN and the ground voltage VSS.

[0149] Figure 18 It is shown Figure 14 Timing diagrams of various signals in a bidirectional voltage converter.

[0150] exist Figure 18 In this context, it is assumed that the first output signal OUT1 and the first delayed clock signal CLK0F are activated with a low level corresponding to the ground voltage VSS, the first clock signal CLK0 is activated with a low level corresponding to the half-input voltage VIN / 2, and the second output signal OUT2 and the second clock signal CLK1 are activated with a high level corresponding to the input voltage VIN.

[0151] Reference Figure 18 The low-level VSS interval of the first output signal OUT1 and the high-level VIN interval of the second output signal OUT2 do not overlap. The first output signal OUT1 and the second output signal OUT2 have non-overlapping activation intervals. Additionally, the low-level VIN / 2 interval of the first clock signal CLK0 and the high-level VIN interval of the second clock signal CLK1 do not overlap. The first clock signal CLK0 and the second clock signal CLK1 have non-overlapping activation intervals.

[0152] The first delayed clock signal CLK0F, indicated by reference numeral 513, has a falling delay relative to the falling edge of the second clock signal CLK1, as indicated by reference numeral 514. Compared to the first delayed clock signal CLK0F, the first delayed clock signal CLK0F', indicated by reference numeral 511, does not have a falling delay relative to the falling edge of the second clock signal CLK1, as indicated by reference numeral 512. Therefore, the first delayed clock signal CLK0F' and the second clock signal CLK1 can have overlapping activation intervals. Conversely, the first delayed clock signal CLK0F and the second clock signal CLK1 can have non-overlapping activation intervals.

[0153] Figure 19 and Figure 20 Show each Figure 14 The operation of the switching circuit and the start-up circuit in the bidirectional voltage converter during the first and second stages of the step-down operation.

[0154] Figure 21 It shows Figure 14 Various signals from a bidirectional voltage converter under step-down operation.

[0155] Reference Figure 19 and Figure 21 In the first stage PH11 of the step-down operation in which the input voltage VIN is applied to the input node NI, the fourth PMOS transistor MP3 is turned off in response to the second delayed clock signal CLK1F, the first NMOS transistor MN0 is turned off in response to the second clock signal CLK1, and the second NMOS transistor MN1 is turned off in response to the fourth clock signal CLK3.

[0156] The third PMOS transistor MP2 turns on in response to the first delayed clock signal CLK0F and connects the input node NI to the first terminal of the storage capacitor CF. The first PMOS transistor MP0 turns on in response to the first clock signal CLK0 and connects the input voltage VIN to the first terminal of the storage capacitor CF. The second PMOS transistor MP1 turns on in response to the third clock signal CLK2 and connects the second terminal of the storage capacitor CF to the output node NO. The output node NO is coupled to the output capacitor COUT. Therefore, the charge based on the input voltage VIN is stored in the storage capacitor CF through paths 611 and 612.

[0157] Reference Figure 20 and Figure 21In the second stage PH12 of the step-down operation, the third PMOS transistor MP2 is turned off in response to the first delayed clock signal CLK0F, the first PMOS transistor MP0 is turned off in response to the first clock signal CLK0, and the second PMOS transistor MP1 is turned off in response to the third clock signal CLK2.

[0158] The fourth PMOS transistor MP3 turns on in response to the second delayed clock signal CLK1F and connects the first terminal of the storage capacitor CF to the output node NO. The first NMOS transistor MN0 turns on in response to the second clock signal CLK1 and connects the first terminal of the storage capacitor CF to the output node NO. The second NMOS transistor MN1 turns on in response to the fourth clock signal CLK3 and connects the ground voltage VSS to the second terminal of the storage capacitor CF. Therefore, the charge stored in the storage capacitor CF is discharged, and the discharged charge is provided to the output node NO as the output voltage VOUT through paths 621 and 622.

[0159] The first stage PH11 and the second stage PH12 of the step-down operation can be repeated alternately. Therefore, the output voltage VOUT increases at the output node NO, and the output voltage VOUT can reach the level of the input voltage VIN.

[0160] Reference Figure 31 The boost operation in which the voltage (contact voltage VDD5PX) is applied to the output node NO may include a first interval INT11, a second interval INT12, and a third interval INT13 determined based on the level of the input voltage VIN boosted by the boost operation.

[0161] During the first interval INT11, the level of the input voltage VIN is lower than the level of the output voltage VOUT, the first sub-power-down signal PDH is high, and the second sub-power-down signal PDL is low.

[0162] During the second interval INT12, the level of the input voltage VIN is greater than the level of the output voltage VOUT, but less than twice the level of the output voltage 2*VOUT. The first sub-power-down signal PDH is at a high level, and the second sub-power-down signal PDL is at a low level.

[0163] During the third interval INT13, the level of the input voltage VIN reaches twice the level of the output voltage 2*VOUT, the first sub-power-down signal PDH is at a low level, and the second sub-power-down signal PDL is at a low level.

[0164] Furthermore, since the first sub-power-down signal PDH is high during the first interval INT11 and the second interval INT12, the first gate driver 430 and the second gate driver 440 are disabled. Therefore, the first clock signal CLK0 and the second clock signal CLK1 are in a floating state, the first PMOS transistor MP0 and the first NMOS transistor MN0 are turned off, and the first PMOS transistor MP0 and the first NMOS transistor MN0 do not perform switching operations.

[0165] Figure 22 and Figure 23 Show each Figure 14 The operation of the switching circuit and the startup circuit in the bidirectional voltage converter during the first and second phases of the first interval of the boost operation.

[0166] Figure 24 The output and input voltages are shown during the first interval of the boost operation of the bidirectional voltage converter.

[0167] Reference Figure 22 During the first phase of the first interval of the boost operation in which voltage VS is applied to output node NO, the third PMOS transistor MP2 is turned off in response to a first delayed clock signal CLK0F, and the second PMOS transistor MP1 is turned off in response to a third clock signal CLK2. The fourth PMOS transistor MP3 is turned on in response to a second delayed clock signal CLK1F and connects the first terminal of the storage capacitor CF to output node NO. The second NMOS transistor MN1 is turned on in response to a fourth clock signal CLK3 and connects the ground voltage VSS to the second terminal of the storage capacitor CF. Therefore, the charge based on the voltage VS at output node NO is stored in the storage capacitor CF through path 631.

[0168] Reference Figure 23 During the second phase of the first interval, the fourth PMOS transistor MP3 is turned off in response to the second delayed clock signal CLK1F, and the second NMOS transistor MN1 is turned off in response to the fourth clock signal CLK3. The third PMOS transistor MP2 is turned on in response to the first delayed clock signal CLK0F and connects the input node NI to the first terminal of the storage capacitor CF. The second PMOS transistor MP1 is turned on in response to the third clock signal CLK2 and connects the output node NO to the second terminal of the storage capacitor CF. Therefore, the charge based on the voltage VS at the output node NO is stored in the storage capacitor CF through path 642, the stored charge is discharged, and the discharged charge is stored in the input capacitor CIN through path 641. The input voltage VIN is provided to the input node NI.

[0169] The first and second stages in the first interval INT11 can be repeated alternately. Therefore, the level of the input voltage VIN gradually increases from the ground voltage VSS, as... Figure 24 As shown in the image.

[0170] Figure 25 and Figure 26 They are shown respectively Figure 14 The operation of the switching circuit and the startup circuit in the bidirectional voltage converter during the first and second phases of the second interval of the boost operation.

[0171] Figure 27 The output and input voltages are shown during the second interval of the boost operation of the bidirectional voltage converter.

[0172] Reference Figure 25 During the first phase of the second interval of the boost operation, the third PMOS transistor MP2 is turned off in response to the first delayed clock signal CLK0F, and the second PMOS transistor MP1 is turned off in response to the third clock signal CLK2. The fourth PMOS transistor MP3 is turned on in response to the second delayed clock signal CLK1F and connects the first terminal of the storage capacitor CF to the output node NO. The second NMOS transistor MN1 is turned on in response to the fourth clock signal CLK3 and connects the ground voltage VSS to the second terminal of the storage capacitor CF. Therefore, the charge based on the voltage VS at the output node NO is stored in the storage capacitor CF through path 651.

[0173] Reference Figure 26 During the second phase of the second interval, the fourth PMOS transistor MP3 turns off in response to the second delayed clock signal CLK1F, and the second NMOS transistor MN1 turns off in response to the fourth clock signal CLK3. The third PMOS transistor MP2 turns on in response to the first delayed clock signal CLK0F and connects the input node NI to the first terminal of the storage capacitor CF. The second PMOS transistor MP1 turns on in response to the third clock signal CLK2 and connects the output node NO to the second terminal of the storage capacitor CF. Therefore, the charge based on the voltage VS at the output node NO is stored in the storage capacitor CF through path 662, the stored charge is discharged, the discharged charge is stored in the input capacitor CIN through path 661, and the input voltage VIN is provided to the input node NI.

[0174] The first and second stages in the second interval INT12 can be repeated alternately. Therefore, the level of the input voltage VIN gradually increases from the level of the output voltage VOUT, as... Figure 27 As shown in the image.

[0175] Figure 28and Figure 29 They are shown respectively Figure 14 The operation of the switching circuit and the start-up circuit in the bidirectional voltage converter during the first and second phases of the third interval of the boost operation.

[0176] Figure 30 The output and input voltages are shown during the third interval of the boost operation of the bidirectional voltage converter.

[0177] Reference Figure 28 In the first stage of the third interval of the boost operation in which the level of input voltage VIN reaches twice the level 2*VOUT, the third PMOS transistor MP2 is turned off in response to the first delayed clock signal CLK0F, and the second PMOS transistor MP1 is turned off in response to the third clock signal CLK2.

[0178] The fourth PMOS transistor MP3 turns on in response to the second delayed clock signal CLK1F and connects the first terminal of the storage capacitor CF to the output node NO. The second NMOS transistor MN1 turns on in response to the fourth clock signal CLK3 and connects the ground voltage VSS to the second terminal of the storage capacitor CF. Therefore, the charge based on the voltage VS at the output node NO is stored in the storage capacitor CF through paths 671 and 672.

[0179] Reference Figure 29 During the second phase of the third interval, the fourth PMOS transistor MP3 turns off in response to the second delayed clock signal CLK1F, and the second NMOS transistor MN1 turns off in response to the fourth clock signal CLK3. The third PMOS transistor MP2 turns on in response to the first delayed clock signal CLK0F and connects the input node NI to the first terminal of the storage capacitor CF. The second PMOS transistor MP1 turns on in response to the third clock signal CLK2 and connects the output node NO to the second terminal of the storage capacitor CF.

[0180] Therefore, the charge based on the voltage VS at the output node NO is stored in the storage capacitor CF through path 683, the stored charge is discharged, the discharged charge is stored in the input capacitor CIN through paths 681 and 682, and the input voltage VIN is provided to the input node NI.

[0181] The first and second stages in the third interval INT13 can be repeated alternately. Therefore, the level of the input voltage VIN is maintained at twice the level 2*VOUT, as shown below. Figure 30 As shown in the image.

[0182] Figure 31 It is shown Figure 14Timing diagrams of various signals in the boost operation of a bidirectional voltage converter.

[0183] Reference Figure 31 Because the first sub-power-down signal PDH is high during the first interval INT11 and the second interval INT12 of the boost operation, the first clock signal CLK0 and the second clock signal CLK1 are in a floating state. During the third interval INT13 of the boost operation, the first sub-power-down signal PDH is low, and the first clock signal CLK0 swings between the input voltage VIN and half the input voltage VIN / 2, while the second clock signal CLK1 swings between the input voltage VIN and half the input voltage VIN / 2.

[0184] Each of the third clock signal CLK2 and the fourth clock signal CLK3 oscillates between the half-input voltage VIN / 2 and the ground voltage VSS during each of the first interval INT11, the second interval INT12, and the third interval INT13. Additionally, the first delayed clock signal CLK0F and the second delayed clock signal CLK1F have non-overlapping activation intervals (low levels).

[0185] Figure 32 It shows that based on Figure 14 A table showing the logic levels of the first and second sub-power-down signals of the input and output voltages in a bidirectional voltage converter.

[0186] Reference Figure 32 The interval where the level of the input voltage VIN is less than the level of the output voltage VOUT corresponds to the first interval INT11, and during the first interval INT11, the first sub-power-down signal PDH has a high level and the second sub-power-down signal PDL has a low level.

[0187] The interval between the input voltage VIN being greater than the output voltage VOUT and less than twice the output voltage (2*VOUT) corresponds to the second interval INT12. During the second interval INT12, the first sub-power-down signal PDH is at a high level and the second sub-power-down signal PDL is at a low level.

[0188] The interval where the level of the input voltage VIN reaches twice the level of the output voltage 2*VOUT corresponds to the third interval INT13, and during the third interval INT13, the first sub-power-down signal PDH is at a low level and the second sub-power-down signal PDL is at a low level.

[0189] Figure 33 An example embodiment is shown. Figure 2 An example of a fingerprint recognition sensor in a smart card chip.

[0190] Reference Figure 33 The fingerprint sensor 270 may include a lens 271 and an image sensor 272, and the image sensor 272 may include a pixel array 273.

[0191] Lens 271 can focus reflected light from the user's finger 80 onto the pixel array 273 of image sensor 272. Image sensor 272 can generate a fingerprint image signal based on the reflected light and can provide the fingerprint image signal to... Figure 2 The processor is 240.

[0192] Processor 240 can compare the fingerprint image signal with the user's original fingerprint and determine whether the user's input fingerprint is forged based on the comparison result. When processor 240 determines that the user's input fingerprint matches the user's original fingerprint, processor 240 can indicate successful user authentication by controlling LED 295 to emit light while performing user authentication on payment data associated with the payment operation.

[0193] Figure 34 An example of a smart card according to an example embodiment is shown.

[0194] Reference Figure 34 The smart card 50 may include an integrated circuit 85, an antenna 61, a fingerprint sensor 270, and an LED 290 formed in a substrate 101.

[0195] Antenna 61 can be coupled to integrated circuit 85. Integrated circuit 85 may include Figure 2 The components of the smart card chip 100, excluding the fingerprint sensor 270 and the LED 290, Figure 1 The contact terminal 63 can be included in the integrated circuit 85.

[0196] In contactless mode, antenna 61 receives contactless voltage from card reader 20 to provide the contactless voltage to the internal voltage generation circuit in integrated circuit 85. In contact mode, contact terminals in integrated circuit 85 receive contact voltage from card reader 20 to provide the contact voltage to the internal voltage generation circuit in integrated circuit 85.

[0197] The fingerprint sensor 270 can generate a fingerprint image signal based on the user's input fingerprint during payment operations in contactless mode, and can provide the fingerprint image signal to the processor 240. The processor 240 can compare the fingerprint image signal with the user's original fingerprint, and can determine whether the user's input fingerprint is forged based on the comparison result. When the processor 240 determines that the user's input fingerprint matches the user's original fingerprint, the processor 240 can indicate successful user authentication by controlling the LED 295 to emit light while performing user authentication on the payment data associated with the payment operation. When the processor 240 determines that the user's input fingerprint does not match the user's original fingerprint, the processor 240 can indicate the mismatch via the LED 295.

[0198] Figure 35 This is a block diagram illustrating an electronic device according to an example embodiment.

[0199] Reference Figure 35 The electronic device 1000 includes an application processor (AP) 1110, a smart card 1200, a memory device 1120, a user interface 1130, and a power supply 1140. In some embodiments, the electronic device 1000 may be a mobile phone, a smartphone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a laptop computer, etc.

[0200] Application processor 1110 can control the overall operation of electronic device 1000. Application processor 1110 can execute applications such as web browsers, game applications, video players, etc. In some embodiments, application processor 1110 may include single-core or multi-core processors. For example, application processor 1110 may be a multi-core processor, such as a dual-core processor, quad-core processor, hexa-core processor, etc. Application processor 1110 may include internal or external cache memory.

[0201] The memory device 1120 can store data required for the operation of the electronic device 1000. For example, the memory device 1120 can store a boot image for booting the electronic device 1000, output data output to an external device, and input data received from an external device. For example, the memory device 1120 can be an electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), or ferroelectric random access memory (FRAM).

[0202] The smart card 1200 may include a matching circuit 1210 and a smart card chip 1220, the smart card chip 1220 including a connection terminal 1221. The smart card chip 1220 can receive voltage from an external card reader in a contactless manner through the matching circuit 1210 and can exchange data with the external card reader. The smart card chip 1220 can also receive voltage from an external card reader in a contact manner through the connection terminal 1221 and can exchange data with the external card reader. The smart card 1200 may employ... Figure 2 50 smart cards.

[0203] Therefore, the smart card 1200 may include an internal voltage generation circuit, which includes a first contact switch, a second contact switch, a switched capacitor converter, and a bidirectional switched capacitor converter. Even if the contact voltage level varies based on the type of card reader, the internal voltage generation circuit generates a second drive voltage used by the operating logic circuit block and a first drive voltage used by the operating fingerprint sensor. The bidirectional switched capacitor converter does not include a charge pump. The bidirectional switched capacitor converter is connected between the input node and the output node. During boost operation, it stores the second drive voltage applied to the output node in a storage capacitor therein and provides the voltage stored in the storage capacitor to the input node. Therefore, the bidirectional switched capacitor converter can gradually boost the first drive voltage at the input node.

[0204] User interface 1130 may include at least one input device (such as a keyboard or touchscreen) and at least one output device (such as a speaker or display device). Power supply 1140 may supply power voltage to electronic device 1000.

[0205] In some embodiments, the electronic device 1000 may also include an image processor and / or a storage device, such as a memory card, a solid-state drive (SSD), a hard disk drive (HDD), or a CD-ROM.

[0206] In some embodiments, the electronic device 1000 and / or components of the electronic device 1000 may be packaged in various forms, such as stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle package, wafer form factor, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small form factor IC (SOIC), shrink small package (SSOP), thin small form factor package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processing stack package (WSP).

[0207] As is conventional in the art, embodiments can be described and illustrated from the perspective of blocks that perform one or more of the described functions. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and / or digital circuitry (such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, etc.) and may optionally be driven by firmware and / or software. The circuitry may be embodied, for example, in one or more semiconductor chips or on a substrate support such as a printed circuit board. The circuitry constituting a block can be implemented by dedicated hardware, or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware performing some functions of the block and a processor performing other functions of the block. Without departing from the scope of this disclosure, each block of an embodiment may be physically divided into two or more interacting and discrete blocks. Similarly, without departing from the scope of this disclosure, the blocks of an embodiment may be physically combined into more complex blocks. One aspect of an embodiment may be implemented by instructions stored in a non-transitory storage medium and executed by a processor.

[0208] The foregoing is illustrative of this disclosure and should not be construed as limiting it. While some exemplary embodiments have been described, those skilled in the art will readily understand that numerous modifications are possible to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims. It will thus be understood that the foregoing is illustrative of various exemplary embodiments and is not to be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims.

[0209] Translation of attached image:

[0210] Figure 1 :

[0211] 30: Reader chip

[0212] 100: Smart Card Chip

[0213] Figure 2 :

[0214] 210: Rectifier

[0215] 240: Processor

[0216] 250: Memory

[0217] 253: Modulator

[0218] 251: Demodulator

[0219] Figure 4 :

[0220] 310: First SC Converter

[0221] 400: Second SC Converter (Bidirectional)

[0222] 330: Mode Selector

[0223] 350: Control signal generator

[0224] 360: First Contact Switch

[0225] 370: Second contact switch

[0226] Figure 9 :

[0227] 333: Contact Detector

[0228] 335: Pattern Signal Generator

[0229] 337: Class Detector

[0230] 341: Level comparator

[0231] Figure 10 , Figure 11 , Figure 12 , Figure 13 :

[0232] Deactivated: Disabled

[0233] Figure 18 :

[0234] VIN2 should be changed to VIN / 2

[0235] Voltage

[0236] Time: time

[0237] Figure 21 :

[0238] Voltage

[0239] Time: time

[0240] Figure 24 , Figure 27 , Figure 30 :

[0241] Time: time

[0242] Figure 31 :

[0243] Voltage

[0244] Time: time

[0245] Figure 32 :

[0246] State: State

[0247] Steady state: a stable state

[0248] Figure 34 :

[0249] Samsung Card

[0250] Figure 35 :

[0251] 1120: Memory

[0252] 1130: User Interface

[0253] 1140: Power Supply

[0254] 1210: Matching Circuit

[0255] 1220: Smart Card Chip

Claims

1. A bidirectional voltage converter for a smart card, the smart card being configured to perform fingerprint authentication, the bidirectional voltage converter comprising: A gate driving circuit is configured to generate a first clock signal to a fourth clock signal based on a first output signal, a second output signal, a first sub-power-down signal, and a second sub-power-down signal, wherein the first output signal and the second output signal have activation intervals that do not overlap with each other, and at least some of the first clock signal to the fourth clock signal have activation intervals that do not overlap with each other. A switching circuit includes a first to a fourth switching element connected in series between an input node and ground voltage, the first to the fourth switching elements being configured to switch in response to a corresponding clock signal among the first to the fourth clock signals, and being configured to store the output voltage applied to the output node in a storage capacitor coupled between the first node and the second node during boost operation. as well as A startup circuit includes a first startup transistor and a second startup transistor connected in series between the input node and the output node. The first startup transistor and the second startup transistor are configured to switch in response to a first delayed clock signal and a second delayed clock signal to provide an output voltage stored in the storage capacitor to the input node during the boost operation. The first delayed clock signal and the second delayed clock signal have an activation interval that does not overlap with each other.

2. The bidirectional voltage converter according to claim 1, further comprising: An idle time generator is configured to generate a first output signal and a second output signal with non-overlapping activation intervals based on a reference clock signal; as well as A delayed clock signal generation circuit is configured to generate the first delayed clock signal and the second delayed clock signal based on the first output signal, the second output signal and the second sub-power-down signal.

3. The bidirectional voltage converter according to claim 2, wherein: The idle time generator is configured to use the voltage level greater than that of the input voltage and the output voltage as the operating voltage, and The first output signal is activated with a ground voltage level, and the second output signal is activated with a high level of the operating voltage.

4. The bidirectional voltage converter according to claim 2, wherein, The delayed clock signal generation circuit includes: A first-delay clock signal generator, configured to be selectively enabled in response to a second sub-power-down signal, and configured to delay the first output signal to generate a first-delay clock signal, the first-delay clock signal generator comprising a plurality of first-delay units connected in cascades, each of the plurality of first-delay units being connected between an input voltage and the ground voltage; and A second delayed clock signal generator is configured to be selectively enabled in response to the second sub-power-down signal and configured to delay the second output signal to generate a second delayed clock signal. The second delayed clock signal generator includes a plurality of second delay units connected in cascades, and each of the plurality of second delay units is connected between the input voltage and the ground voltage.

5. The bidirectional voltage converter according to claim 4, wherein: The first-delay clock signal generator is configured to generate a first-delay clock signal based on the first output signal, having a first fall-off delay relative to the first clock signal and oscillating between the input voltage and the ground voltage; as well as The second-delayed clock signal generator is configured to generate a second-delayed clock signal based on the second output signal, which has a first fall-off delay relative to the first clock signal and oscillates between the input voltage and the ground voltage.

6. The bidirectional voltage converter according to claim 1, wherein, The gate driving circuit includes: A first gate driver is configured to be selectively enabled in response to a first sub-power-down signal and configured to delay the first output signal to output the first clock signal. The first gate driver includes a plurality of first delay units connected in cascades, and each of the plurality of first delay units is connected between an input voltage and a half-input voltage corresponding to half of the input voltage. A second gate driver is configured to be selectively enabled in response to the first sub-power-down signal and configured to delay the second output signal to output the second clock signal. The second gate driver includes a plurality of second delay units connected in cascades, and each of the plurality of second delay units is connected between the input voltage and the half-input voltage. A third gate driver, configured to be selectively enabled in response to a second sub-power-down signal and configured to delay the first output signal to output the third clock signal, the third gate driver comprising a plurality of third delay units connected in cascades, each of the plurality of third delay units being connected between the half-input voltage and ground; and A fourth gate driver, configured to be selectively enabled in response to the second sub-power-down signal and configured to delay the second output signal to output the fourth clock signal, the fourth gate driver including a plurality of fourth delay units connected in cascades, each of the plurality of fourth delay units being connected between the half-input voltage and the ground voltage.

7. The bidirectional voltage converter according to claim 6, wherein: The first clock signal and the third clock signal have an activation interval that overlaps with each other, and each of the first clock signal and the third clock signal is activated by the half-input voltage; and The second clock signal and the fourth clock signal have an activation interval that overlaps with each other, and the second clock signal is activated by the input voltage and the half-input voltage.

8. The bidirectional voltage converter according to claim 1, wherein: The first switching element includes a first p-channel metal-oxide-semiconductor transistor, the first p-channel metal-oxide-semiconductor transistor having a source coupled to the input node, a gate for receiving the first clock signal, and a drain coupled to the first node; The second switching element includes a first n-channel metal-oxide-semiconductor transistor, the first n-channel metal-oxide-semiconductor transistor having a drain coupled to the first node, a gate for receiving the second clock signal, and a source coupled to the output node; The third switching element includes a second p-channel metal-oxide-semiconductor transistor, the second p-channel metal-oxide-semiconductor transistor having a source coupled to the output node, a gate for receiving the third clock signal, and a drain coupled to the second node; The fourth switching element includes a second n-channel metal-oxide-semiconductor transistor, the second n-channel metal-oxide-semiconductor transistor having a drain coupled to the second node, a gate for receiving the fourth clock signal, and a source coupled to the ground voltage; The channel width to channel length ratio of each of the first p-channel metal-oxide-semiconductor transistor and the second p-channel metal-oxide-semiconductor transistor is M, where M is an integer greater than one; and The channel width to channel length ratio of each of the first n-channel metal-oxide-semiconductor transistor and the second n-channel metal-oxide-semiconductor transistor is N, and N is an integer greater than one.

9. The bidirectional voltage converter according to claim 8, wherein: The first startup transistor includes a third p-channel metal-oxide-semiconductor transistor connected in parallel with the first p-channel metal-oxide-semiconductor transistor. The third p-channel metal-oxide-semiconductor transistor has a source coupled to the input node, a gate for receiving the first delayed clock signal, and a drain coupled to the first node. The second startup transistor includes a fourth p-channel metal-oxide-semiconductor transistor, the fourth p-channel metal-oxide-semiconductor transistor having a source coupled to the first node, a gate for receiving the second delayed clock signal, and a drain coupled to the output node; The channel width to channel length ratio of the third p-channel metal-oxide-semiconductor transistor is M / K, where K is an integer greater than nine; and The ratio of the channel width to the channel length of the fourth p-channel metal-oxide-semiconductor transistor is N / K.

10. The bidirectional voltage converter according to claim 9, wherein, In the first phase of the step-down operation of applying the input voltage to the input node, the third p-channel metal-oxide-semiconductor transistor turns on in response to the first delayed clock signal, and the first p-channel metal-oxide-semiconductor transistor turns on in response to the first clock signal, such that charge based on the input voltage is stored in the storage capacitor.

11. The bidirectional voltage converter according to claim 10, wherein, In the second stage of the gradual pressure reduction operation: The second n-channel metal-oxide-semiconductor transistor is turned on in response to the fourth clock signal to connect the second terminal of the storage capacitor to the ground voltage. The first n-channel metal-oxide-semiconductor transistor turns on in response to the second clock signal, and the fourth p-channel metal-oxide-semiconductor transistor turns on in response to the second delayed clock signal, causing the charge stored in the storage capacitor to be discharged, thereby providing the output voltage to the output node. During the first and second phases, the first sub-power-down signal has a low level, and the second sub-power-down signal has a low level.

12. The bidirectional voltage converter according to claim 10, wherein: The boost operation includes a first interval, a second interval, and a third interval; During the first interval, the level of the input voltage is lower than the level of the output voltage; During the second interval, the level of the input voltage is equal to or greater than the level of the output voltage, and less than twice the level of the output voltage; and During the third interval, the level of the input voltage reaches twice the level of the output voltage.

13. The bidirectional voltage converter according to claim 12, wherein: In the first phase of the first interval, the fourth p-channel metal-oxide-semiconductor transistor is turned on in response to the second delayed clock signal to charge the storage capacitor based on the output voltage at the output node; In the second phase of the first interval, the second p-channel metal-oxide-semiconductor transistor turns on in response to the third clock signal to charge the storage capacitor with charge based on the output voltage, and the third p-channel metal-oxide-semiconductor transistor turns on in response to the first delayed clock signal and discharges the charge stored in the storage capacitor to provide the input voltage to the input node; and During the first and second phases of the first interval, the first sub-power-down signal has a high level and the second sub-power-down signal has a low level.

14. The bidirectional voltage converter according to claim 12, wherein: In the first phase of the second interval, the fourth p-channel metal-oxide-semiconductor transistor is turned on in response to the second delayed clock signal to charge the storage capacitor with charge based on the output voltage at the output node; In the second phase of the second interval, the second p-channel metal-oxide-semiconductor transistor turns on in response to the third clock signal to charge the storage capacitor with charge based on the output voltage, and the third p-channel metal-oxide-semiconductor transistor turns on in response to the first delayed clock signal and discharges the charge stored in the storage capacitor to provide the input voltage to the input node; and During the first and second phases of the second interval, the first sub-power-down signal has a high level and the second sub-power-down signal has a low level.

15. The bidirectional voltage converter according to claim 12, wherein: In the first phase of the third interval, the fourth p-channel metal-oxide-semiconductor transistor turns on in response to the second delayed clock signal, and the first n-channel metal-oxide-semiconductor transistor turns on in response to the second clock signal to store charge based on the output voltage at the output node in the storage capacitor. In the second phase of the third interval, the second p-channel metal-oxide-semiconductor transistor turns on in response to the third clock signal to charge the storage capacitor with charge based on the output voltage, the third p-channel metal-oxide-semiconductor transistor turns on in response to the first delayed clock signal, the first p-channel metal-oxide-semiconductor transistor turns on in response to the first clock signal, and the third p-channel metal-oxide-semiconductor transistor and the first p-channel metal-oxide-semiconductor transistor discharge the charge stored in the storage capacitor to provide the input voltage to the input node; and During the first and second phases of the third interval, the first sub-power-down signal has a low level, and the second sub-power-down signal has a low level.

16. A smart card configured to perform fingerprint authentication, the smart card comprising: A matching circuit is configured to receive voltage from an external card reader without contact and to provide the received voltage as a contactless voltage. as well as The smart card chip is coupled to the matching circuit via a first power terminal and a second power terminal, wherein: The smart card chip includes: A connection terminal is configured to contact the external card reader to receive voltage, thereby providing a contact voltage; An internal voltage generation circuit is configured to generate a first driving voltage and a second driving voltage based on the contactless voltage in a contactless mode, and is configured to generate the first driving voltage and the second driving voltage based on the contact voltage according to the category of the level of the contact voltage in a contact mode. A fingerprint recognition sensor, which operates based on the first driving voltage, is configured to generate a fingerprint image signal based on an input fingerprint; and A processor, which operates based on the second driving voltage, is configured to perform fingerprint authentication based on the fingerprint image signal, and The internal voltage generation circuit includes a bidirectional voltage converter connected between the input node and the output node, and is configured to: in boost operation, gradually boost the first drive voltage by storing a second drive voltage applied to the output node in a storage capacitor therein, and by providing the second drive voltage stored in the storage capacitor to the input node. The bidirectional voltage converter includes: A startup circuit includes a first startup transistor and a second startup transistor connected in series between the input node and the output node. The first startup transistor and the second startup transistor are configured to switch in response to a first delayed clock signal and a second delayed clock signal during the boost operation to provide a second drive voltage stored in the storage capacitor to the input node. The first delayed clock signal and the second delayed clock signal have an activation interval that does not overlap with each other.

17. The smart card according to claim 16, wherein, The bidirectional voltage converter also includes: A gate driving circuit configured to generate a first clock signal to a fourth clock signal based on a first output signal, a second output signal, a first sub-power-down signal, and a second sub-power-down signal, wherein the first clock signal and the second clock signal have non-overlapping activation intervals, and at least some of the first clock signal to the fourth clock signal have non-overlapping activation intervals; and A switching circuit includes a first to a fourth switching element connected in series between the input node and ground voltage. The first to fourth switching elements are configured to switch in response to a corresponding clock signal among the first to fourth clock signals, and are configured to store a second drive voltage applied to the output node in a storage capacitor coupled between the first and second nodes during the boost operation.

18. The smart card according to claim 17, wherein: The internal voltage generation circuit also includes: A mode selector configured to output a first mode signal and a second mode signal, the first mode signal specifying one of a contact mode and a contactless mode, and the second mode signal specifying one of a sub-mode of the contact mode; and A control signal generator is configured to generate a first power-down signal and a second power-down signal based on the first mode signal and the second mode signal, and The second power-down signal includes the first sub-power-down signal and the second sub-power-down signal.

19. The smart card according to claim 18, wherein, The bidirectional voltage converter also includes: An idle time generator is configured to generate a first output signal and a second output signal with non-overlapping activation intervals based on a reference clock signal; and A delayed clock signal generator is configured to generate a first delayed clock signal and a second delayed clock signal based on a first output signal, a second output signal, and a second power-down signal.

20. A bidirectional voltage converter for a smart card, the smart card being configured to perform fingerprint authentication, the bidirectional voltage converter comprising: An idle time generator is configured to generate a first output signal and a second output signal with non-overlapping activation intervals based on a reference clock signal. A gate driving circuit is configured to generate a first clock signal to a fourth clock signal based on the first output signal, the second output signal, the first sub-power-down signal, and the second sub-power-down signal, wherein at least some of the first clock signal to the fourth clock signal have activation intervals that do not overlap with each other. A switching circuit includes a first to a fourth switching element connected in series between an input node and ground voltage. The first to the fourth switching elements are configured to switch in response to a corresponding clock signal among the first to the fourth clock signals, and are configured to store the output voltage applied to the output node in a storage capacitor coupled between the first node and the second node during boost operation. A startup circuit includes a first startup transistor and a second startup transistor connected in series between the input node and the output node. The first startup transistor and the second startup transistor are configured to switch in response to a first delayed clock signal and a second delayed clock signal during the boost operation to provide an output voltage stored in the storage capacitor to the input node. The first delayed clock signal and the second delayed clock signal have an activation interval that does not overlap with each other. as well as A delayed clock signal generation circuit is configured to generate the first delayed clock signal and the second delayed clock signal based on the first output signal, the second output signal and the second sub-power-down signal.

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