Bus encryption for non-volatile memory

Abstract

The present disclosure relates to apparatuses and methods for memory management. The present disclosure further relates to an interface protocol for a flash memory device including at least a memory array and a memory controller coupled to the memory array. A host device is coupled to the memory device through a communication channel, and a hardware and / or software complete encryption-decryption scheme is employed in the communication channel for data, addresses, and commands exchanged between the host device and the memory array.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically, to apparatus and methods for memory management. This disclosure further relates to interface protocols for flash memory devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM), among others.

[0003] Non-volatile memory provides persistent data by retaining the stored data when no power is supplied, and can include NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), self-selected chalcogenide-based memory, resistive random access memory (RRAM), 3D XPoint memory (3DXP), and magnetoresistive random access memory (MRAM), etc.

[0004] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications and systems. Non-volatile memory can be used in, for example, personal computers, portable memory sticks, digital cameras, cellular phones, portable music players such as MP3 players and video players, and other electronic devices. Memory cells can be arranged in arrays, wherein the arrays are used in the memory device.

[0005] Data storage has always been related to system performance, but it has also become a key component of system security.

[0006] Most current mobile NAND flash memory implementations are based on UFS, standardized by the JEDEC group. The UFS protocol provides two security primitives: data encryption with AES-XTS and Replay Protected Memory Block (RPMB) functionality, and enforces SHA-256 HMAC authentication for commands. However, these cryptographic mechanisms lack driver authentication and access pattern obfuscation on one end. Furthermore, they are not designed to fully utilize emerging non-volatile memory (NVM) features such as small page sizes and in-situ updates.

[0007] A new interface architecture is needed that can be easily integrated into the UFS stack and improve performance without increasing write amplification. Attached Figure Description

[0008] Figure 1A A schematic diagram illustrating a comparison between the OSI / RM layer and UniPro layer specifications of the UFS interface protocol used in the memory device of this disclosure;

[0009] Figure 1 A block diagram illustrating a device in the form of a computing system including a memory device according to several embodiments of the present disclosure;

[0010] Figure 2 A schematic diagram illustrating the encryption and decryption scheme according to this disclosure;

[0011] Figure 3 A schematic diagram illustrating a block diagram of a host device and an associated memory device for exchanging data according to several embodiments of the present disclosure;

[0012] Figure 4 This is another schematic diagram illustrating a block diagram of a host device and an associated memory device for exchanging data according to several embodiments of the present disclosure;

[0013] Figure 5 A schematic diagram illustrating the data scrambling technique used within the UniPro layer protocol of the device disclosed herein;

[0014] Figure 6 A schematic block diagram illustrating the stages of the method according to this disclosure;

[0015] Figure 7 This diagram illustrates another schematic block diagram of some other stages of the method according to this disclosure. Detailed Implementation

[0016] As is known in this particular field of technology, Universal Flash Memory (UFS) is designed for high-performance interfaces in electronic applications that require minimal power consumption, including mobile systems such as smartphones and tablets, as well as automotive applications. Its high-speed serial interface and optimized protocols enable significant improvements in throughput and system performance.

[0017] More precisely, UFS is a flash storage specification for digital cameras, mobile phones, and consumer electronics. It aims to bring higher data transfer speeds and enhanced reliability to flash memory storage, while reducing market confusion and eliminating the need for different adapters for different types of memory cards.

[0018] This standard flash memory specification is supported by leading firms in the consumer electronics industry. Furthermore, UFS is positioned as an alternative to eMMC (embedded multimedia card) and SD cards.

[0019] The electrical interface used for UFS employs a high-speed serial interface and implements a full-duplex low-voltage differential signaling (LVDS) serial interface. The LVDS interface is a technical standard that specifies the electrical characteristics of a differential serial communication protocol, which scales to higher bandwidths better than the 8-way parallel interface of eMMC.

[0020] The UFS standard is developed by the JEDEC Solid State Technology Association, which periodically updates the standard, and is available for purchase. Even the Linux kernel supports UFS.

[0021] This UFS protocol is popular in the mobile market because users require faster response times and use high-bandwidth applications such as video games. In its latest version (3.0), UFS provides two security primitives: data encryption with AES-XTS and RPMB functionality, and enforces SHA-256 HMAC authentication.

[0022] Figure 1A This diagram illustrates a comparison between stack 10 of the OSI / RM layers and stack 20 of the UniPro layer specification for the UFS interface protocol. The protocol stacks are considered as a processing pipeline, where any layer in the stack provides services dependent on the layers below it.

[0023] Figure 1A The Open Systems Interconnection (OSI) model shown in the left column is a conceptual model that characterizes and standardizes the communication functions of telecommunications or computing systems without considering their underlying internal structure and technology. Its goal is the interoperability of different communication systems with standard protocols. The model divides communication systems into abstract layers. The original version of the model defined seven layers.

[0024] Communication between higher layers tends to be at a high level of abstraction, while communication between lower layers tends to be at a low level of abstraction.

[0025] The two protocols shown can support communication to and from devices such as cameras or display modules, high-speed modems, coprocessors, etc., and can be implemented entirely in hardware or as software or any other combination of hardware and software running on a general-purpose processor.

[0026] Each layer in the right stack 20 of the UniPro protocol provides substantially the same functionality as the corresponding layer in the left stack 10 of the OSI / RM protocol.

[0027] Each layer is represented by a corresponding label and reference letters from L1 to L7. The interfaces between protocol layers are defined at an abstraction level called Service Access Point (SAP).

[0028] The first three media layers of stack 10, L1, L2, and L3, are: Physical Layer 11, Data Link Layer 12, and Network Layer 13. The remaining layers are host layers and are defined as: Transport Layer 14, Session Layer 15, Presentation Layer 16, and Application Layer 17. The last three layers, 15 through 17, are dedicated to data. In the right stack 20, these last three layers are represented by a single dedicated protocol LA block 40.

[0029] It should be noted that the physical layer L1 of the stacked 10OSI / RM has been split into two sub-layers in the UniPro specification: the physical adapter layer L1.5 and the lower physical sub-layer L1 that supports the specification as M-PHY.

[0030] Block 30, designated as the Device Management Entity (DME), is not shown in the OSI / RM protocol stack, but acts as the control plane to initialize and control the layers involved in actual data delivery rather than data communication.

[0031] While these cryptographic mechanisms can be used in security applications, they have limitations because they only protect data and expose information transmitted over communication channels to potential attackers. New, emerging non-volatile memories (NVMs) with small page sizes, in-situ updates, and other features are under development.

[0032] In all applications involving non-volatile memory (NVM), it is highly desirable to ensure the confidentiality, integrity, and authenticity of commands, addresses, and data.

[0033] However, existing solutions provided by the UFS standard and its primitives do not address this need due to their lack of driver authentication and access pattern obfuscation.

[0034] Therefore, there is a need to provide a more secure UFS protocol that can be implemented in all devices using non-volatile memory.

[0035] Furthermore, such a more secure UFS protocol should be usable in all future architectures that incorporate emerging memory technologies.

[0036] This disclosure proposes to intervene at an intermediate layer between the physical layers of the UFS protocol, essentially between the physical adapter layer L1.5 and the lower physical sublayer L1 supporting the M-PHY specification, by employing a complete encryption / decryption scheme for data, addresses, and comments traveling on communication channels, such as interconnect buses. Of course, wireless or optical communication channels can be implemented instead of interconnect buses.

[0037] One embodiment of this disclosure relates to an apparatus comprising:

[0038] - A memory device comprising at least a memory array and a memory controller coupled to said at least the memory array;

[0039] - A host device coupled to the memory device via a communication channel; and

[0040] - Hardware and / or software encryption-decryption schemes employed in the communication channels used for exchanging data, addresses, and commands with the at least memory array.

[0041] In addition, bus encryption or decryption of data, addresses, and commands for the at least memory array is implemented in accordance with the UFS protocol.

[0042] Furthermore, the memory controller communicating with the communication channel is configured to encrypt and / or decrypt the data, addresses, and commands, and the host device includes at least one controller communicating with the communication channel bus and configured to encrypt and / or decrypt the data, addresses, and commands.

[0043] Memory devices include NAND memory devices or non-volatile memory devices.

[0044] However, in one embodiment of this disclosure, the memory device may be a hybrid memory device comprising at least a first memory class array and at least a second non-volatile memory array.

[0045] While the description below refers to embodiments including storage-type memory and NAND memory, other embodiments are possible, including different memory types such as: NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory, such as phase-change random access memory (PCRAM), self-selected chalcogenide-based memory, resistive random access memory (RRAM), 3DXPoint memory (3DXP), and magnetoresistive random access memory (MRAM), etc.

[0046] For example, the first memory array and the second memory array may be the first memory array portion and the second memory array portion of a single die memory array, or other memory types may be used.

[0047] This disclosure further relates to a method for managing data, addresses, and commands from / to a device, comprising:

[0048] Data, addresses, and commands are exchanged on the communication channel of the device.

[0049] Hardware and / or software encryption and decryption are performed on the data, addresses, and commands exchanged on the communication channel.

[0050] To better understand this disclosure, it should be noted that data encryption with AES-XTS, when properly configured, will guarantee the three properties of the required data: confidentiality, integrity, and authenticity. However, this encryption does not provide protection for addresses or commands.

[0051] Conversely, protecting systems from unintentional overwriting, malicious attacks, and cloning is essential. In some applications, a technique known as Replay Protected Memory Block (RPMB) is used to provide the integrity and authenticity of data, commands, and addresses. Using this technique, RPMB data erase and write protection commands are authenticated and their integrity verified, but they are never encrypted.

[0052] Furthermore, the memory address was never encrypted.

[0053] By tampering with commands and addresses, attackers can, for example, compromise the security of the entire system by recovering data that has been discarded but not yet erased, or by exploiting hidden vendor commands.

[0054] By observing memory access patterns, attackers may be able to launch cache-based attacks, which could lead to the extraction of secrets such as encryption keys.

[0055] Furthermore, the memory controller is also exposed to fuzzing by external attackers. This could reveal vulnerabilities in the driver implementation and lead to licensed code execution within the system.

[0056] In any case, current encryption schemes are not designed to take full advantage of emerging memory features, such as smaller page sizes and in-situ updates. This results in high latency and a rewrite amplification factor.

[0057] Several known techniques have been proposed to reduce the number of write cycles, such as Data Compare Write (DCW) and Flip-N Write (FNW).

[0058] Both techniques take full advantage of the sparsity of the bits that change within the data word to reduce the number of bits written to large portions of memory. However, a good encryption algorithm is characterized by its diffusion properties, and therefore, two plaintexts with a Hamming distance of 1 will have an average Hamming distance of n / 2 when encrypted, where n is the ciphertext size.

[0059] Therefore, storing encrypted data in emerging memory devices causes the eventual write-and-hold technology to fail, thus reducing its expected lifespan.

[0060] For example, the smallest granularity of data encryption with AES-XTS in a UFS drive is 128 bits, so even a single bit change in a plaintext will result in an average change of 64 bits in the corresponding ciphertext.

[0061] To avoid all the above-mentioned drawbacks, some embodiments of this disclosure provide a new bus encryption method for non-volatile memory devices using the UFS protocol.

[0062] The proposed architecture stores data in plaintext, thus leveraging all existing write reduction techniques and providing a write amplification factor equivalent to unencrypted alternatives.

[0063] The novel architecture of this technology performs bus-only encryption to ensure that data, addresses, and commands sent to the storage peripheral device are not disclosed to or modified by external attackers.

[0064] Furthermore, according to some embodiments of this disclosure, the disclosed architecture paves the way for future integration of emerging memories such as 3D XPoint (3DXP) with the UFS protocol.

[0065] The idea behind this disclosed architecture is to employ an encryption-decryption scheme that prevents bus snooping while defining a complete computing architecture.

[0066] The original idea of ​​integrating bus-only encryption schemes into existing storage protocols allows for improvements in the security of electronic devices that include memory portions interconnected to the controller, as will be more clearly described below.

[0067] This disclosure includes devices and methods related to hybrid memory management; for example, memory devices comprising at least a first memory class array and at least a second non-volatile memory array.

[0068] An example device may include a first memory array, a plurality of second memory arrays, and a controller coupled to the first memory array and coupled to the plurality of second memory arrays.

[0069] The memory device may be a hybrid memory device, wherein the first memory array may be a storage type memory, and the plurality of second memory arrays may be different types of memory, such as NAND flash memory.

[0070] All of the above-described memory devices can be configured to perform write operations. In several embodiments, write operations can be performed on memory devices comprising a first memory array and several second memory arrays.

[0071] The execution of a write operation involves writing data into a first memory array starting at the position indicated by the write cursor, and placing the write cursor at the updated position in the first memory array after the execution of the write operation is completed, wherein the updated position is the next available position in the first memory array.

[0072] A write operation may involve writing data to a first memory array and / or several second memory arrays. Data may be written to the first memory array in response to the amount of data stored in the first memory array falling below a threshold.

[0073] In several embodiments, a write operation performed on the first memory array may be written based on a write cursor indicating the position where the write operation will begin.

[0074] The position of the write cursor can be based on the state of several management units in the write array, where each management unit can be in a valid, invalid, idle, or unused state.

[0075] The position of the write cursor can be updated after each write operation and placed at the next management unit with an idle state.

[0076] For example, addresses can be assigned to management units sequentially based on their physical location, and management units can iterate sequentially based on their addresses to determine their state and place the write cursor at the updated location.

[0077] Similarly, in several embodiments, the read operation may include determining the management unit pattern interference level and raw bit error rate (RBER) of the data in the first memory array.

[0078] When the pattern interference level of the management unit is higher than a threshold or the raw bit error rate (RBER) is higher than a threshold, a move operation can be performed to move the data to a new location in the first memory array.

[0079] Data can be moved to a new location when the RBER is above a threshold because error correction (ECC) operations may not be able to correct errors when data is read from the original location.

[0080] Data can be moved to a new location when the interference level of the management unit pattern is higher than a threshold, because errors are more likely to occur when data is read from a location where adjacent management units have been programmed at least several times.

[0081] In the following detailed description of this disclosure, reference is made to the accompanying drawings, which form a part of this disclosure, and the drawings illustrate by way of illustration how one or more embodiments of this disclosure may be practiced.

[0082] These embodiments have been described in sufficient detail to enable those skilled in the art to practice the embodiments of this disclosure, and it should be understood that other embodiments may be utilized and process, electrical and / or structural changes may be made without departing from the scope of this disclosure.

[0083] As used herein, designators such as “N” or “M” specifically relating to reference numerals in the figures indicate that certain features may be included. It should also be understood that the terminology used herein is for describing particular embodiments only and is not intended to be limiting.

[0084] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” may include both a single indicator and multiple indicators. Additionally, “several,” “at least one,” and “one or more” (e.g., several memory arrays) may refer to one or more memory arrays, while “multiple” is intended to mean more than one of such things.

[0085] Furthermore, throughout this application, the word "can / may" is used in a permissive sense (i.e., possible, able) rather than in a mandatory sense (i.e., certain). The term "contains" and its derivatives mean "including but not limited to".

[0086] Depending on the context, the term "coupled / coupling" means physically, directly or indirectly, connecting or accessing and moving (transmitting) commands and / or data. Depending on the context, the terms "data" and "data value" are used interchangeably and may have the same meaning herein.

[0087] The diagrams in this article follow a numbering convention, where the first one or more numbers correspond to the diagram number, and the remaining numbers identify the elements or components in the diagram.

[0088] Similar numbers may be used to identify similar elements or components between different diagrams. As will be understood, elements shown in the various embodiments herein may be added, swapped, and / or removed to provide several additional embodiments of this disclosure.

[0089] Furthermore, the scale and / or relative dimensions of the elements provided in the figures are intended to illustrate certain embodiments of this disclosure and should not be construed as limiting.

[0090] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory device 106, according to several embodiments of the present disclosure.

[0091] As used herein, “device” can mean, but is not limited to, any or a combination of a variety of structures, such as a circuit or circuit system, one or more dies, one or more modules, one or more devices or one or more systems.

[0092] In several embodiments, the computing system 100 may include a plurality of memory devices. Figure 1In the embodiments shown, the memory device 106 may include a first memory type (e.g., a first memory array 110) and a second memory type (e.g., a plurality of second memory arrays 112-1, ..., 112-N).

[0093] The memory device 106 may be a hybrid memory device, wherein the memory device 106 includes a first memory array 110, which is a memory of a different type from a plurality of second memory arrays 112-1, ..., 112-N.

[0094] The first memory array 110 may be a storage class memory (SCM), which may be a non-volatile memory that serves as the main memory for the memory device 106, because it has a faster access time than several second memory arrays 112-1, ..., 112-N.

[0095] The first memory array 110 may be a phase change memory (PCM), a spin torque transfer (SST) memory, a ferroelectric (FeRAM), a 3D XPoint memory (3DXP), a selectable chalcogenide-based memory and / or a resistive (RRAM), and other types of non-volatile memory.

[0096] Several second memory arrays 112-1, ..., 112-N can serve as data storage devices (e.g., storage memory) for memory device 106, and can be NAND flash memory, as well as other types of memory.

[0097] For example, several second memory arrays 112-1, ..., 112-N can be RAM, ROM, DRAM, SDRAM, PCRAM, RRAM, and flash memory, etc.

[0098] like Figure 1 As shown, host 102 can be coupled to memory device 106 via interface 104. Host 104 and memory device 106 can communicate (e.g., send commands and / or data) on interface or channel 104.

[0099] The host device 102 may be a system-on-a-chip having an embedded memory component 106 or a more complex electronic device including a system connected to the memory device, as will be presented from the description of other embodiments of this disclosure with reference to other figures.

[0100] The host 102 may be a laptop computer, personal computer, digital camera, digital recording and playback device, mobile phone, PDA, memory card reader, interface hub and other host system, and may include memory access device, such as a processor.

[0101] Those skilled in the art will understand that "processor" can mean one or more processors, such as a parallel processing system, several coprocessors, etc.

[0102] The memory device 106 includes a controller 108 for communicating with the host 102, a first memory array 110, and several second memory arrays 112-1, ..., 112-N.

[0103] The controller 108 can send commands to perform operations on the first memory array 110 and several second memory arrays 112-1, ..., 112-N. The controller 108 can communicate with the first memory array 110 and the several second memory arrays 112-1, ..., 112-N to read, write, move and / or erase data, and perform other operations.

[0104] The controller 108 can control several data streams on the memory device 106.

[0105] For example, controller 108 can control the writing of data to a first memory array 110, the writing of data to several second memory arrays 112-1, ..., 112-N, the reading of data from the first memory array 110, the reading of data from several second memory arrays 112-1, ..., 112-N, the moving of data from the first memory array 110 to several second memory arrays 112-1, ..., 112-N, and the moving of data from several second memory arrays 112-1, ..., 112-N to the first memory array 110.

[0106] Host 102 includes a host controller for communicating with memory device 106. The host controller can send commands to memory device 106 via interface 104. The host controller can communicate with memory device 106 and / or controller 108 on memory device 106 to read, write, and erase data, as well as perform other operations.

[0107] The controller 108 on the memory device 106 and / or the host controller on the host 102 may include control circuitry (e.g., hardware, firmware, and / or software).

[0108] In one or more embodiments, the controller 108 on the memory device 106 and / or the host controller on the host 102 may include a control circuitry system, which may be an application-specific integrated circuit (ASIC) coupled to a printed circuit board containing a physical interface. Furthermore, the memory device 106 and the host 102 may include buffers of volatile and / or non-volatile memory and several registers.

[0109] For the purposes of this disclosure, the entire computing system 100 is assumed to be a security domain, which means that even the host 102 and memory device 106 are also security domains. This assumption that the host 102 and memory device 106 are security domains is reasonable, given that several tamper-proof technologies are available in silicon chips.

[0110] In at least one embodiment of this disclosure, a bus encryption architecture is proposed to be integrated into the interface 104 between the host device 102 and the memory device 106 as a UFS standard to protect data, commands, and addresses.

[0111] The UFS protocol for interface or channel 104 uses an LFSR (Linear Feedback Shift Register) to scramble the data before it is encoded at layer L1.5 in the UniPro specification, such as... Figure 1A and Figure 1 They are displayed separately in the middle.

[0112] By replacing the LFSR with a secure stream cipher according to this disclosure, it is possible to guarantee important security features. As previously mentioned, this disclosure shows intervention at an intermediate layer between the physical layers of the UFS protocol, essentially between the physical adapter layer L1.5 and the lower physical sublayer L1 that supports the specification M-PHY typically used for transmitting symbols. The encryption / decryption layer is essentially integrated into the existing layer.

[0113] More specifically, according to this embodiment, the symbols ready for transmission are processed in the adapter layer L1.5 to make such symbols more likely to resemble noise, i.e., random data. This allows for the avoidance of possible interference on the transmission channel 104.

[0114] In other words, the present invention intervenes in the UFS protocol by employing a complete encryption / decryption scheme on data, addresses, and commands traveling on communication channels such as interconnect buses at the physical layer.

[0115] The model used for the encryption and / or decryption phases is Authenticated Encryption with Associated Data (AEAD), a form of encryption that simultaneously ensures the confidentiality and authenticity of the data. These properties are provided within a single, easy-to-use programming interface.

[0116] For example, now refer to Figure 2 The text describes a display of a generic primitive AEAD encryption block 200 along with a generic AEAD decryption block 250.

[0117] The input K of block 200 is the secret key. The input DATA can also be viewed as plaintext PTX with associated data AD. This associated data is not encrypted, but it affects the result of the encrypted data, for example, similar to signing data.

[0118] Therefore, one output of block 200 is represented by a data stream of encrypted data CTX DATA, and the other output is represented by a TAG value that will be transmitted over the communication channel.

[0119] If we consider decrypting block 250, we can observe that the data input is the first output CTX DATA of encrypted block 200, and the second input is represented by the associated data AD of the same block 200. Using the same associated data AD will allow us to obtain the original plaintext PTX.

[0120] The above-disclosed information ensures data confidentiality. If, for example, one or the other of two blocks 200 or 250 is modified based on associated data, then different plaintext PTX and different TAGs will be obtained. However, since the TAG value is transmitted via the channel to the decrypted block 250, it is possible to check whether the TAG value remains the same (otherwise the data has been changed), thereby also ensuring data integrity.

[0121] If we obtain confidentiality and integrity, then we also obtain the third characteristic of data authenticity.

[0122] For performance reasons, it is appropriate to use stream ciphers to make it possible to generate pseudo-random byte streams in advance without depending on the data being transmitted. However, encryption guarantees confidentiality rather than integrity, while, as we have seen, using hash functions guarantees integrity rather than confidentiality. The combination of these two measures guarantees both properties, and therefore also authenticity.

[0123] The UFS protocol must be somewhat adapted to support the exchange of initialization vector IVs, protected against downgrade attacks and key initialization. This initialization vector is a data array used to initialize the cipher and helps determine the cipher output.

[0124] In this regard, the functional blocks of the protocol architecture disclosed herein are... Figure 3 It is displayed in the middle.

[0125] The UFS protocol has adopted a 256-bit shared secret to provide RPMB functionality. Figure 3 The same shared secret can be used in the instances shown in the architecture.

[0126] The shared secret is typically initialized by host 102 during production and can be reset after a secure erase of the entire mass storage portion.

[0127] To avoid anti-reuse attacks, the same data must never be encrypted twice with the same initialization vector IV and the same key.

[0128] If an attacker actively accesses the bus, he / she can tamper with the IVs that are always sent in plaintext, thereby forcing an endpoint to generate the same pseudo-random stream twice.

[0129] One possibility for resolving this potential problem is to initialize the authentication vector IV message so that the other endpoint can be assured that the IV has not been tampered with.

[0130] For this purpose, the HMAC message authentication protocol, standardized by NIST in 2008, can be used. See: NI Standards & Technologies, 2008, "The keyed-hash message authentication code (HMAC)".

[0131] Figure 3 The presentation report is in the computing system architecture 100 disclosed in this publication. Figure 2 A schematic diagram illustrating the application of encryption and decryption schemes.

[0132] For example, computing system 300 corresponds to Figure 1 The computing system 100 includes a host system 302 and a memory device 306 operating according to the UFS protocol in a communication channel established therebetween. Both the host system 302 and the memory device 306 include UFS L2 blocks representing the upper adaptive physical layer of the UFS protocol.

[0133] UFS L1 block 304 can be regarded as a communication channel as a physical sublayer.

[0134] Both host system 302 and memory device 306 possess the same key K1 (i.e., password) that was presented as common in the previous step. In other words, in this instance, we do not have key exchange.

[0135] In this implementation plan, Figure 2 Encryption block 200 is equivalent to block 320, where the associated data AD is represented by the initialization vector IV, and the cryptographic primitive functions are a stream cipher and a hash function. In other words, here we have a combination of a hash function and a symmetric stream cipher used as cryptographic primitives in block 320.

[0136] In this example, the dashed block labeled "System" 302 can be viewed as follows: Figure 1 Block 102 is a general-purpose host device, while the dashed block 306, marked "UFS device," can be considered as... Figure 1 The memory device 106.

[0137] Both blocks 302 and 306 contain hardware for transmitting and receiving information on a communication channel 304, which may be a physical channel such as a wired bus, a wireless channel, or an optical channel.

[0138] Focusing our attention on system block 302, we can see that it contains hash function block 325 that acts on the p0 value generated by block 330, which represents UFS layer L2. The cryptographic hash function of block 325 contains a mathematical algorithm that maps data of arbitrary size to a fixed-size (hash) bit string and is designed as a one-way function.

[0139] Block 325 generates a value h0 combined with the value p0. The result of this combination is added to the output of the stream cipher block E, which acts as a pseudo-random number generator using the secret key K1 as a seed, in logical summation node 335. The initialization vector IV also provides input to the stream cipher block E.

[0140] The output of summing node 335 is addressed to communication channel 304 and received by a symmetric structure containing decryption block 350 located in UFS device block 306, i.e., memory device.

[0141] Therefore, the combination of hash block 325 and stream cipher E is doubled in a symmetric encryption block 350 constructed in a similar manner, where hash function 360 acts on the values ​​p0 and h0 to verify the correctness of the hash values. The decryption result is then provided to block 370, representing the UFS layer L2 in memory device 306.

[0142] The basic structure of the encryption and decryption blocks 320 and 350 disclosed above has been doubled in the corresponding encryption and decryption blocks 340 and 380, which are respectively incorporated in the memory device 306 and the host device 302.

[0143] These blocks 340 and 380 also contain the combined hash functions and symmetric stream ciphers of the corresponding blocks 320 and 350, and operate on the values ​​p1 and h1 that use the secret key K2 as the seed for the stream cipher E.

[0144] Since the internal structures of these blocks 340 and 380 correspond to the internal structures of symmetrical blocks 320 and 350, we will omit a detailed description of them.

[0145] Memory device 306 includes what can be considered equivalent to Figure 2 Decryption block 250 and decryption block 350. Even in this case, symmetric stream cipher and hash function primitives are used.

[0146] As should be clear from previously disclosed information, the choice of primitive functions is not essential for the correct implementation of this technique.

[0147] For example, in Figure 4 The report's alternative implementation flowchart utilizes certified encrypted AEs with associated data (AEAD).

[0148] Figure 4 The presentation report is in the computing system architecture 100 disclosed in this publication. Figure 2 A schematic diagram illustrating the application of encryption and decryption schemes.

[0149] For example, computing system 400 corresponds to Figure 1 The computing system 100 includes a host system 402 and a memory device 406 operating according to the UFS protocol. Both the host system 402 and the memory device 406 include UFS L2 blocks representing the upper adaptive physical layer.

[0150] UFS L1 block 404 can be regarded as a communication channel as a physical sublayer.

[0151] Both host system 402 and memory device 406 possess the same key K1 (i.e., password) that was presented as common in the previous step. In other words, in this instance, we do not have key exchange.

[0152] In this example, host device 402 includes encryption block 420, which includes authenticated encryption AE 425 that receives secret key K1 and initialization vector IV as input.

[0153] The authenticated encryption block 425 operates on value p0 and produces value c0 and a tag as output. This output is addressed to communication channel 404.

[0154] Similarly, the memory device 406 includes a corresponding and symmetrical decryption block 450, which further includes an authenticated decryption block 460 that receives a secret key K1 and an initialization vector IV as input.

[0155] The memory device also includes an authenticated encryption block 465 that receives a secret key K2 and an initialization vector IV as input. The authenticated encryption block 465 operates on the value p1 and produces a value c1 and a tag as output. This output is addressed to the communication channel 404.

[0156] Similarly, host device 402 includes a corresponding and symmetrical decryption block 480, which further includes an authenticated decryption block 475 that receives the secret key K2 and the initialization vector IV as input.

[0157] For the sake of completeness of the disclosed content, it should be noted that the physical layer UFS does not include a single interconnect pair in many cases, as... Figure 3 and 4 It is not those shown in the diagram, but includes multiple interconnections called pathways.

[0158] Therefore, for any pathway, use Figure 3 and 4 The second key K2 in both is used for repeated encryption, as shown in the symmetric block.

[0159] To prevent birthday paradox attacks and avoid duplicate initialization vector IVs, the party transmitting the IV should use a big counter to generate it.

[0160] With the current UFS data scrambling algorithm, synchronization between hosts may be lost. If this occurs, the de-scrambling pattern is sent in plaintext. Upon receiving the pattern, encryption must be reset, and a new IV must be generated and transmitted to the host.

[0161] For the sake of completeness of this disclosure, we will now refer to Figure 5 The example shown illustrates a data scrambling technique used within the M-PHY block to mitigate problems related to electromagnetic interference.

[0162] More specifically, refer to the single channel #0 indicated by number 550 within a group of at least four channels to report instances of scrambling. The scrambling feature is optional, but the UniPro implementation includes support for scrambling.

[0163] The transmitted data should be scrambled using a pseudo-random bit stream (PRBS) to reduce the likelihood of repeating patterns in the link. Scrambling support will be implemented in both the inbound and outbound directions of the PA layer. The UniPro PA layer (or PHY adapter layer) is an intermediate layer between L1 and L2 levels, and skip symbol insertion is implemented at PA-TX, as will be seen below. Scrambling will be enabled or disabled at each power mode change request. After the power mode change procedure is completed, the new scrambling settings are applied to the link at the first burst.

[0164] Once scrambling is activated, it will not be deactivated; instead, it will only be reset.

[0165] The scrambling process is disabled after a UniPro cold or warm reset, either in one or another command. Scrambling is requested only if the peer has marked the ability to descramble data during PACP_CAP_EXT1_ind exchange (PA_PeerScrambling). Scrambling requests always involve scrambling inbound and outbound links. However, scrambling will only be applied to links in Fast_Mode or FastAuto_Mode. Although scrambling is actively requested, links in Slow_Mode or SlowAuto_Mode will not be scrambled.

[0166] The PA layer is scrambled at the transmitter after the PA_PDU is mapped to an 8-bit M-PHY symbol and before 8b10b encoding is performed inside the M-TX. The PA layer is descrambled at the receiver after 10b8b decoding is performed inside the M-RX and before the 8-bit M-RX symbol is matched with the PA_PDU.

[0167] The M-PHY skip symbol is always inserted at PA TX between the scrambler and the 8b10b encoder, and removed at PA RX between the 10b8b decoder and the descrambler when in use.

[0168] Data scrambling will be applied to each path basis. In a multi-path M-PORT link, scrambling will be presented as independent between paths. Scrambling will be applied to all active paths and paths transmitting virtual bursts in the same direction. M-PHY symbol markers will never be scrambled. If the scrambling process is enabled, then M-PHY data symbols will be scrambled.

[0169] The PRBS should be generated using the Galois form of a linear feedback shift register (LFSR) containing cells from 500 to 515, and the generator polynomial should be implemented:

[0170] G(x) = x16 + x5 + x4 + x3 + 1

[0171] The LFSR will be initialized to the following 16-bit seed value depending on the logical path number:

[0172] ·Logical path 0: Seed = 0x0040

[0173] ·Logical Path 1: Seed = 0x0080

[0174] ·Logical Path 2: Seed = 0x00C0

[0175] ·Logical path 3: Seed = 0x0100

[0176] In the action pathway, initialization will occur in the debiased sequence.<MK0,MK1> Triggered during transmission or reception, and the following M-PHY data symbols will be scrambled starting from the (re)initialized LFSR output G(x). The path for transmitting the virtual burst will initialize the LFSR at the start of the burst. Test equipment attempting flight line snooping can use a debias pattern to synchronize its own descrambler.

[0177] The LFSR generates an octet sequence at G(x) for each M-PHY symbol to be scrambled, starting from its reset value. The LFSR generates a new bit sequence at G(x) for each M-PHY symbol, and the LFSR polynomial generation is advanced by eight bits when the M-PHY symbol is presented to the scrambler. However, if a skipped symbol insertion logically occurs after the scrambling process, the skipped symbol insertion will not advance the LFSR.

[0178] Scrambling is achieved by bitwise addition (X-OR) of an eight-bit sequence of G(x), where the M-PHY data symbol bits to be scrambled start from bit 0 to bit 7 of the 8-bit M-PHY data symbol. The scrambler first scrambles the high symbol of the <high, low> symbol pair.

[0179] The bus encryption architecture proposed in this disclosure is generally effective and can be implemented in many ways.

[0180] Figure 3 and 4 These are reported as possible implementation examples. Those examples involve implementation assumptions tailored to mobile high-performance storage infrastructure.

[0181] The two attached implementation schemes assume that they are based on well-known cryptographic building blocks that have undergone extensive and independent encryption work.

[0182] Figure 3 The first alternative implementation shown is an architecture with fast stream cipher and additional hash extracts of plaintext messages to ensure integrity.

[0183] We need a hash algorithm that uses an arbitrary input length and an output with a low latency of at least 128 bits.

[0184] The chosen hash function must be secure in its encryption method to avoid collisions between the first and second preimages.

[0185] Among the possible alternatives, those shown in Table 1 have been selected as SHA-256, which is already embedded in the UFS controller and SHA-3, which were standardized by NIST in 2015.

[0186] Table 1: (Hash Algorithm Benchmark)

[0187]

[0188] SHA-3 carries high area consumption, but will be able to cover a single path at full speed with a single hash core.

[0189] Part of the ISO / IEC standard

[0190] • Optimized for lightweight hardware encryption

[0191] • When implemented in an FPGA, it is 10× more energy efficient than AES-GCM.

[0192] As an alternative, such as Figure 4 As shown in the paper, an architecture using Authenticated Encryption (AE) primitives is proposed to generate an integrity tag during encryption and perform decryption and authentication steps simultaneously.

[0193] In Table 2 below, we can see two reference implementations of the Enocoro-128v2.

[0194] Table 2: (Encryption Algorithm Benchmark)

[0195]

[0196] A block diagram of this implementation scheme is shown in Figure 4 middle.

[0197] AE primitives function like stream ciphers in their operation, except that they can generate authentication tags of arbitrary length.

[0198] If the tag received during decryption does not match the calculated tag, no result is returned to prevent selection-ciphertext attacks (CCA).

[0199] Using the ACORN function as an authenticated stream cipher has allowed for valid results in all hardware implementations.

[0200] Cryptoanalysis work has reported that ACORN functions are susceptible to adaptive-choice-plaintext (CPA2) attacks and are vulnerable to fault injection side-channel attacks.

[0201] However, neither of the two attacks renders everyday passwords insecure.

[0202] The authentication tag size can be set by selecting a 128-bit size, and the probability of brute-forcing the tag may be as high as the probability of brute-forcing the encryption key.

[0203] When using the ACORN cipher, a different IV / key pair must be used for each encrypted message. Instead of exchanging a new 128-bit IV at each message, we can use a 128-bit counter that increments with each new message sent.

[0204] The counter can be synchronized after the de-biased pattern is sent.

[0205] For path synchronization, a possible approach is as follows: whenever a debiased pattern is received, the PA layer RX will lock the PA layer symbol synchronization on each path. The M-RX handles M-PHY symbol synchronization by locking to MK0, which is the high portion of the debiased pattern.

[0206] In multi-path applications, the PA layer will synchronize multiple incoming paths due to the skew between paths and the independent RX clocks of the M-RX. Path synchronization occurs by aligning the incoming de-skew patterns transmitted in parallel from the transmitter. Depending on the de-skew requirements, this may require, for example, creating a shallow de-skew FIFO within the PA layer RX.

[0207] The principle and operation of the alignment device will be as follows:

[0208] 1. When the outbreak begins, the pathways are not synchronized.

[0209] 2. If no debiasing pattern is detected in each action path, the PA layer RX discards the PA symbol until it detects a debiasing pattern.

[0210] 3. Once all active paths have received the debiasing pattern, path synchronization will be successful and the PA layer RX will begin consuming PA symbols.

[0211] 4. If the PA layer RX detects a new de-biasing pattern, then the synchronization of all paths will be lost and the operation will return to step 2.

[0212] In the event of debiasing pattern loss and PA layer RX failing to acquire path synchronization, the debiasing FIFO of the synchronization path overflows due to predetermined behavior. PA layer RX should wait until the peer device transmits another debiasing pattern and locks into this second mode.

[0213] At a minimum, the PA layer will be able to operate correctly at its PHY_SAP with a path-to-path deviation of four PA symbols, see Table 22 for details.

[0214] We will now consider key management in this content.

[0215] The latest UFS 3.0 standard achieves a throughput of 1248 MB / s per channel at its maximum speed (GEAR4).

[0216] UFS implementations are typically full-duplex with two independent paths in each direction. As a result, up to four cryptographic cores may be required for each endpoint.

[0217] Each core requires an encryption key, and care must be taken not to use the same key on all passwords, otherwise they will generate the same pseudo-random stream, thus creating an IV reuse attack setup.

[0218] This will ultimately lead to the retrieval of portions of the protocol message.

[0219] The concatenation of all encryption keys consumes 512 bits. Because this information is exchanged only once, a convenient solution is to derive all key bits from a voice pseudo-random number generator on the host side.

[0220] Secondly, the generated key must be stored in SRAM so that it can be rewritten when the driver is reinitialized.

[0221] Finally, for the sake of completeness, it should be noted that the management of the computing system's capabilities can be handled as follows.

[0222] Local and peer M-TX and M-RX can differ in terms of capability. To simplify capability checks, the PA layer forms a common capability value for the entire inbound link, starting with the peer M-TX and ending with the local M-RX. The equation used to calculate the common capacity value is listed later in this section. This capability degradation is performed automatically at the end of the link initiation sequence.

[0223] Because the automatic degradation process cannot take into account the underlying OMC or limitations from the physical interconnect, applications have the ability to rewrite the computation through these properties.

[0224] Although capability degradation occurs only once, a capability check is performed whenever a request to change the power mode is received at the end of the link initiation sequence. The PA layer will verify the inbound link capability. For example, if a local device wants to change the parameters of an outbound link, the peer PA layer is responsible for verifying the link capability.

[0225] To summarize the techniques disclosed in the previously reported embodiments, we may refer to Figure 6 and 7 A block diagram.

[0226] A method for managing the exchange of data, addresses, and commands in a device is disclosed, the device comprising:

[0227] - A memory device comprising at least a non-volatile memory array and a controller coupled to the memory array, and

[0228] - A host device coupled to the memory device via a communication channel;

[0229] The exchange of data, addresses, and commands includes hardware and / or software encryption / decryption schemes employed in the communication channel.

[0230] Figure 6 Block 610 illustrates a method phase in which a memory device is configured to exchange data, addresses, and commands via a communication channel, for example, for communicating with a host device, such as host device 102. The memory device may be... Figure 1 Schematic block 106 of the computing system.

[0231] Block 610 indicates that the method disclosed herein is applicable to managing the exchange of data, addresses, and commands from / to devices, i.e., memory devices.

[0232] Subsequently, in phase 620, a complete hardware and / or software encryption-decryption scheme is applied to the data, addresses, and commands.

[0233] In this way, the three basic characteristics of the data obtained from the exchanged data, such as the data re-tagged by block 630, are: confidentiality, integrity, and authenticity.

[0234] This block 630 illustrates the efficient exchange of hardware and / or software encrypted / decrypted data, addresses, and commands over a communication channel.

[0235] In an alternative manner to the method defined in this disclosure, such as Figure 7 As reported, in phase 710, the memory device is configured for use with a communication channel, for example in... Figure 1 The host device 102 and the memory device 106 establish a channel 104 for communication.

[0236] Subsequently, in phase 720, the UFS protocol is implemented in the communication channel between the host device and the memory device.

[0237] Subsequently, in phase 730, an encryption-decryption scheme is employed for all data, addresses, and commands exchanged on the communication channel.

[0238] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that arrangements calculated to achieve the same results may replace the specific embodiments shown. This disclosure is intended to cover modifications or variations of various embodiments of this disclosure.

[0239] It should be understood that the above description has been presented in an illustrative rather than restrictive manner. After reviewing the above description, combinations of the above embodiments and other embodiments not specifically described herein will be apparent to those skilled in the art. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A device for memory management, comprising: A memory device comprising a memory array; A host device coupled to the memory device via a communication channel; The memory device is configured to store data in plaintext. The memory device and the host device are configured to implement an encryption-decryption scheme integrated in the communication channel for the data, addresses, and commands exchanged via the communication channel between the host device and the memory array; and The encryption-decryption scheme includes encrypting the data, address, and command prepared for transmission via the communication channel, decrypting the encrypted data received via the communication channel back to plaintext, and decrypting the address and command. The encryption includes a first hash function, a second hash function arranged symmetrically with the first hash function in the encryption block, a first stream cipher, and a second stream cipher arranged symmetrically with the first stream cipher in the encryption block.

2. The device according to claim 1, wherein the encryption-decryption scheme is implemented according to the UFS protocol.

3. The device of claim 2, wherein the encryption-decryption scheme is implemented as an intervention integrated between the physical adapter layer and the lower physical sublayer supporting the M-PHY specification.

4. The device of claim 1, wherein the memory device comprises a non-volatile NAND memory device.

5. The device of claim 1, wherein the memory device includes a memory controller that communicates with the communication channel and is configured to encrypt the data, addresses, and commands prepared for transmission via the communication channel and to decrypt the encrypted data, addresses, and commands received via the communication channel.

6. The device of claim 1, wherein the host device includes a controller that communicates with the communication channel and is configured to encrypt the data, addresses, and commands prepared to be transmitted via the communication channel and to decrypt the encrypted data, addresses, and commands received via the communication channel.

7. The device of claim 1, wherein the encryption-decryption scheme comprises an authenticated encrypted AE block that receives a secret key and an initialization vector as input.

8. The device of claim 1, wherein the data, addresses, and commands exchanged through the communication channel are encrypted using a replay protected memory block (RPMB) to ensure the integrity of the data, addresses, and commands through symmetric encryption.

9. The device of claim 1, wherein the communication channel is an interconnect bus, a wireless channel, or an optical channel.

10. A memory device comprising: A memory controller that is communicatively coupled to an external device via a communication channel; The memory controller is configured to: Enable or disable data scrambling for each power mode change request. The inbound and outbound data are subjected to the aforementioned data scrambling. The address, command, and data prepared for transmission via the communication channel are encrypted, and the encrypted address, command, and data received via the communication channel are decrypted. The encryption includes a first hash function, a second hash function arranged symmetrically with the first hash function in the encryption block, a first stream cipher, and a second stream cipher arranged symmetrically with the first stream cipher in the encryption block.

11. The memory device of claim 10, wherein the memory device includes a storage-type memory.

12. The memory device of claim 10, wherein the memory device is a hybrid memory device comprising a first memory array and a second non-volatile memory array.

13. The memory device of claim 12, wherein the second non-volatile memory array comprises a non-volatile NAND flash memory device.

14. A method for memory management, the method comprising: The Universal Flash Memory (UFS) communication protocol is used to exchange data, addresses, and commands across communication channels coupled to the memory device. as well as A complete encryption and decryption scheme is implemented for the data, addresses, and commands exchanged on the communication channel, wherein implementing the complete encryption and decryption scheme includes encrypting the data, addresses, and commands prepared to be sent through the communication channel and decrypting the encrypted data, addresses, and commands received via the communication channel, wherein the encryption includes a first hash function, a second hash function symmetrically arranged with the first hash function in the encryption block, a first stream cipher, and a second stream cipher symmetrically arranged with the first stream cipher in the encryption block; as well as As part of the communication channel encryption and decryption scheme, the encryption and decryption are performed as an intervention integrated between the physical adapter layer and the lower physical sublayer supporting the M-PHY specification.

15. The method of claim 14, wherein the encryption and decryption include a scrambling phase, the scrambling phase being reset rather than deactivated once activated.

16. The method of claim 14, wherein the encryption and decryption comprise encrypting the data, address, and command prepared for transmission via the communication channel using certified encryption primitives.

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