A method of manufacturing a memory array with improved word line edge defects, a circuit, and applications thereof

Abstract

The application relates to the technical field of semiconductor manufacturing, and discloses a storage array manufacturing method for improving word line edge defects, a circuit and application thereof. The method comprises the following steps: setting a redundant bit line, and matching a photomask of the bit line according to a region of the bit line which at least covers an edge region of a word line of a storage array unit; preparing a bit line layer of the storage array unit; depositing a polysilicon layer used for manufacturing the word line; and manufacturing the word line layer by using a photomask of the word line. The application can effectively improve the occurrence of the defect condition of the fracture of the word line edge without increasing the process and the chip area, greatly improves the yield of the chip, and has practical value.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and more specifically to a method, circuit, and application of a memory array manufacturing process for improving word line edge defects. Background Technology

[0002] In existing floating-gate flash memory designs, 4-6 redundant bit lines (Dummy BLs) and 4-6 redundant word lines (Dummy WLs) are typically reserved on the top, bottom, left, and right sides of the memory cell array. The main purpose is to address the issue that during the actual fabrication of integrated circuit wafers, the outermost edges of the memory cell are prone to defects due to uneven exposure or etching processes, as the outermost edges lack patterns. Therefore, adding 4-6 redundant bit lines and 4-6 redundant word lines helps avoid these potential defects, ensuring the functional integrity of the memory cells actually used inside. These redundant bit lines or word lines are simply designed to reduce the probability of defects in the bit line or word line fabrication process.

[0003] In general, the edges of word lines in a memory array cell need to be connected to contact holes to transmit current and voltage to operate the connected memory cells. However, in actual production, we have found that the current design method is prone to defects at the edges of word lines. The polysilicon that carries the function of word lines has a certain probability of breaking. Since the edges of word lines need to be connected to the metal layer through contact holes, this can lead to the failure of the connected memory cells. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a method, circuit, and application for manufacturing a memory array that improves word line edge defects. This method can effectively reduce the occurrence of word line edge breakage defects and improve chip fabrication yield.

[0005] The present invention solves the technical problem by adopting the following technical solution:

[0006] A method for manufacturing a memory array to improve word line edge defects, the method comprising:

[0007] Set up redundant bit lines and fabricate photomasks for the bit lines according to their area, which at least covers the edge area of ​​the word lines of the memory array cell.

[0008] Fabrication of bitline layers for memory array cells;

[0009] A polycrystalline silicon layer is deposited to form the word lines, and a photomask is used to create the word line layer.

[0010] Preferably, the bit line layer fabrication includes: depositing a polysilicon layer for fabricating bit lines on a wafer on which a shallow trench isolation layer has been fabricated, and using a photomask of the bit lines to fabricate the bit line layer.

[0011] Preferably, the bit line layer comprises a plurality of bit line polysilicon, the word line layer comprises a plurality of word line polysilicon, and an isolation layer is formed between the bit line polysilicon and the word line polysilicon.

[0012] Preferably, the number of redundant bit lines is 8-20.

[0013] Preferably, the method further includes creating contact holes above the letter lines for connecting the letter lines and the metal layer.

[0014] The present invention also provides a method for fabricating a floating gate type flash memory circuit, including the memory array manufacturing method described above.

[0015] The present invention also provides a floating gate type flash memory circuit, including a memory array unit, which is manufactured using the method described above.

[0016] The present invention also provides a chip including the floating gate flash memory circuit as described above.

[0017] The present invention also provides an electronic device comprising the chip as described above.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The memory array manufacturing method provided by this invention improves the chip yield by changing the height difference of polysilicon at the word line edge of the memory array cell in the existing process, without increasing any process or circuit area.

[0020] Specifically, this invention increases the number of redundant bit lines in the redundant bit line region to 8-20, requiring the bit line region to cover the edge of the word line of the memory array cell. Therefore, the redundant bit lines not only prevent defects caused by unevenness in the bit line pattern at the outermost edge of the memory array cell layer due to exposure or etching processes, but also, through this unique optimization design, ensure that the redundant bit line region covers the edge of the word line of the memory array cell, thus avoiding the problem of easy breakage of the word line edge during subsequent word line layer fabrication. It is simple, efficient, and has wide application value.

[0021] Other outstanding substantive features and significant advancements of this invention compared to the prior art are further described in detail in the Embodiments section. Attached Figure Description

[0022] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0023] Figure 1 This is a layout of a memory array with redundant bit lines in the prior art;

[0024] Figure 2 Scanning electron microscope image of edge letter line defects;

[0025] Figure 3 This is a schematic diagram of a cross-section of a memory array with redundant bit lines in the prior art;

[0026] Figure 4 This is the redundant bitline layout of the storage array design in this embodiment;

[0027] Figure 5 This is a schematic diagram of the redundant bit line cross-section of the storage array design in this embodiment;

[0028] Figure 6 This is a schematic cross-sectional view of the polysilicon deposited to prepare the word line layer in this embodiment.

[0029] Figure 7 This is a cross-sectional view of the character line layer after its fabrication in this embodiment.

[0030] Figure 8 This is a schematic cross-sectional view of the wafer structure after the contact holes are formed in this embodiment. Detailed Implementation

[0031] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] It should be noted that certain names are used in the specification and claims to refer to specific components. It should be understood that those skilled in the art may use different names to refer to the same component. This specification and claims do not distinguish components based on differences in name, but rather on substantial differences in function. As used in this specification and claims, "comprising" or "including" is an open-ended term and should be interpreted as "comprising but not limited to" or "including but not limited to". The embodiments described in the Detailed Description section are preferred embodiments of the present invention and are not intended to limit the scope of the invention.

[0033] Example 1

[0034] In actual production, word line edge defects are prone to occur. The polysilicon that carries the word line function has a certain probability of breaking. Since the word line edge needs to be connected to the metal layer through contact holes, it can lead to the failure of the connected memory cells. Therefore, avoiding or improving word line edge defects is the main direction for improving product yield.

[0035] How to solve this defect, or rather, what exactly affects this defect, based on multiple analyses and experiments, such as... Figure 2 As shown, the defect of edge breakage of word lines in memory array cells only occurs on the edge of the last redundant bit line. Therefore, multiple experiments have verified that this is because part of the edge of the word line of the memory array cell is located on the bit line array, and the other part is located on the silicon oxide (STI) used for shallow trench isolation. Due to the pattern density, there will be a large height difference between these two before the polysilicon layer used to make the word line is deposited. On the edge of the last redundant bit line, due to the large height difference, the deposited polysilicon layer will be subjected to greater stress, which will make it easy to break during the deposition of the polysilicon layer or in the subsequent etching process, resulting in the failure of the memory cell connected to the word line. Based on this, this embodiment provides a specific fabrication method to solve this problem.

[0036] like Figure 1-8 As shown, this embodiment provides a method for manufacturing a memory array to improve word line edge defects. In this embodiment, the steps and parameters that are the same as those in the prior art will not be described in detail. Those skilled in the art can choose according to their needs. In this embodiment, only the content of the innovative design of the present invention will be described in detail.

[0037] The preparation method of this embodiment includes:

[0038] like Figure 1 and 3 The diagram shows the layout of redundant bit lines in the conventional design of a memory cell, which typically has 4 to 6 redundant bit lines. In the design of a floating gate flash memory array cell, the number of redundant bit lines in the Dummy BL area is increased from the conventional 4-6 to 8-20.

[0039] In this embodiment, 13 rods are used as an example for illustration. Figure 4 As shown, the number is not absolute; it is only necessary to ensure that the bit line area covers the edge area of ​​the word line of the memory array cell.

[0040] like Figure 5-8 As shown, with other circuit structure fabrication processes remaining unchanged, the photomask of the bit line is fabricated to match the edge region of the word line of the memory array cell, which at least covers the bit line region.

[0041] Then, the bit line layer of the floating gate flash memory array cell is fabricated. Specifically, a polysilicon layer for fabricating bit lines is deposited on a wafer on which a shallow trench isolation layer has been prepared, and the bit line layer is fabricated using a photomask of the bit lines.

[0042] Depositing and forming a polycrystalline silicon layer used to create letter lines;

[0043] like Figure 6 and 7 As shown, a photomask is used to create the word line region. The edges of the word lines of the memory array cell are completely covered by redundant bit line regions, avoiding the stress problem caused by the height difference in polysilicon and effectively preventing the occurrence of word line edge breakage defects. This processing method can be used not only in NOR Flash, but also in flash memory such as NAND, to avoid similar problems.

[0044] In this embodiment, the bit line layer includes a plurality of bit line polysilicon, the word line layer includes a plurality of word line polysilicon, and an isolation layer is formed between the bit line polysilicon and the word line polysilicon.

[0045] like Figure 8 As shown, after the word line layer is prepared, an insulating isolation layer is deposited, and contact holes for connecting the word lines and the metal layer are made.

[0046] Example 2

[0047] This embodiment provides a method for fabricating a floating-gate flash memory circuit, including the use of the memory array manufacturing method as described in Example 1.

[0048] Example 3

[0049] This embodiment provides a floating gate type flash memory circuit, including a storage array unit, which is manufactured using the method described in Embodiment 1.

[0050] Example 4

[0051] This embodiment provides a chip, including the floating gate flash memory circuit as described in claim 3.

[0052] Example 5

[0053] This embodiment provides an electronic device, including the chip described in Embodiment 4.

[0054] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0055] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for manufacturing a memory array to improve word line edge defects, characterized in that, The method includes: Set up redundant bit lines and fabricate photomasks for the bit lines according to their area, which at least covers the edge area of ​​the word lines of the memory array cell. Fabrication of bitline layers for memory array cells; A polycrystalline silicon layer is deposited to form the word lines, and a photomask for the word lines is used to create the word line layer. The bit line layer fabrication includes: depositing a polysilicon layer for fabricating bit lines on a wafer on which a shallow trench isolation layer has been fabricated, and using a photomask of the bit lines to fabricate the bit line layer.

2. The method for manufacturing a memory array to improve word line edge defects according to claim 1, characterized in that, The bit line layer includes a plurality of bit line polysilicon, the word line layer includes a plurality of word line polysilicon, and an isolation layer is formed between the bit line polysilicon and the word line polysilicon.

3. The method for manufacturing a memory array to improve word line edge defects according to claim 1, characterized in that, The number of redundant bit lines is 8-20.

4. The method for manufacturing a memory array to improve word line edge defects according to claim 1, characterized in that, The method also includes creating contact holes above the word lines for connecting the word lines and the metal layer.

5. A method for fabricating a floating-gate flash memory circuit, characterized in that, This includes the method for manufacturing a storage array as described in any one of claims 1-4.

6. A floating-gate flash memory circuit, comprising a memory array unit, characterized in that, The storage array unit is manufactured using the method described in any one of claims 1-4.

7. A chip, characterized in that, Includes the floating-gate flash memory circuit as described in claim 6.

8. An electronic device, characterized in that, Includes the chip as described in claim 7.

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