Method of making three-dimensional memory

Abstract

The application provides a three-dimensional memory manufacturing method, comprising: providing a substrate and forming a stack layer on the substrate; the stack layer comprises interlayer insulating layers and dielectric layers arranged alternately in a longitudinal direction, and the stack layer comprises a channel region and a gate line gap region adjacent to the channel region; forming a first mask layer on a surface of the stack layer away from the substrate; the first mask layer covers the channel region and the gate line gap region; thinning the first mask layer opposite to the position of the gate line gap region to form a trench; forming a longitudinally extending channel hole in the channel region of the stack layer; forming a channel structure in the channel hole; and forming a gate line gap structure in the gate line gap region. The three-dimensional memory manufacturing method provided by the application can avoid the phenomenon of insufficient etching of the outer discharge hole in the etching process.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a method for fabricating a three-dimensional memory. Background Technology

[0002] In the process of 3D NAND (three-dimensional memory), deep hole etching is a very important process. Existing technologies require that after ultra-deep hole etching, the inner and outer holes have very uniform etching critical size and etching depth to ensure good electrical performance.

[0003] Currently, the commonly used etching process for vias employs double-layer stacking etching to reduce the aspect ratio during the etching process. However, in this process, a height difference exists between the mask layer remaining in the channel region and the gate line gap region during etching. This height difference causes a severe masking effect on the external vias, resulting in insufficient etching of the external vias. Summary of the Invention

[0004] In view of this, this application provides a method for fabricating a three-dimensional memory that can avoid insufficient etching of external holes during the etching process.

[0005] To solve the above problems, the technical solution provided in this application is as follows:

[0006] This application provides a method for fabricating a three-dimensional memory, including:

[0007] A substrate is provided and a stacked layer is formed on the substrate; the stacked layer includes an interlayer insulating layer and a dielectric layer alternately arranged in a longitudinal direction, and the stacked layer includes a channel region and a gate line slot region adjacent to the channel region;

[0008] A first mask layer is formed on the surface of the stacked layer opposite to the substrate; the first mask layer covers the channel region and the gate line gap region;

[0009] The first mask layer, which is opposite to the location of the gate line slot region, is thinned to form a trench;

[0010] A plurality of longitudinally extending channel holes are formed in the channel region of the stacked layers; and

[0011] A channel structure is formed within the channel hole.

[0012] In an optional embodiment of this application, the trench is formed by recessing from the surface of the first mask layer away from the stacked layer into the interior of the first mask layer.

[0013] In an optional embodiment of this application, after the step of forming a longitudinally extending channel hole in the channel region of the stacked layer, the portion of the first mask layer corresponding to the channel region and the gate wire gap region is thinned into a second mask layer; the height of the second mask layer is the same as the height of the bottom wall of the trench.

[0014] In an optional embodiment of this application, the stacked layer further includes a stepped region; the thinning step further includes: thinning a first mask layer on the stepped region, so that the first mask layer on the stepped region becomes a third mask layer.

[0015] In an optional embodiment of this application, the longitudinal depth of the trench is defined as D1, the thickness difference between the first mask layer corresponding to the trench region and the second mask layer corresponding to the trench region is defined as D2, and the thickness of the reaction product deposited on the first mask layer corresponding to the gate wire gap region during the formation of the trench hole is defined as D3, and D1 = D2 + D3.

[0016] In an optional embodiment of this application, the height of the third mask layer is the same as the height of the bottom wall of the trench.

[0017] In an optional embodiment of this application, the channel structure includes a storage functional layer formed within the channel aperture and a channel layer formed within the storage functional layer; the storage functional layer includes a tunneling barrier layer, a charge storage layer, and a tunneling layer; the tunneling barrier layer is formed on the dielectric layer exposed within the channel aperture, the charge storage layer is formed on the inner wall of the tunneling barrier layer, the tunneling layer is formed on the charge storage layer, and the channel layer is formed on the tunneling layer.

[0018] In an optional embodiment of this application, it further includes:

[0019] A grid line slot structure is formed in the grid line slot region. The grid line slot structure includes a grid line slot, an insulating layer formed on the inner wall of the grid line slot, and a conductive layer within the insulating layer.

[0020] In an optional embodiment of this application, after "forming a longitudinally extending channel hole in the channel region of the stacked layer" and before "forming a channel structure in the channel hole", the step of removing the second mask layer is further included.

[0021] In an optional embodiment of this application, the material of the first mask layer is a silicon oxide layer or a silicon nitride layer.

[0022] The method for fabricating a three-dimensional memory provided in this application forms a trench on a first mask layer formed on the stacked layer before forming a channel hole on the stacked layer. This ensures that the thickness difference of the first mask layer remaining in the channel region and the gate line gap region is reduced after the channel hole is etched. This avoids the first mask layer remaining in the gate line gap region from causing a severe shielding effect on the external holes, and thus avoids the phenomenon of insufficient etching of the external holes during the etching process. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1A This is a flowchart illustrating a method for fabricating a three-dimensional memory according to a preferred embodiment of this application.

[0025] Figure 1B for Figure 1A A flowchart detailing the specific steps of step S5;

[0026] Figure 1C for Figure 1A A flowchart detailing the specific steps of step S6;

[0027] Figure 2 A cross-sectional view of a first stacking structure provided in an embodiment of this application;

[0028] Figure 3 In order to be in Figure 2 A cross-sectional view of the first mask layer of the first stacked structure after trenches have been formed;

[0029] Figure 4 In order to be in Figure 3 A cross-sectional view of the first stacked structure after the channel holes have been formed;

[0030] Figure 5 exist Figure 3 A cross-sectional view of another location on the first stacked structure after the channel holes have been formed;

[0031] Figure 6 This is a top view of the first stacked structure after the formation of the channel holes, where, Figure 4 This is a sectional view along line III-III. Figure 5 It is a sectional view along IV-IV;

[0032] Figure 7 To remove Figure 4A cross-sectional view of the second mask layer on the first stacked structure shown, forming the second stacked structure;

[0033] Figure 8 for Figure 7 A cross-sectional view of a partial second stacked structure with a channel hole and a grid line slot area;

[0034] Figure 9 To remove Figure 8 The cross-sectional view shown is of the sacrificial oxide layer and part of the interlayer insulation layer.

[0035] Figure 10 In order to be in Figure 9 A cross-sectional view of the bottom wall of the channel hole after a selective silicon epitaxial layer has been formed;

[0036] Figure 11 In order to be in Figure 10 The diagram shows a cross-sectional view after a first oxide layer has been formed on the dielectric layer exposed within the channel hole;

[0037] Figure 12 In order to be in Figure 11 The cross-sectional view shown is a cross-sectional view of the channel hole sidewall after the formation of the functional layer and the channel layer.

[0038] Figure 13 In order to be in Figure 12 The cross-sectional view shown is after the channel holes are filled with silicon oxide to form a channel insulating filler layer.

[0039] Figure 14 For erosion Figure 13 The portion of the trench insulating fill layer and the portion of the stacked layer shown are formed in a recessed cross-sectional view;

[0040] Figure 15 In order to be in Figure 14 The diagram shows a cross-sectional view of polysilicon deposited within the recess to form a channel structure, an insulating oxide layer, and gate wire slots.

[0041] Figure 16 To utilize such Figure 15 The cross-sectional view shown is obtained by removing the remaining dielectric layer from the gate wire slot to form the groove structure.

[0042] Figure 17 For example Figure 16 A cross-sectional view of the groove structure after the gate layer has been formed;

[0043] Figure 18 To remove Figure 17 A cross-sectional view of the portion of the adhesive layer adjacent to the gate line gap in the gate layer shown; and

[0044] Figure 19A cross-sectional view showing the formation of the grid slot structure after an insulating layer is formed on the sidewall of the grid slot, and a conductive layer and a filling material are formed within the insulating layer. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0046] In the description of this application, it should be understood that the terms "upper," "lower," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0047] Reference numerals and / or reference letters may be repeated in different embodiments of this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate the relationship between the various implementations and / or settings discussed.

[0048] This application addresses the technical problem of insufficient etching of external vias during the etching process in existing 3D NAND processes. Before forming the channel via on the stacked layer, this application forms a trench on a first mask layer formed on the stacked layer. This ensures that after etching to form the channel via, the thickness difference of the first mask layer remaining in the channel region and the gate line gap region is reduced. This avoids the first mask layer remaining in the gate line gap region from causing severe masking of the external vias, thereby preventing insufficient etching of the external vias during the etching process.

[0049] Since the channel holes, channel structures, and gate wire slot structures can all be fabricated using existing methods, the following description will specifically use one existing method for fabricating channel holes, channel structures, and gate wire slot structures to describe the fabrication method of the three-dimensional memory. It should be emphasized that the fabrication method for the channel holes, channel structures, and gate wire slot structures in this application is not limited to the method described below. The fabrication method of the three-dimensional memory in this application will be described in detail below with reference to specific embodiments.

[0050] Please see Figures 1A to 1C and Figures 2 to 19 This application provides a preferred embodiment of a method for fabricating a three-dimensional memory, comprising the following steps:

[0051] Step S1: Please refer to Figure 1A and Figure 2 A substrate 100 is provided and a stacked layer 110 is formed on the substrate 100; the stacked layer 110 includes an interlayer insulating layer 111 and a dielectric layer 112 disposed alternately in the longitudinal direction, and the stacked layer 110 includes a channel region 102 and a gate line gap region 101 adjacent to the channel region 102.

[0052] The stacked layer 110 further includes a stepped region 103, which is located at one end of the channel region 102 and the gate wire gap region 101 (see details). Figure 5 and Figure 6 ).

[0053] In this embodiment, the substrate 100 can be a Si substrate, a Ge substrate, a SiGe substrate, SOI (Silicon On Insulator), or GOI (Germanium On Insulator), etc. In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as SiC, and can also be a stacked structure, such as Si / SiGe, etc.

[0054] Specifically, the thicknesses of the interlayer insulating layer 111 and the dielectric layer 112 may be equal or unequal.

[0055] Specifically, the number of stacked layers 110 is determined according to the number of storage cells to be formed in the vertical direction. The number of stacked layers 110 can be, for example, 8 layers, 32 layers, 64 layers, or higher. The more stacked layers there are, the higher the integration of the storage device can be.

[0056] Specifically, chemical vapor deposition, atomic layer deposition, or other suitable deposition methods can be used to sequentially and alternately deposit the interlayer insulating layer 111 and the dielectric layer 112 to form the stacked layer 110.

[0057] In this embodiment, the material of the interlayer insulating layer 111 can be silicon oxide (SiOx), and the material of the dielectric layer 112 can be silicon nitride (SiNx). In other embodiments, the material of the interlayer insulating layer 111 is not limited to silicon oxide, and the material of the dielectric layer 112 is not limited to silicon nitride.

[0058] Step S2: Please refer to Figure 1A and Figure 2 A first mask layer 120 is formed on the surface of the stacked layer 110 opposite to the substrate 100, and the first mask layer 120 covers the channel region 102 and the gate line gap region 101.

[0059] The substrate 100, the stacked layer 110 and the first mask layer 120 constitute a first stacked structure 1000.

[0060] In this embodiment, the first mask layer 120 is a hard mask layer, and the material of the first mask layer 120 is a silicon oxide layer or a silicon nitride layer, which is used to ensure that the pattern of the subsequent stacked layer 110 will not change after patterning.

[0061] Step S3: Please refer to Figure 1A and Figure 3 The first mask layer 120, which is opposite to the position of the gate line gap region 101, is thinned to form a trench 1201.

[0062] The trench 1201 can be formed by methods such as chemical etching or mechanical cutting. In this embodiment, the trench 1201 is formed by chemical etching.

[0063] After step S3, the portion of the first mask layer 120 corresponding to the channel region 102 and the gate gap region 101 is thinned into a second mask layer 160. In this embodiment, the height of the second mask layer 160 is the same as the height of the bottom wall of the trench 1201, that is, the surface 161 of the second mask layer 160 away from the stacked layer 110 is flush with the bottom wall of the trench 1201.

[0064] Step S3 further includes: thinning the first mask layer 120 on the stepped region 103, so that the first mask layer on the stepped region becomes a third mask layer (not shown). The height of the third mask layer is the same as the height of the bottom wall of the trench 1201.

[0065] The longitudinal depth of the trench 1201 is defined as D1, and the thickness difference between the first mask layer 120 corresponding to the trench region 102 and the second mask layer 160 corresponding to the trench region 102 is defined as D2. During the formation of the trench aperture, a chemical reaction occurs, and at least some of the reaction products are deposited on the first mask layer 120. Therefore, the thickness of the reaction products deposited on the first mask layer 120 during the formation of the trench aperture is further defined as D3, and D1 = D2 + D3.

[0066] In this embodiment, the longitudinal depth D1 of the trench 1201 is 800 nm.

[0067] Step S4: Please refer to Figure 1A , Figures 4 to 6 A plurality of longitudinally extending channel holes 121 are formed in the channel region 102 of the stacked layer 110.

[0068] The channel holes 121 all penetrate the second mask layer 160 and the stacked layer 110.

[0069] In this application, the channel aperture 121 is perpendicular to the stacked layer 110. The channel aperture 121 includes an inner channel aperture and an outer channel aperture. The outer channel aperture is disposed adjacent to the gate line slot region 101, and the inner channel aperture is disposed away from the gate line slot region 101. That is, the outer channel aperture is located between the inner channel aperture and the gate line slot region 101.

[0070] In this embodiment, the channel hole 121 is perpendicular to the stacked layer 110.

[0071] Specifically, the method for forming the channel hole 121 includes: first, forming a patterned photoresist on the stacked layer 110; and second, etching the stacked layer 110 using an etching process to form the channel hole 121.

[0072] The etching process of the channel hole 121 is a plasma / polymer process, such as anisotropic plasma dry etching process, which is typically used to etch the stacked layer 110 to form the channel hole 121.

[0073] Specifically, the channel hole 121 can extend to the substrate 100, forming a groove of a certain depth on the substrate 100. (See also...) Figure 7 After step S4, the method further includes the step of removing the second mask layer 160 to obtain the second stacked structure 2000.

[0074] The following will be Figures 8-18 In this paper, we will take one of the channel holes 121 as an example to illustrate the subsequent fabrication method of the three-dimensional memory.

[0075] Step S5: Please refer to Figures 8 to 15 A channel structure is formed within the channel hole 121.

[0076] The channel structure includes a storage functional layer formed within the channel aperture 121 and a channel layer 124 formed within the storage functional layer; the storage functional layer includes a tunneling barrier layer (i.e., the first oxide layer 1122 hereinafter), a charge storage layer 122 and a tunneling layer 123; the tunneling barrier layer is formed on the dielectric layer 112 exposed within the channel aperture 121, the charge storage layer 122 is formed on the inner wall of the tunneling barrier layer (1122), the tunneling layer 123 is formed on the charge storage layer 122, and the channel layer 124 is formed on the tunneling layer 123.

[0077] Specifically, step S5 includes:

[0078] For step S51, please refer to... Figure 1B Figures 8 to 11 A first oxide layer 1122 is formed on the dielectric layer 112 exposed within the channel hole 121.

[0079] The first oxide layer 1122 can serve as a tunneling barrier layer on the sidewall of the channel hole 121. By using the first oxide layer 1122 as a tunneling barrier layer, the number of steps required to deposit the tunneling barrier layer is reduced, thus improving the uniformity of the tunneling barrier layer.

[0080] In an optional embodiment of this application, the dielectric layer 112 exposed within the channel hole 121 is oxidized using an in-situ oxidation process to form the first oxide layer 1122. Specifically, the dielectric layer 112 exposed within the channel hole 121 is oxidized in-situ to form the first oxide layer 1122, which serves as a tunneling barrier layer. Because the in-situ oxidation process oxidizes any location on the inner wall of the channel hole 121, and the lateral oxidation depth can be controlled by adjusting process parameters, the uniformity of the tunneling barrier layer covering the entire inner side of the channel hole 121 is improved, thus enhancing the uniformity of the tunneling barrier layer. Specifically, the oxidation temperature is 700-1000℃, for example, 700℃, 800℃, 900℃, or 1000℃, or any temperature between these temperatures. The lateral thickness of the first oxide layer 1122 can be 2-15 nm.

[0081] In another optional embodiment of this application, the first oxide layer 1122 can also be formed by depositing silicon oxide on the sidewall of the channel hole 121, for example, by using an ALD process to deposit silicon oxide on the sidewall of the channel hole 121 to form a tunneling barrier layer. That is, in this application, the formation process of the first oxide layer 1122 is not limited.

[0082] Please refer to Figures 9-10 Before "forming the first oxide layer 1122", the method further includes the steps of: oxidizing the dielectric layer 112 and the substrate 100 exposed in the channel hole 121 to form a sacrificial oxide layer 1121; using the line connecting the contact point of the sacrificial oxide layer 1121 and the stacked layer 110 as a cutting line to remove the sacrificial oxide layer 1121 and a portion of the interlayer insulating layer 111; and forming a selective silicon epitaxial layer 130 on the bottom wall of the channel hole 121. In the step of "forming the first oxide layer", the selective silicon epitaxial layer 130 is simultaneously oxidized on a portion of the selective silicon epitaxial layer 130 adjacent to the bottom wall of the channel hole 121, that is, the first oxide layer 1122 is also formed on the surface of the selective silicon epitaxial layer 130 exposed in the channel hole 121.

[0083] Since the etching process for the channel via 121 is a plasma / polymer process, such as anisotropic plasma dry etching, the stacked layer 110 is typically etched to form the channel via 121. These plasma / polymer processes can damage the sidewalls of the channel via 121 and the exposed substrate 100, making subsequent epitaxial growth of single-crystal silicon difficult and also causing leakage current, affecting the stability of the 3D memory. Therefore, the sacrificial oxide layer 1121 is partially formed on the groove surface of the substrate 100. The sacrificial oxide layer 1121 repairs the damage to the silicon nitride layer on the sidewalls of the channel via 121 and the surface damage to the exposed substrate 100, reducing leakage current and improving the stability of the 3D memory.

[0084] Step S52: Please refer to Figure 1B and Figure 12 A functional layer and a channel layer 124 are formed on the sidewall of the channel hole 121.

[0085] The functional layer, extending inward along the sidewall of the channel hole 121, sequentially includes a charge storage layer 122 and a tunneling layer 123. The first oxide layer 1122 serves as a tunneling barrier layer, forming the storage functional layer of the three-dimensional memory together with the charge storage layer 122 and the tunneling layer 123. The tunneling layer 123 can be made of silicon oxide (SiOx), the charge storage layer 122 can be made of silicon nitride (SiNx) or silicon oxynitride (SiON), and the channel layer 124 can be made of polycrystalline silicon.

[0086] The first oxide layer 1122, the charge storage layer 122, the tunneling layer 123, and the channel layer 124 are etched to form a recessed region on the upper surface of the selective silicon epitaxial layer 130. Polysilicon is then deposited to form a connection region 1241 in the channel layer 124 that contacts the upper surface of the selective silicon epitaxial layer 130 at the bottom of the channel via 121.

[0087] In the above steps, chemical vapor deposition or atomic layer deposition methods can be used to form the charge storage layer 122, the tunneling layer 123, and the channel layer 124.

[0088] In other alternative embodiments of this application, the shape of the connection region 1241 is not limited to a groove type, and can be any known shape, as long as the channel layer 124 and the selective silicon epitaxial layer 130 are connected.

[0089] Furthermore, the outer diameter of the charge storage layer 122 and the maximum outer diameter of the selective silicon epitaxial layer 130 are on the same vertical extension line. Compared to conventional three-dimensional memories where the maximum outer diameter of the selective silicon epitaxial layer 130 and the tunneling barrier layer are on the same vertical extension line, the three-dimensional memory manufactured by the method provided in this application reduces the critical channel size, thereby compressing the size of the selective silicon epitaxial layer 130 and improving the uniformity of the size of the selective silicon epitaxial layer 130.

[0090] Step S53: Please refer to Figure 1B and Figures 13 to 15 Silicon oxide is filled into the channel hole 121 to form a channel insulating fill layer 125. Then, part of the channel insulating fill layer 125 is etched back to remove the silicon oxide layer and silicon nitride layer located at the topmost layer of the stacked layer 110. Insertion polysilicon 1242 is deposited and chemical mechanical polishing (CMP) is performed to form a channel structure. Silicon oxide is deposited on the surface of the stacked layer 110 to form an insulating oxide layer 140 (also known as a cap oxide layer, CAPOxide).

[0091] The etching depth is 30-120 nm from the top layer of the stacked layer 110 downwards; the insulating oxide layer 140 covers the polysilicon plug 1242 to protect the channel structure and provide insulation.

[0092] Step S6: Please refer to Figure 1A , Figures 15 to 19 A grid line slot structure is formed in the grid line slot region 101.

[0093] The gate wire slot structure includes a gate wire slot 150, an insulating layer 151 formed on the inner wall of the gate wire slot 150, and a conductive layer within the insulating layer 151.

[0094] Specifically, step S6 includes:

[0095] Step S61, please refer to Figure 1C and Figure 15 In the stacked layer 110, longitudinally extending gate line slots 150 are formed, which divide the stacked layer 110 into several stacked layer sub-blocks.

[0096] The gate line gap 150 penetrates the insulating oxide layer 140, the stacked layer 110, and a portion of the associated substrate 100.

[0097] Specifically, longitudinally extending gate line slots 150 are formed in the stacked layer 110 through patterning. Among them, a plurality of channel structures are included between adjacent gate line slots 150.

[0098] For step S62, please refer to... Figure 1C , Figures 16 to 18 The remaining portion of the dielectric layer 112 is removed using the gate line gap 150 and replaced with the gate layer 113.

[0099] Specifically, step S62 includes: First, please refer to... Figure 16 The remaining portion of the dielectric layer 112 is removed using the gate gap 150 to form a groove structure 1123. Then, the sidewalls of the selective silicon epitaxial layer 130 are oxidized using a high-temperature wet oxidation process to form a second oxide layer 131. Next, please refer to... Figure 17 The gate layer 113 is formed by filling the groove structure 1123 with a conductive material. Again, please refer to... Figure 18 Remove a portion of the adhesive layer in the gate layer 113 adjacent to the gate line gap 150, so that the adhesive layer forms an inwardly recessed adhesive layer and a lateral void portion 1134 between the gate line gaps 150.

[0100] Specifically, after the remaining portion of the dielectric layer 112 is exposed through the gate line gap 150, the remaining portion of the dielectric layer 112 is wet-etched through the gate line gap 150 to remove the remaining portion of the dielectric layer 112, thereby forming a groove structure 1123. Specifically, to prevent metal atoms in the gate layer 113 from diffusing into the interlayer insulating layer 111, the gate layer 113 includes a high-k layer 1131 and a bonding layer; wherein the bonding layer includes a bonding buffer layer 1132 and a metal material layer 1133. The material of the high-k layer 1131 can be alumina (Al2O3) or zirconium oxide (ZrO2); the material of the bonding buffer layer 1132 can be titanium nitride (TiN); the material of the metal material layer 1133 can be tungsten (W), and may also include polycrystalline silicon or metal silicide materials. For example, the metal silicide material can be provided as a silicide material comprising metals selected from tungsten (W) and titanium (Ti). In this application, to achieve a better blocking effect on metal atoms, an aluminum oxide layer, serving as the high-k layer 1131, is located near the interlayer insulating layer 111, and a TiN layer, serving as the bonding buffer layer 1132, is located between the high-k layer 1131 and the metal material layer 1133. The bonding buffer layer 1132 also serves as a conductive layer and an F2 blocking layer, further improving the stability of the device. Furthermore, the high-k layer 1131 on the sidewall of the gate line gap 150 extends outward to cover the interlayer insulating layer 111 exposed on the sidewall of the gate line gap 150, ensuring that the metal material layer 1133 does not enter the interlayer insulating layer 111 during filling, thus avoiding damage to the interlayer insulating layer 111.

[0101] Specifically, a portion of the adhesive layer adjacent to the gate line gap 150 in the gate layer 113 is removed. Typically, the high-K layer 1131 is used as the etching starting point, and 0-100nm is etched inward along the adhesive layer to form an inwardly recessed adhesive layer and a lateral void portion 1134, the lateral width of which is 0-100nm.

[0102] For step S63, please refer to... Figure 19 An insulating layer 151 is formed on the sidewall of the grid slot 150, and a conductive layer and a filling material (not shown) are formed within the insulating layer 151.

[0103] The insulating layer 151 covers the vacant portion 1134, further ensuring insulation and improving device stability. Subsequently, a conductive layer and a filler material (not shown) are formed within the insulating layer 151 according to prior art.

[0104] The method for fabricating a three-dimensional memory provided in this application forms a trench on a first mask layer formed on the stacked layer before forming a channel hole on the stacked layer. This ensures that the thickness difference of the first mask layer remaining in the channel region and the gate line gap region is reduced after the channel hole is etched. This avoids the first mask layer remaining in the gate line gap region from having a severe shielding effect on the external holes, and thus avoids the phenomenon of insufficient etching of the external holes during the etching process.

[0105] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Provide a substrate and form a stacked layer on the substrate; The stacked layer includes an interlayer insulating layer and a dielectric layer alternately arranged in the longitudinal direction, and the stacked layer includes a channel region and a gate line gap region adjacent to the channel region, as well as a step region; A first mask layer is formed on the surface of the stacked layer opposite to the substrate; The first mask layer covers the trench area, the grid line gap area, and the stepped area; In the same process, the first mask layer opposite to the location of the gate gap region is thinned to form a trench, and the first mask layer on the stepped region is thinned so that the first mask layer on the stepped region becomes a third mask layer, the height of the third mask layer being the same as the height of the bottom wall of the trench. A plurality of longitudinally extending channel holes are formed in the channel region of the stacked layers; and A channel structure is formed within the channel hole.

2. The method for manufacturing a three-dimensional memory as described in claim 1, characterized in that, The groove is formed by recessing from the surface of the first mask layer away from the stacked layers into the interior of the first mask layer.

3. The method for manufacturing a three-dimensional memory as described in claim 1, characterized in that, After the step of forming a longitudinally extending channel hole in the channel region of the stacked layer, the portion of the first mask layer corresponding to the channel region and the gate wire gap region is thinned into a second mask layer; the height of the second mask layer is the same as the height of the bottom wall of the trench.

4. The method for manufacturing a three-dimensional memory as described in claim 3, characterized in that, The longitudinal depth of the trench is defined as D1, the thickness difference between the first mask layer corresponding to the trench region and the second mask layer corresponding to the trench region is defined as D2, and the thickness of the reaction product deposited on the first mask layer corresponding to the gate gap region during the formation of the trench hole is defined as D3, and D1=D2+D3.

5. The method for manufacturing a three-dimensional memory as described in claim 1, characterized in that, The channel structure includes a storage functional layer formed within the channel aperture and a channel layer formed within the storage functional layer; the storage functional layer includes a tunneling barrier layer, a charge storage layer and a tunneling layer; the tunneling barrier layer is formed on the dielectric layer exposed within the channel aperture, the charge storage layer is formed on the inner wall of the tunneling barrier layer, the tunneling layer is formed on the charge storage layer, and the channel layer is formed on the tunneling layer.

6. The method for manufacturing a three-dimensional memory as described in claim 1, characterized in that, Also includes: A grid line slot structure is formed in the grid line slot region. The grid line slot structure includes a grid line slot, an insulating layer formed on the inner wall of the grid line slot, and a conductive layer within the insulating layer.

7. The method for manufacturing a three-dimensional memory as described in claim 3, characterized in that, After "forming longitudinally extending channel holes in the channel region of the stacked layer" and before "forming channel structures in the channel holes", the step of removing the second mask layer is further included.

8. The method for manufacturing a three-dimensional memory as described in claim 3, characterized in that, The material of the first mask layer is a silicon oxide layer or a silicon nitride layer.

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