Method for generating independent clock signals from the same oscillator

Abstract

A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal that tracks a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first frequency division value based on the first reference clock signal and a first frequency division value adjustment. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second frequency division value, and a second frequency division value adjustment. The second clock signal tracks the second reference clock signal. The second frequency division value adjustment is based on the first frequency division value adjustment and is opposite the first frequency division value adjustment.

Description

Technical Field

[0001] This invention relates to electronic devices, and more particularly to generating clock signals for electronic devices. Background Technology

[0002] In an exemplary application, the radio network uses clock signals aligned to the same reference clock signal for time synchronization. Within the same network, high-speed data transmission on the transmission line can reference different reference clock signals for time synchronization. A first set of clock signals tracks a high-speed data time reference clock signal for frequency stability and a time synchronization reference clock signal for tracking absolute time. Another output clock signal tracks the high-speed data time reference clock signal but not the time synchronization reference clock signal. Techniques are needed to generate those types of output clock signals that meet target phase noise specifications. Summary of the Invention

[0003] In at least one embodiment of the present invention, a clock product includes: a first phase-locked loop (PLL) circuit including a first frequency divider. The first PLL circuit is configured to generate a first clock signal that tracks a first reference clock signal and a second reference clock signal. The first PLL circuit is controlled by a first frequency division value and a first frequency division value adjustment based on the first reference clock signal. The clock product also includes: a circuit including a second frequency divider. This circuit is configured to generate a second clock signal based on the first clock signal, a second frequency division value, and a second frequency division value adjustment. The second clock signal tracks the second reference clock signal. The second frequency division value adjustment is based on and opposite to the first frequency division value adjustment.

[0004] In at least one embodiment of the present invention, a method for generating a clock signal includes: controlling a first phase-locked loop circuit including a first frequency divider circuit to generate a first clock signal that tracks a first reference clock signal and a second reference clock signal by using a first frequency divider value based on a reference clock signal and a first frequency divider value adjustment. The method includes generating a second clock signal based on the first clock signal, a second frequency divider value, and a second frequency divider value adjustment. The second clock signal tracks a second reference clock signal. The second frequency divider value adjustment is based on and opposite to the first frequency divider value adjustment.

[0005] In at least one embodiment of the present invention, a method for generating a clock signal includes: generating a frequency-stable clock signal synchronized with a network clock signal and a second reference clock signal using a first frequency division value and a first frequency division value adjustment based on a second reference clock signal. The frequency-stable clock signal tracks the frequency of the second reference clock signal. The method includes filtering the frequency-stable clock signal to regenerate the network clock signal as an output network clock signal. The filtering uses a second frequency divider that responds to a second frequency division value modulated by the second frequency division value adjustment. The second frequency division value adjustment is based on and opposite to the first frequency division value adjustment. Attached Figure Description

[0006] The invention can be better understood by referring to the accompanying drawings, and its many objects, features and advantages will be clear to those skilled in the art.

[0007] Figure 1 A functional block diagram of a conventional clock generator including cascaded phase-locked loops is shown.

[0008] Figure 2 A functional block diagram of an exemplary clock generator circuit including nested phase-locked loops is shown.

[0009] Figure 3 A functional block diagram of an exemplary clock generator is shown, which includes a filter circuit configured to regenerate a reference clock signal from an internal clock signal generated by a nested phase-locked loop circuit consistent with at least one embodiment of the present invention.

[0010] Figure 4 A functional block diagram of an exemplary clock generator is shown, including a filter circuit implemented using a frequency divider that responds to an adjusted frequency divider value generated based on an adjustment of a feedback frequency divider of a nested phase-locked loop consistent with at least one embodiment of the present invention.

[0011] Figure 5 It shows the target of being made by Figure 4 An exemplary timing waveform of the frequency error of the network clock signal regenerated by the clock generator.

[0012] Figure 6 It shows the target of being made by Figure 4 An exemplary timing waveform of the time interval error (TIE) of the network clock signal regenerated by the clock generator.

[0013] Figure 7 An exemplary timing waveform is shown illustrating the response of the output clock signal to modulation of a division value, which is used in... Figure 4 The adjustment is made by adjusting the synchronization delay between the corresponding feedback dividers in the phase-locked loop.

[0014] Figure 8 A functional block diagram of an exemplary clock generator is shown, including a filter circuit implemented using a phase-locked loop circuit that responds to an internal clock signal and an adjusted divider value generated based on an adjustment of a feedback divider of a nested phase-locked loop consistent with at least one embodiment of the present invention.

[0015] Figure 9 A functional block diagram of an exemplary clock generator is shown, including a filter circuit implemented using a phase-locked loop circuit, which responds to an output clock signal and an adjusted divider value generated based on an adjustment of a feedback divider of a nested phase-locked loop consistent with at least one embodiment of the present invention.

[0016] Using the same reference numerals in different figures to indicate similar or identical items. Detailed Implementation

[0017] Clock products include a high-speed voltage-controlled oscillator (or internal oscillator) that adjusts the input clock signal to track an absolute time reference clock signal. The output clock signal derived from the internal oscillator meets the target phase noise performance specifications for time synchronization. Filtering of the internal oscillator signal reduces or eliminates the effect of tracking adjustment on at least one other output clock signal. Therefore, a single high-performance clock product uses the same oscillator to generate multiple clock signals, each with a different time base and phase noise performance that meets the target specifications.

[0018] Typically, data transmission networks (e.g., Ethernet, broadcast video, wireless networks) do not require the transmission of clock synchronization information. IEEE Standard 1588-2008 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) ITU-T REC. G8262 are typical packet timing (ToP) technologies used to synchronize clock frequencies between devices in computing networks, wired networks, and wireless networks, and to improve clock accuracy to meet the timing requirements of target applications.

[0019] For example, IEEE specification 1588-2008 PTP is a master / slave packet-based solution for synchronizing clock signals across a computing network based on message exchange across communication media. A remote master clock can send timestamp information over a data network for synchronization with a local clock. The actual clock value (e.g., the timestamp) is transmitted within the payload of a special packet dedicated to the task. The highest node (T-GM) traceable to a Coordinated Universal Time (UTC) source sends synchronization information to the clock residing on its network segment. The boundary clock nodes (T-BCs) present on that segment then relay the accurate time to other network segments to which they are also connected. Auxiliary Partial Timing Support (T-APTS) is a method for timing in wireless environments (e.g., Long Term Evolution, i.e., LTE) and is similar to boundary clock implementations. T-APTS uses a UTC source (when available) to correct for network impairments in a PTP network. Clock products can be configured to comply with one or more of the T-GM, T-BC, or T-APTS specifications. PTP is a packet-layer protocol that can be used to allocate frequency or phase information. PTP systems can provide phase signals in the form of one pulse per second and frequency information.

[0020] Synchronous Ethernet (SyncE), as described in ITU-T Rec. G8262, specifies the timing characteristics of the slave clock signal used in a master-slave approach for allocating frequency synchronization references to synchronous network devices. SyncE uses the physical layer to allocate frequencies from the master reference clock to the slave clock. SyncE clocks provide accurate frequencies with high stability and low drift and can be used to synchronize radios in wireless communication base stations. However, SyncE does not provide a phase component. Network elements can support domains conforming to each protocol. Wireless infrastructure solutions require synchronizing RF interfaces with the computing network and regenerating SyncE clock signals to propagate a highly stable, low-drift frequency reference throughout the network.

[0021] refer to Figure 1 The exemplary clock product regenerates the SyncE clock signal from the input clock signal SYNCE_IN. The SyncE phase-locked loop (SYNCE PLL) 202 removes jitter from the input clock signal SYNCE_IN and regenerates the SyncE clock signal as the output clock signal SYNCE_OUT. The PTP phase-locked loop (PTP PLL) 204 uses the clock signal PTP_IN and the output clock signal SYNCE_OUT to generate the RF output signal and the PTP output signal. Since the output clock signal SYNCE_OUT and the output clock signals RF_OUTPUTS and PTP_OUTPUTS can have different frequencies, in order to meet the target specifications, Figure 1The implementation uses two high-frequency oscillators, which consumes a lot of power, or uses multiple fractional dividers, which can reduce the jitter performance of the output clock signal.

[0022] refer to Figure 2 Instead of using cascaded phase-locked loops to generate a reference clock signal PTP_IN with a frequency stable output clock signal (e.g., output clock signals RF_OUTPUTS and PTP_OUTPUTS), clock integrated circuit 100 nests phase-locked loop (PLL) 110 within phase-locked loop 104 and uses phase-locked loop 150 to generate an output clock signal OUTB (e.g., output clock signal SYNCE_OUT) using clock signal CLKVCO as a low-jitter reference clock signal. In at least one embodiment, clock generator integrated circuit 100 includes a multi-loop phase-locked loop that generates a low-jitter clock signal CLKVCO by tracking clock signals SYNCE_IN and PTP_IN. The adjusted frequency division value M... A +Δ MA The clock signal is generated based on the clock signal PTP_IN. In at least one embodiment, the local reference clock signal REFCLK, provided by the reference clock source (REF) 101, stabilizes the clock signal CLKVCO in the absence of clock signals SYNCE_IN and PTP_IN. In other embodiments of the clock generator integrated circuit 100, a different type of controllable oscillator is used instead of the phase-locked loop 110. The phase-locked loop 110 is an inner phase-locked loop, which includes a phase / frequency detector (PFD) 112, a loop filter 114, and a voltage-controlled oscillator (VCO) 116. The voltage-controlled oscillator 116 can be implemented as a ring oscillator, an LC oscillator, or other suitable oscillator structure. The phase / frequency detector 112 receives the clock signal from the reference clock source 101, which includes a fixed source, such as a crystal oscillator, a temperature-controlled crystal oscillator, a microelectromechanical system (MEMS) oscillator, or other suitable low-jitter source. In at least one embodiment, the phase-locked loop 110 is coupled to the innermost phase-locked loop (not shown), which is locked to the local crystal oscillator.

[0023] Phase-locked loop 104 is an external phase-locked loop, which includes a phase / frequency detector 136, a loop filter 138, a frequency divider 140 (e.g., a fractional frequency divider), and uses an internal phase-locked loop 110 as a numerically controlled oscillator for phase-locked loop 104. The numerically controlled oscillator responds to the frequency divider value M. RThe divider value can be a fractional division value provided by loop filter 138. Phase / frequency detector 136 receives the clock signal SYNCE_IN and the feedback clock signal generated by divider 140, and can be based on a divided version of the clock signal CLKVCO. Phase / frequency detector 136 provides a phase error signal reflecting the difference between the clock signal SYNCE_IN and the feedback clock signal. The frequency of clock signal CLKVCO is determined by the frequency of clock signal SYNCE_IN and the divider value M. R Confirm that the value M of the frequency divider is... R The frequency divider 118 (e.g., a fractional frequency divider) is provided by the loop filter 138 and supplied to the feedback path of the inner phase-locked loop 110. The phase-locked loop 104 adjusts the frequency divider value M. R The frequency of the clock signal CLKVCO is matched to a multiple of the frequency of the clock signal SYNCE_IN implemented using the frequency divider 140 (e.g., frequency (SYNCE_IN) = frequency (CLKVCO) / M). A Due to the frequency division value M A It is adjusted based on the clock signal PTP_IN, therefore the frequency of the clock signal CLKVCO also tracks the clock signal PTP_IN.

[0024] Frequency divider 140 receives the adjusted frequency division value M. A +Δ MA (Based on the clock signal PTP_IN), the phase-locked loop 104 is configured as a numerically controlled oscillator conforming to the PTP standard protocol, and the frequency of the clock signal CLKVCO is stabilized for generating the PTP clock signals (e.g., output clock signals RF_OUTPUTS and PTP_OUTPUTS). The radio interface 170 (e.g., a general public radio interface) divides the clock signal CLKVCO to generate the output clock signal RF_OUTPUTS consistent with the target application. In at least one embodiment, another phase-locked loop (not shown) generates the adjusted division value M. A +Δ MA It also has a bandwidth an order of magnitude smaller than that of the phase-locked loop 104. In at least one embodiment, the radio interface 170 uses a high-performance integer divider. The output divider 166 (e.g., a fractional divider) is configured to generate an output clock signal OUTA that meets a target specification (e.g., PTP).

[0025] In at least one embodiment, phase-locked loop 110 has a bandwidth in the range of 30Hz-100Hz. In at least one embodiment, phase-locked loop 104 has a bandwidth set according to the PTP standard protocol (e.g., 2Hz-10Hz) and phase-locked loop 150 has a bandwidth set according to the SyncE standard protocol (e.g., 0.2Hz-1Hz) to suppress jitter on the clock signal SYNCE_IN and generate an output clock signal SYNCE_OUT with low phase noise (e.g., phase noise that meets the SyncE standard protocol). In at least one embodiment, the bandwidth of phase-locked loop 104 is at least one order of magnitude smaller than the bandwidth of phase-locked loop 150 (e.g., ten times smaller). However, the frequency division value M A Modulated at a rate similar to the bandwidth of phase-locked loop 150, and therefore, phase-locked loop 150 fails to filter out the frequency division value M performed by phase-locked loop 104 for the stable clock signal CLKVCO. A This adjustment can reduce the jitter performance of the output clock signal OUTB, for example, causing the output clock signal OUTB to exceed the SyncE standard protocol specifications (e.g., less than 0.2dB of peak drift transmission).

[0026] refer to Figure 3 In at least one embodiment, the clock generator integrated circuit 404 includes a nested phase-locked loop (PLL) architecture to generate a frequency-stable output using the clock signal PTP_IN. The clock generator integrated circuit 404 includes a PTP filter 450 cascaded with the nested PLL to regenerate the output clock signal SYNCE_OUT, unaffected by frequency division modulation of the internal clock signal used to generate frequency-stable output clock signals RF OUTPUTS and PTP OUTPUTS. In at least one embodiment, the clock generator integrated circuit 404 includes a multi-loop PLL that generates a low-jitter clock signal CLKVCO by tracking the clock signal SYNCE_IN and a signal based on the clock signal PTP_IN. For example, the PTP PLL 103 provides an adjusted frequency division value M generated based on the clock signal PTP_IN. A +Δ MA In at least one embodiment, phase-locked loop 110 receives a reference clock signal REFCLK from a reference clock source 101, which includes a fixed source, such as a crystal oscillator, a temperature-controlled crystal oscillator, a microelectromechanical system (MEMS) oscillator, or other suitable low-jitter source. In at least one embodiment, phase-locked loop 110 is coupled to an innermost phase-locked loop (not shown), which is locked to a local crystal oscillator.

[0027] Phase-locked loop 104 is an external phase-locked loop, which uses internal phase-locked loop 110 as a numerically controlled oscillator. Phase-locked loop 104 receives the adjusted frequency division value M. A+Δ MA (Generated based on the clock signal PTP_IN), the phase-locked loop 104 is configured as a numerically controlled oscillator conforming to the PTP standard protocol, and the frequency of the clock signal CLKVCO is stabilized for generating PTP clock signals (e.g., output clock signals RF_OUTPUTS and PTP_OUTPUTS). The radio interface 170 divides the clock signal CLKVCO to generate the output clock signal RF_OUTPUTS consistent with the target application. The output divider 166 (e.g., a fractional divider) is configured to generate a clock signal that meets the target specification (e.g., PTP). In at least one embodiment, the PTP filter 450 includes an updated fractional divider that receives updates from control logic 172, as further described below. In at least one embodiment, the PTP filter 450 includes a fractional divider configured in the phase-locked loop. As further described below, the phase-locked loop receives adjusted division values ​​from control logic 172. In at least one embodiment, the phase-locked loop of the PTP filter 450 has the same bandwidth settings as phase-locked loop 104.

[0028] The clock generator integrated circuit 404 uses only one high-frequency oscillator to generate output clock signals conforming to both the SyncE and PTP standards and performs integer division of the high-frequency oscillator. The clock generator integrated circuit 404 uses the same high-frequency voltage-controlled oscillator to generate two independent output clock signals. Therefore, compared to... Figure 1 Compared to other clock generator integrated circuits, the 404 clock generator integrated circuit achieves lower power consumption and clearer frequency-stable RF and PTP clock signals.

[0029] refer to Figure 4 In an exemplary embodiment, phase-locked loop 104 generates a PTP clock signal (e.g., frequency-stabilized output clock signals OUTA and RF OUTPUTS) and PTP filter 450 generates an output clock signal OUTB (e.g., output clock signal SYNCE_OUT). In at least one embodiment, PTP filter 450 includes only divider 168. In other embodiments, PTP filter 450 is configured with a phase-locked loop circuit including a disabled phase / frequency detector 158, a loop filter 160, and a divider 164 (e.g., a fractional divider) and an enabled divider 168 (e.g., a fractional divider). In at least one embodiment of clock generator integrated circuit 404, phase-locked loop 104 responds with the same first-order response and time constant Δ. MA Different step sizes (e.g., from 0.1 ppb to tens of ppm), frequency division value M A There are no rapid updates, such as via the PTP / 1PPS ring (not shown). For example, any individual adjustment Δ MAAll are less than + / -10 ppb, and the phase noise performance is essentially unaffected by the activity of the numerically controlled oscillator implemented using the frequency divider 140.

[0030] In at least one embodiment, the frequency divider 168 receives the clock signal CLKVCO and the adjusted frequency division value N. B +Δ NB Used for modulating the frequency division value M A Adjustment value Δ MA Known by control logic 172 or based on the adjusted frequency division value M by control logic 172 A +Δ MA Estimation. Control logic 172 uses the adjustment value Δ MA Frequency division value M A and frequency division value N B To generate the modulation frequency division value N B Adjustment value Δ NB This provides modulation of the output clock signal OUTB (i.e., a divided version of the clock signal CLKVCO), which is equal to and opposite to the modulation of CLKVCO. For example, if Δ is adjusted... MA If the clock signal CLKVCO is adjusted to increase by 15 parts per billion (ppb), then control logic 172 generates an adjustment Δ. NB The value of N adjusts the output clock signal OUTB to decrease by 15 ppb. However, the output clock signal OUTB responds to the division value N. B The adjustment ratio of the clock signal CLKVCO response to the frequency division value M A The rapid adjustment results in a phase error in the output clock signal OUTB relative to the clock signal SYNCE_IN (e.g., approximately 0.5 fs / s per ppb step) and introduces a frequency error on the output clock signal. The frequency error on the output is greater than that of the clock signal SYNCE_IN. Figure 5 This is converted into the time interval error on the output clock signal SYNCE_OUT. Figure 6 In at least one embodiment, multiple incremental steps (e.g., multiple updates of 1-3 ppb) are used to adjust the frequency division value N. B This makes the response of the clock signal CLKVCO smoother, similar to the response of OUTB.

[0031] refer to Figure 4 and Figure 7 In at least one embodiment, control logic 172 introduces a division value N into frequency divider 168. B The adjustment delay is used to compensate for the frequency division value M. A The update, thus from Figure 5 and Figure 6To reduce time interval error in the time interval error. In at least one embodiment, control logic 172 at time t MA The update of the frequency divider 140 is triggered to generate response 304 and the frequency division value N is set. B Update delay time T SYNC And at time t NB The update of frequency divider 168 is triggered to generate a response 302 for frequency divider 168, which results in zero net error in the phase of the output clock signal OUTB from frequency divider 168. In at least one embodiment, control logic 172 includes a processor executing firmware that controls the frequency division value M. A and frequency division value N B T between updates SYNC .

[0032] refer to Figure 3 and Figure 8 In at least one embodiment of the clock generator integrated circuit 404, it is not from the division value M A The update frequency division value N is updated at the time delay. B The PTP filter 450 includes a phase-locked loop (PLL) comprising a phase-frequency detector 158, a loop filter 160, a frequency divider 168, and a frequency divider 164, operatively coupled and configured to generate an output clock signal OUTB using a clock signal CLKVCO as an input reference clock signal. In at least one embodiment, the bandwidth of the PLP 104 is the same as the bandwidth of the PLP 450. In at least one embodiment, the PTP filter 450 is implemented by configuring the PLP in a virtual hold mode (i.e., a mode using an internally generated clock signal as a reference clock signal), where the PLP receives the clock signal CLKVCO from the phase / frequency detector 158 and the loop filter 160 generates a frequency division value N. B The clock signal CLKVCO is divided using frequency divider 168. Frequency divider 164 receives the adjusted division value M. B +Δ MB Its application adjusts Δ MB The adjustment Δ MB This causes the adjustment Δ to the clock signal CLKVCO. MA The responses are approximately equal and opposite, used to track the input to generate the output clock signal OUTB. This is because the frequency division value M is used for modulation. A Adjustment value Δ MA Known by control logic 172 or based on the adjusted frequency division value M by control logic 172 A +Δ MA Therefore, control logic 172 uses the adjustment value Δ. MB To generate the adjustment value Δ MB Used to modulate MB To provide an equal and opposite modulation of the output clock signal OUTB (i.e., a frequency-divided version of the clock signal CLKVCO). In at least one embodiment, the adjustment value Δ MB With adjustment value Δ MA The same amount. In other embodiments, control logic 172 is based on the adjustment value Δ MA Frequency division value M A Frequency division value N B and frequency division value M B To determine the adjustment value Δ MB .

[0033] refer to Figure 3 and Figure 9 In at least one embodiment of the clock generator integrated circuit 404, the frequency divider 166 generates an output clock signal OUTA, which is provided as a reference clock signal to the phase / frequency detector 158. In embodiments of the clock generator integrated circuit 404, the output clock signal OUTA is externally coupled from an output terminal (e.g., pin) of the clock generator integrated circuit 404 to an input terminal (e.g., pin) of the clock generator integrated circuit 404, thereby cascading the PTP filter 450 with the phase-locked loop 104. In an alternative embodiment, the clock generator integrated circuit 404 includes internal conductors for coupling the output clock signal OUTA as an input reference clock signal to the phase / frequency detector 158. Control logic 172 adjusts Δ... MB To adjust the frequency division value M B This effectively adjusts the frequency division value to weaken or eliminate the effect on the frequency division value M. A The amount of adjustment is used to generate an output clock signal OUTB that conforms to the target specification (e.g., the SyncE standard protocol). Figure 8 and Figure 9 The embodiments have at most negligible time interval errors on the output clock signal OUTBSyncE (e.g., time interval errors in the range of -70 picoseconds to 65 picoseconds, which are within the noise range and are negligible in at least one application).

[0034] Therefore, a clock generation technique with improved jitter and reduced output spuriousness has been described. This clock generation technique uses only a single high-frequency oscillator to generate a unique output clock signal and achieves lower power consumption and clearer RF and PTP clock signals (e.g., less spuriousness and reduced phase noise) compared to conventional clock generation techniques. The technique generates a frequency-stable output clock signal OUTA and an output clock signal RF OUTPUTS that tracks the clock signal CLKVCO, which is generated using a high-frequency oscillator. Although the reference clock signal used to generate the output clock signal OUTB is derived from the clock signal CLKVCO, the output clock signal OUTB does not track the clock signal CLKVCO.

[0035] Although Figure 4 , Figure 8 and Figure 9 An embodiment using analog signals has been described, but those skilled in the art will understand that the teachings herein can be used with digital signals. For example, in other embodiments, a reference clock signal input and a feedback clock signal are converted into a digital representation (e.g., a timestamp generated by a time-to-digital converter circuit) and provided to a digital phase / frequency detector and a digital loop filter.

[0036] The structures described herein can be implemented using software that executes on a processor (including firmware) or through a combination of software and hardware. As described herein, software may be encoded in at least one tangible (i.e., non-transitory) computer-readable medium. As referred to herein, a tangible computer-readable medium includes at least a disk, tape, or other magnetic, optical, or electronic storage medium. While circuitry and physical structures are generally assumed in the description of embodiments of the invention, it is well known that in modern semiconductor design and manufacturing, physical structures and circuitry can be embodied in a computer-readable description suitable for subsequent design, simulation, testing, or manufacturing phases. Structures and functions shown as discrete components in exemplary configurations may be implemented as combined structures or components. Various embodiments of the invention are contemplated to include circuits, systems of circuits, associated methods, and tangible computer-readable media having encodings of such circuits, systems, and methods thereon (e.g., VHSIC Hardware Description Language (VHDL), Verilog, GDSII data, Electronic Design Exchange Format (EDIF), and / or Gerber files), all as described herein and as defined in the appended claims. Furthermore, the computer-readable medium may store instructions and data that can be used to implement the invention. Instructions / data can be associated with hardware, software, firmware, or a combination thereof.

[0037] The description of the invention set forth herein is illustrative and not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention is described in embodiments conforming to the SyncE and PTP standard protocol specifications, the techniques described herein can be applied to generate output clock signals conforming to other protocols. The terms “first,” “second,” “third,” etc., used in the claims are for distinguishing different items in the claims unless the context clearly indicates otherwise, and do not otherwise indicate or imply any order in time, location, or quality. For example, “first received network signal” and “second received network signal” do not indicate or imply that the first received network signal occurred before the second received network signal in time. Variations and modifications may be made to the embodiments disclosed herein based on the description set forth herein without departing from the scope of the invention as set forth in the following claims.

Claims

1. A clock product, comprising: The first phase-locked loop circuit includes a first frequency divider, the first phase-locked loop circuit being configured to generate a first clock signal that tracks a first reference clock signal and a second reference clock signal, the first phase-locked loop circuit being controlled by a first frequency division value and an adjustment based on the first frequency division value of the first reference clock signal; as well as The circuit includes a second frequency divider configured to generate a second clock signal based on a first clock signal, a second frequency division value, and a second frequency division value adjustment. The second clock signal tracks a second reference clock signal, and the second frequency division value adjustment is based on and opposite to the first frequency division value adjustment. The first phase-locked loop circuit includes: An internal phase-locked loop (PLL) is configured to generate the first clock signal based on a local reference clock signal. The PLL includes a controllable oscillator and a feedback divider that responds to control signals. The external phase-locked loop (PLL) includes the first frequency divider and is configured to generate the control signal based on the second reference clock signal, the first clock signal, the first frequency division value, and the adjustment of the first frequency division value.

2. The clock product according to claim 1, wherein, The first phase-locked loop circuit includes: The output frequency divider is configured to generate a first output clock signal based on the first clock signal. The first frequency division value is modulated by adjusting the first frequency division value.

3. The clock product according to claim 1, in, The first clock signal is used to generate a frequency-stable output clock signal, and The second clock signal is a regenerated version of the second reference clock signal.

4. The clock product according to claim 1, further comprising: A phase-locked loop is configured to generate the first frequency division value adjustment; as well as The control logic is configured to generate the second frequency division value adjustment based on the first frequency division value adjustment.

5. The clock product according to claim 4, wherein, The control logic includes: Storage elements are configured to store instructions; and The processor is configured to execute the instructions to cause the clock product to generate the second division value.

6. The clock product according to claim 1, 2, 3, 4 or 5, in, The circuit includes a second phase-locked loop configured to use the first clock signal as a reference clock signal, and The second frequency divider is coupled to the output of the second phase-locked loop.

7. The clock product according to claim 1, 2, 3, 4 or 5, in, The circuit includes a second phase-locked loop configured to use the first clock signal as a reference clock signal, and The first bandwidth of the first phase-locked loop circuit is the same as the second bandwidth of the second phase-locked loop.

8. The clock product according to claim 1, 2, 3, 4 or 5, in, The circuit includes a second phase-locked loop, and The second frequency divider is included in the feedback path of the second phase-locked loop, and the second phase-locked loop is configured in virtual hold mode or cascaded with the first phase-locked loop circuit, and the second frequency divider receives the second frequency division value adjusted by the second frequency division value adjustment.

9. The clock product according to claim 1, 2, 3, 4 or 5, wherein, The circuit is a filter coupled to receive a clock signal based on the first clock signal.

10. The clock product according to claim 1, 2, 3, 4 or 5, wherein, The first frequency division value adjustment is equal to and opposite to the second frequency division value adjustment.

11. A method for generating a clock signal, comprising: A first clock signal that tracks the first reference clock signal and the second reference clock signal is generated by controlling a first phase-locked loop circuit including a first frequency divider circuit using a first frequency divider value and a first frequency divider value adjustment based on a first reference clock signal. as well as A second clock signal is generated based on the first clock signal, a second frequency division value, and a second frequency division value adjustment. The second clock signal tracks the second reference clock signal. The second frequency division value adjustment is based on the first frequency division value adjustment and is the opposite of the first frequency division value adjustment. The first clock signal is generated based on a local reference clock signal and a control signal. The control signal is generated based on the second reference clock signal, the first clock signal, the first frequency division value, and the adjustment of the first frequency division value.

12. The method according to claim 11, in, Generating the first clock signal includes modulating the first frequency division value using the first frequency division value adjustment, and Generating the second clock signal includes modulating the second division value using the second division value adjustment.

13. The method according to claim 11, in, The first clock signal is used to generate a frequency-stable output clock signal, and The second clock signal is a regenerated version of the second reference clock signal.

14. The method of claim 11, further comprising: Generate and adjust the first frequency division value; as well as The second frequency division value adjustment is generated based on the first frequency division value adjustment.

15. The method according to claim 11, 12, 13 or 14, wherein, Generating the second clock signal includes: The second phase-locked loop is configured in a virtual hold mode in response to an internally generated clock signal based on the first clock signal; The second frequency division value is adjusted by adjusting the second frequency division value to generate the adjusted second frequency division value; and The adjusted second frequency division value is provided to the second frequency divider circuit in the feedback path of the second phase-locked loop.

16. The method according to claim 15, wherein, The first bandwidth of the first phase-locked loop circuit is the same as the second bandwidth of the second phase-locked loop.

17. The method according to claim 11, 12, 13 or 14, further comprising: A first output clock signal is generated based on the first clock signal and the fractional frequency division value. Generating the second clock signal includes: The second frequency division value is adjusted by adjusting the second frequency division value to generate the adjusted second frequency division value; The adjusted second frequency division value is provided to the second frequency divider circuit in the feedback path of the second phase-locked loop circuit; and The first output clock signal is provided as the input to the second phase-locked loop circuit, thereby cascading the first phase-locked loop circuit and the second phase-locked loop circuit.

18. The method according to claim 11, 12, 13 or 14, wherein, Generating the second clock signal includes: The second frequency division value is adjusted by adjusting the second frequency division value to generate the adjusted second frequency division value; and The first clock signal is divided using the adjusted second division value.

19. The method according to claim 18, wherein, Generating the second clock signal includes: The adjustment of the second frequency division value is delayed by an interval sufficient to align the adjustment of the second frequency division value with the adjustment of the first frequency division value.

20. A method for generating a clock signal, comprising: A frequency-stable clock signal synchronized with the network clock signal and the second reference clock signal is generated by using a first frequency division value and adjusting based on the first frequency division value of the second reference clock signal, the frequency-stable clock signal tracking the frequency of the second reference clock signal; as well as The frequency-stable clock signal is filtered to regenerate the network clock signal as the output network clock signal. The filtering uses a second frequency divider that responds to a second frequency division value modulated by a second frequency division value adjustment, the second frequency division value adjustment being based on and opposite to the first frequency division value adjustment. The frequency-stable clock signal is generated based on a local reference clock signal and a control signal, and The control signal is generated based on the second reference clock signal, the frequency-stable clock signal, the first frequency division value, and the adjustment of the first frequency division value.

Images