Apparatus and method including multi-level command and address signals

Abstract

Multi-level command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. The use of multi-level signals CA signals can allow the same number of command and / or address space to be represented using fewer signals, or a greater number of command and / or address space to be represented using the same number of multi-level CA signals, as compared to binary signals. The number of external command / address terminals can be reduced without reducing the set of command and / or address space. Alternatively, the number of external terminals can be maintained, but an expanded set of command and / or address space is provided.

Description

[0001] Cross-references to related applications

[0002] This application claims the right of filing of U.S. Provisional Application No. 62 / 854,525, filed May 30, 2019. This application is incorporated herein by reference in its entirety and for all purposes. Background Technology

[0003] Semiconductor memories are used in many electronic systems to store data that can be retrieved at a later time. As electronic systems increasingly demand faster speeds, larger memory capacities, and additional features, semiconductor memories are constantly being developed to meet these changing needs, enabling faster access, storage of more data, and the inclusion of new features. The goal of each generation of semiconductor memory development is to improve the performance of memory in electronic systems.

[0004] Semiconductor memories are typically controlled by providing command signals, address signals, and clock signals to the memory. For example, various signals can be provided by a memory controller. Command and address signals contain memory commands and memory addresses that control the semiconductor memory to perform various memory operations at memory locations corresponding to memory addresses, such as read operations for retrieving data from memory and write operations for storing data into memory. Reading and writing data can be provided between the controller and the memory at a known timing relative to one or more clock signals, such as system clock signals CK and CKF.

[0005] As semiconductor memories are developed to offer greater performance, for example by increasing memory capacity and the number of commands and features, the number of memory commands and addresses can increase accordingly. Consequently, the amount of memory control information in the form of command and address signals can also increase, typically requiring additional external terminals to receive these signals. However, adding external terminals increases the size of the semiconductor memory die and circuit complexity, both of which may be undesirable. Future semiconductor memory designs will benefit from solutions that overcome the design limitations imposed by current methods of providing memory control information via command and address signals. Summary of the Invention

[0006] Apparatus and methods incorporating multi-level command and address signals are disclosed. For example, an example apparatus includes an address decoder configured to receive address signals and provide decoded addresses, and a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations. The example apparatus further includes command / address input circuitry configured to receive the multi-level command and address signals and provide output signals representing the values ​​of the multi-level command and address signals to the address decoder and the command decoder. Multiple command and address signals represent more than one bit.

[0007] Another example device includes an address decoder configured to receive address signals and provide decoded addresses, and a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations. The example device further includes command / address input circuitry configured to receive a plurality of multi-level command and address signals and provide output signals representing the values ​​of the plurality of multi-level command and address signals to the address decoder and the command decoder. Each multi-level command and address signal has a corresponding voltage corresponding to one of three or more distinct values.

[0008] Another example device includes an address decoder configured to receive address signals and provide decoded addresses, and a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations. The example device further includes command / address input circuitry configured to receive a plurality of multi-level command and address signals and provide output signals to the address decoder and the command decoder. The output signals include signals representing binary values ​​and signals representing non-binary values.

[0009] Another example device includes an address decoder configured to receive address signals and provide decoded addresses, and a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations. The example device further includes command / address input circuitry configured to receive a plurality of multilevel command and address signals and provide output signals to the address decoder and the command decoder. The multilevel command and address signals represent a command structure, which includes command operands for identifying a memory command and further includes memory address information for identifying the memory location pointed to by the memory command. The command operands are represented by a first portion of the plurality of multilevel command and address signals, and each of the first portion of the multilevel command and address signals represents a non-binary value. The address information is represented by a second portion of the plurality of multilevel command and address signals, and the second portion of the multilevel command and address signals represents bits of the memory address information.

[0010] Another example device includes an address decoder configured to receive address signals and provide decoded addresses, and a command decoder configured to receive internal command signals and provide internal control signals for performing memory operations. The example device further includes command / address input circuitry configured to receive a plurality of multilevel command and address signals and provide output signals to the address decoder and the command decoder. The multilevel command and address signals represent a command structure, which includes command operands for identifying a memory command and further includes memory address information for identifying the memory location pointed to by the memory command. The command operands are represented by a first portion of the plurality of multilevel command and address signals, and each of the first portion of the multilevel command and address signals represents a non-binary value. The address information is represented by a second portion of the plurality of multilevel command and address signals, and the second portion of the multilevel command and address signals represents bits of the memory address information.

[0011] Another example device includes a command and address bus, a controller, and a memory system. The controller is configured to provide multi-level command and address signals to the command and address bus. Each of the multi-level command and address signals has a corresponding voltage corresponding to one of at least three or more distinct values. The memory system is coupled to the controller via the command and address bus and includes multiple memories. Each memory is configured to receive the multi-level command and address signals and decode them to represent a binary value representing a memory address.

[0012] Another example device includes a memory configured to receive a plurality of multilevel command and address signals representing a command structure including a command operand and a memory address. The multilevel command and address signals have corresponding voltages corresponding to non-binary values. The memory includes means for providing an internal command signal representing the command operand based on the multilevel command and address signals, and means for providing an internal address signal representing the memory address. The memory address includes a plurality of bits represented by the internal address signal. The memory further includes means for performing a memory operation on a memory location based on the internal address signal based on the internal command signal.

[0013] An example method includes receiving, at a memory location, a plurality of multilevel command and address signals representing a command structure comprising a command operand and a memory address. The multilevel command and address signals have corresponding voltages corresponding to one of at least three different voltages. Each of the at least three different voltages corresponds to a different value. The example method further includes: providing an internal command signal representing the command operand based on the multilevel command and address signals; providing an internal address signal representing the memory address, the memory address comprising a plurality of bits represented by the internal address signal; and performing a memory operation on a memory location based on the internal address signal based on the internal command signal. Attached Figure Description

[0014] Figure 1 This is a block diagram of a system according to an embodiment of the present disclosure.

[0015] Figure 2 This is a block diagram of an apparatus according to an embodiment of the present disclosure.

[0016] Figure 3 This is a block diagram of a multilevel input buffer and a command and address input decoder circuit according to embodiments of the present disclosure.

[0017] Figure 4 This is a schematic diagram of a multilevel input buffer circuit according to an embodiment of the present disclosure.

[0018] Figure 5 This is a diagram showing the relationship between a three-level input signal and the logic level of an output signal representing the value of the three-level input signal according to an embodiment of the present disclosure.

[0019] Figure 6 This is a diagram showing the relationship between the voltage of a three-level input signal and the logic value represented by the three-level input signal according to an embodiment of the present disclosure.

[0020] Figure 7This is a schematic diagram of a multilevel input buffer including a pair of multilevel input buffer circuits according to an embodiment of the present disclosure.

[0021] Figure 8 This is a diagram showing the relationship between two three-level input signals, an output signal, and a decoding signal according to an embodiment of this disclosure.

[0022] Figure 9 This is a timing diagram illustrating various signals for receiving commands and / or addresses at a semiconductor device, according to embodiments of the present disclosure.

[0023] Figure 10 It is a command structure according to embodiments of the present disclosure, such as a diagram of commands and addresses for multi-level commands and address signals.

[0024] Figure 11 This is a block diagram of a multilevel input buffer, a command and address (CA) input decoder circuit, and a signal latch according to embodiments of the present disclosure.

[0025] Figure 12 It is a command structure according to embodiments of the present disclosure, such as a diagram of commands and addresses for multi-level commands and address signals. Detailed Implementation

[0026] Apparatus and methods for providing information between a controller and a memory system using multilevel signals are described. In some embodiments of this disclosure, multilevel command and address (CA) signals are used to provide command and memory addresses from the controller to the memory system. For example, using multilevel signals for CA signals can allow the same number of commands and / or address spaces to be represented using fewer signals (compared to binary signals), or the same number of signals to represent a larger number of commands and / or address spaces. In the former instance, the number of external terminals (e.g., command / address terminals) can be reduced without reducing the set of commands and / or address spaces. In the latter instance, the number of external terminals can be maintained, but an expanded set of commands and / or address spaces can be provided.

[0027] Figure 1This is a block diagram of system 100 according to an embodiment of the present disclosure. System 100 includes a controller 10 and a memory system 105. Memory system 105 includes memories 110(0)-110(p) (e.g., “device 0” to “device p”), where p is a non-zero integer. In some embodiments of the present disclosure, memory 110 may be dynamic random access memory (DRAM), such as low-power dual data rate (LPDDR) DRAM. Memories 110(0)-110(p) are each coupled to command / address, data, and clock buses. Each bus may include one or more signal lines on which signals are provided. Controller 10 and memory system 105 communicate via several buses. For example, command and address (CA) signals are received by memory system 105 on command / address bus 115, and data is provided between controller 10 and memory system 105 via data bus 125. Various clock signals may be provided between controller and memory system 105 via clock bus 130. The clock bus 130 may include signal lines for providing the controller 10 with system clock signals CK and CKF received by the memory system 105, data clock signals WCK and WCKF received by the memory system 105, and access data clock signal RDQS provided by the memory system 105.

[0028] The CK and CKF signals provided by controller 10 to memory system 105 are used for timing the provision and reception of commands and addresses. The WCK and WCKF signals, as well as the RDQS signal, are used for timing the provision of data. The CK and CKF signals are complementary, and the WCK and WCKF signals are also complementary. The WCK and WCKF signals provided by controller 10 to memory system 105 can be synchronized with the CK and CKF signals also provided by controller 10 to memory system 105.

[0029] The controller 10 provides commands to the memory system 105 to perform memory operations. Non-limiting examples of memory commands include timing commands for controlling the timing of various operations, access commands for accessing the memory, such as read commands for performing read operations and write commands for performing write operations. The command signals provided by the controller 10 to the memory system 105 further include selection signals (e.g., chip select CS signals CS0, CS1, CSP). When all memories 110 are provided with command, address, data, and clock signals, selection signals provided on the corresponding selection signal lines are used to select which memory 110 will respond to the command and perform the corresponding operation. In some embodiments of this disclosure, a corresponding selection signal is provided to each memory 110 of the memory system 105. The controller 10 provides a valid selection signal to select the corresponding memory 110. When the corresponding selection signal is valid, the corresponding memory 100 is selected to receive the command and address provided on the command / address bus 115.

[0030] The CA signal provided by controller 10 to memory system 105 can be a multi-level signal representing a command and an address. The multi-level CA signal has a corresponding voltage level corresponding to one of a plurality of different voltage ranges. Each voltage range in the different voltage ranges corresponds to a corresponding value. Memory system 105 uses combinations of values ​​represented by the multi-level CA signal to identify commands issued by controller 10 and the memory addresses to which those commands point. In some embodiments of this disclosure, the CA signal may have a corresponding voltage level corresponding to one of three different voltage ranges (e.g., three-level signaling). In other embodiments of this disclosure, the CA signal may have a corresponding voltage level corresponding to one of four different voltage ranges (e.g., four-level signaling). This disclosure is not intended to be limited to three-level or four-level signaling, and more generally, is not intended to be limited to any particular number of level signaling.

[0031] In operation, when the controller 10 provides an activation command and a read command, along with an associated address, to the memory system 105, the memory 110 selected by the selection signal receives the read command and the associated address and performs a read operation to provide the controller 10 with read data from the memory location corresponding to the associated address. When preparing the selected memory 110 to provide read data to the controller 10, the controller provides valid WCK and WCKF signals to the memory system 105. The WCK and WCKF signals can be used by the selected memory 110 to generate an access data clock signal RDQS. The RDQS signal is provided by the memory 110 performing the read operation to the controller 10 for timing the provision of read data to the controller 10. The controller 10 can use the RDQS signal to receive the read data.

[0032] When the controller 10 provides an activation command and a write command, along with an associated address, to the memory system 105, the memory 110 selected by the selection signal receives the command and the associated address and performs a write operation to write data from the controller 10 to the memory location corresponding to the associated address. Before the selected memory 110 is prepared to receive write data from the controller 10, the controller provides valid WCK and WCKF signals to the memory system 105. The WCK and WCKF signals can be used by the selected memory 110 to generate internal clock signals for timing the operation of the circuitry receiving the write data. Data is provided by the controller 10, and the selected memory 110 receives the write data according to the WCK and WCKF signals; the write data is written to the memory corresponding to the memory address.

[0033] Figure 2 This is a block diagram of an apparatus according to embodiments of the present disclosure. The apparatus may be a semiconductor device 200 and will be referred to as such. In some embodiments, the semiconductor device 200 may include, but is not limited to, memory, such as, for example, LPDDR memory integrated into a single semiconductor die. In some embodiments of the present disclosure, the semiconductor die may contain only the semiconductor device 200. In some embodiments of the present disclosure, the semiconductor die may include the semiconductor device 200 with other systems integrated on the same semiconductor die embedded therein. In some embodiments of the present disclosure, the semiconductor device 200 may include... Figure 1 In the memory system 105. For example, each memory in memory 110 may contain a semiconductor device 200.

[0034] Semiconductor device 200 may include memory array 250. Memory array 250 includes multiple memory banks, each containing multiple word lines WL, multiple bit lines BL, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple bit lines BL. The selection of word lines WL is performed by row decoder 240, and the selection of bit lines BL is performed by column decoder 245. A sense amplifier (SAMP) is positioned relative to its corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which in turn is coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) acting as a switch.

[0035] Semiconductor device 200 may employ multiple external terminals (e.g., pins), including command / address terminals coupled to a command / address bus to receive command and address signals CA. The CA signals may be multi-level signals representing commands and addresses. For example, the CA signals may represent commands and addresses having a command structure that includes command operands and memory addresses.

[0036] Command / address input circuit 205 receives a CA signal at the command / address terminal and provides an address signal and a command signal ICMD to address decoder 212 and command decoder 215, respectively. The address signal and command signal are based on a combination of the values ​​of the multi-level CA signal received by command / address input circuit 205. Address decoder 212 receives the address signal and provides the decoded row address signal XADD to row decoder 240 and the decoded column address signal YADD to column decoder 245. Address decoder 212 also provides a bank address signal BADD to row decoder 240 and column decoder 245. Command decoder 215 includes circuitry for decoding the command signal ICMD to generate various internal signals and commands for performing operations. For example, command decoder 215 provides internal signals to control the circuitry of semiconductor device 200 to access memory array 250 based on the command signal, such as reading data from memory array 250 or writing data to memory array 250 based on a read command or write command, respectively.

[0037] The semiconductor device 200 may further include a selection terminal for receiving the selection signal CS, a clock terminal for receiving the clock signals CK and CKF, a data clock terminal for receiving the data clock signals WCK and WCKF, data terminals DQ and RDQS, power supply terminals VDD, VSS and VDDQ, and a ZQ calibration terminal (ZQ).

[0038] The selection terminal may be provided with a selection signal CS for selecting the semiconductor device 200 to receive the CA signal. For example, when the CS signal is valid (e.g., a valid high logic level), the semiconductor device 200 is activated to respond to the command / address bus (e.g., ...). Figure 1 The CA signal is received on the command / address bus 115.

[0039] When an activation command is received and promptly provided to the memory bank and row address, and a read command is received and promptly provided to the memory bank and column address, read data is read from the memory array 250 specified by the address. The command / address input circuit 205 provides the activation and read commands to the command decoder 215 and the address to the address decoder 212. The command decoder 215 provides internal commands to the input / output circuit 260, and the address decoder 212 provides the decoded address to the row and column decoders, thereby outputting the read data from the memory specified by the address to the outside via the read / write amplifier 255 and the input / output circuit 260 from the data terminal DQ according to the RDQS clock signal.

[0040] When an activation command is received and promptly provided to the memory bank and row address, and a write command is received and promptly provided to the memory bank and column address, the write data provided to the data terminal DQ is written to the memory array 250 specified by the address. The command / address input circuit 205 provides the activation and write commands to the command decoder 215 and the address to the address decoder 212. The command decoder 215 provides the internal command to the input / output circuit 260, and the address decoder 212 provides the decoded address to the row and column decoders, such that the write data is received by the data receiver in the input / output circuit 260 and provided to the memory of the memory array 250 specified by the address through the input / output circuit 260 and the read / write amplifier 255.

[0041] An external clock signal is provided to the clock terminal and the data clock terminal. The external clock signals CK, CKF, WCK, and WCKF can be provided to the clock input circuit 220. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. When enabled, the input buffer included in the clock input circuit 220 receives the external clock signal. For example, when enabled by the CKE signal from the command decoder 215, the input buffer receives the CK and CKF signals, and when enabled by the WCKIBEN signal from the command decoder 215, the input buffer receives the WCK and WCKF signals. The clock input circuit 220 can receive the external clock signal to generate internal clock signals ICK, IWCK, and IWCKF. The internal clock signals ICK, IWCK, and IWCKF are provided to the internal clock circuit 230. The internal clock circuit 230 includes circuitry that provides various phase and frequency-controlled internal clock signals IWCKn based on the received internal clock signals. The multiphase clock signal IWCKn can be provided to the input / output circuit 260 to control the output timing for reading data and the input timing for writing data.

[0042] Power supply potentials VDD and VSS are provided to the power supply terminals. These power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 270. The internal voltage generator circuit 270 generates various internal potentials VPP, VOD, VARY, VPERI, etc., and a reference potential ZQVREF based on the power supply potentials VDD and VSS. The internal potential VPP is mainly used in the line decoder 240, the internal potentials VOD and VARY are mainly used in the sense amplifier contained in the memory array 250, and the internal potential VPERI is used in many other circuit blocks. The reference potential ZQVREF is used in the ZQ calibration circuit 265.

[0043] The power supply terminal also provides a power supply potential VDDQ. This power supply potential VDDQ, together with the power supply potential VSS, is provided to the input / output circuit 260. In an embodiment of this disclosure, the power supply potential VDDQ can be the same potential as the power supply potential VDD. In another embodiment of this disclosure, the power supply potential VDDQ can be a different potential from the power supply potential VDD. However, using a dedicated power supply potential VDDQ for the input / output circuit 260 prevents power supply noise generated by the input / output circuit 260 from propagating to other circuit blocks.

[0044] The calibration terminal ZQ is connected to the ZQ calibration circuit 265. When activated via the ZQ calibration command ZQ_com, the ZQ calibration circuit 265 performs a calibration operation with reference to the impedance of RZQ and the reference potential ZQVREF. The impedance code ZQCODE obtained through the calibration operation is provided to the input / output circuit 260, and thus specifies the impedance of the output buffer (not shown) contained in the input / output circuit 260.

[0045] Figure 3 This is a block diagram of a multilevel input buffer 310 and a command and address input decoder circuit 320 according to embodiments of the present disclosure. In some embodiments of the present disclosure, the multilevel input buffer 310 and the command and address input decoder circuit 320 may be included in... Figure 2 In the command / address input circuit 205 of the semiconductor device 200.

[0046] The multilevel input buffer 310 includes multilevel input buffer circuits 315(0)-315(n), where n is a non-zero integer. Each input buffer circuit in the input buffer circuits 315 receives a corresponding command / address (CA) signal CA0-CAn. For example, input buffer circuit 315(0) receives command / address signal CA0, input buffer circuit 315(1) receives command / address signal CA1, and so on. Each of the CA signals can be provided on a corresponding command / address terminal. For example, in some embodiments of this disclosure, the corresponding terminals are... Figure 2 The corresponding command / address terminal in the command / address terminals of the semiconductor device 200.

[0047] In some embodiments of this disclosure, the CA signal is a multi-level input signal. For example, as detected by input buffer circuit 315, the command / address signal has a corresponding voltage level corresponding to one of a plurality of different voltage ranges. In some embodiments of this disclosure, the CA signal may have a corresponding voltage level corresponding to one of three different voltage ranges (e.g., three-level signaling). In other embodiments of this disclosure, the command / address signal may have a corresponding voltage level corresponding to one of four different voltage ranges (e.g., four-level signaling). This disclosure is not intended to be limited to three-level or four-level signaling, and more generally, is not intended to be limited to any particular number of level signaling.

[0048] Input buffer circuit 315 provides output signals CAn_H and CAn_L with logic levels based on the corresponding CAn signals. For example, input buffer circuit 315(0) provides CA0_H and CA0_L signals with logic levels based on the voltage level of the CA0 signal, input buffer circuit 315(1) provides CA1_H and CA1_L signals with logic levels based on the voltage level of the CA1 signal, and so on.

[0049] In some embodiments of this disclosure, the CAn_H and CAn_L signal pairs may have corresponding logic levels representing values ​​based on the respective CA signals. For example, a low logic level CAn_H signal and a low logic level CAn_L signal (i.e., "00") may represent the value 0; a low logic level CAn_H signal and a high logic level CAn_L signal (i.e., "01") may represent the value 1; and a high logic level CAn_H signal and a high logic level CAn_L signal (i.e., "11") may represent the value 2. The values ​​represented by the CAn_H and CAn_L signals may correspond to the values ​​of the corresponding CA signals.

[0050] Output signals CAn_H and CAn_L can be provided to command and address input decoder circuit 320. Input decoder circuit 320 provides decoded signals CAO0-CAO2 with corresponding logic levels based on the logic levels of the CAn_H and CAn_L signals. For example, input decoder circuit 320 can provide decoded signals CAO0-CAO2 with corresponding logic levels based on the logic levels of the CA0_H and CA0_L and CA1_H and CA1_L signals provided by input buffer circuit 315(0) and input buffer circuit 315(1), respectively. In some embodiments of this disclosure, such as Figure 8As shown, the input decoder circuit 320 can provide decoding signals CAO0-CAO2 based on the corresponding logic levels of the CA0_H and CA0_L signals, as well as the CA1_H and CA1_L signals, which will be described below. CAO0-CAO2 can represent three bits of information, with each decoding signal corresponding to one bit.

[0051] The decoded signals CAO0-CAO2 can be provided to the address decoder and / or command decoder accordingly (e.g., Figure 2 (Address decoder 212 and / or command decoder 215). As previously described, the address decoder and / or command decoder receive signals and provide internal address and control signals to perform operations corresponding to the CA signal.

[0052] As previously described, in some embodiments of this disclosure, input buffer circuit 315 receives multi-level CA signals. Multi-level signals can be used to represent more information than, for example, binary (i.e., two-level) signals with two different voltage levels to represent one bit of information. In contrast, in an example comprising two input buffer circuits 315 (e.g., input buffer circuits 315(0) and 315(1)) each receiving a corresponding three-level CA signal, two multi-level signals can represent three bits of data (compared to two bits representing a binary signal). Scaled down from two input buffer circuits 315 to, for example, six input buffer circuits 315 each receiving a corresponding three-level CA signal, six signals can represent nine bits of data compared to six bits of data for six binary signals.

[0053] For example, using multi-level signals for CA signals allows for representing the same number of commands and / or address spaces with fewer signals (compared to binary signals), or representing a larger number of commands and / or address spaces with the same number of signals. In the former instance, the number of external terminals (e.g., command / address terminals) can be reduced without decreasing the set of commands and / or address spaces. In the latter instance, the number of external terminals can be maintained, but an expanded set of commands and / or address spaces can be provided.

[0054] Figure 4 This is a schematic diagram of a multilevel input buffer circuit 400 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the multilevel input buffer circuit 400 may be included... Figure 3 In the multi-level input buffer circuit 315.

[0055] The multi-level input buffer circuit 400 includes buffer circuit 410 and buffer circuit 420. Buffer circuit 410 is provided with a (high) reference voltage Vref_H, and buffer circuit 420 is provided with a (low) reference voltage Vref_L. The Vref_H voltage is greater than the Vref_L voltage. Buffer circuits 410 and 420 are also provided with a command / address signal CA. Buffer circuit 410 provides an output signal CA_H based on the CA signal and the Vref_H voltage, and buffer circuit 420 provides an output signal CA_L based on the CA signal and the Vref_L voltage. For example, buffer circuit 410 provides a CA_H signal with a logic level relative to the Vref_H voltage based on the CA signal, and buffer circuit 420 provides a CA_L signal with a logic level relative to the Vref_L voltage based on the CA signal.

[0056] In the example operation, when the voltage of the CA signal is greater than the Vref_H voltage, the buffer circuit 410 provides a high logic level CA_H signal, and when the voltage of the CA signal is less than the Vref_H voltage, the buffer circuit provides a low logic level CA_H signal; and when the voltage of the CA signal is greater than the Vref_L voltage, the buffer circuit 420 provides a high logic level CA_L signal, and when the voltage of the CA signal is less than the Vref_L voltage, the buffer circuit provides a low logic level CA_L signal.

[0057] The decoder circuit can be accessed via commands and addresses (e.g., Figure 3 The command and address input decoder circuit 320) decodes the resulting CA_H and CA_L signals together with other CA_H and CA_L signals to provide the decoded output signal.

[0058] Figure 5 This is a diagram showing the relationship between a three-level input signal and the logic level of an output signal representing the value of the three-level input signal according to embodiments of the present disclosure. In some embodiments of the present disclosure, Figure 5 The relationship can be derived from Figure 4 A multi-level input buffer circuit 400 is provided. In such embodiments of this disclosure, the three-level input signal may be represented by a command / address signal CA.

[0059] The multilevel input buffer circuit 400 will be described with reference to it. Figure 5 The relationship between the three-level input signals and logic values.

[0060] When the voltage of the CA signal is less than the (low) reference voltage Vref_L (and necessarily less than the (high) reference voltage Vref_H), buffer circuit 420 provides a low logic level CA_L signal (i.e., "0"), and buffer circuit 410 also provides a low logic level CA_H signal (i.e., "0"). "00" for both CA_H and CA_L signals corresponds to the value 0. Therefore, a multi-level CA signal less than Vref_L and Vref_H corresponds to the value 0 and can be represented by "00" for both CA_H and CA_L signals.

[0061] When the voltage of the CA signal is less than the Vref_H voltage but greater than the Vref_L voltage, buffer circuit 420 provides a low logic level CA_L signal (i.e., "0"), and buffer circuit 410 provides a high logic level CA_H signal (i.e., "1"). "10" in both the CA_H and CA_L signals corresponds to the value 1. Therefore, a multi-level CA signal less than Vref_H and greater than Vref_L corresponds to the value 1 and can be represented by "10" in both the CA_H and CA_L signals.

[0062] When the voltage of the CA signal is greater than the Vref_H voltage (and necessarily greater than the Vref_L voltage), buffer circuit 420 provides a high logic level CA_L signal (i.e., "1"), and buffer circuit 410 also provides a high logic level CA_H signal (i.e., "1"). The "11" of the CA_H and CA_L signals corresponds to the value 2. Therefore, a multi-level CA signal greater than Vref_L and Vref_H corresponds to the value 2 and can be represented by the "11" of the CA_H and CA_L signals.

[0063] As shown in the previous example, a three-level CA signal can represent three different values ​​(e.g., values ​​0, 1, and 2). Each of these values ​​can be represented by the logic levels of the output signals CA_H and CA_L pair.

[0064] Figure 6 This is a graph showing the relationship between the voltage of a three-level input signal and the logic value represented by the three-level input signal according to embodiments of this disclosure. In some embodiments of this disclosure, Figure 6 The relationship can be represented Figure 5 The relationship between the three-level signals and logic values. In some embodiments of this disclosure, Figure 6 The relationship can be derived from Figure 4 A multi-level input buffer circuit 400 is provided. In such embodiments of this disclosure, Figure 6 The voltage shown can represent the voltage of the command / address signal CA.

[0065] Figure 6 The relationship between the voltage and logic value of the three-level input signal will be referenced. Figure 5 It is described by the relationship between the three-level signal and the logic value.

[0066] A three-level input signal whose voltage is less than the (low) reference voltage Vref_L (and is also necessarily less than the (high) reference voltage Vref_H) corresponds to the logic value 0.

[0067] A three-level input signal with a voltage less than Vref_H but greater than Vref_L corresponds to a logic value of 1.

[0068] A three-level input signal with a voltage greater than Vref_H (and necessarily greater than Vref_L) corresponds to a logic value of 2.

[0069] Figure 7 This is a schematic diagram of a multilevel input buffer 700 comprising a pair of multilevel input buffer circuits 715(0) and 715(1) according to embodiments of the present disclosure. In some embodiments of the present disclosure, Figure 2 The command / address input circuit 205 of the semiconductor device 200 may include multi-level input buffer circuit pairs 715(0) and 715(1). In some embodiments of this disclosure, Figure 3 The multilevel input buffer 310 may include multilevel input buffer circuit pairs 715(0) and 715(1).

[0070] Multilevel input buffer circuit 715(0) includes buffer circuit 710(0) and buffer circuit 720(0). Buffer circuit 710(0) is provided with a (high) reference voltage Vref_H, and buffer circuit 720(0) is provided with a (low) reference voltage Vref_L. The voltage Vref_H is greater than the voltage Vref_L. Buffer circuits 710(0) and 720(0) are also provided with a command / address signal CA0. Multilevel input buffer circuit 715(1) includes buffer circuit 710(1) and buffer circuit 720(1). Buffer circuit 710(1) is provided with a voltage Vref_H, and buffer circuit 720(1) is provided with a voltage Vref_L. Buffer circuits 710(1) and 720(1) are also provided with a command / address signal CA1. The CA0 and CA1 signals can be multilevel input signals (e.g., three-level signals).

[0071] Buffer circuit 710(0) provides an output signal CA0_H based on the CA0 signal and the Vref_H voltage, and buffer circuit 720(0) provides an output signal CA0_L based on the CA0 signal and the Vref_L voltage. For example, buffer circuit 710(0) provides a CA_H signal having a logic level relative to the Vref_H voltage based on the CA0 signal, and buffer circuit 720(0) provides a CA_L signal having a logic level relative to the Vref_L voltage based on the CA0 signal.

[0072] Buffer circuit 710(1) provides output signal CA1_H based on CA1 signal and Vref_H voltage, and buffer circuit 720(1) provides output signal CA1_L based on CA1 signal and Vref_L voltage. Buffer circuits 710(1) and 720(1) can operate in a manner similar to the previously described buffer circuits 710(0) and 720(0).

[0073] As previously referenced Figure 3 In the described example, where two input buffer circuits each receive a corresponding three-level command / address signal, the two signals can represent three bits of data. In such embodiments of this disclosure, a pair of input buffer circuits may be included for each pair of CA signals.

[0074] Example operation of two input buffer circuits receiving corresponding three-level command / address signals will be described with reference to multi-level input buffer circuit pairs 715(0) and 715(1). In the example operation, the CA0_H and CA0_L signals from input buffer circuit 715(0) and the CA1_H and CA1_L signals from input buffer circuit 715(1) are provided to the command and address input decoder circuits, for example, Figure 3 The command and address input decoder circuit 320. As previously described, the command and address input decoder circuit provides decoded signals CAO0, CAO1, and CAO2 representing three bits of data.

[0075] In some embodiments of this disclosure, two three-level command / address (CA) signals may be provided by a pair of multi-level input buffer circuits (e.g., multi-level input buffer circuits 715(0) and 715(1)) and a command and address input decoder circuit (e.g., command and address input decoder circuit 320) to provide the following three bits of information CAO0-CAO2:

[0076] Example of CA decoding:

[0077] When CA1=0→CAO2=L, CAO1=CA0_H, CAO0=CA0_L

[0078] When CA1=2→CAO2=H, CAO1=CA0_H, CAO0=CA0_L

[0079] When CA1 = 1 → CAO2 = CA0_H, CAO1 = H, CAO0 = L

[0080] Figure 8 This diagram illustrates the relationship between two three-level input signals CA1 and CA0, output signals CA1_H and CA1_L, CA0_H and CA0L, and decoding signals CAO2-CAO0, according to embodiments of this disclosure. The decoding signals CAO2-CAO0 can represent three bits of data. Figure 8 The relationship can be provided by the previously described CA decoding example.

[0081] In some embodiments of this disclosure, Figure 8 The relationship can be derived from Figure 7 The multi-level input buffer circuits 715(0) and 715(1) and Figure 3 The command and address input decoder circuit 320 provides this information.

[0082] The multilevel input buffer circuits 715(0) and 715(1) and the command and address input decoder circuit 320 will be described in reference. Figure 8 The relationship.

[0083] Figure 8 The diagram shows CA1 and CA0 signals that can have one of three different values ​​(e.g., 0, 1, or 2), and output signals CA1_H and CA1_L and CA0_H and CA0_L provided by input buffer circuits 715(1) and 715(0), respectively. The output signals can have a low logic level "L" (e.g., bit "0") or a high logic level "H" (e.g., bit "1").

[0084] In one instance, such as Figure 8 As shown in the relationship, when the voltage of the CA1 signal corresponds to value 0 and the voltage of the CA0 signal corresponds to value 1, the resulting high and low output signals are CA1_H = L and CA1_L = L, and CA0_H = L and CA0_L = H (provided, for example, by multilevel input buffer circuit 715(1) and multilevel input buffer circuit 715(0)). In another example, when the voltage of the CA1 signal corresponds to value 2 and the voltage of the CA0 signal corresponds to value 1, the resulting high and low output signals are CA1_H = H and CA1_L = H, and CA0_H = L and CA0_L = H. Figure 8 Other combinations of the CA1 and CA0 signals and their corresponding output signals CA1_H and CA1_L, as well as CA0_H and CA0_L, are also shown.

[0085] like Figure 8 As shown, the output signals CA1_H and CA1_L, as well as CA0_H and CA0_L, can be decoded by the command and address input decoder circuit 320 to provide decoded signals CAO2, CAO1, and CAO0. The decoded signals can have a low logic level "L" (e.g., "0" bit) or a high logic level "H" (e.g., "1" bit).

[0086] In one instance, such as Figure 8 As shown in the relationship, when CA1_H = L and CA1_L = L, and CA0_H = L and CA0_L = H (this is one of the previously described examples), the corresponding decoded signals are CAO2 = L, CAO1 = L, and CAO0 = H. In another example, when CA1_H = H and CA1_L = H, and CA0_H = L and CA0_L = H (this is another previously described example), the corresponding decoded signals are CAO2 = H, CAO1 = L, and CAO0 = H. Other combinations of the high and low output signals CA1_H and CA1_L, CA0_H and CA0_L, and the corresponding CAO2, CAO1, and CAO0 signals are also... Figure 8 As shown in the image.

[0087] Figure 9 This is a timing diagram illustrating various signals for receiving commands and / or addresses at a semiconductor device, according to embodiments of the present disclosure. In some embodiments of the present disclosure, Figure 2 Semiconductor device 200 can receive, for example Figure 9 The commands and / or addresses shown in the timing diagram. For example, signals can be generated by a controller (e.g., Figure 1 The controller 10) is provided to the semiconductor device. In some embodiments of this disclosure, Figure 1 The memory 110 receives Figure 9 The commands and / or addresses shown in the timing diagram.

[0088] Figure 9 The system clock signals CK and CKF, the selection signal CS, the command and address signals CA, and the command generated based on the CA signal are shown. The CA signal can be a multi-level input signal (e.g., a three-level signal, a four-level signal, a two-level signal, etc.). The CK and CKF clock signals can be complementary. Figure 9 In the example, the commands generated by the CA signal are activation commands ACT-1 and ACT-2.

[0089] In some embodiments of this disclosure, the command may comprise two parts: a first command part is received when the CK clock signal transitions from a low clock level to a high clock level (e.g., the rising clock edge R of the CK clock signal), and a second command part is received when the CK clock signal transitions from a high clock level to a low clock level (e.g., the falling clock edge F of the CK clock signal). The first command part may include a command operand and an address, and the second command part may include an address. The command operand can be decoded to identify the corresponding command (e.g., ACT-1 or ACT-2 command), and the address may include a memory address, such as a bank address, row address, etc.

[0090] Before time T0, the selection signal CS is valid (e.g., a valid high logic level), and the multi-level CA signal corresponding to the first command section is valid. At time T0, the CK clock signal transitions to a high clock level, and the rising edge R0 causes the CA signal to be received, for example, by the command / address input circuit 205, multi-level input buffer 310, input buffer 400, multi-level input buffer 700, etc. The command operand of the first command section is decoded to identify the ACT-1 command. Before the falling clock edge F0 of the CK clock signal, the CA signal corresponding to the second command section is valid. The falling edge F0 of the CK clock signal causes the CA signal to be received. The memory address of the second command section identifies the memory bank pointed to by the ACT-1 command. Other addresses included in the first and second command sections can identify memory cells (e.g., row addresses) in the active memory bank to be accessed.

[0091] Before time T1, the selection signal CS is valid, and the multi-level CA signal corresponding to the first command section is valid. At time T1, the CK clock signal transitions to a high clock level, and the rising edge R1 causes the CA signal to be received. The command operand of the first command section is decoded to identify the ACT-2 command. Before the falling clock edge F1 of the CK clock signal, the CA signal corresponding to the second command section is valid. The falling edge F1 of the CK clock signal causes the CA signal to be received. The memory address of the second command section identifies the memory bank pointed to by the ACT-2 command. Other addresses included in the first and second command sections can identify the memory cells in the active memory bank to be accessed.

[0092] Before time T2, the CS signal is invalid (e.g., an invalid low logic level), and the CA signal corresponds to the deselect command DES. At time T2, the rising edge R2 of the CK clock signal causes the CA signal to be received and decoded to identify the DES command. The DES command deactivates the active memory bank.

[0093] As previously described, for example, using multi-level signals for command / address signals can allow the same number of commands and / or addresses to be represented with fewer signals, or the same number of signals to be represented with more commands and / or addresses.

[0094] Figure 10 This is a command structure 1000 according to embodiments of the present disclosure, for example, a diagram of commands and addresses for multi-level command and address signals. In some embodiments of the present disclosure, the command structure 1000 may be... Figure 1 The system 100 is used together. For example, the multi-level command and address signals provided by the controller 10 to the memory system 105 can represent signals with, for example, a multi-level command and address signal. Figure 10 The command structure shown includes commands and addresses. In some embodiments of this disclosure, the command structure 1000 can be related to... Figure 2 The semiconductor device 200 is used together. For example, multi-level command and address signals received by the semiconductor device 200 can represent signals with, for example, Figure 10 The command and address shown are part of the command structure.

[0095] Command structure 1000 illustrates a selection signal CS provided to the selection terminal and multi-level command and address signals CA0-CA5 provided to the command / address terminal. In some embodiments of this disclosure, a three-level CA signal is provided to the command / address terminal. The CA signal includes a multipurpose output (MPO) that can be used for other features. For example, in some embodiments of this disclosure, the MPO can be used to send commands to a controller (e.g., Figure 1 The controller 10) provides error correction code (ECC) transparency. In some embodiments of this disclosure, the MPO may additionally or alternatively be used to provide on-demand feedback to the controller (e.g., to provide uncorrectable error reports to the controller for WRITELink ECC). The MPO may be used for other features in other embodiments of this disclosure. For example, in some embodiments of this disclosure, alternative command and address signals CA6 may be provided instead of the MPO to provide an extended set of command and / or address ranges.

[0096] The example commands and addresses shown in command structure 1000 include activation commands ACT-1 and ACT-2. Each of the ACT-1 and ACT-2 commands includes a first part and a second part. The first part is received on the rising edge of a clock signal (e.g., a CK clock signal), and the second part is received on the falling edge of the clock signal. The first part of the ACT-1 and ACT-2 commands may contain a command operand and an address. The command operand may identify the command, and the address may be a portion of the memory address pointed to by the activation command. The second part may contain an address, for example, the address of the memory bank pointed to by the activation command, and other portions of the memory address pointed to by the activation command. The ACT-1 and ACT-2 commands can be paired such that the complete memory address is provided by the portion of the memory address contained in the activation command.

[0097] Referring to command structure 1000, when the CS signal is valid and the multilevel command signals CA0 = 1 and CA1 = 0 (e.g., the command operand is 10), the first part of the ACT-1 command is received at the rising clock edge R of the CK clock signal. Multilevel signals CA2 and CA3 represent three bits R[18:20] of the memory address (e.g., row address), and multilevel signals CA4 and CA5 represent another three bits R[21:23] of the memory address. The second part of the ACT-1 command is received at the falling clock edge F of the CK clock signal. The second part of the ACT-1 command contains the memory address (e.g., memory bank address and row address). For example, multilevel signals CA0 and CA1 represent three bits BA[0:2] of the bank address, and multilevel signals CA2 and CA3 represent another two bits BA[3:4] of the bank address and a bit flag. Multilevel signals CA4 and CA5 represent another three bits R[15:17] of the memory address.

[0098] Following the second part of the ACT-1 command, when the CS signal is active and the multilevel command signals CA0 = 1 and CA1 = 1 (e.g., the command operand is 11), the first part of the ACT-2 command is received at the rising clock edge R of the CK clock signal. Multilevel signals CA2 and CA3 represent three bits R[9:11] of the memory address, and multilevel signals CA4 and CA5 represent another three bits R[12:14] of the memory address. The second part of the ACT-2 command is received at the falling clock edge F of the CK clock signal. The second part of the ACT-2 command contains the memory address (e.g., the row address). For example, multilevel signals CA0 and CA1 represent three bits R[0:2] of the memory address, multilevel signals CA2 and CA3 represent another three bits R[3:5] of the memory address, and multilevel signals CA4 and CA5 represent another three bits R[6:8] of the memory address.

[0099] Upon receiving the ACT-1 and ACT-2 commands, the memory bank corresponding to memory bank address BA[0:4] is activated, and the memory bank corresponding to memory address R[0:23] is prepared for memory operations (e.g., memory access operations).

[0100] Figure 11 This is a block diagram of a multilevel input buffer 1110, a command and address (CA) input decoder circuit 1120, and an output signal (CA_H / L) latch 1130 according to embodiments of the present disclosure. In some embodiments of the present disclosure, the multilevel input buffer 1110, the command and address input decoder circuit 1120, and the high and low output signal latches 1130 may be included... Figure 2 In the command / address input circuit 205 of the semiconductor device 200.

[0101] In some embodiments of this disclosure, the multi-level input buffer 1110, the CA input decoder circuit 1120, and the CA_H / L signal latch 1130 can be connected with... Figure 10 and 12 The example commands are used together to provide internal signals representing non-binary values ​​(e.g., 0, 1, and 2) and binary values ​​(e.g., 0 and 1) from multi-level input signals (e.g., CA0 and CA1). The signals representing non-binary and / or binary values ​​can be provided to the command decoder and / or address decoder (e.g., ...). Figure 2 The command decoder 215 and address decoder 212 are specified. For example, in some embodiments of this disclosure, output signals (e.g., CAO0_H / L and CAO1_H / L) may be provided to the command decoder by the CA_H / L latch 1130, and the CA input decoder circuit 1120 may provide decoded signals (e.g., CAO0-CAO2) to the address decoder. In some embodiments of this disclosure, the output signal is provided by the CA_H / L latch 1130 on the rising edge of the clock signal (e.g., CK_R clock active), and the decoded signal is provided by the CA input decoder circuit 1120 on the falling edge of the clock signal (e.g., CK_F clock active).

[0102] In embodiments of this disclosure that use more than two multilevel signals, additional multilevel input buffers, CA input decoder circuits, and / or CA_H / L signal latches may be included from some or all of the multilevel input buffer 1110, CA input decoder circuit 1120, and / or CA_H / L signal latch 1130. For example, for each pair of multilevel CA signals (e.g., CA2-CA5), an additional multilevel input buffer 1110 may be included. Additional CA input decoder circuits may be included and / or combined into a single CA input decoder circuit 1120 to provide the decoded signal. Additional CA_H / L signal latches 1130 are included and / or combined into a single CA_H / L signal latch 1130 to provide the CA_H / L signal.

[0103] In some embodiments of this disclosure, the multilevel input buffer 1110 may include Figure 3 Multilevel input buffer 310 or Figure 7 A multilevel input buffer 700. In some embodiments of this disclosure, the multilevel input buffer circuits 1115(0) and / or 1115(1) may include Figure 3 Multi-level input buffer circuit 315 Figure 4 400 multi-level input buffer circuit or Figure 7 The multi-level input buffer circuit 715. In some embodiments of this disclosure, such as reference... Figure 8 The relationship between the two three-level input signals CA1 and CA0, the output signals CA1_H and CA1_L, CA0_H and CA0L, and the decoding signals CAO2-CAO0 is described, and the multi-level input buffer 1110 can provide the output signals.

[0104] In some embodiments of this disclosure, the CA input decoder circuit 1120 may include Figure 3 The command and address input decoder circuit 320. In some embodiments of this disclosure, as referenced... Figure 8 The relationship between the two three-level input signals CA1 and CA0, the high and low output signals CA1_H and CA1_L, and CA0_H and CA0L, and the decoding signals CAO2-CAO0 describes that the CA input decoder circuit 1120 can provide the decoding signal.

[0105] Figure 12 This is a command structure 1200 according to embodiments of the present disclosure, for example, a diagram of commands and addresses for multi-level command and address signals. In some embodiments of the present disclosure, the command structure 1200 may be... Figure 1The system 100 is used together. For example, the multi-level command and address signals provided by the controller 10 to the memory system 105 can represent signals with, for example, a multi-level command and address signal. Figure 12 The command structure shown includes commands and addresses. In some embodiments of this disclosure, the command structure 1200 can be related to... Figure 2 The semiconductor device 200 is used together. For example, multi-level command and address signals received by the semiconductor device 200 can represent signals with, for example, Figure 12 The command and address shown are part of the command structure.

[0106] The example command shown in command structure 1200 includes previous references. Figure 10 The activation commands ACT-1 and ACT-2 are described. Figure 12 This includes additional instances of commands that can be identified by multi-level commands and the address signal CA. For example, Figure 12 This includes commands such as Precharge PRE, Refresh REF, Write 16-bit WR16, Write 32-bit WR32, Mask Write MWR, Read 16-bit RD16, and Read 32-bit RD32. The example commands are not intended to limit the scope of this disclosure. Figure 12 The specific commands shown are provided only as examples.

[0107] and Figure 10 The command structure is the same. Figure 12 The command structure illustrates a selection signal CS provided to the select terminal and multi-level command and address signals CA0-CA5 provided to the command / address terminals. In some embodiments of this disclosure, three-level command and address signals are provided to the command / address terminals. As previously described, the command address signals include a multipurpose output (MPO) that can be used for additional features. However, for example, in some embodiments of this disclosure, an additional command and address signal CA6 may be provided instead of an MPO to provide an extended set of command and / or address ranges.

[0108] Figure 12Many of the example commands have a structure similar to the previously described activation commands ACT-1 and ACT-2. For example, many of these commands include a first part and a second part. The first part is received within the rising edge R of a clock signal (e.g., the CK clock signal), and the second part is received within the falling edge F of the clock signal. The first part of the command may contain a command operand and an address, and the second part may contain an address. The command operand may identify the command, and the address may be the memory address to which the command points, for example, the memory bank and the column of the memory to which the command points. For these example commands, such as WR16, WR32, MWR, RD16, and RD32, the two parts define the command and provide the memory address BA[0:4] for the memory bank address and the memory address C[0:5] for the column address.

[0109] Figure 12 Other commands in the example commands may contain modified structures. For example, referring to the example commands PRE and REF, the first part contains command operands for multilevel signals CA0-CA3 and feature settings for multilevel signals CA4 and CA5, and the second part contains the memory addresses (e.g., memory bank addresses RA[0:4]) of the multilevel signals CA0-CA3 to which the command points, as well as the feature settings for multilevel signals CA4 and CA5.

[0110] refer to Figure 10 and 12 The example command uses multi-level CA0-CA5 signals to provide command operands to identify the command and to provide memory addresses (e.g., memory bank address, row address, and column address (though not shown)). In some embodiments of this disclosure, command operands may be represented by non-binary values ​​(e.g., 0, 1, 2, etc.), and memory addresses may be represented by binary values ​​(e.g., bits 0 and 1). In some embodiments of this disclosure, command operands and memory addresses may be represented by binary values. In some embodiments of this disclosure, command operands and memory addresses may be represented by non-binary values.

[0111] In some embodiments of this disclosure, some or all of the multilevel CA signals can represent non-binary values. In some embodiments of this disclosure, some or all of the multilevel CA signals can represent binary values. In some embodiments of this disclosure, the multilevel CA signals can represent a combination of non-binary and binary values.

[0112] In some embodiments of this disclosure, multilevel input buffers and multilevel input buffer circuits (e.g., Figure 3 Multilevel input buffer 310 and multilevel input buffer circuit 315 Figure 4400 multi-level input buffer circuit Figure 7 The multilevel input buffer 700 and multilevel input buffer circuit 715 can provide non-binary values ​​representing multilevel signals (e.g., Figure 5 The relationship between the three-level input signals and the logic values ​​represented by the three-level input signals (e.g., a high output signal CA_H and a low output signal CA_L). In some embodiments of this disclosure, the command and address input decoder circuitry (e.g., command and address input decoder circuitry 320) may be based, for example, on the output signals from the multi-level input buffer (e.g., Figure 8 The relationship between the two three-level input signals, the output signal, and the decoded signal provides a decoded signal (e.g., CAOn) that represents a binary value.

[0113] Modifications may be made without departing from the scope of this disclosure. Figure 10 and 12 Details of the example commands shown are provided. For example, the number of bits representing the memory address can be modified, the command can have more or fewer parts, the information contained in the parts can be different, the number of multi-level signals used for the command can be more or less, additional and / or alternative commands, different command operands, etc., can be included, and all remain within the scope of this disclosure.

[0114] Certain details have been described to provide a full understanding of examples of this disclosure. However, it will be apparent to those skilled in the art that examples of this disclosure can be practiced without these specific details. Furthermore, the specific examples of this disclosure described herein should not be construed as limiting the scope of this disclosure to those specific examples. In other instances, well-known circuits, control signals, timing schemes, and software operations have not been shown in detail to avoid unnecessarily obscuring this disclosure. Additionally, terms such as “coupled” and “coupled” mean that two components can be electrically coupled directly or indirectly. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0115] Based on the foregoing, it should be understood that although specific embodiments of this disclosure have been described for illustrative purposes, various modifications may be made without departing from the spirit or scope of this disclosure. Therefore, the scope of this disclosure should not be limited to any specific embodiments described herein.

Claims

1. A memory comprising: An address decoder, configured to receive address signals and provide decoded addresses; A command decoder, configured to receive internal command signals and provide internal control signals for performing memory operations; as well as A command / address input circuit, configured to receive multi-level command and address signals and provide output signals representing the values ​​of the multi-level command and address signals to the address decoder and the command decoder, wherein multiple command and address signals represent more than one bit. The command / address input circuit includes: A multilevel input buffer, configured to receive the multilevel command and address signals and provide a corresponding output signal for each of the multilevel command and address signals, the corresponding output signal having a logic level based on the corresponding multilevel command and address signal. The address decoder and the command decoder perform decoding based on the output signal from the multilevel input buffer.

2. The memory of claim 1, wherein the multilevel command and address signals comprise at least two multilevel command and address signals representing three-bit address information.

3. The memory according to claim 1, wherein the multi-level command and address signals include three-level signals.

4. The memory according to claim 1, wherein the command / address input circuit comprises: A command and address input decoder circuit is configured to receive the output signal from the multilevel input buffer and is configured to provide a decoded signal representing the bits of the multilevel command and address signal.

5. The memory of claim 4, wherein the command / address input circuitry further comprises a signal latch configured to latch the output signal from the multilevel input buffer.

6. The memory of claim 4, wherein the multilevel input buffer comprises a plurality of multilevel input buffer circuits each configured to receive a corresponding multilevel command and address signal from the multilevel command and address signals, each of the plurality of multilevel input buffers comprising: A first buffer circuit is configured to receive the corresponding multilevel command and address signal and to receive a first reference voltage. The first buffer circuit is configured to provide a first output signal in the output signal based on the voltage of the corresponding multilevel command and address signal relative to the first reference voltage. as well as A second buffer circuit is configured to receive the corresponding multilevel command and address signals and to receive a second reference voltage. The second buffer circuit is configured to provide a second output signal in the output signal based on the voltage of the corresponding multilevel command and address signals relative to the second reference voltage.

7. A memory comprising: An address decoder, configured to receive address signals and provide decoded addresses; A command decoder, configured to receive internal command signals and provide internal control signals for performing memory operations; as well as A command / address input circuit is configured to receive a plurality of multi-level command and address signals and provide an output signal representing the values ​​of the plurality of multi-level command and address signals to an address decoder and a command decoder, wherein each multi-level command and address signal has a corresponding voltage corresponding to one of three or more distinct values. The command / address input circuitry includes a multilevel input buffer configured to receive the plurality of multilevel command and address signals and provide a corresponding pair of output signals for each of the plurality of multilevel command and address signals, the pair of output signals having a corresponding logic level based on the value represented by the corresponding multilevel command and address signal. The address decoder and the command decoder perform decoding based on the output signal from the multilevel input buffer.

8. The memory of claim 7, wherein each multilevel command and address signal has a voltage corresponding to 0, 1, or 2.

9. The memory of claim 7, wherein the values ​​of the plurality of multilevel command and address signals provided to the address decoder are represented by bits, and the values ​​of the plurality of multilevel command and address signals provided to the command decoder are represented by output signals having logic levels corresponding to non-binary values.

10. The memory of claim 9, wherein the command / address input circuitry is configured to provide three bits to the address decoder based on the values ​​of two multi-level command and address signals.

11. The memory of claim 9, wherein the command / address input circuitry is configured to provide four output signals to the command decoder based on a multi-level command and address signal.

12. A memory comprising: An address decoder, configured to receive address signals and provide decoded addresses; A command decoder, configured to receive internal command signals and provide internal control signals for performing memory operations; as well as A command / address input circuit, configured to receive multiple multi-level command and address signals and provide output signals to the address decoder and the command decoder, wherein the output signals include signals representing binary values ​​and signals representing non-binary values. The command / address input circuitry includes a multilevel input buffer configured to receive the plurality of multilevel command and address signals and provide a corresponding pair of output signals for each of the plurality of multilevel command and address signals, the pair of output signals having a corresponding logic level based on the value represented by the corresponding multilevel command and address signal. The address decoder and the command decoder perform decoding based on the output signal from the multilevel input buffer.

13. The memory of claim 12, wherein the signal representing a binary value corresponds to an internal address signal, and the signal representing a non-binary value corresponds to an internal command signal.

14. The memory of claim 12, wherein the command / address input circuitry further comprises command and address input decoder circuitry configured to provide decoded signals based on multiple pairs of output signals from the multilevel input buffer, wherein the decoded signals represent bits and are provided to the address decoder.

15. The memory of claim 12, wherein the command / address input circuitry further comprises a signal latch configured to receive multiple pairs of output signals from the multilevel input buffer and provide the multiple pairs of output signals to the command decoder.

16. A memory comprising: An address decoder, configured to receive address signals and provide decoded addresses; A command decoder, configured to receive internal command signals and provide internal control signals for performing memory operations; as well as A command / address input circuit is configured to receive multiple multi-level command and address signals and provide output signals to the address decoder and the command decoder, wherein the multi-level command and address signals represent a command structure, the command structure including command operands for identifying a memory command and further including memory address information for identifying the memory location pointed to by the memory command. The command operand is represented by a first portion of the plurality of multilevel command and address signals, and each multilevel command and address signal in the first portion represents a non-binary value; the address information is represented by a second portion of the plurality of multilevel command and address signals, and the second portion of the multilevel command and address signals represents bits of memory address information. The command / address input circuitry includes a multilevel input buffer configured to receive the plurality of multilevel command and address signals and provide a corresponding pair of output signals for each of the plurality of multilevel command and address signals, the pair of output signals having a corresponding logic level based on the value represented by the corresponding multilevel command and address signal. The address decoder and the command decoder perform decoding based on the output signal from the multilevel input buffer.

17. The memory of claim 16, wherein the multi-level command and address signal pair of the second portion represents three-bit memory address information.

18. The memory of claim 16, wherein the command structure comprises a first portion and a second portion, the first portion being received by the command / address input circuitry on the rising edge of a clock signal, and the second portion being received by the command / address input circuitry on the falling edge of the clock signal.

19. The memory of claim 18, wherein the first multi-level command and address signal and the second multi-level command and address signal of the plurality of multi-level command and address signals in the first portion represent the command operand, and wherein the first multi-level command and address signal and the second multi-level command and address signal of the plurality of multi-level command and address signals in the second portion represent address information.

20. A memory comprising: Command and address bus; A controller configured to provide multilevel command and address signals to the command and address bus, each of the multilevel command and address signals having a corresponding voltage corresponding to one of at least three or more distinct values; as well as A memory system, coupled to the controller via the command and address bus, comprising multiple memories, each memory configured to receive the multilevel command and address signals and decode the multilevel command and address signals to represent a binary value representing a memory address. Each of the plurality of memories includes: A multilevel input buffer, configured to receive the multilevel command and address signals and provide a corresponding output signal for each of the multilevel command and address signals, the corresponding output signal having a logic level based on the corresponding multilevel command and address signal; The plurality of memories perform decoding based on the output signal from the multilevel input buffer.

21. The memory of claim 20, wherein each memory in the memory system is further configured to receive the multilevel command and address signals and decode the command and address signals into non-binary values ​​of command operands.

22. A memory comprising: A memory configured to receive a plurality of multilevel command and address signals, the multilevel command and address signals representing a command structure including command operands and a memory address, the multilevel command and address signals having corresponding voltages corresponding to non-binary values, wherein the memory comprises: A component for providing internal command signals representing the command operands based on the multi-level command and address signals; A component for providing an internal address signal representing the memory address, the memory address comprising a plurality of bits represented by the internal address signal; as well as A component for performing memory operations on memory locations based on internal address signals, based on the internal command signals. A buffer component is configured to receive the multilevel command and address signals and provide a corresponding output signal for each of the multilevel command and address signals, the corresponding output signal having a logic level based on the corresponding multilevel command and address signal. The component for providing internal command signals and the component for providing internal address signals perform decoding based on the output signal from the component for buffering.

23. A method for performing memory operations, the method comprising: At the memory, a plurality of multilevel command and address signals representing a command structure including command operands and memory address are received, the multilevel command and address signals having corresponding voltages corresponding to one of at least three different voltages, each of the at least three different voltages corresponding to a different value; The internal command signal representing the command operand is provided based on the multi-level command and address signals; Provide an internal address signal representing the memory address, the memory address comprising a plurality of bits represented by the internal address signal; and Memory operations are performed on memory locations based on the internal address signals, according to the internal command signals. The provision of the internal address signal includes decoding multiple multi-level command and address signals as output signals and providing a decoding signal, the logic level of which is based on the logic level of the output signal. The internal address signal is provided by three bits of the memory address provided by two of the multi-level command and address signals.

24. The method of claim 23, wherein providing the internal command signal comprises providing an output signal based on each of the multilevel command and address signals, wherein the output signal represents the value of the corresponding multilevel command and address signal.

25. The method of claim 23, wherein providing the internal command signal comprises providing a plurality of output signals having corresponding logic levels, the corresponding logic levels being based on values ​​represented by multi-level command and address signals.

26. The method of claim 25, wherein providing the internal address signal includes providing bits of the memory address based on the plurality of output signals.

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