Display panel and display device comprising the same

Abstract

A display panel and a display device including the same are provided. The display panel includes a substrate including a planar portion, a first edge portion extending from one side of the planar portion, a second edge portion extending from the other side of the planar portion, a first side surface portion extending from one side of the first edge portion, and a first corner portion disposed between the first edge portion and the second edge portion, a first data line disposed in a display area of the planar portion, a second data line disposed in a display area of the first side surface portion, a first fan-out line disposed in a non-display area of the planar portion and connected to the first data line, a second fan-out line disposed in the first corner portion and connected to the second data line, and an encapsulation film for covering the first data line, the second data line, and the first fan-out line.

Description

Technical Field

[0001] This disclosure relates to a display panel and a display device including the display panel. Background Technology

[0002] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices are now used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] Display devices can be flat panel displays such as liquid crystal displays, field emission displays, or organic light-emitting diode (OLED) displays. OLED displays offer advantages such as wide viewing angles, excellent contrast ratios, and fast response times. Furthermore, OLED displays can be implemented as flexible displays that can be bent or rolled up; therefore, their use in electronic devices is gradually increasing. For example, recently, display devices have been developed that implement OLED displays as flexible displays, showing images not only on the front surface but also on the side surfaces. Summary of the Invention

[0004] Technical issues

[0005] This disclosure provides a display panel that minimizes the dead space on the front surface when an image is displayed not only on the front surface but also on the side surface.

[0006] This disclosure also provides a display device that minimizes dead zones on the front surface when an image is displayed not only on the front surface but also on the side surface.

[0007] However, the scope of this disclosure is not limited to those set forth herein. These and other aspects of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0008] Technical solution

[0009] In an exemplary embodiment, the display panel includes: a substrate, comprising a planar portion, a first edge portion extending from one side of the planar portion, a second edge portion extending from the other side of the planar portion, a first side surface portion extending from one side of the first edge portion, and a first corner portion disposed between the first edge portion and the second edge portion; a first data line disposed in a display area of ​​the planar portion; a second data line disposed in a display area of ​​the first side surface portion; a first fan-out line disposed in a non-display area of ​​the planar portion and connected to the first data line; a second fan-out line disposed in the first corner portion and connected to the second data line; a light-emitting element disposed in the display area of ​​the planar portion on the first data line and in the display area of ​​the first side surface portion on the second data line, and each including a first electrode, a light-emitting layer, and a second electrode; and an encapsulation film configured to cover the light-emitting element and comprising at least one inorganic film and at least one organic film, wherein the at least one inorganic film and at least one organic film cover the first data line, the second data line, and the first fan-out line.

[0010] The second outgoing line may not be covered by at least one inorganic membrane.

[0011] At least one inorganic membrane and at least one organic membrane may cover the second outgoing line.

[0012] The display panel may also include a first source voltage line disposed between the first fan-out line and the second fan-out line at the first corner.

[0013] At least one inorganic film and at least one organic film may cover the first source voltage line.

[0014] The second fan can be located in the non-display area of ​​the first side surface.

[0015] The display panel may further include: a scan line disposed in the display area of ​​the planar portion and intersecting with the first data line; and a scan driver disposed in the first corner outside the second fan-out line and including a stage connected to the scan line.

[0016] The level may not be covered by at least one inorganic membrane.

[0017] The display panel may also include organic film patterns set between adjacent levels in the stage.

[0018] The display panel may also include scan control lines that are connected to the stage and intersect with the organic film pattern.

[0019] At least one of the scan control lines can be set on a different layer than the first data line and the second data line.

[0020] At least one of the first sector outgoing lines and at least one of the second sector outgoing lines can be placed on the same layer as the first data line and the second data line.

[0021] At least one of the first sector outgoing lines and at least one of the second sector outgoing lines can be set on a different layer than the first data line and the second data line.

[0022] In an exemplary embodiment, the display panel includes: a substrate including a planar portion, a first edge portion bending from the planar portion along a first curvature line, a second edge portion bending from the planar portion along a second curvature line, and a first side surface portion extending from one side of the first edge portion; a first data line disposed in a display area of ​​the planar portion; a second data line disposed in a display area of ​​the first side surface portion; and a first fan-out line disposed inside a first angular curvature line defined by the first curvature line and the second curvature line and connected to the first data line.

[0023] The display panel may also include a second fan-out line disposed outside the first corner bend line and connected to the second data line.

[0024] The display panel may also include a second fan-out line disposed inside the first corner bend and connected to the second data line.

[0025] The display panel may also include a first source voltage line disposed between the first fan-out line and the second fan-out line.

[0026] The first source voltage line can be located inside the first angle bend line.

[0027] The display panel may further include: a scan line disposed in the display area of ​​the planar portion and intersecting with the first data line; and a scan driver including a stage connected to the scan line and disposed outside the first angular bend line.

[0028] The stage can be set outside the second fan-out.

[0029] The display panel may further include: a light-emitting element disposed on a first data line in the display area of ​​the planar portion and on a second data line in the display area of ​​the first side surface portion, and each including a first electrode, a light-emitting layer and a second electrode; and an encapsulation film configured to cover the light-emitting element and including at least one inorganic film and at least one organic film, wherein the at least one inorganic film and at least one organic film cover the first data line, the second data line and the first fan-out line.

[0030] At least one inorganic membrane and at least one organic membrane may be disposed inside the first angular bend line.

[0031] At least one inorganic membrane may not be disposed outside the first angular bend line.

[0032] In an exemplary embodiment, the display device includes: a display panel; and a cover window disposed above the display panel, wherein the display panel includes: a substrate including a planar portion, a first edge portion extending from one side of the planar portion, a second edge portion extending from the other side of the planar portion, a first side surface portion extending from one side of the first edge portion, and a first corner portion disposed between the first edge portion and the second edge portion; a first data line disposed in the display area of ​​the planar portion; a second data line disposed in the display area of ​​the first side surface portion; a first fan-out line disposed in the non-display area of ​​the planar portion and connected to the first data line; a second fan-out line disposed in the first corner portion and connected to the second data line; a light-emitting element disposed in the display area of ​​the planar portion on the first data line and disposed in the display area of ​​the first side surface portion on the second data line, and each including a first electrode, a light-emitting layer, and a second electrode; and an encapsulation film configured to cover the light-emitting element and including at least one inorganic film and at least one organic film, wherein the at least one inorganic film and at least one organic film cover the first data line, the second data line, and the first fan-out line.

[0033] The covering window may include a covering plane portion corresponding to the planar portion, a first covering edge portion corresponding to the first edge portion, a second covering edge portion corresponding to the second edge portion, a first covering side surface portion corresponding to the first side surface portion, and a first covering corner portion corresponding to the first corner portion.

[0034] The width of the first coverage corner can be larger than the width of the first corner.

[0035] Details of other embodiments are described in detail and shown in the accompanying drawings.

[0036] Beneficial effects

[0037] For the display panel and display device including the display panel according to the embodiment, the first scan driver, the second fan-out line, and the sixth fan-out line, which do not need to be covered by the encapsulation film, are disposed in the first corner. Therefore, even if strain is applied to the first corner due to the bending forces of the first edge portion and the first side surface portion, and the bending forces of the second edge portion and the second side surface portion, the encapsulation film can be unaffected by the strain at the first corner. Therefore, cracks in the encapsulation film due to strain at the first corner can be prevented or reduced.

[0038] For the display panel and display device including the display panel according to the embodiment, at the first corner, an organic film pattern is disposed in a hole penetrating a plurality of inorganic films to expose the substrate. Therefore, cracks in the inorganic films due to strain at the first corner can be reduced.

[0039] The effects of this disclosure are not limited to those described above, and various other effects are included in this specification. Attached Figure Description

[0040] Figure 1 This is a perspective view showing the display panel according to an embodiment.

[0041] Figure 2a and Figure 2b They are Figure 1 The unfolded view and floor plan of the display panel.

[0042] Figure 3a and Figure 3b These are the unfolded view and the plan view of the display panel when the first intersection point to the fourth intersection point of the first curved line to the fourth curved line are superimposed with the first corner to the fourth corner.

[0043] Figure 4 This is an unfolded view showing the display panel in its unbent state according to an embodiment.

[0044] Figure 5 It is shown Figure 4 An enlarged plan view of an example of region A.

[0045] Figure 6 It is shown Figure 4 An enlarged plan view of an example of region B.

[0046] Figure 7 It is shown Figure 5 A circuit diagram of an example pixel.

[0047] Figure 8 It is shown Figure 5 A circuit diagram of an example of a scan driver stage.

[0048] Figure 9 It shows along Figure 5 The example sectional view is taken from line II-II'.

[0049] Figure 10 It shows along Figure 5 A cross-sectional view of an example taken from line III-III'.

[0050] Figure 11 It is shown Figure 4 An enlarged plan view of an example of region A.

[0051] Figure 12 It shows along Figure 11 A cross-sectional view of an example taken by line IV-IV'.

[0052] Figure 13 It is shown Figure 4 An enlarged plan view of an example of region C.

[0053] Figure 14 It is shown Figure 4An enlarged plan view of an example of region D.

[0054] Figure 15 It shows along Figure 13 A cross-sectional view of an example cut by line V-V'.

[0055] Figure 16 This is a perspective view showing a display device according to an embodiment.

[0056] Figure 17 It shows along Figure 16 The example sectional view is taken by line VI-VI'.

[0057] Figure 18 It shows along Figure 16 The example sectional view is taken from line VII-VII'.

[0058] Figure 19 It shows the setting Figure 9 A plan view of an example sensor electrode on the encapsulation film. Detailed Implementation

[0059] The advantages and features of this disclosure, as well as methods of implementing it, will become apparent from the following detailed description of embodiments with reference to the accompanying drawings. However, this disclosure is not limited to the embodiments described below, but can be implemented in various different forms. These embodiments are provided only to enable this disclosure to be complete and to allow those skilled in the art to fully appreciate the scope of this disclosure, which is defined by the scope of the claims.

[0060] The phrase "an element or layer 'on' another element or layer" includes both the case where one element or layer is directly on another element or layer and the case where one element or layer is on another element or layer with other layers or elements placed in between. Throughout this specification, the same components will be indicated by the same reference numerals. The shapes, dimensions, scales, angles, quantities, etc., disclosed in the drawings used to describe embodiments are exemplary, and therefore, this disclosure is not limited to the shapes, dimensions, scales, angles, quantities, etc., shown in the drawings.

[0061] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, within the technical spirit of this disclosure, the first component mentioned below can be the second component.

[0062] Features of each of the various embodiments of this disclosure may be combined with each other in part or in whole, and may interact with each other technically differently, and the various embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0063] In the following description, specific embodiments will be described with reference to the accompanying drawings.

[0064] Figure 1 This is a perspective view showing the display panel according to an embodiment. Figure 2a and Figure 2b They are Figure 1 The unfolded view and floor plan of the display panel.

[0065] In this specification, the term "above" refers to the Z-axis direction, and the term "below" refers to the direction opposite to the Z-axis direction. Additionally, "left," "right," "up," and "down" refer to the directions when the display panel 100 is viewed in a plan view. For example, "left" refers to the direction opposite to the X-axis direction, "right" refers to the X-axis direction, "up" refers to the Y-axis direction, and "down" refers to the direction opposite to the Y-axis direction.

[0066] Reference Figure 1 , Figure 2a and Figure 2b The display panel 100 may include a substrate 110, which has a planar portion PS, a first side surface portion SS1, a second side surface portion SS2, a third side surface portion SS3, a fourth side surface portion SS4, a first edge portion ES1, a second edge portion ES2, a third edge portion ES3, a fourth edge portion ES4, a first corner portion CS1, a second corner portion CS2, a third corner portion CS3, and a fourth corner portion CS4.

[0067] The substrate 110 is a flexible substrate that can be bent, folded, and rolled, and can be formed of plastic. For example, the substrate 110 may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl compounds, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. Optionally, the substrate 110 may include a metallic material.

[0068] The planar portion PS can be formed as a flat, non-curved surface. The planar portion PS can be a rectangular surface having a short side in a first direction (X-axis direction) and a long side in a second direction (Y-axis direction). The angle where the short side and the long side intersect each other in the planar portion PS can be formed with a predetermined curvature and be curved. The planar portion PS can be the upper surface of the display panel 100.

[0069] The first edge portion ES1 may extend from a first side of the planar portion PS. The first edge portion ES1 may extend from the left side of the planar portion PS. The first edge portion ES1 may be disposed between the planar portion PS and the first side surface portion SS1. The first edge portion ES1 may be a surface that is bent at a predetermined curvature in the first bending line BL1 and the fifth bending line BL5. The first bending line BL1 may be the boundary between the planar portion PS and the first edge portion ES1, and the fifth bending line BL5 may be the boundary between the first side surface portion SS1 and the first edge portion ES1.

[0070] The first side surface portion SS1 may extend from the first side of the first edge portion ES1. The first side surface portion SS1 may be the left surface of the display panel 100. The first side surface portion SS1 may be a rectangular surface having a short side in the third direction (Z-axis direction) and a long side in the second direction (Y-axis direction).

[0071] The second edge portion ES2 may extend from the second side of the planar portion PS. The second edge portion ES2 may extend from the lower side of the planar portion PS. The second edge portion ES2 may be disposed between the planar portion PS and the second side surface portion SS2. The second edge portion ES2 may be a surface that is bent at a predetermined curvature in the second bending line BL2 and the sixth bending line BL6. The second bending line BL2 may be the boundary between the planar portion PS and the second edge portion ES2, and the sixth bending line BL6 may be the boundary between the second side surface portion SS2 and the second edge portion ES2.

[0072] The second side surface portion SS2 can extend from the first side of the second edge portion ES2. The second side surface portion SS2 can be the lower surface of the display panel 100. The second side surface portion SS2 can be a rectangular surface having a short side in the third direction (Z-axis direction) and a long side in the first direction (X-axis direction).

[0073] The third edge portion ES3 may extend from the third side of the planar portion PS. The third edge portion ES3 may extend from the upper side of the planar portion PS. The third edge portion ES3 may be disposed between the planar portion PS and the third side surface portion SS3. The third edge portion ES3 may be a surface that is bent with a predetermined curvature in the third bending line BL3 and the seventh bending line BL7. The third bending line BL3 may be the boundary between the planar portion PS and the third edge portion ES3, and the seventh bending line BL7 may be the boundary between the third side surface portion SS3 and the third edge portion ES3.

[0074] The third side surface portion SS3 can extend from the first side of the third edge portion ES3. The third side surface portion SS3 can be the upper surface of the display panel 100. The third side surface portion SS3 can be a rectangular surface having a short side in the third direction (Z-axis direction) and a long side in the first direction (X-axis direction).

[0075] The fourth edge portion ES4 can extend from the fourth side of the planar portion PS. The fourth edge portion ES4 can extend from the right side of the planar portion PS. The fourth edge portion ES4 can be disposed between the planar portion PS and the fourth side surface portion SS4. The fourth edge portion ES4 can be a surface curved with a predetermined curvature in the fourth bending line BL4 and the eighth bending line BL8. The fourth bending line BL4 can be the boundary between the planar portion PS and the fourth edge portion ES4, and the eighth bending line BL8 can be the boundary between the fourth side surface portion SS4 and the fourth edge portion ES4.

[0076] The fourth side surface portion SS4 can extend from the first side of the fourth edge portion ES4. The fourth side surface portion SS4 can be the right surface of the display panel 100. The fourth side surface portion SS4 can be a rectangular surface having a short side in the third direction (Z-axis direction) and a long side in the second direction (Y-axis direction).

[0077] The first corner portion CS1 can be disposed between the first edge portion ES1 and the second edge portion ES2. The first corner portion CS1 is not disposed between the first side surface portion SS1 and the second side surface portion SS2, therefore an empty space can be provided between the first side surface portion SS1 and the second side surface portion SS2. The width of the first corner portion CS1 can be smaller than the width of the first edge portion ES1 and the width of the second edge portion ES2. Therefore, as... Figure 2b As shown, the first dead zone DS1 can be located outside the first corner CS1 in the plan view. The first dead zone DS1 can be defined as an empty space, and the first corner CS1 is not located in the empty space of the first corner region that connects the first edge ES1 and the second edge ES2 to each other.

[0078] The second corner portion CS2 can be disposed between the first edge portion ES1 and the third edge portion ES3. Since the second corner portion CS2 is not disposed between the first side surface portion SS1 and the third side surface portion SS3, an empty space can be provided between the first side surface portion SS1 and the third side surface portion SS3. The width of the second corner portion CS2 can be smaller than the width of the first edge portion ES1 and the width of the third edge portion ES3. Therefore, as... Figure 2b As shown, the second dead zone DS2 can be located outside the second corner CS2 in the plan view. The second dead zone DS2 can be defined as an empty space, and the second corner CS2 is not located in the empty space of the second corner region that connects the first edge ES1 and the third edge ES3 to each other.

[0079] The third corner portion CS3 can be disposed between the second edge portion ES2 and the fourth edge portion ES4. Since the third corner portion CS3 is not disposed between the second side surface portion SS2 and the fourth side surface portion SS4, an empty space can be provided between the second side surface portion SS2 and the fourth side surface portion SS4. The width of the third corner portion CS3 can be smaller than the width of the second edge portion ES2 and the width of the fourth edge portion ES4. Therefore, as... Figure 2b As shown, the third dead zone DS3 can be located outside the third corner CS3 in the plan view. The third dead zone DS3 can be defined as an empty space, and the third corner CS3 is not located in the empty space of the third corner region that connects the second edge ES2 and the fourth edge ES4 to each other.

[0080] The fourth corner portion CS4 can be disposed between the third edge portion ES3 and the fourth edge portion ES4. The fourth corner portion CS4 is not disposed between the third side surface portion SS3 and the fourth side surface portion SS4, therefore an empty space can be provided between the third side surface portion SS3 and the fourth side surface portion SS4. The width of the fourth corner portion CS4 can be smaller than the width of the third edge portion ES3 and the width of the fourth edge portion ES4. Therefore, as... Figure 2b As shown, the fourth dead zone DS4 can be located outside the fourth corner CS4 in the plan view. The fourth dead zone DS4 can be defined as an empty space, and the fourth corner CS4 is not located in the empty space of the fourth corner region that connects the third edge ES3 and the fourth edge ES4 to each other.

[0081] At the same time, such as Figure 2b As shown, the first intersection point CP1 between the first bending line BL1 and the second bending line BL2 can overlap with the first corner CS1. In this case, strain is applied to the first corner CS1 due to the bending forces of the first edge portion ES1 and the first side surface portion SS1, as well as the bending forces of the second edge portion ES2 and the second side surface portion SS2.

[0082] Figure 3a and Figure 3b These are the unfolded view and the plan view of the display panel when the first intersection point to the fourth intersection point of the first curved line to the fourth curved line are superimposed with the first corner to the fourth corner.

[0083] To eliminate the strain applied to the first corner CS1, such as Figure 3a and Figure 3b As shown, the first intersection point CP1 between the first curved line BL1 and the second curved line BL2 may not overlap with the first corner CS1. That is, the first intersection point CP1 between the first curved line BL1 and the second curved line BL2 may be located outside the first corner CS1. However, as... Figure 3bThe width of the first dead zone DS1 shown, when the first intersection point CP1 is located outside the first corner CS1, will be, for example... Figure 2b As shown, the first intersection point CP1 overlaps with the first corner CS1. Therefore, in order to reduce the width of the first dead zone DS1, it is preferable that the first intersection point CP1 between the first curved line BL1 and the second curved line BL2 overlaps with the first corner CS1. However, in this case, it is necessary to reduce the strain applied to the first corner CS1.

[0084] Figure 4 This is an unfolded view showing the display panel in its unbent state according to an embodiment.

[0085] exist Figure 4 For ease of explanation, only data lines D1, D2, D3, D4 and D5, fan-out lines F1, F2, F3, F4, F5, F6 and F7, a first scan driver 120, a second scan driver 130, an integrated drive circuit 140 and a circuit board 150 disposed on the substrate 110 are shown.

[0086] Reference Figure 4 The substrate 110 may include a planar portion PS, a first side surface portion SS1, a second side surface portion SS2, a third side surface portion SS3, a fourth side surface portion SS4, a first edge portion ES1, a second edge portion ES2, a third edge portion ES3, a fourth edge portion ES4, a first corner portion CS1, a second corner portion CS2, a third corner portion CS3, a fourth corner portion CS4, a curved portion BS, and a pad (or "solder pad") portion PAS.

[0087] Planar portion PS, first side surface portion SS1, second side surface portion SS2, third side surface portion SS3, fourth side surface portion SS4, first edge portion ES1, second edge portion ES2, third edge portion ES3, fourth edge portion ES4, first corner portion CS1, second corner portion CS2, third corner portion CS3 and fourth corner portion CS4 and reference Figure 1 , Figure 2a and Figure 2b The planar portion PS, the first side surface portion SS1, the second side surface portion SS2, the third side surface portion SS3, the fourth side surface portion SS4, the first edge portion ES1, the second edge portion ES2, the third edge portion ES3, the fourth edge portion ES4, the first corner portion CS1, the second corner portion CS2, the third corner portion CS3, and the fourth corner portion CS4 are the same, so their descriptions will be omitted.

[0088] The curved portion BS can extend from the first side of the second side surface portion SS2. The curved portion BS can extend from the lower side of the second side surface portion SS2. The curved portion BS can be disposed between the second side surface portion SS2 and the pad portion PAS. The curved portion BS can be a surface curved with a predetermined curvature in the ninth bending line BL9 and the tenth bending line BL10. The ninth bending line BL9 can be the boundary between the second side surface portion SS2 and the curved portion BS, and the tenth bending line BL10 can be the boundary between the curved portion BS and the pad portion PAS.

[0089] The pad portion PAS can extend from the first side of the bend portion BS. The pad portion PAS can extend from the lower side of the bend portion BS. The pad portion PAS can be a rectangular surface having a short side in the third direction (Z-axis direction) and a long side in the first direction (X-axis direction).

[0090] Data lines D1, D2, D3, D4, and D5 can be configured to extend in a second direction (Y-axis direction). Data lines D1, D2, D3, D4, and D5 can be arranged side by side.

[0091] The first data line D1 can be disposed in the planar portion PS. The first data line D1 can be superimposed on the first corner portion CS1 and the second corner portion CS2 in the second direction (Y-axis direction). The first data line D1 can be connected to the first fan-out line F1 at the planar portion PS adjacent to the first corner portion CS1.

[0092] The second data line D2 can be disposed in the first side surface portion SS1 and the first edge portion ES1. The second data line D2 can be connected to the second fan-out line F2 at the first side surface portion SS1 and the first edge portion ES1.

[0093] The third data line D3 can be provided in the planar part PS, the second side surface part SS2, and the third side surface part SS3. The third data line D3 can be connected to the third fan-out line F3 at the second side surface part SS2.

[0094] The fourth data line D4 can be disposed in the planar portion PS. The fourth data line D4 can be superimposed on the third corner portion CS3 and the fourth corner portion CS4 in the second direction (Y-axis direction). The fourth data line D4 can be connected to the fourth fan-out line F4 at the planar portion PS adjacent to the third corner portion CS3.

[0095] The fifth data line D5 can be located in the fourth side surface portion SS4 and the fourth edge portion ES4. The fifth data line D5 can be connected to the fifth fan-out line F5 at the fourth side surface portion SS4 and the fourth edge portion ES4.

[0096] The first data line D1 can be set between the second data line D2 and the third data line D3. The fourth data line D4 can be set between the third data line D3 and the fifth data line D5.

[0097] Fan-out lines F1, F2, F3, F4, F5, F6 and F7 can connect the integrated drive circuit 140 located in the pad PAS to data lines D1, D2, D3, D4 and D5, the first scan driver 120 and the second scan driver 130.

[0098] The first fan-out line F1 can connect the integrated drive circuit 140 and the first data line D1 to each other. The first fan-out line F1 can be provided in the pad portion PAS, the curved portion BS, the second side surface portion SS2, and the flat surface portion PS. The first fan-out line F1 can be connected to the integrated drive circuit 140 at the pad portion PAS. The first fan-out line F1 can be connected to the first data line D1 at the flat surface portion PS adjacent to the first corner portion CS1.

[0099] The second fan-out line F2 can connect the integrated drive circuit 140 and the second data line D2 to each other. The second fan-out line F2 can be disposed in the pad portion PAS, the bent portion BS, the second side surface portion SS2, the first corner portion CS1, the first edge portion ES1, and the first side surface portion SS1. The second fan-out line F2 can be connected to the integrated drive circuit 140 at the pad portion PAS. The second fan-out line F2 can be connected to the second data line D2 at the first edge portion ES1 and the first side surface portion SS1.

[0100] The third fan-out line F3 can connect the integrated drive circuit 140 and the third data line D3 to each other. The third fan-out line F3 can be disposed in the pad portion PAS, the bent portion BS, and the second side surface portion SS2. The third fan-out line F3 can be connected to the integrated drive circuit 140 at the pad portion PAS. The third fan-out line F3 can be connected to the third data line D3 at the second side surface portion SS2.

[0101] The fourth fan-out line F4 can connect the integrated drive circuit 140 and the fourth data line D4 to each other. The fourth fan-out line F4 can be disposed in the pad portion PAS, the curved portion BS, the second side surface portion SS2, and the flat surface portion PS. The fourth fan-out line F4 can be connected to the integrated drive circuit 140 at the pad portion PAS. The fourth fan-out line F4 can be connected to the fourth data line D4 at the flat surface portion PS adjacent to the third corner portion CS3.

[0102] The fifth fan-out line F5 can connect the integrated drive circuit 140 and the fifth data line D5 to each other. The fifth fan-out line F5 can be located in the pad portion PAS, the bent portion BS, the second side surface portion SS2, the third corner portion CS3, the fourth edge portion ES4, and the fourth side surface portion SS4. The fifth fan-out line F5 can be connected to the integrated drive circuit 140 at the pad portion PAS. The fifth fan-out line F5 can be connected to the fifth data line D5 at the fourth edge portion ES4 and the fourth side surface portion SS4.

[0103] The sixth fan-out line F6 can connect the integrated drive circuit 140 and the first scan driver 120 to each other. The sixth fan-out line F6 can be connected to the integrated drive circuit 140 at the pad portion PAS. The sixth fan-out line F6 can be connected to the first scan driver 120 at the second side surface portion SS2. The sixth fan-out line F6 can be stacked with the first scan driver 120 at the second side surface portion SS2, the second edge portion ES2, the first corner portion CS1, the first edge portion ES1, the first side surface portion SS1, the second corner portion CS2, the third edge portion ES3, and the third side surface portion SS3. Therefore, the sixth fan-out line F6 can be provided in the pad portion PAS, the curved portion BS, the second side surface portion SS2, the second edge portion ES2, the first corner portion CS1, the first edge portion ES1, the first side surface portion SS1, the second corner portion CS2, the third edge portion ES3, and the third side surface portion SS3. Simultaneously, the sixth fan-out line F6 is a line used to supply scan control signals to the first scan driver 120, and therefore can be referred to as the first scan control line.

[0104] The seventh fan-out line F7 can connect the integrated drive circuit 140 and the second scan driver 130 to each other. The seventh fan-out line F7 can be connected to the integrated drive circuit 140 at the pad portion PAS. The seventh fan-out line F7 can be connected to the second scan driver 130 at the second side surface portion SS2. The seventh fan-out line F7 can be stacked with the second scan driver 130 at the second side surface portion SS2, the second edge portion ES2, the third corner portion CS3, the fourth edge portion ES4, the fourth side surface portion SS4, the fourth corner portion CS4, the third edge portion ES3, and the third side surface portion SS3. The seventh fan-out line F7 can be provided in the pad portion PAS, the curved portion BS, the second side surface portion SS2, the second edge portion ES2, the third corner portion CS3, the fourth edge portion ES4, the fourth side surface portion SS4, the fourth corner portion CS4, the third edge portion ES3, and the third side surface portion SS3. Simultaneously, the seventh fan-out line F7 is a line used to supply scan control signals to the second scan driver 130, and therefore can be referred to as the second scan control line.

[0105] The first scan driver 120 may be disposed on the edge of a first side of the substrate 110, and the second scan driver 130 may be disposed on the edge of a second side of the substrate 110 opposite to the first side of the substrate 110. For example, as Figure 4 As shown, the first scan driver 120 can be disposed on the left edge of the substrate 110, and the second scan driver 130 can be disposed on the right edge of the substrate 110. Either the first scan driver 120 or the second scan driver 130 can be omitted. Specifically, as... Figure 4As shown, the first scan driver 120 may be disposed in the second side surface portion SS2, the second edge portion ES2, the first corner portion CS1, the first edge portion ES1, the first side surface portion SS1, the second corner portion CS2, the third edge portion ES3, and the third side surface portion SS3. Additionally, as... Figure 4 As shown, the second scan driver 130 may be disposed in the second side surface portion SS2, the second edge portion ES2, the third corner portion CS3, the fourth edge portion ES4, the fourth side surface portion SS4, the fourth corner portion CS4, the third edge portion ES3, and the third side surface portion SS3.

[0106] The first scan driver 120 and the second scan driver 130 can be connected to scan lines. The scan lines can be configured to extend in a first direction (X-axis direction). The scan lines can intersect with data lines.

[0107] The first scan driver 120 can be connected to the sixth fan-out line F6 at the second side surface portion SS2. Therefore, the first scan driver 120 can receive scan control signals from the integrated drive circuit 140 through the sixth fan-out line F6. The first scan driver 120 can generate scan signals according to the scan control signals and output the scan signals to the scan lines.

[0108] The second scan driver 130 can be connected to the seventh fan-out line F7 at the second side surface portion SS2. Therefore, the second scan driver 130 can receive scan control signals from the integrated drive circuit 140 through the seventh fan-out line F7. The second scan driver 130 can generate scan signals according to the scan control signals and output the scan signals to the scan lines.

[0109] The integrated drive circuit 140 can be disposed in the pad portion PAS. The integrated drive circuit 140 can be formed as an integrated circuit (IC). The integrated drive circuit 140 can be disposed on the substrate 110 by means of chip-on-glass (COG), chip-on-plastic (COP), or ultrasonic bonding. Optionally, the integrated drive circuit 140 can be disposed on the circuit board 150 by means of chip-on-plastic (COP).

[0110] The integrated driver circuit 140 can be connected to the pads of the pad portion PAS. The integrated driver circuit 140 can receive digital video data and timing signals through the pads of the pad portion PAS. The integrated driver circuit 140 can use the timing signals to generate scan control signals. The scan control signals may include a start signal and a clock signal. The integrated driver circuit 140 can convert digital video data into analog data voltage.

[0111] The integrated driver circuit 140 can be connected to fan-out lines F1, F2, F3, F4, F5, F6, and F7. The integrated driver circuit 140 can output scan control signals to the sixth fan-out line F6 and the seventh fan-out line F7. The integrated driver circuit 140 can output analog data voltages to the first through fifth fan-out lines F1, F2, F3, F4, and F5.

[0112] The circuit board 150 can be attached to the pad of the pad portion PAS using an anisotropic conductive film. The leads of the circuit board 150 can be electrically connected to the pad of the pad portion PAS. The circuit board 150 can be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0113] Figure 5 It is shown Figure 4 An enlarged plan view of an example of region A. Figure 6 It is shown Figure 4 An enlarged plan view of an example of region B.

[0114] Figure 5 It is a detailed enlarged plan view showing the first corner portion CS1 and the planar portion PS, the first edge portion ES1 and the second edge portion ES2 surrounding the first corner portion CS1. Figure 6 This is a detailed enlarged plan view of the first side surface portion SS1.

[0115] Reference Figure 5 and Figure 6 The planar portion PS and the first side surface portion SS1 may include a display area DA and a non-display area NDA. A first data line D1, a scan line SL, and pixels PX (e.g., PX1, PX2, and PX3) may be disposed in the display area DA of the planar portion PS adjacent to the first corner portion CS1. A second data line D2, a scan line SL, and pixels PX may be disposed in the display area DA of the first side surface portion SS1.

[0116] First data line D1 and second data line D2 can be positioned in a second direction (Y-axis direction). Scan line SL can be positioned in a first direction (X-axis direction). Pixel PX can be positioned in the area defined by the intersection of scan line SL and data lines D1 and D2. Each pixel PX can be connected to at least one scan line SL and at least one first data line D1 or at least one second data line D2. Each pixel PX may include, for example,... Figure 7 The light-emitting element EL shown here emits light. (See later...) Figure 7 A detailed description of the pixel PX.

[0117] The first outgoing line F1 can be located in the non-display area NDA of the planar part PS. The first power line VSSL can be located in the non-display area NDA of the planar part PS and the non-display area NDA of the first side surface part SS1.

[0118] The first source voltage applied to the second electrode of the light-emitting element EL in each pixel PX can be applied to the first power line VSSL. The first power line VSSL can be electrically connected to the second electrode of the light-emitting element EL in each pixel PX. In the non-display area NDA of the planar portion PS, the first power line VSSL can be set to be closer to the first corner CS1 than the first fan-out line F1. In the non-display area NDA of the first side surface portion SS1, the first power line VSSL can be set to be farther away from the first scan driver 120 than the second fan-out line F2.

[0119] The first fan-out line F1 can be connected to the first data line D1. The first data line D1 refers to the data line that overlaps with the first corner section CS1 and the second corner section CS2 in the second direction (Y-axis direction). For example... Figure 5 As shown, the first fan-out line F1 connected to the first data line D1 adjacent to the second edge ES2 can be shorter than the first fan-out line F1 connected to the first data line D1 adjacent to the first edge ES1.

[0120] The first corner CS1 refers to the area located outside the first corner bend line CBL1 defined by the first bend line BL1 and the second bend line BL2. The first corner CS1 may be a non-display area in which no light-emitting pixel PX is provided. The first scan driver 120 and the second fan-out line F2 may be located in the first corner CS1.

[0121] The first scan driver 120 can be disposed outside the second fan-out line F2. In the first corner CS1, the first scan driver 120 can be disposed on the left side of the second fan-out line F2. The first scan driver 120 can be disposed at the end closer to the substrate 110 than the second fan-out line F2.

[0122] The first scan driver 120 may include stages 121 to 129 that are connected to each other and sequentially output scan signals. Stages 121 to 129 may be located in the first corner CS1, such as... Figure 5 The curvature shown is set along the first corner CS1, and can be configured in the first side surface portion SS1 as follows. Figure 6 The sections shown are arranged along the long side in the second direction (Y-axis direction). Sections 121 to 129 are not arranged along the short side in the first side surface portion SS1 in the first direction (X-axis direction).

[0123] The first scan driver 120 and the sixth fan-out line F6 can be disposed in the second edge portion ES2, the first corner portion CS1, the first edge portion ES1, and the first side surface portion SS1. Stages 121 to 129 can be stacked with the sixth fan-out line F6. Each of stages 121 to 129 can be connected to the sixth fan-out line F6 and the scan line SL. Each of stages 121 to 129 can receive a scan control signal through the sixth fan-out line F6, generate a scan signal according to the scan control signal, and output the scan signal to the scan line SL.

[0124] To reduce the strain at the first corner CS1, the tension at the first corner CS1 needs to be increased. Therefore, each of the organic membrane patterns TO can be positioned between multiple stages 121 to 127. The organic membrane pattern TO can fill the spaces in which the inorganic membrane has been removed to increase the tension. The organic membrane pattern TO can intersect with the second fan-out line F2 and the sixth fan-out line F6.

[0125] The second fan-out line F2 can be disposed in the second edge portion ES2, the first corner portion CS1, the first edge portion ES1, and the first side surface portion SS1. The second fan-out line F2 is not disposed along the long side in the second direction (Y-axis direction) in the first side surface portion SS1. The second fan-out line F2 can pass through the first corner portion CS1 and can be connected to the second data line D2 at the first edge portion ES1 and the first side surface portion SS1. The second fan-out line F2 can be disposed closer to the plane portion PS than the first scan driver 120.

[0126] Meanwhile, when the encapsulation film is formed in the first corner CS1, cracks may appear in the encapsulation film due to strain in the first corner CS1. When cracks appear in the encapsulation film, the light-emitting element EL of the pixel PX will be exposed to oxygen or moisture. Therefore, in order to prevent cracks from appearing in the encapsulation film due to strain in the first corner CS1, the encapsulation film is not formed in the first corner CS1. Therefore, the first scan driver 120, the second fan-out line F2, and the sixth fan-out line F6, which do not need to be covered by the encapsulation film, are disposed in the first corner CS1.

[0127] The third corner CS3, and the second edge ES2, fourth edge ES4, and fourth side surface SS4 surrounding the third corner CS3, are referenced. Figure 5 and Figure 6 The first corner portion CS1 and the second edge portion ES2, the first edge portion ES1 and the first side surface portion SS1 around the first corner portion CS1 are substantially the same, so their description will be omitted.

[0128] Figure 7 It is shown Figure 5 A circuit diagram of an example pixel.

[0129] Reference Figure 7Each pixel PX may include a driving transistor DT, at least one switching transistor ST, a light-emitting element EL, and a capacitor Cst.

[0130] When a scan signal is applied to the k-th (k is a positive integer) scan line SLk, the switching transistor ST can be turned on. When the switching transistor ST is turned on, the data voltage of the j-th (j is a positive integer) data line DLj can be applied to the gate electrode of the driving transistor DT. The gate electrode of the switching transistor ST can be connected to the k-th scan line SLk, the source electrode of the switching transistor ST can be connected to the gate electrode of the driving transistor DT, and the drain electrode of the switching transistor ST can be connected to the j-th data line DLj.

[0131] The driving transistor DT can allow the light-emitting element to emit light by supplying a driving current to the light-emitting element according to the data voltage applied to its gate electrode. The gate electrode of the driving transistor DT can be connected to the source electrode of the switching transistor ST, the source electrode of the driving transistor DT can be connected to the first electrode of the light-emitting element EL, and the drain electrode of the driving transistor DT can be connected to the second power supply line VDDL to which a second source voltage is applied.

[0132] The driving transistor DT and at least one switching transistor ST can be thin-film transistors. Additionally, in Figure 7 The present specification has shown that the driving transistor DT and at least one switching transistor ST are formed as N-type semiconductor transistors with N-type semiconductor characteristics, but the embodiments herein are not limited thereto. That is, the driving transistor DT and at least one switching transistor ST can be formed as P-type semiconductor transistors with P-type semiconductor characteristics.

[0133] The light-emitting element (EL) can be an organic light-emitting diode (OLED) comprising a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. Optionally, the light-emitting element (EL) can be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. Optionally, the light-emitting element (EL) can be a quantum dot light-emitting element comprising a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first and second electrodes. Optionally, the light-emitting element (EL) can be a miniature light-emitting diode.

[0134] The light-emitting element EL can emit light according to the driving current of the driving transistor DT. The first electrode of the light-emitting element EL can be connected to the source electrode of the driving transistor DT, and the second electrode of the light-emitting element EL can be connected to a first power supply line VSSL that is subjected to a first source voltage lower than the second source voltage. The first electrode of the light-emitting element EL can be an anode electrode, and the second electrode of the light-emitting element EL can be a cathode electrode.

[0135] A capacitor Cst can be connected between the gate and drain electrodes of the driving transistor DT. Therefore, capacitor Cst can be used to maintain a constant data voltage applied to the gate electrode of the driving transistor DT.

[0136] It should also be noted that the structure of each pixel PX is not limited to Figure 7 The structure shown.

[0137] Figure 8 It is shown Figure 5 A circuit diagram of an example of a scan driver stage.

[0138] Reference Figure 8 The first scan driver 120 may include multiple stage STAs, and each stage STA may sequentially output scan signals to scan lines SL. Each stage STA may receive a scan control signal and output a scan signal, and the scan control signal may include a start signal, a gate on voltage, a gate off voltage, and a clock signal.

[0139] like Figure 8 As shown, each of the stages STA includes a pull-up node NQ, a pull-down node NQB, a pull-up transistor TU that is turned on when the pull-up node NQ has a gate on voltage, a pull-down transistor TD that is turned on when the pull-down node NQB has a gate on voltage, and a node controller NC for controlling the charging / discharging of the pull-up node NQ and the pull-down node NQB.

[0140] The node controller NC can be connected to a start terminal STT, which receives a start signal or the output signal of the previous stage; a reset terminal RT, which receives the output signal of the next stage; a gate on-voltage terminal VGHT, which applies a gate on-voltage; and a gate off-voltage terminal VGLT, which applies a gate off-voltage. The node controller NC controls the charging / discharging of the pull-up node NQ and the pull-down node NQB based on the start signal or the output signal of the previous stage input to the start terminal STT. The node controller NC sets the pull-down node NQB to a gate off-voltage when the pull-up node NQ has a gate on-voltage, and sets the pull-up node NQ to a gate off-voltage when the pull-down node NQB has a gate on-voltage, in order to stably control the output of the control stage STA. For this purpose, the node controller NC may include multiple transistors.

[0141] When stage STA is pulled up (i.e., when pull-up node NQ has a gate on-voltage), pull-up transistor TU turns on to output the clock signal input to clock terminal CT to output terminal OT. When stage STA is pulled down (e.g., when pull-down node NQB has a gate on-voltage), pull-down transistor TD turns on to output the gate off-voltage of gate off-voltage terminal VGLT to output terminal OT.

[0142] The pull-up transistor TU, pull-down transistor TD, and multiple transistors of the node controller NC in the stage STA can be formed as thin-film transistors. Additionally, in Figure 8 The pull-up transistor TU, pull-down transistor TD, and multiple transistors of the node controller NC in the stage STA have been shown to be formed as N-type semiconductor transistors with N-type semiconductor characteristics, but the embodiments in this specification are not limited thereto. That is, the pull-up transistor TU, pull-down transistor TD, and multiple transistors of the node controller NC in the stage STA can be formed as P-type semiconductor transistors with P-type semiconductor characteristics.

[0143] Figure 9 It shows along Figure 5 The example sectional view is taken from line II-II'. Figure 10 It shows along Figure 5 A cross-sectional view of an example taken from line III-III'. Figure 11 It is shown Figure 4 An enlarged plan view of an example of region A. Figure 12 It shows along Figure 11 A cross-sectional view of an example taken by line IV-IV'. Figure 19 It shows the setting Figure 9 A plan view of an example sensor electrode on the encapsulation film.

[0144] exist Figure 9 The diagram shows the non-display area NDA and display area DA of the first corner portion CS1 and the planar portion PS. Figure 10 The image shows a cross-section of the organic film pattern TO of the first corner CS1.

[0145] Reference Figure 9 and Figure 10 Thin-film transistor layer (TFTL), light-emitting element layer (EML), and encapsulation film (TFE) can be sequentially formed on substrate 110.

[0146] The thin-film transistor layer (TFTL) includes an active layer 331, a gate metal layer, a first source-drain metal layer, a second source-drain metal layer, a buffer film 302, a gate insulating film 316, an interlayer insulating film 337, a protective film 338, a first planarization film 3391, and a second planarization film 3392.

[0147] A buffer film 302 may be formed on one surface of the substrate 110. The buffer film 302 may be formed on the substrate 110 to protect the thin-film transistor 335 and the light-emitting element from moisture that permeates through the moisture-sensitive substrate 110. The buffer film 302 may comprise a plurality of inorganic films stacked alternately. For example, the buffer film 302 may be formed in which silicon oxide films (SiO2) are stacked alternately. x ), silicon nitride film (SiN)x Multiple membranes consisting of one or more inorganic membranes, such as SiON and 1. Buffer membranes may be omitted.

[0148] Thin-film transistor 335 is formed on buffer film 302. Thin-film transistor 335 may be formed in display area DA of planar portion PS, and first scan driver 120 is disposed in first corner portion CS1.

[0149] Each of the thin-film transistors 335 includes an active layer 331, a gate electrode 332, a source electrode 333, and a drain electrode 334. Figure 9 The thin-film transistor 335 has been shown to be a top-gate type in which the gate electrode 332 is positioned above the active layer 331; however, it should be noted that this disclosure is not limited thereto. That is, the thin-film transistor 335 may be formed as a bottom-gate type in which the gate electrode 332 is positioned below the active layer 331, or as a dual-gate type in which the gate electrode 332 is positioned both above and below the active layer 331.

[0150] An active layer 331 is formed on a buffer film 302. The active layer 331 can be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. A light-blocking layer for blocking external light from entering the active layer 331 can be formed between the buffer film and the active layer 331.

[0151] A gate insulating film 316 can be formed on the active layer 331. The gate insulating film 316 can be, for example, a silicon oxide film (SiO2). x ), silicon nitride film (SiN) x Inorganic membranes of or multiple membranes thereof.

[0152] A gate metal layer, including the gate electrode 332 and the scan line SL, can be formed on the gate insulating film 316. The gate metal layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0153] The interlayer insulating film 337 can be formed on the gate metal layer. The interlayer insulating film 337 can be, for example, a silicon oxide film (SiO2). x ), silicon nitride film (SiN) x Inorganic membranes of or multiple membranes thereof.

[0154] A first source-drain metal layer, including source electrode 333, drain electrode 334, first power line VSSL, data lines D1, D2, D3, D4 and D5, and some of the first fan-out line F1 and the second fan-out line F2, can be formed on the interlayer insulating film 337. Some of the third to fifth fan-out lines F3, F4 and F5 can also be formed in the first source-drain metal layer. Each of the source electrode 333 and drain electrode 334 can be connected to the active layer 331 through a contact hole passing through the gate insulating film 316 and the interlayer insulating film 337. The first source-drain metal layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0155] At the first corner CS1, an organic film pattern TO can be disposed in the hole H that penetrates the buffer film 302, the gate insulating film 316, and the interlayer insulating film 337 to expose the substrate 110. The tension at the first corner CS1 can be increased by forming the organic film pattern TO in the space where the inorganic film has been removed, thus reducing the occurrence of cracks in the inorganic film due to strain at the first corner CS1. The organic film pattern TO can be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0156] A protective film 338 for insulating the thin-film transistor 335 can be formed on the first source-drain metal layer. The protective film 338 can be, for example, a silicon oxide film (SiO2). x ), silicon nitride film (SiN) x Inorganic membranes of or multiple membranes thereof.

[0157] A first planarization film 3391 for planarizing the step caused by the thin-film transistor 335 can be formed on the protective film 338. The first planarization film 3391 can be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0158] A second source-drain metal layer, including the anode connection electrode ANDE and other fan-out lines among the first fan-out line F1 and the second fan-out line F2, can be formed on the first planarization film 3391. Other fan-out lines among the third to fifth fan-out lines F3, F4, and F5 can also be formed in the second source-drain metal layer. The anode connection electrode ANDE can be connected to the source electrode 333 or the drain electrode 334 through contact holes passing through the protective film 338 and the first planarization film 3391.

[0159] The second source-drain metal layer can be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0160] Since the first fan-out line F1 and the second fan-out line F2 are formed at high density in a narrow region such as the non-display area NDA of the planar portion PS and the first corner portion CS1, some of the fan-out lines of the first fan-out line F1 and the second fan-out line F2 can be formed as a first source-drain metal layer, and the other fan-out lines of the first fan-out line F1 and the second fan-out line F2 can be formed as a second source-drain metal layer. For similar reasons, some of the fan-out lines of the third to fifth fan-out lines F3, F4 and F5 can be formed as a first source-drain metal layer, and the other fan-out lines of the third to fifth fan-out lines F3, F4 and F5 can be formed as a second source-drain metal layer. In this case, as Figure 9 As shown, some of the fan-out lines from the first to the fifth fan-out lines F1, F2, F3, F4, and F5, as well as other fan-out lines from the first to the fifth fan-out lines F1, F2, F3, F4, and F5, can be alternately configured. Additionally, as... Figure 9 As shown, some of the outgoing lines from the first to the fifth outgoing lines F1, F2, F3, F4 and F5, and other outgoing lines from the first to the fifth outgoing lines F1, F2, F3, F4 and F5, may not overlap with each other.

[0161] At the pad portion PAS and the bend portion BS where the sixth fan-out line F6 and the first scan driver 120 do not overlap, some of the sixth fan-out lines F6 can be formed as a first source-drain metal layer, and the other sixth fan-out lines F6 can be formed as a second source-drain metal layer. Therefore, some of the sixth fan-out lines F6 and the other sixth fan-out lines F6 can be alternately arranged. Furthermore, some of the sixth fan-out lines F6 and the other sixth fan-out lines F6 can be non-overlapping. Additionally, as... Figure 9 As shown, at the second side surface portion SS2, second edge portion ES2, first corner portion CS1, first edge portion ES1, first side surface portion SS1, second corner portion CS2, third edge portion ES3 and third side surface portion SS3 where the sixth fan-out line F6 and the first scan driver 120 are stacked on each other, the sixth fan-out line F6 can be formed as a second source-drain metal layer.

[0162] At the pad portion PAS and the bend portion BS where the seventh fan-out line F7 and the second scan driver 130 do not overlap, some of the seventh fan-out lines F7 can be formed as a first source-drain metal layer, and the other seventh fan-out lines F7 can be formed as a second source-drain metal layer. Therefore, some of the seventh fan-out lines F7 and the other seventh fan-out lines F7 can be alternately arranged. In addition, some of the seventh fan-out lines F7 and the other seventh fan-out lines F7 can be non-overlapping. Furthermore, at the second side surface portion SS2, the second edge portion ES2, the third corner portion CS3, the fourth edge portion ES4, the fourth side surface portion SS4, the fourth corner portion CS4, the third edge portion ES3, and the third side surface portion SS3 where the seventh fan-out line F7 and the second scan driver 130 overlap, the seventh fan-out line F7 can be formed as a second source-drain metal layer.

[0163] The second planarization film 3392 can be formed on the second source-drain metal layer. The second planarization film 3392 can be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0164] The light-emitting element layer (EML) is formed on the thin-film transistor layer (TFTL). The EML includes a light-emitting element and a pixel defining film 340.

[0165] The light-emitting elements and pixel defining film 340 are formed on the planarization film 339. Each of the light-emitting elements may include a first electrode 341, an organic light-emitting layer 342, and a second electrode 343.

[0166] The first electrode 341 can be formed on the second planarization film 3392. The first electrode 341 can be connected to the anode connection electrode ANDE through a contact hole through the second planarization film 3392.

[0167] In the top-emitting structure in which light is emitted from the organic light-emitting layer 342 toward the second electrode 343, the first electrode 341 can be formed of a metallic material with high reflectivity (such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO) (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO)). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0168] The pixel defining film 340 can be formed on the second planarization film 3392 to delineate the first electrode 341 for defining the emission region of each of pixels PX1, PX2, and PX3. The pixel defining film 340 can be formed to cover the edge of the first electrode 341. The pixel defining film 340 can be formed as an organic film made of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0169] Additionally, the spacer SPC can be formed in the first corner portion CS1 on the second planarization film 3392. The spacer SPC can be made of the same material as the pixel defining film 340 and disposed on the same layer as the pixel defining film 340.

[0170] Each of pixels PX1, PX2, and PX3 has a first electrode 341, an organic light-emitting layer 342, and a second electrode 343 stacked sequentially therein, and holes from the first electrode 341 and electrons from the second electrode 343 recombine with each other in the organic light-emitting layer 342 to emit light.

[0171] An organic light-emitting layer 342 is formed on the first electrode 341 and the pixel defining film 340. The organic light-emitting layer 342 may include organic materials to emit light of a predetermined color. For example, the organic light-emitting layer 342 may include a hole transport layer, an organic material layer, and an electron transport layer. The organic light-emitting layer 342 of the first pixel PX1 may emit light of a first color, the organic light-emitting layer 342 of the second pixel PX2 may emit light of a second color, and the organic light-emitting layer 342 of the third pixel PX3 may emit light of a third color. Optionally, the organic light-emitting layers 342 of pixels PX1, PX2, and PX3 may emit white light, and in this case, the first pixel PX1 may be stacked with a color filter layer of the first color, the second pixel PX2 may be stacked with a color filter layer of the second color, and the third pixel PX3 may be stacked with a color filter layer of the third color. In this specification, for ease of explanation, the first color has been primarily described as red, the second color as green, and the third color as blue.

[0172] The second electrode 343 is formed on the organic light-emitting layer 342. The second electrode 343 may be formed to cover the organic light-emitting layer 342. The second electrode 343 may be a common layer formed together in pixels PX1, PX2, and PX3. A capping layer may be formed on the second electrode 343.

[0173] The second electrode 343 can be connected to the first power line VSSL in the non-display area NDA of the planar portion PS. The second electrode 343 can be connected to the first power line VSSL through contact holes passing through the first planarization film 3391 and the second planarization film 3392.

[0174] In the top-emitting structure, the second electrode 343 can be formed of a transparent conductive material (TCO) (such as ITO or indium zinc oxide (IZO)) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)) capable of transmitting transmitted light. When the second electrode 343 is formed of a semi-transmissive conductive material, the emission efficiency can be improved through the microcavity.

[0175] The encapsulation film TFE can be formed on the light-emitting element layer EML. The encapsulation film TFE may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer EML. Alternatively, the encapsulation film TFE may include at least one organic film to protect the light-emitting element layer EML from foreign matter such as dust. For example, the encapsulation film TFE may include a first inorganic film 351 disposed on the second electrode 343, an organic film 352 disposed on the first inorganic film 351, and a second inorganic film 353 disposed on the organic film 352.

[0176] The dam DAM can be located in the non-display area NDA of the planar portion PS. The dam DAM can be configured to cover a portion of the first power line VSSL. The first planarization film 3391, the second planarization film 3392, the pixel defining film 340, and the organic film 352 of the encapsulation film TFE can be blocked by the dam DAM, and the first inorganic film 351 and the second inorganic film 353 of the encapsulation film TFE can be in contact with each other on the dam DAM. The first inorganic film 351 and the second inorganic film 353 of the encapsulation film TFE can be configured to not exceed the first angular bending line CBL1.

[0177] The encapsulation film TFE is configured to cover the display area DA and non-display area NDA of the planar portion PS, but not to cover the first corner portion CS1. Therefore, the first scan driver 120, the second fan-out line F2, and the sixth fan-out line F6 of the first corner portion CS1 are not covered by the encapsulation film TFE.

[0178] exist Figure 9 The first scan driver 120, the second fan-out line F2, and the sixth fan-out line F6 of the first corner CS1 have been shown not to be covered by the first inorganic film 351, the organic film 352, and the second inorganic film 353 of the encapsulation film TFE, but this disclosure is not limited thereto. For example, the first scan driver 120, the second fan-out line F2, and the sixth fan-out line F6 of the first corner CS1 may be covered by the organic film 352 of the encapsulation film TFE, instead of being covered by the first inorganic film 351 and the second inorganic film 353.

[0179] It is equipped with sensor electrodes SE for sensing user touch input or proximity input (see Figure 19The sensor electrode layer can be disposed on the encapsulation film TFE. When the sensor electrode SE is superimposed on the first to third pixels PX1, PX2, and PX3, the first to third pixels PX1, PX2, and PX3 are hidden by the sensor electrode SE. Therefore, as... Figure 19 As shown, the sensor electrode SE may not be stacked with the first to third pixels PX1, PX2, and PX3. The sensor electrode SE may be stacked with the pixel defining film 340. For example, as... Figure 19 As shown, the sensor electrode SE can be formed in a grid shape or a mesh shape in a planar view.

[0180] The sensor electrode SE can sense user touch or proximity input as either self-capacitance or mutual capacitance. In the self-capacitance type, the sensor electrode SE can be formed on a single layer. In the mutual capacitance type, the sensor electrode SE may include a driving electrode, a sensing electrode, and a connecting electrode connecting adjacent driving or sensing electrodes to each other. In the mutual capacitance type, the driving electrode, sensing electrode, and connecting electrode can be formed on a single layer. Optionally, in the mutual capacitance type, the driving electrode and sensing electrode can be formed on a first layer, the connecting electrode can be formed on a second layer, and the first and second layers can be electrically separated from each other by an insulating film.

[0181] exist Figure 19 The diagram has shown that each of the first to third pixels PX1, PX2, and PX3 is formed in a rectangular shape, such as a rhombus, in a planar view; however, this disclosure is not limited thereto. Each of the first to third pixels PX1, PX2, and PX3 can be formed in a polygonal shape other than a circular or rectangular shape in a planar view.

[0182] like Figure 19 As shown, a first pixel PX1, two second pixels PX2, and a third pixel PX3 can be defined as a unit pixel PX. In this case, the size of the second pixel PX2 can be smaller than the size of the first pixel PX1 or the size of the third pixel PX3. A unit pixel PX refers to a group of pixels capable of representing white grayscale.

[0183] Due to the bending forces of the first edge portion ES1 and the first side surface portion SS1, as well as the bending forces of the second edge portion ES2 and the second side surface portion SS2, strain is applied to the first corner portion CS1. When the encapsulation film TFE is formed in the first corner portion CS1, cracks will appear in the encapsulation film TFE due to the strain of the first corner portion CS1. When cracks appear in the encapsulation film, the light-emitting element EL of the pixel PX will be exposed to oxygen or moisture. Therefore, in order to prevent cracks from appearing in the encapsulation film TFE due to the strain of the first corner portion CS1, the encapsulation film TFE is not formed in the first corner portion CS1. Since the light-emitting element layer EML is not formed in the first corner portion CS1, the corner does not need to be covered by the encapsulation film TFE. Therefore, the first scan driver 120, the second fan-out line F2, and the sixth fan-out line F6 of the first corner portion CS1 are not covered by the encapsulation film TFE.

[0184] At the same time, Figure 5 and Figure 9 The second fan-out line F2 has been shown to be located at the first corner CS1 and is not covered by the encapsulation film TFE, but this disclosure is not limited thereto. For example, as Figure 11 and Figure 12 As shown, the second fan-out line F2 can be located in the non-display area NDA of the planar portion PS, instead of in the first corner portion CS1. In this case, in the non-display area NDA of the planar portion PS, the second fan-out line F2 can be located closer to the first corner portion CS1 than the first fan-out line F1. Alternatively, in the non-display area NDA of the planar portion PS, the second fan-out line F2 can be located between the first power line VSSL and the first fan-out line F1.

[0185] Figure 13 It is shown Figure 4 An enlarged plan view of an example of region C. Figure 14 It is shown Figure 4 An enlarged plan view of an example of region D. Figure 15 It shows along Figure 13 A cross-sectional view of an example cut by line V-V'.

[0186] Figure 13 It is a detailed enlarged plan view showing the second corner CS2 and the planar portion PS, the first edge portion ES1 and the third edge portion ES3 surrounding the second corner CS2. Figure 14 This is a detailed enlarged plan view of the third side surface portion SS3.

[0187] Figures 13 to 15 The embodiments shown are similar to Figure 5 , Figure 6 and Figure 9 The difference in the embodiment shown is that the first outgoing line F1 and the second outgoing line F2 are omitted. Therefore, in Figures 13 to 15 In the middle, omission and Figure 5 , Figure 6 and Figure 9 The description of the embodiments shown is repeated.

[0188] Reference Figures 13 to 15 The first outgoing line F1 is as follows Figure 5 As shown, the first data line D1 is connected to the flat portion PS around the first corner CS1, and is therefore located in the pad portion PAS, the curved portion BS, the second side surface portion SS2, and the flat portion PS. Therefore, the first fan-out line F1 is not present in the flat portion PS around the second corner CS2. Furthermore, the second fan-out line F2 is as follows... Figure 6 As shown, the second data line D2 is connected to the lower short side of the first side surface portion SS1, and is therefore provided in the pad portion PAS, the bend portion BS, the second side surface portion SS2, the first corner portion CS1, the first edge portion ES1, and the first side surface portion SS1. Therefore, the second fan-out line F2 is not present in the second corner portion CS2.

[0189] Figure 16 This is a perspective view showing a display device according to an embodiment. Figure 17 It shows along Figure 16 The example sectional view is taken by line VI-VI'. Figure 18 It shows along Figure 16 The example sectional view is taken from line VII-VII'.

[0190] Reference Figures 16 to 18 The display device 10 according to the embodiment is a device for displaying moving or still images, and can be used as a display screen for each of various products such as televisions, laptops, monitors, billboards and Internet of Things (IoT) devices and portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs).

[0191] The display device 10 may include a display panel 100, a touch sensing device 200, a cover window 300, and a panel under-contact member 400.

[0192] The coverage window 300 may include a coverage plane portion CPS, a first coverage side surface portion CSS1, a second coverage side surface portion CSS2, a third coverage side surface portion CSS3, a fourth coverage side surface portion CSS4, a first coverage edge portion CES1, a second coverage edge portion CES2, a third coverage edge portion CES3, a fourth coverage edge portion CES4, a first coverage corner portion CCS1, a second coverage corner portion CCS2, a third coverage corner portion CCS3, and a fourth coverage corner portion CCS4.

[0193] The covering plane portion CPS of the cover window 300 can correspond to the flat portion PS of the display panel 100. The first covering side surface portion CSS1 of the cover window 300 can correspond to the first side surface portion SS1 of the display panel 100, and the second covering side surface portion CSS2 of the cover window 300 can correspond to the second side surface portion SS2 of the display panel 100. The third covering side surface portion CSS3 of the cover window 300 can correspond to the third side surface portion SS3 of the display panel 100, and the fourth covering side surface portion CSS4 of the cover window 300 can correspond to the fourth side surface portion SS4 of the display panel 100. The first covering edge portion CES1 of the cover window 300 can correspond to the first edge portion ES1 of the display panel 100, and the second covering edge portion CES2 of the cover window 300 can correspond to the second edge portion ES2 of the display panel 100. The third covering edge CES3 of the cover window 300 can correspond to the third edge ES3 of the display panel 100, and the fourth covering edge CES4 of the cover window 300 can correspond to the fourth edge ES4 of the display panel 100. The first covering corner CCS1 of the cover window 300 can correspond to the first corner CS1 of the display panel 100, and the second covering corner CCS2 of the cover window 300 can correspond to the second corner CS2 of the display panel 100. The third covering corner CCS3 of the cover window 300 can correspond to the third corner CS3 of the display panel 100, and the fourth covering corner CCS4 of the cover window 300 can correspond to the fourth corner CS4 of the display panel 100.

[0194] Since the first coverage corner CCS1 of the cover window 300 should cover the first corner CS1 and the first dead zone DS1 of the display panel 100, the width of the first coverage corner CCS1 of the cover window 300 can be equal to or greater than the width of the first coverage corner CCS1. Figure 2b The sum of the width of the first corner CS1 and the width of the first dead zone DS1 of the display panel 100 shown.

[0195] Since the second coverage corner CCS2 of the cover window 300 should cover the second corner CS2 and the second dead zone DS2 of the display panel 100, the width of the second coverage corner CCS2 of the cover window 300 can be equal to or greater than that of the second coverage corner CCS2. Figure 2b The width of the second corner CS2 and the width of the second dead zone DS2 of the display panel 100 shown are combined.

[0196] Since the third coverage corner CCS3 of the cover window 300 should cover the third triangular portion CS3 and the third dead zone DS3 of the display panel 100, the width of the third coverage corner CCS3 of the cover window 300 can be equal to or greater than that of the third coverage corner CCS3. Figure 2b The sum of the width of the triangular portion CS3 and the width of the third dead zone DS3 of the display panel 100 shown.

[0197] Since the fourth coverage corner CCS4 of the cover window 300 should cover the fourth corner CS4 and the fourth dead zone DS4 of the display panel 100, the width of the fourth coverage corner CCS4 of the cover window 300 can be equal to or greater than that of the fourth coverage corner CCS4. Figure 2b The sum of the width of the fourth corner CS4 and the width of the fourth dead zone DS4 of the display panel 100 shown.

[0198] Cover window 300 can be used to protect the flat portion PS, edge portions ES1, ES2, ES3 and ES4, and the upper portion of the side surfaces SS1, SS2, SS3 and SS4 of the display panel 100. Cover window 300 can be made of glass, sapphire, and / or plastic. Cover window 300 can be formed as rigid or flexible. Cover window 300 may include light-blocking portions formed in the regions corresponding to the first to fourth dead zones DS1, DS2, DS3 and DS4. The light-blocking portions may include opaque materials such as black dye.

[0199] The cover window 300 can be attached to the touch sensing device 200 via an adhesive component. The adhesive component can be an optically clear adhesive film (OCA) or an optically clear resin (OCR).

[0200] A touch sensing device 200 can be disposed between the cover window 300 and the display panel 100. The touch sensing device 200 can be disposed on the planar portion PS, edge portions ES1, ES2, ES3 and ES4, and side surface portions SS1, SS2, SS3 and SS4 of the display panel 100. Therefore, the touch sensing device 200 can sense user touches on the planar portion PS, edge portions ES1, ES2, ES3 and ES4, and side surface portions SS1, SS2, SS3 and SS4 of the display device 10.

[0201] The touch sensing device 200 can sense a user's touch as capacitive, such as self-capacitance or mutual capacitance. When the touch sensing device 200 is implemented as self-capacitance, it may only include a touch driving electrode, while when it is implemented as mutual capacitance, it may include both a touch driving electrode and a touch sensing electrode.

[0202] The touch sensing device 200 may include a separate substrate and touch driving electrodes disposed on the separate substrate. In this case, the touch sensing device 200 can be attached to the thin-film encapsulation film of the display panel 100 by means of an adhesive member. The adhesive member may be an optically transparent adhesive film (OCA) or an optically transparent resin (OCR). Alternatively, the touch sensing device 200 may be integrally formed with the display panel 100. In this case, the touch driving electrodes and touch sensing electrodes of the touch sensing device 200 may be formed on the thin-film encapsulation film of the display panel 100.

[0203] A polarizing film to prevent visibility degradation due to reflection of external light can be added between the cover window 300 and the touch sensing device 200. In this case, the touch sensing device 200 can be attached to the lower surface of the polarizing film, and the polarizing film can be attached to the lower surface of the cover window 300 by an adhesive member.

[0204] like Figure 4 As shown, the curved portion BS can be provided on one side of the second side surface portion SS2 of the display panel 100, and the pad portion PAS can be provided on one side of the curved portion BS. Figure 18 As shown, since the curved portion BS is bent at a predetermined curvature, the pad portion PAS can be disposed below the flat portion PS. That is, the pad portion PAS can be superimposed on the flat portion PS in the third direction (Z-axis direction).

[0205] The integrated drive circuit 140 can be disposed in the pad PAS. The integrated drive circuit 140 can be disposed on the substrate 110 by means of chip-on-glass (COG), chip-on-plastic (COP), or ultrasonic bonding. Optionally, the integrated drive circuit 140 can be disposed on the circuit board 150 by means of chip-on-plastic (COP).

[0206] The circuit board 150 can be attached to one side of the pad portion PAS. The circuit board 150 can be attached to the pad portion PAS using an anisotropic conductive film. The circuit board 150 can be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0207] like Figure 18 As shown, the lower panel member 400 can be disposed below the display panel 100. The lower panel member 400 can be attached to the lower surface of the display panel 100 by means of an adhesive member. The adhesive member can be a pressure-sensitive adhesive (PSA).

[0208] The panel under-panel component 400 may include at least one of the following: a light-absorbing component for absorbing external incident light, a buffer component for absorbing external impact, a heat dissipation component for effectively dissipating heat from the display panel 100, and a light-blocking layer for blocking external incident light.

[0209] A light-absorbing component may be disposed below the display panel 100. The light-absorbing component blocks the transmission of light to prevent components disposed below the light-absorbing component from being visible from above the display panel 100. The light-absorbing component may include a light-absorbing material such as black pigment or dye.

[0210] A buffer member can be disposed below the light-absorbing member. The buffer member absorbs external impacts to prevent damage to the display panel 100. The buffer member can be formed as a single layer or multiple layers. For example, the buffer member can be formed from a polymer resin such as polyurethane, polycarbonate, polypropylene, or polyethylene, or can include an elastic material such as a sponge formed by foamed rubber, urethane materials, or acrylic materials.

[0211] The heat dissipation component can be disposed below the buffer component. The heat dissipation component may include a first heat dissipation layer and a second heat dissipation layer. The first heat dissipation layer includes graphite or carbon nanotubes, and the second heat dissipation layer is formed as a thin metal film such as copper, nickel, ferrite or silver that can shield electromagnetic waves and has excellent thermal conductivity.

[0212] The embodiments of this disclosure have been described above with reference to the accompanying drawings. However, those skilled in the art will understand that various modifications and changes can be made without departing from the technical spirit or essential characteristics of this disclosure. Therefore, it will be understood that the above embodiments are exemplary in all respects and not restrictive.

Claims

1. A display panel, the display panel comprising: The base includes a planar portion, a first edge portion extending from one side of the planar portion, a second edge portion extending from the other side of the planar portion, a first side surface portion extending from one side of the first edge portion, and a first corner portion disposed between the first edge portion and the second edge portion; A first data cable is disposed in the display area of ​​the flat portion; The second data line is disposed in the display area of ​​the first side surface. The first fan-out cable is located in the non-display area of ​​the flat portion and is connected to the first data cable; The second fan-out line is located in the first corner and connected to the second data line; The light-emitting element is disposed on the first data line in the display area of ​​the planar portion and on the second data line in the display area of ​​the first side surface portion, and each includes a first electrode, a light-emitting layer and a second electrode; A scan driver is disposed outside the second fan-out line in the first corner; as well as An encapsulation film is configured to cover the light-emitting element and comprises at least one inorganic film and at least one organic film. Wherein, the at least one inorganic membrane and the at least one organic membrane cover the first data line, the second data line, and the first fan-out line, and The scanning driver is not covered by the at least one inorganic membrane.

2. The display panel according to claim 1, wherein, The second fan-out line is not covered by the at least one inorganic membrane.

3. The display panel according to claim 1, wherein, The at least one inorganic membrane and the at least one organic membrane do not cover the second fan-out line.

4. The display panel according to claim 1, wherein the display panel further comprises a first source voltage line disposed between the first fan-out line and the second fan-out line at the first corner.

5. The display panel according to claim 4, wherein, The at least one inorganic membrane and the at least one organic membrane cover the first source voltage line.

6. The display panel according to claim 1, wherein, The second fan-out line is located in the non-display area of ​​the first side surface.

7. The display panel according to claim 1, further comprising: Scan lines are disposed in the display area of ​​the planar portion and intersect with the first data lines. The scan driver includes stages connected to the scan lines.

8. The display panel according to claim 7, wherein, The level is not covered by the at least one inorganic membrane.

9. The display panel according to claim 7, wherein the display panel further comprises an organic film pattern disposed between adjacent levels in the level.

10. The display panel of claim 9, further comprising a scan control line connected to the stage and intersecting the organic film pattern.

11. The display panel according to claim 10, wherein, At least one of the scan control lines is disposed on a different layer than the first data line and the second data line.

12. The display panel according to claim 1, wherein, At least one of the first fan-out lines and at least one of the second fan-out lines are disposed on the same layer as the first data line and the second data line.

13. The display panel according to claim 1, wherein, At least one of the first fan-out lines and at least one of the second fan-out lines are disposed on a different layer than the first data line and the second data line.

14. A display panel, the display panel comprising: The substrate includes a planar portion, a first edge portion that bends from the planar portion along a first curvature line, a second edge portion that bends from the planar portion along a second curvature line, and a first side surface portion that extends from one side of the first edge portion. A first data cable is disposed in the display area of ​​the flat portion; The second data line is disposed in the display area of ​​the first side surface. The first fan-out line is disposed inside the first angle bend line defined by the first bend line and the second bend line and is connected to the first data line; A scan driver is positioned outside the first angular bend line; as well as An encapsulation film is configured to cover the display area of ​​the planar portion and comprises at least one inorganic film and at least one organic film. Wherein, at least one inorganic membrane is not disposed outside the first angular bending line.

15. The display panel according to claim 14, the display panel further comprising a second fan-out line disposed outside the first angular bend line and connected to the second data line.

16. The display panel according to claim 14, the display panel further comprising a second fan-out line disposed inside the first angular bend line and connected to the second data line.

17. The display panel according to claim 15 or 16, wherein the display panel further comprises a first source voltage line disposed between the first fan-out line and the second fan-out line.

18. The display panel according to claim 17, wherein, The first source voltage line is located inside the first angled bend line.

19. The display panel according to claim 15 or 16, further comprising: Scan lines are disposed in the display area of ​​the planar portion and intersect with the first data lines. The scan driver includes a stage connected to the scan line and disposed outside the first angular bend line.

20. The display panel according to claim 19, wherein, The stage is located outside the second fan-out line.

21. The display panel according to claim 19, further comprising: A light-emitting element is disposed on the first data line in the display area of ​​the planar portion and on the second data line in the display area of ​​the first side surface portion, and each includes a first electrode, a light-emitting layer, and a second electrode, wherein the encapsulation film is configured to cover the light-emitting element, and The at least one inorganic membrane and the at least one organic membrane cover the first data line, the second data line, and the first fan-out line.

22. The display panel according to claim 21, wherein, The at least one inorganic membrane and the at least one organic membrane are disposed inside the first angular bending line.

23. A display device, the display device comprising: Display panel; as well as A cover window is positioned above the display panel. The display panel includes: a substrate comprising a planar portion, a first edge portion extending from one side of the planar portion, a second edge portion extending from the other side of the planar portion, a first side surface portion extending from one side of the first edge portion, and a first corner portion disposed between the first edge portion and the second edge portion; a first data line disposed in the display area of ​​the planar portion; a second data line disposed in the display area of ​​the first side surface portion; a first fan-out line disposed in the non-display area of ​​the planar portion and connected to the first data line; a second fan-out line disposed in the first corner portion and connected to the second data line; light-emitting elements disposed in the display area of ​​the planar portion on the first data line and in the display area of ​​the first side surface portion on the second data line, each including a first electrode, a light-emitting layer, and a second electrode; a scan driver disposed in the first corner portion outside the second fan-out line; and an encapsulation film configured to cover the light-emitting elements and comprising at least one inorganic film and at least one organic film. The at least one inorganic membrane and the at least one organic membrane cover the first data line, the second data line, and the first fan-out line, and The scanning driver is not covered by the at least one inorganic membrane.

24. The display device according to claim 23, wherein, The covering window includes a covering plane portion corresponding to the planar portion, a first covering edge portion corresponding to the first edge portion, a second covering edge portion corresponding to the second edge portion, a first covering side surface portion corresponding to the first side surface portion, and a first covering corner portion corresponding to the first corner portion.

25. The display device according to claim 24, wherein, The width of the first covered corner is greater than the width of the first corner.

Images