Configuring multiple register clock drivers of a memory subsystem

Abstract

This application relates to configuring multiple register clock drivers of a memory sub-system. In some examples, configuration of two RCD devices with different configuration information can include receiving and storing first RCD configuration data using a serial data bus, the configuration data provided to both the RCD devices to configure one or more parameters of each respective RCD device. One of the RCD devices can be capable of receiving second configuration data via a command and address bus to independently update the one or more configuration parameters of one of the two RCD devices.

Description

Technical Field

[0001] This application relates to a memory system, and more particularly to a multiple register clock driver for configuring a memory subsystem. Background Technology

[0002] High data reliability, high memory access speed, low power consumption, and reduced chip / package size are characteristics required for semiconductor memories. In some memory module implementations, the number of memory dies that can be supported may be limited by the signaling drivers on the module. For example, a register clock driver's subchannel driver circuitry may only have the physical capacity to drive command and address bus information to a fixed number of memory devices within the memory module. Furthermore, existing memory module architectures only support a single register clock driver chip. Therefore, the register clock driver circuitry may limit the number of memory devices that can be supported, which may limit the size of the memory module. Summary of the Invention

[0003] According to one aspect of this application, an apparatus is provided. The apparatus includes: a first register clock driver configured to receive first configuration data from a memory controller via a first command and address bus, comprising first configuration data in first sub-channel command and address information corresponding to a channel; a second register clock driver configured to receive the first configuration data from the memory controller via a second command and address bus, comprising second sub-channel command and address information corresponding to the channel; and a control plane hub configured to receive the first configuration data via a serial data bus and provide the first configuration data to the first register clock driver and the second register clock driver.

[0004] According to another aspect of this application, a memory subsystem is provided. The memory subsystem includes: a first memory package containing a first register clock driver configured to receive first subchannel commands and address information corresponding to a channel via a first bus; a second memory package containing a second register clock driver configured to receive second subchannel commands and address information corresponding to the channel via a second bus; and a control plane hub configured to receive first configuration data via a third bus and provide the first configuration data to the first register clock driver and the second register clock driver.

[0005] According to another aspect of this application, a method is provided. The method includes: receiving first configuration data from a memory controller via a first bus at a control plane hub of a memory subsystem; providing the first configuration data to a first register clock driver and a second register clock driver of the memory subsystem, wherein the first register clock driver and the second register clock driver each set a corresponding configuration parameter to a first value based on the first configuration data; and receiving second configuration data from the memory controller via a second bus at the first register clock driver, wherein the first register clock driver sets the corresponding configuration parameter to a second value based on the second configuration data. Attached Figure Description

[0006] Figure 1 This is a block diagram of a memory system including a memory subsystem according to an embodiment of the present disclosure.

[0007] Figure 2 This is a block diagram of a memory system including a memory subsystem coupled to a memory controller, according to an embodiment of the present disclosure.

[0008] Figure 3A and 3B These are block diagrams of a dual-stacked memory package and a single-stacked memory package according to embodiments of the present disclosure.

[0009] Figure 4 This is a block diagram of a memory system including a memory subsystem coupled to a memory controller, according to an embodiment of the present disclosure.

[0010] Figure 5 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 6 This is a timing diagram of a dual-register clock driver for configuring a memory subsystem according to an embodiment of the present disclosure.

[0012] Figure 7 This is a flowchart of a method for configuring a dual-register clock driver for a memory subsystem according to an embodiment of the present disclosure. Detailed Implementation

[0013] This disclosure describes methods, systems, and apparatus for configuring a dual-register clock driver (RCD) device on a single memory subsystem with different configuration information. Some memory device standards consider a single RCD device memory subsystem architecture and a corresponding configuration procedure for a single RCD device. In some instances based on these standards, configuring two RCD devices with different configuration information may involve using a serial data bus (e.g., including a serial clock signal SCL and a serial data signal SDA) to receive and store first RCD configuration data, which is provided to both RCD devices to configure one or more parameters of each respective RCD device. Subsequently, one of the RCD devices may receive second configuration data via a command and address bus to update the one or more configuration parameters of one of the two RCD devices. In some instances, the serial data bus may include an SM bus or an I bus. 2 C-bus. The one or more configuration parameters may relate to the configuration of the receiver components (e.g., one or more coefficients of the decision feedback equalizer (DFE), the configuration of the transmitter components (e.g., one or more coefficients of the feedforward equalizer (FFE), timing parameters, power levels, etc., or any combination thereof.

[0014] In some architectures, for a single channel, the memory controller (e.g., the host, central processing unit, one or more other processor units, etc.) can provide corresponding command and address (C / A) information in parallel via two independent sub-channels (e.g., using correspondingly different sets of C / A signal lines) along with a single clock signal used to synchronize the timing of the two sub-channels. This allows the corresponding C / A information for each sub-channel to be simultaneously provided to the corresponding group (e.g., memory rank, memory package, or some other grouping) of the memory (e.g., die, device, etc.). Therefore, in a dual RCD device implementation, the clock signal can be separated (e.g., via a clock tee) so that the clock signal is simultaneously provided to both RCD devices to reduce the possibility of asynchronous timing between the two RCD devices. In one example, the first and second RCD devices can be configured to provide first and second sub-channel C / A information to corresponding first and second sets of memory in the memory subsystem, respectively. However, physical differences in the arrangement of each RCD device relative to the corresponding C / A bus and the corresponding memory group, as well as process differences within each RCD device or the connected memory, may result in different configurations between the two RCD devices. Therefore, to accommodate different configurations, two RCD devices can be configured based on first configuration data received via a serial data bus from a control plane hub (e.g., a chip, device, circuit, etc.), and then the first of the RCDs can be configured based on second configuration data received from the first sub-channel C / A information received via the first C / A bus. As previously mentioned, the ability to independently configure more than one RCD device on the memory subsystem improves the reliability of the dual RCD device memory subsystem architecture.

[0015] Figure 1This is a block diagram of a memory system 100 including a memory subsystem 104 according to one embodiment of the present disclosure. The memory subsystem 104 may be coupled to a serial data bus SCL / SDA, a C / AA bus, a C / AB bus, and a clock bus providing a clock signal CLK to receive commands and address information from a memory controller (e.g., a host, central processing unit, one or more other processor units or controllers, a DRAM controller, etc.) (not shown) of the memory system 100. The memory subsystem 104 may include a control plane hub 116, a memory package 110 (1), and a memory package 110 (2). The memory subsystem 104 may include memory modules, such as dual in-line memory modules (DIMMs) (e.g., registered DIMMs, load-reduced DIMMs (LRDIMMs), micro DIMMs, non-volatile DIMMs (NVDIMMs) (e.g., containing non-volatile memory and a controller (not shown)) or any other type of DIMM). In some instances, the memory subsystem 104 may include a soldered memory subsystem different from the memory modules and / or DIMMs.

[0016] Control plane hub 116 is configured to receive and store configuration data from the memory controller via the SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to components of memory subsystem 104 and / or one or both of memory packages 110(1) and 110(2). In some instances, the SCL / SDA bus may include an SM bus or an I bus. 2 C-bus. Configuration data may include configuration data relating to the operation of memory subsystem 104 and memory packages 110(1) and 110(2), such as timing parameters, addressing parameters, power levels, receiver and transmitter component coefficients, etc., or any combination thereof. Control plane hub 116 may provide configuration data to memory packages 110(1) and 110(2) during operation. Control plane hub 116 may include chips, devices, circuitry, etc. In some instances, control plane hub 116 may include electrically erasable programmable read-only memory (EEPROM), which is configured in some instances to store configuration data.

[0017] Memory package 110(1) may include register clock driver circuitry 112(1) coupled to memory 114(1), and memory package 110(2) may include register clock driver circuitry 112(2) coupled to memory 114(2). Register clock driver circuitry 112(1) and register clock driver circuitry 112(2) may be configured to receive configuration data from control plane hub 116 to set one or more configurable parameters for operation. The one or more configurable parameters may include timing parameters, power levels, addressing parameters, receiver and transmitter component coefficients (e.g., DFE or FFE coefficients), or any combination thereof.

[0018] The register clock driver circuit 112(1) can also be configured to receive first sub-channel C / A information from the C / AA bus and the CLK signal, and the register clock driver circuit 112(2) can also be configured to receive second sub-channel C / A information from the C / AB bus and the CLK signal. The first and second sub-channel C / A information can correspond to the C / A information of a single channel. The first and second sub-channel C / A information can contain memory access commands and addresses, chip select signals, etc., corresponding to the first and second sub-channels, respectively. The register clock driver circuit 112(1) can provide the first sub-channel C / A information in parallel to each of the C / A A1-A4 buses in response to the CLK signal, and the register clock driver circuit 112(2) can provide the second sub-channel C / A information in parallel to each of the C / A B1-B4 buses in response to the CLK signal.

[0019] In some instances, the first subchannel C / A information may also include information for configuring components of memory package 110(1). For example, the first subchannel C / A information may include second configuration data for setting one or more configurable parameters of register clock driver circuit 112(1).

[0020] Each memory in memory 114(1) may be coupled to a corresponding one of the C / A A1-A4 buses to receive first sub-channel C / A information, and each memory in memory 114(2) may be coupled to a corresponding one of the C / A B1-B4 buses to receive second sub-channel C / A information. Each memory in memory 114(1) may also be coupled to a corresponding data bus to receive write data from the memory controller and provide read data to the memory controller in response to the first sub-channel C / A information. Additionally, each memory in memory 114(2) may be coupled to a corresponding data bus to receive write data from the memory controller and provide read data to the memory controller in response to the second sub-channel C / A information. Memory 114(1) and / or memory 114(2) may each comprise one or more memory devices, packages, and / or memory dies. In some instances, the one or more memory devices or packages may each comprise one or more memory die stacks. In some instances, memory 114(1) and / or memory 114(2) may each contain dynamic random access memory (DRAM) (e.g., double data rate (DDR) 4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.).

[0021] In operation, for a given communication channel, the memory controller of the memory system 100 can simultaneously provide the corresponding first and second sub-channel C / A information via two independent sub-channels through the C / AA bus and the C / AB bus, along with a single clock signal used to synchronize the timing of the two sub-channels to the memory subsystem 104.

[0022] In some instances, memory subsystem 104 may further include a control plane hub 116 configured to receive and store configuration data from the memory controller via an SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to components of memory subsystem 104 (e.g., thermal sensors, power management integrated circuits, etc.) and / or one or both of memory packages 110(1) and 110(2). The configuration data may include configuration data relating to the operation of memory subsystem 104 and the operation of memory packages 110(1) and 110(2), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. Control plane hub 116 may provide configuration data to memory packages 110(1) and 110(2) during operation and / or initialization.

[0023] Specifically, the control plane hub 116 can be configured to simultaneously provide at least some of the configuration data to the register clock driver circuits 112(1) and 112(2). The configuration data can be used to configure one or more parameters of the register clock driver circuits 112(1) and 112(2), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. In some instances, the configuration data can be the same configuration data from the control plane hub 116. However, physical differences in the arrangement of each of the register clock driver circuits 112(1) and 112(2) relative to the corresponding C / AA or B bus and the corresponding memory 114(1) or 114(2), as well as process differences within each of the register clock driver circuits 112(1) and 112(2) or the connected memories 114(1) and 114(2), may result in different configurations between the register clock driver circuits 112(1) and 112(2). Therefore, in order to adapt to different configurations, the register clock driver circuit 112(1) can be configured to receive second configuration data via the first sub-channel C / A information, and can update one or more parameters of the register clock driver circuit 112(1) based on the second configuration data.

[0024] The memory package 110(1) is configured to receive and respond to a first subchannel C / A message to receive and store write data at memory 114(1) and provide read data from the memory to the memory controller via a corresponding data bus, and the memory package 110(2) is configured to receive and respond to a second subchannel C / A message to receive and store write data at memory 114(2) and provide read data from the memory to the memory controller via a corresponding data bus.

[0025] Register clock driver circuits 112(1) and 112(2) can each be configured to drive first and second sub-channel C / A information received from the C / AA bus and C / AB bus, respectively, to the C / A A1-A4 bus and C / A B1-B4 bus in response to a CLK signal. The CLK signal can be separated (e.g., via a clock tee) so that it is simultaneously routed to and received by register clock driver circuits 112(1) and 112(2). The clock tee can be arranged (e.g., impedance matching, trace length and shape, etc.) to reduce the possibility of timing differences between register clock driver circuits 112(1) and 112(2). Each of the register clock driver circuits 112(1) and 112(2) may include dual (e.g., A and B) independent sub-channel driver circuits, each configured to drive corresponding sub-channel C / A information to corresponding two of the C / A A1-A4 buses or corresponding two of the C / A B1-B4 buses. For example, in response to a CLK signal, the first sub-channel driver circuit of register clock driver circuit 112(1) may provide first sub-channel C / A information to the C / A A1-A2 bus, and the second sub-channel driver circuit of register clock driver circuit 112(1) may provide first sub-channel C / A information to the C / A A3-A4 bus. The sub-channel driver circuits of register clock driver circuit 112(2) may similarly provide second sub-channel C / A information to corresponding two of the C / A B1-B4 buses in response to a CLK signal.

[0026] Memory 114(1) can be divided into four subsets, each subset having its memory coupled to a single C / A A1-A4 bus to receive first sub-channel C / A information. Similarly, memory 114(2) can be divided into four subsets, each subset having its memory coupled to a single C / A B1-B4 bus to receive second sub-channel C / A information. One or more of memory 114(1) can receive write data from the memory controller or provide read data to the memory controller via the corresponding data bus in response to first sub-channel C / A information, and perform other operations. Similarly, one or more of memory 114(2) can receive write data from the memory controller or provide read data to the memory controller via the corresponding data bus in response to second sub-channel C / A information, and perform other operations.

[0027] It should be understood that, without departing from the scope of this disclosure, the memory subsystem 104 can be scaled to include more than two memory packages, more than two RCD circuits, and / or more than two sets of memory, for example, to support additional subchannels. It should also be understood that each of the register clock driver circuits 112(1) and 112(2) can be configured with additional driver circuitry to support more than four independent C / A buses. In some instances, without departing from the scope of this disclosure, the control plane hub 116 can be included in one of the memory packages 110(1) and 110(2). Furthermore, instead of a single control plane hub 116 on the memory subsystem 104, each of the memory packages 110(1) and 110(2) can include a corresponding control plane hub, which is simultaneously programmed with common data from the SCL / SDA bus without departing from the scope of this disclosure. The ability to support more than one RCD circuit on memory subsystem 104 can increase the number of output drivers, which can correspondingly support an increase in the number of memories on memory subsystem 104 compared to a single RCD device memory subsystem implementation.

[0028] Figure 2 This is a block diagram of a memory system 200 according to one embodiment of the present disclosure, including a memory subsystem 204 coupled to a memory controller 202. The memory subsystem 204 may be coupled to a C / AA bus, a C / AB bus, and a clock signal CLK driven by the memory controller 202. The memory controller 202 may include a host, a central processing unit, one or more other processor units or controllers, a DRAM controller, etc. The memory subsystem 204 may include a printed circuit board 205 with traces to support the signal lines of the C / AA bus, C / AB bus, and CLK signal, and may include infrastructure to support the mounting of memory packages 210(1), 210(2), and / or a control plane hub 216. In some instances, the printed circuit board 205 may include a memory module printed circuit board, such as a DIMM printed circuit board. In other instances, the printed circuit board 205 includes a motherboard printed circuit board or any other type of printed circuit board. In some instances, memory subsystem 204 may include memory modules, such as DIMMs (e.g., register DIMMs, LRDIMMs, micro DIMMs, NVDIMMs, or any other type of DIMM). In some instances, memory subsystem 204 may include soldered memory subsystems that are different from memory modules and / or DIMMs. In some instances, Figure 1 The memory subsystem 104 can implement the memory subsystem 204.

[0029] Control plane hub 216 is configured to receive and store configuration data from memory controller 202 via SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to components of memory subsystem 204 and / or one or both of memory packages 210(1) and 210(2). In some instances, the SCL / SDA bus may include an SM bus or an I bus. 2 C-bus. Configuration data may include configuration data relating to the operation of memory subsystem 204 and memory packages 210(1) and 210(2), such as timing parameters, addressing parameters, power levels, receiver and transmitter component coefficients, etc., or any combination thereof. Control plane hub 216 may provide configuration data to memory packages 210(1) and 210(2) during operation. Control plane hub 216 may include chips, devices, circuitry, etc. In some instances, control plane hub 216 may include electrically erasable programmable read-only memory (EEPROM), which is configured in some instances to store configuration data.

[0030] Memory package 210(1) may include register clock driver circuitry 212(1) coupled to memory 214(1), and memory package 210(2) may include register clock driver circuitry 212(2) coupled to memory 214(2). Register clock driver circuitry 212(1) and register clock driver circuitry 212(2) may be configured to receive configuration data from control plane hub 216 to set one or more configurable parameters for operation. The one or more configurable parameters may include timing parameters, power levels, addressing parameters, receiver and transmitter component coefficients (e.g., DFE or FFE coefficients), or any combination thereof.

[0031] The register clock driver circuit 212(1) can also be configured to receive first sub-channel C / A information from the C / AA bus and the CLK signal, and the register clock driver circuit 212(2) can also be configured to receive second sub-channel C / A information from the C / AB bus and the CLK signal. The first and second sub-channel C / A information can correspond to the C / A information of a single channel. The first and second sub-channel C / A information can contain memory access commands and addresses, chip select signals, etc., corresponding to the first and second sub-channels, respectively. The first and / or second sub-channel C / A information can also contain information for configuring the components of the memory subsystem 204 and / or memory package 210(1) and / or memory package 210(2). Register clock driver circuit 212(1) can provide first sub-channel C / A information to each of the C / A A1-A4 buses in parallel (e.g., simultaneously) in response to the CLK signal, and register clock driver circuit 212(2) can provide second sub-channel C / A information to each of the C / A B1-B4 buses in parallel in response to the CLK signal.

[0032] The register clock driver circuit 212(1) may include a first driver circuit 240(1) and a second driver circuit 242(1), each configured to receive first sub-channel C / A information in parallel (e.g., simultaneously) from the C / AA bus via 232(1); and a clock driver circuit 244(1) configured to receive a CLK signal. In response to the CLK signal driven from the clock driver circuit 244(1), the first driver circuit 240(1) may be configured to drive the first sub-channel C / A information to the C / AA1-A2 bus, and the second driver circuit 242(1) may be configured to drive the first sub-channel C / A information to the C / AA3-A4 bus.

[0033] In some instances, the first subchannel C / A information may also include information for configuring components of memory package 210(1). For example, the first subchannel C / A information may include second configuration data for setting one or more configurable parameters of register clock driver circuit 212(1).

[0034] Similarly, the register clock driver circuit 212(2) may include a first driver circuit 240(2) and a second driver circuit 242(2), each configured to receive second sub-channel C / A information in parallel (e.g., simultaneously) from the C / AB bus via 232(2); and a clock driver circuit 244(2) configured to receive a CLK signal. In response to a CLK signal driven from the clock driver circuit 244(1), the first driver circuit 240(1) may be configured to drive the second sub-channel C / A information to the C / A B1-B2 bus, and the second driver circuit 242(1) may be configured to drive the second sub-channel C / A information to the C / A B3-B4 bus.

[0035] Each memory in memory 214(1) may be coupled to a corresponding one of the C / A A1-A4 buses to receive first sub-channel C / A information, and each memory in memory 214(2) may be coupled to a corresponding one of the C / A B1-B4 buses to receive second sub-channel C / A information. Each memory in memory 214(1) may also be coupled to a corresponding data bus to receive write data from the memory controller and provide read data to the memory controller in response to the first sub-channel C / A information. Additionally, each memory in memory 214(2) may be coupled to a corresponding data bus to receive write data from the memory controller and provide read data to the memory controller in response to the second sub-channel C / A information. Memory 214(1) and / or memory 214(2) may each comprise one or more memory devices, packages, and / or memory dies. In some instances, the one or more memory devices or packages may each comprise one or more memory die stacks. In some instances, memory 214(1) and / or memory 214(2) may each contain dynamic random access memory (DRAM) (e.g., double data rate (DDR) 4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.).

[0036] In operation, for a given communication channel, the C / AA and C / AB drivers of the memory controller 202 can simultaneously provide the corresponding first and second sub-channel C / A information via the C / AA bus and C / AB bus through two independent sub-channels, respectively, and the CLK driver can provide a single clock signal to synchronize the timing of the two sub-channels to the memory subsystem 204 via the clock signal line.

[0037] In some instances, memory subsystem 204 may further include control plane hub 216, configured to receive and store configuration data from memory controller 202 via an SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to components of memory subsystem 204 (e.g., thermal sensors, power management integrated circuits, etc.) and / or one or both of memory packages 210(1) and 210(2). The configuration data may include configuration data relating to the operation of memory subsystem 204 and the operation of memory packages 210(1) and 210(2), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. Control plane hub 216 may provide configuration data to memory packages 210(1) and 210(2) during operation and / or initialization.

[0038] Specifically, the control plane hub 216 can be configured to simultaneously provide at least some of the configuration data to the register clock driver circuits 212(1) and 212(2). The configuration data can be used to configure one or more parameters of the register clock driver circuits 212(1) and 212(2), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. In some instances, the configuration data can be the same configuration data from the control plane hub 216. However, physical differences in the arrangement of each of the register clock driver circuits 212(1) and 212(2) relative to the corresponding C / AA or B bus and the corresponding memory 214(1) or 214(2), as well as process differences within each of the register clock driver circuits 212(1) and 212(2) or the connected memories 214(1) and 214(2), may result in different configurations between the register clock driver circuits 212(1) and 212(2). Therefore, in order to adapt to different configurations, the register clock driver circuit 212(1) can be configured to receive second configuration data via the first sub-channel C / A information, and can update one or more parameters of the register clock driver circuit 212(1) based on the second configuration data.

[0039] The memory package 210(1) is configured to receive and respond to first subchannel C / A information to receive and store write data at memory 214(1) and provide read data from the memory to the memory controller via a corresponding data bus, and the memory package 210(2) is configured to receive and respond to second subchannel C / A information to receive and store write data at memory 214(2) and provide read data from the memory to the memory controller via a corresponding data bus.

[0040] Register clock driver circuits 212(1) and 212(2) can each be configured to drive first and second sub-channel C / A information received from the C / AA bus and C / AB bus, respectively, to the C / A A1-A4 bus and C / A B1-B4 bus in response to a CLK signal. The CLK signal can be separated (e.g., via a clock tee) so that it is simultaneously routed to and received by register clock driver circuits 212(1) and 212(2). The clock tee can be arranged (e.g., impedance matching, trace length and shape, etc.) to reduce the possibility of timing differences between register clock driver circuits 212(1) and 212(2).

[0041] The first driver circuit 240(1) and the second driver circuit 242(1) of the register clock driver circuit 212(1) can each receive first sub-channel C / A information in parallel (e.g., simultaneously) from the C / AA bus, and the clock driver circuit 244(1) can receive a CLK signal. The C / AA bus can be split via a tee 230(1) to provide the first sub-channel C / A information to each of the first driver circuit 240(1) and the second driver circuit 242(1). In response to the CLK signal driven from the clock driver circuit 244(1), the first driver circuit 240(1) can drive the first sub-channel C / A information to the C / AA1-A2 bus, and the second driver circuit 242(1) can drive the first sub-channel C / A information to the C / AA3-A4 bus.

[0042] The first driver circuit 240(2) and the second driver circuit 242(2) of the register clock driver circuit 212(2) can receive second sub-channel C / A information in parallel (e.g., simultaneously) from the C / AB bus, and the clock driver circuit 244(2) can receive the CLK signal. The C / AB bus can be split via a tee 230(2) to provide first sub-channel C / A information to each of the first driver circuit 240(2) and the second driver circuit 242(2). In response to the CLK signal driven from the clock driver circuit 244(1), the first driver circuit 240(1) can drive the second sub-channel C / A information to the C / A B1-B2 bus, and the second driver circuit 242(1) can drive the second sub-channel C / A information to the C / A B3-B4 bus. The second driver circuit 242(1), the clock driver circuit 244(1), the second driver circuit 242(2), and the clock driver circuit 244(2) can all operate in a timing-synchronized manner based on a common CLK signal.

[0043] Memory 214(1) can be divided into four subsets, each subset having its memory coupled to a single C / A A1-A4 bus to receive first sub-channel C / A information. Similarly, memory 214(2) can be divided into four subsets, each subset having its memory coupled to a single C / A B1-B4 bus to receive second sub-channel C / A information. One or more of memory 214(1) can receive write data from the memory controller or provide read data to the memory controller via the corresponding data bus in response to first sub-channel C / A information, and perform other operations. Similarly, one or more of memory 214(2) can receive write data from the memory controller or provide read data to the memory controller via the corresponding data bus in response to second sub-channel C / A information, and perform other operations.

[0044] It should be understood that, without departing from the scope of this disclosure, the memory subsystem 204 can be scaled to include more than two memory packages, more than two RCD circuits, and / or more than two sets of memory, for example, to support additional subchannels. It should also be understood that each of the register clock driver circuits 212(1) and 212(2) can be configured with additional driver circuitry to support more than four independent C / A buses. In some instances, without departing from the scope of this disclosure, the control plane hub 216 may be contained within one of the memory packages 210(1) and 210(2), rather than on the printed circuit board 206. Furthermore, instead of a single control plane hub 216 on the memory subsystem 204, each of the memory packages 210(1) and 210(2) may contain a corresponding control plane hub, which is simultaneously programmed with common data from the SCL / SDA bus without departing from the scope of this disclosure. The ability to support more than one RCD circuit on memory subsystem 204 can increase the number of output drivers, which can correspondingly support an increase in the number of memories on memory subsystem 204 compared to a single RCD device memory subsystem implementation.

[0045] Figure 3A and 3B These are block diagrams of a dual-stacked memory package 310 and a single-stacked memory package 311, respectively, according to embodiments of the present disclosure. In some instances, Figure 1 The memory package 110(1) and / or the memory package 110(2) and / or Figure 2 The memory package 210(1) and / or memory package 210(2) may implement a dual-stack memory package 310 and / or a single-stack memory package 311.

[0046] Figure 3ASide view 301 and top (e.g., planar) view 302 of a dual-stacked memory package 310. Side view 301 from Figure 3A The memory package 310 is depicted at an angle from side 305 (i.e., the right side of top view 302). The dual-stacked memory package 310 may include register clock driver circuitry 312, memory 314, and control plane hub 316. Register clock driver circuitry 312 may be configured to provide a reference... Figure 1 Register clock driver circuit 112(1) or register clock driver circuit 112(2) and / or Figure 2 The operation is described in register clock driver circuit 212(1) or register clock driver circuit 212(2). The dual-stacked memory package 310 can be coupled to a C / A bus (e.g., Figure 1 (and / or one of the two C / A A1-A4 buses or one of the C / A B1-B4 buses) to receive the corresponding sub-channel C / A information; coupled to the clock signal line to receive the clock signal CLK (e.g., Figure 1 (and / or 2 CLK signals); and coupled to the corresponding data bus to receive write data and provide read data.

[0047] Memory 314 may include die stacks 342(1) and 342(2), each containing 10 memory dies 360 stacked in a shingle or cascaded arrangement (e.g., each of the memory dies 360 is horizontally offset from its adjacent memory die 360). In some instances, each of the memory dies 360 may include a DRAM architecture, such as DDR4 DRAM, DDR5 DRAM, DDR6 DRAM, etc. Each of the memory dies 360 in die stacks 342(1) and 342(2) may be coupled to other circuitry for memory access operations via corresponding wirebonding 350. It should be understood that die stacks 342(1) and 342(2) may contain more or fewer than 10 memory dies 360 without departing from the scope of this disclosure. It should also be understood that in some instances, the die stack 342(1) may contain a different number of memory dies 360 than the die stack 342(2). It should also be understood that, without departing from the scope of this disclosure, the die stack 342(1) and / or the die stack 342(2) may be arranged to use other stacking and interconnection implementations, such as 3D through-silicon via stacking.

[0048] The dual-stacked memory package 310 may further include a control plane hub 316 configured to receive and store configuration data from the memory controller via an SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to the components of the dual-stacked memory package 310. The configuration data may include configuration data related to the operation of the dual-stacked memory package 310, such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. The control plane hub 316 may provide configuration data to the register clock driver circuitry 312 and / or the memory 314 during operation and / or initialization.

[0049] Specifically, the control plane hub 316 can be configured to provide at least some of the configuration data to the register clock driver circuit 312. The configuration data can be used to configure one or more parameters of the register clock driver circuit 312, such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. Furthermore, the register clock driver circuit 312 can be configured to receive second configuration data via a first sub-channel C / A information provided on the C / A bus, and can update one or more parameters of the register clock driver circuit 312 based on the second configuration data. The control plane hub 316 can include chips, devices, circuits, etc. In some instances, the control plane hub 316 can include an electrically erasable programmable read-only memory (EEPROM), which is configured in some instances to store the configuration data.

[0050] Figure 3B Side view 303 and top (e.g., planar) view 304 of a single-stacked memory package 311. Side view 303 from Figure 3B The memory package 311 is depicted at an angle from side 306 (i.e., the right side of top view 304) of the memory package 310. The single-stacked memory package 311 may include register clock driver circuitry 312 and memory 315. Register clock driver circuitry 312 can be configured to provide a reference... Figure 1 Register clock driver circuit 112(1) or register clock driver circuit 112(2) and / or Figure 2 The operation is described in register clock driver circuit 212(1) or register clock driver circuit 212(2). The single-stack memory package 311 can be coupled to a C / A bus (e.g., Figure 1 (and / or one of the two C / A A1-A4 buses or one of the C / A B1-B4 buses) to receive the corresponding sub-channel C / A information; coupled to the clock signal line to receive the clock signal CLK (e.g., Figure 1 (and / or 2 CLK signals); and coupled to the corresponding data bus to receive write data and provide read data.

[0051] Memory 315 may include a die stack 343 comprising 20 memory dies 360 stacked in a shingled or cascaded arrangement (e.g., each of the memory dies 360 is horizontally offset from its adjacent counterpart). Each of the memory dies 360 in the die stack 343 may be coupled to other circuitry for memory access operations via corresponding wire bonds 350. It should be understood that the die stack 343 may contain more or fewer than 20 memory dies 360 without departing from the scope of this disclosure. It should also be understood that the die stack 343 may be arranged using other stacking and interconnection implementations, such as 3D through-silicon via (TSV) stacks, without departing from the scope of this disclosure.

[0052] The single-stack memory package 311 may further include a control plane hub 316 configured to receive and store configuration data from the memory controller via an SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to the components of the single-stack memory package 311. The configuration data may include configuration data related to the operation of the single-stack memory package 311, such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. The control plane hub 316 may provide configuration data to the register clock driver circuitry 312 and / or the memory 315 during operation and / or initialization.

[0053] Specifically, the control plane hub 316 can be configured to provide at least some of the configuration data to the register clock driver circuit 312. The configuration data can be used to configure one or more parameters of the register clock driver circuit 312, such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. Furthermore, the register clock driver circuit 312 can be configured to receive second configuration data via a first sub-channel C / A information provided on the C / A bus, and can update one or more parameters of the register clock driver circuit 312 based on the second configuration data. The control plane hub 316 can include chips, devices, circuits, etc. In some instances, the control plane hub 316 can include an electrically erasable programmable read-only memory (EEPROM), which is configured in some instances to store the configuration data.

[0054] Figure 4This is a block diagram of a memory system 400 according to one embodiment of the present disclosure, including a memory subsystem 404 coupled to a memory controller 402. The memory subsystem 404 may include memory modules, such as DIMMs (e.g., registered DIMMs, load-reducing DIMMs (LRDIMMs), micro DIMMs, NVDIMMs, or any other type of DIMM). In some instances, the memory subsystem 404 may include a soldered memory subsystem different from memory modules and / or DIMMs. In some instances, Figure 1 The memory subsystem 104 and / or Figure 2 The memory subsystem 204 can implement the memory subsystem 404.

[0055] The memory subsystem 404 can be configured to communicate with the memory controller 402 to receive and store configuration data via the SCL / SDA bus. In some instances, the SCL / SDA bus may include an SM bus or an I bus. 2 The configuration data may include configuration data related to the operation of the memory subsystem 404, such as timing parameters, addressing parameters, power levels, receiver and transmitter component coefficients, or any combination thereof. The memory subsystem 404 may also be configured to communicate with the memory controller 402 to perform memory access operations based on the clock signal CLK, first sub-channel C / A information from the C / A / A bus, second sub-channel C / A information from the C / A / B bus, and / or data transmitted via signal lines through the corresponding data buses. In some instances, the memory controller 402 may include an SCL / SDA driver 468 configured to drive configuration data to the SCL / SDA bus, a C / AA bus driver 462 configured to drive first sub-channel C / A information to the C / AA bus, a C / AB bus driver 464 configured to drive second sub-channel C / A information to the C / A / B bus, and a clock driver 466 configured to drive the CLK signal via a clock signal line. The memory controller 402 may further include a driver and a receiver (not shown) coupled to the respective data bus to provide write data and receive read data, respectively.

[0056] The memory subsystem 404 may include a control plane hub 416, memories 414(1)-(16), register clock driver circuitry 412(1), and register clock driver circuitry 412(2). The control plane hub 416 may be configured to receive and store configuration data from the memory controller via an SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to components of the memory subsystem 404. The control plane hub 416 may provide configuration data to the memories 414(1)-(16), register clock driver circuitry 412(1), and / or register clock driver circuitry 412(2) during operation. The control plane hub 416 may include chips, devices, circuitry, etc. In some instances, the control plane hub 416 may include an electrically erasable programmable read-only memory (EEPROM), which is configured to store configuration data.

[0057] Memory 414(1)-(8) may be coupled to register clock driver circuit 412(1), and memory 414(9)-(16) may be coupled to register clock driver circuit 412(2). Register clock driver circuit 412(1) and register clock driver circuit 412(2) may be configured to receive configuration data from control plane hub 416 to set one or more configurable parameters for operation. The one or more configurable parameters may include timing parameters, power levels, addressing parameters, receiver and transmitter component coefficients (e.g., DFE or FFE coefficients), etc., or any combination thereof.

[0058] The register clock driver circuit 412(1) can also be configured to receive first sub-channel C / A information from the C / AA bus and the CLK signal, and the register clock driver circuit 412(2) can also be configured to receive second sub-channel C / A information from the C / AB bus and the CLK signal. The first and second sub-channel C / A information can correspond to the C / A information of a single channel. The first and second sub-channel C / A information can contain memory access commands and addresses, chip select signals, etc., corresponding to the first and second sub-channels, respectively. The first and / or second sub-channel C / A information can also contain information for configuring the memory subsystem 404 and / or the components of the memory subsystem 404. The register clock driver circuit 412(1) can provide first sub-channel C / A information in parallel to each of the C / A A1-A2 buses in response to the CLK signal, and the register clock driver circuit 412(2) can provide second sub-channel C / A information in parallel to each of the C / A B1-B2 buses in response to the CLK signal. It should be understood that Figure 4The memory subsystem 404 may include a dual-sided memory subsystem, wherein the opposite side (not shown) of the memory subsystem 404 includes an additional memory arranged similarly to the memory 414(0)-(15); and without departing from the scope of this disclosure, the register clock driver circuit 412(1) and the register clock driver circuit 412(2) may provide first and second sub-channel C / A information on separate C / A A3-A4 and C / A B3-B4 buses, respectively.

[0059] In some instances, the first subchannel C / A information may also include information for configuring components of the register clock driver circuit 412(1). For example, the first subchannel C / A information may include second configuration data for setting one or more configurable parameters of the register clock driver circuit 412(1).

[0060] In some instances, memories 414(1)-(16) may all be of the same type. In other instances, memories 414(1)-(16) may be a mixture of different types of memories. In some instances, memories 414(1)-(16) may be... Figure 1 The memory 114(1) and / or the memory 114(2), Figure 1 The memory 214(1) and / or the memory 214(2), Figure 3A The memory 314 and / or one or more memory dies 360, Figure 3B Implemented in memory 315 and / or one or more memory dies 360 or any combination thereof. Although Figure 4 The memory module 404 shown has 16 memories 414(1)-(16), but in other embodiments, more or fewer memories may be used. In some instances, the memory subsystem 404 may include additional memory (not shown) for error correction code (ECC) storage. Each of the memories 414(1)-(16) may include one or more memory devices, packages, and / or memory dies. In some instances, the one or more memory devices or packages may each include one or more memory die stacks. The memories 414(1)-(16) may include DRAM architectures such as DDR4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.

[0061] Each of the memories 414(1)-(4) can be coupled to the C / A A1 bus, and each of the memories 414(5)-(8) can be coupled to the C / A A2 bus to receive first sub-channel C / A information. Each of the memories 414(9)-(12) can be coupled to the C / A B1 bus, and each of the memories 414(13)-(16) can be coupled to the C / A B2 bus to receive second sub-channel C / A information. Each of the memories 414(1)-(16) can also be coupled to a corresponding data bus to receive write data from the memory controller 202 and provide read data to the memory controller in response to first sub-channel C / A information or second sub-channel C / A information.

[0062] In some embodiments, the memories 414(1)-(16) may be organized into different physical rows and / or may be contained on one or both sides of the memory subsystem 404. In some embodiments, each physical row may contain 4, 8, 16 or more memories, and the memory subsystem 404 may contain one or more physical rows. For example, the memory subsystem 404 may contain a first physical row (e.g., 16 memories 414(1)-(16)) on a first side of the memory subsystem 404 and a second physical row (e.g., another 16 memories on the back side of the memory subsystem 404) on the rear side of the memory subsystem 404.

[0063] In operation, for a given communication channel, the C / AA bus driver 462 and the C / AB bus driver 464 of 402 can simultaneously provide the corresponding first and second sub-channel C / A information via the C / AA bus and the C / AB bus through two independent sub-channels, respectively, and the clock driver 466 can provide a single clock signal through the clock signal line to synchronize the timing of the two sub-channels to the memory subsystem 404.

[0064] In some instances, the memory subsystem 404 may further include a control plane hub 416 configured to receive and store configuration data from the memory controller 402 via an SCL / SDA bus and provide control plane communication to facilitate the provision of configuration data to components of the memory subsystem 404 (e.g., thermal sensors, power management integrated circuits, etc.) and / or the memories 414(1)-(16) and register clock driver circuits 412(1) and 412(2). The configuration data may include configuration data relating to the operation of the memory subsystem 404 (including the memories 414(1)-(16) and register clock driver circuits 412(1) and 412(2)), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. The control plane hub 416 may provide configuration data to the memories 414(1)-(16) and register clock driver circuits 412(1) and 412(2) during operation and / or initialization.

[0065] Specifically, the control plane hub 416 can be configured to simultaneously provide at least some of the configuration data to the register clock driver circuits 412(1) and 412(2). The configuration data can be used to configure one or more parameters of the register clock driver circuits 412(1) and 412(2), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. In some instances, the configuration data can be the same configuration data from the control plane hub 416. However, physical differences in the arrangement of each of the register clock driver circuits 412(1) and 412(2) relative to the corresponding C / AA or B bus and the corresponding memory 414(1)-(16), as well as process differences within each of the register clock driver circuits 412(1) and 412(2) or the connected memory 414(1)-(16), may result in different configurations between the register clock driver circuits 412(1) and 412(2). Therefore, in order to adapt to different configurations, the register clock driver circuit 412(1) can be configured to receive second configuration data via the first sub-channel C / A information, and can update one or more parameters of the register clock driver circuit 412(1) based on the second configuration data.

[0066] Register clock driver circuits 412(1) and 412(2) can each be configured to drive first and second sub-channel C / A information received from the C / AA bus and C / AB bus, respectively, to the C / A A1-A2 bus and C / A B1-B2 bus in response to a CLK signal. The CLK signal can be separated (e.g., via a clock tee) so that it is simultaneously routed to and received by register clock driver circuits 412(1) and 412(2). The clock tee can be arranged (e.g., impedance matching, trace length and shape, etc.) to reduce the possibility of timing discrepancies between register clock driver circuits 412(1) and 412(2).

[0067] Each of the memories 414(1)-(4) can receive first sub-channel C / A information via the C / A A1 bus, and each of the memories 414(5)-(8) can receive first sub-channel C / A information via the C / A A2 bus. One or more of the memories 414(1)-(8) can perform memory access operations in response to the first sub-channel C / A information to receive data from and provide data to the corresponding data bus communicating with the memory controller 402.

[0068] Each of the memories 414(9)-(12) can receive second sub-channel C / A information via the C / A B1 bus, and each of the memories 414(13)-(16) can receive second sub-channel C / A information via the C / A B2 bus. One or more of the memories 414(9)-(16) can perform memory access operations in response to the second sub-channel C / A information to receive data from and provide data to the corresponding data bus communicating with the memory controller 402.

[0069] It should be understood that, without departing from the scope of this disclosure, the memory subsystem 404 can be scaled to include more than 16 (or 32) memories, more than two register clock driver circuits, and / or more than two sets of memories, for example, to support additional subchannels. It should also be understood that each of the register clock driver circuits 412(1) and 412(2) can be configured with additional driver circuitry to support more than four independent C / A buses. The ability to support more than one register clock driver circuit on the memory subsystem 404 can increase the number of output drivers, which can correspondingly support an increase in the number of memories on the memory subsystem 404 compared to a single RCD device memory subsystem implementation.

[0070] Figure 5This is a block diagram of a semiconductor device 500 according to at least one embodiment of the present disclosure. The semiconductor device 500 may be a semiconductor memory device integrated on a single semiconductor chip, such as a DRAM device (e.g., Double Data Rate (DDR) 4 DRAM, DDR5 DRAM, DDR6 DRAM, etc.). Figure 5 The exemplary device 500 may include a memory package, such as a stack of memory dies on a substrate 523, which may be used as (and may be referred to as) an interface. Although some components are shown in the memory dies of the memory die stack and some components are shown on the substrate 523, other arrangements of the components of the device 500 between the memory die stack and the substrate 523 are possible in other exemplary embodiments. In some embodiments, the device 500 may include multiple memory die stacks. In other embodiments, the memory die stack may include a single memory die. In some instances, Figure 1 The memory package 110(1) and / or the memory package 110(2), Figure 2 The memory package 210(1) and / or the memory package 210(2), Figure 3A The dual-stacked memory package 310 and / or one or both of die stack 342(1) and die stack 342(2), Figure 3B Single-stacked memory package 311 and / or die stack 343, Figure 4 Any one or any combination of the memory register clock driver circuits 412(1)-(16) can be used to implement the semiconductor device 500.

[0071] For the sake of brevity and clarity, Figure 5 Only components of one memory die in a memory die stack are shown. Typically, different memory dies in a memory die stack may each have similar components to each other. In some embodiments, each memory die in a memory die stack may be physically identical to each other. Substrate 523 can act as an interface and can send and receive information (e.g., data, commands) to and from the outside while the memory dies in the memory die stack communicate with the components of the substrate. As described herein, commands and other signals sent by substrate 523 can be sent to all memory dies in the memory die stack or can be individually addressed to individual memory dies in the memory die stack.

[0072] Semiconductor device 500 includes a memory array 518. The memory array 518 may be located within a stack of memory dies. The memory array 518 is shown as comprising a plurality of memory cells. Figure 5In this embodiment, the memory array 518 is shown as comprising N+1 memory banks BANK0-N, where N is any integer value, such as 2, 4, 8, 16, 32, etc. Each of the memory banks BANK0-N may contain multiple word lines WL, multiple bit lines BL and / or BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / or BL. The selection of word lines WL is performed by row decoder 508, and the selection of bit lines BL and / or BL is performed by column decoder 510. Row and column decoders 508 and 510 may also be located within memory dies in a memory die stack. Figure 5 In this embodiment, row decoder 508 includes a corresponding row decoder for each memory bank, and column decoder 510 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by the sense amplifier SAMP and transmitted to the read / write amplifier 520 via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary main data line (MIOT / B). Conversely, write data output from the read / write amplifier 520 is transmitted to the sense amplifier SAMP via the complementary main data line MIOT / B, the transmission gate TG, and the complementary local data line LIOT / B, and written to the memory cell MC coupled to bit lines BL or / BL.

[0073] Semiconductor device 500 may employ multiple external terminals, including command and address (C / A) terminals coupled to the command and address bus to receive command and address signals and CS signals, clock terminals for receiving clock signals CK and CK / CK, data terminals DQ for receiving and providing data (e.g., via a multi-channel data bus), and power terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The external terminals may be located on substrate 523.

[0074] The clock terminals are supplied with external clocks CK and / CK for input circuitry 514. The external clocks can be complementary. Input circuitry 514 generates an internal clock ICLK based on CK and / CK. The ICLK clock is provided to command decoder 510 and internal clock generator 512. Internal clock generator 512 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuitry 522 to time the operation of circuits contained within input / output circuitry 522 (e.g., to a data receiver to time the reception of written data).

[0075] The C / A terminal can be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 504 via command / address input circuitry 502. Address decoder 504 receives the address and supplies the decoded row address XADD to row decoder 508 and the decoded column address YADD to column decoder 510. Address decoder 504 can also supply a decoded bank address BADD, which can indicate a bank of memory in memory array 518 containing the decoded row address XADD and column address YADD. In some embodiments, address decoder 504 can also indicate a specific memory die in a stack of memory dies for activation. The C / A terminal can be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), and other commands and operations. Access commands can be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate one or more memory cells to be accessed.

[0076] Commands can be provided to command decoder 506 as internal command signals via command / address input circuitry 502. Command decoder 506 includes circuitry for decoding internal command signals to generate various internal signals and commands for operation. For example, command decoder 506 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0077] Semiconductor device 500 can receive access commands as read commands. When a read command is received and, when appropriate, a bank address, row address, and column address (and optionally a die address) are supplied along with the read command, read data is read from a memory cell in memory array 518 corresponding to the row and column addresses. The read command is received by command decoder 506, which provides an internal command causing the read data from memory array 518 to be provided to read / write amplifier 520. The read data is output to the outside via input / output circuitry 522 from data terminal DQ.

[0078] Semiconductor device 500 can receive access commands as write commands. When a write command is received and a bank address, row address, and column address (and optionally die address) are supplied in a timely manner along with the write command, write data supplied to the data terminal DQ is written to the memory cells in the memory array 518 corresponding to the row and column addresses. The write command is received by command decoder 506, which provides an internal command causing the write data to be received by the data receiver in input / output circuitry 522. A write clock can also be provided to an external clock terminal for timing the data receiver in input / output circuitry 522 to receive the write data. The write data is supplied to read / write amplifier 520 via input / output circuitry 522 and then to memory array 518 to be written into memory cells MC.

[0079] Power supply terminals are supplied with power potentials VDD and VSS. These power potentials VDD and VSS are supplied to the internal voltage generator circuit 524. The internal voltage generator circuit 524 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is mainly used in the row decoder 508, internal potentials VOD and VARY are mainly used in the sense amplifier SAMP included in the memory array 518, and internal potential VPERI is used in many peripheral circuit blocks.

[0080] The power terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to the input / output circuit 522. In one embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be the same potentials as the power potentials VDD and VSS supplied to the power terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power terminals may be different potentials from the power potentials VDD and VSS supplied to the power terminals. The power potentials VDDQ and VSSQ supplied to the power terminals are used in the input / output circuit 522 so that power supply noise generated by the input / output circuit 522 does not propagate to other circuit blocks.

[0081] Figure 6 This is a timing diagram 600 for configuring a dual-register clock driver circuit for a memory subsystem according to an embodiment of the present disclosure. Timing diagram 600 can be implemented using a memory controller 610, a control plane hub 620, a first register clock driver circuit 630, and a second register clock driver circuit 640. The control plane hub 620, the first register clock driver circuit 630, and the second register clock driver circuit 640 can be included as a single memory subsystem (e.g., Figure 1The memory subsystem 104 Figure 2 The memory subsystem 204 Figure 4 It is part of the memory subsystem 404 or any combination thereof. The memory controller 610 may contain Figure 1 The memory controller of the memory system Figure 2 Memory controller 202, Figure 4 The memory controller 402 or any combination thereof. The control plane hub 620 may include... Figure 1 Control plane hub 116 Figure 2 Control plane hub 216 Figure 3A and / or 3B control plane hub 316, Figure 4 The control plane hub 416 or any combination thereof. The first register clock driver circuit 630 may include... Figure 1 Register clock driver 112(1), Figure 2 Register clock driver 212(1), Figure 3A and / or 3B register clock driver 312, Figure 4 The register clock driver 412(1) or any combination thereof. The second register clock driver circuit 640 may include... Figure 1 Register clock driver 112(2), Figure 2 Register clock driver 212(2), Figure 3A and / or 3B register clock driver 312, Figure 4 The register clock driver 412(2) or any combination thereof.

[0082] As shown in timing diagram 600, memory controller 610 can be configured to provide first configuration data to control plane hub 620 via the SCL / SDA bus. Control plane hub 620 can be configured to receive and store the configuration data. In some instances, the SCL / SDA bus may include an SM bus or an I bus. 2 C-bus. The configuration data may include configuration data related to the operation of the first register clock driver circuit 630 and the second register clock driver circuit 640, such as timing parameters, addressing parameters, power levels, receiver and transmitter component coefficients, or any combination thereof.

[0083] The control plane hub 620 can be configured to simultaneously provide first configuration data to the first register clock driver circuit 630 and the second register clock driver circuit 640. The configuration data can be used to configure one or more parameters of the register clock driver circuit 112(1) and the register clock driver circuit 112(2), such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof.

[0084] However, physical differences in the arrangement of each of the first register clock driver circuit 630 and the second register clock driver circuit 640 relative to the corresponding C / AA or B bus and the corresponding memory (not shown), as well as process differences within each of the first register clock driver circuit 630 and the second register clock driver circuit 640 or the connected memory, may result in different configurations between the first register clock driver circuit 630 and the second register clock driver circuit 640. Therefore, to accommodate different configurations, the first register clock driver circuit 630 can be configured to receive second configuration data from the first sub-channel C / A information via the C / AA bus from the memory controller 610, and can update one or more parameters of the first register clock driver circuit 630 based on the second configuration data.

[0085] Figure 7 This is a flowchart of a method 700 for configuring a dual-register clock driver for a memory subsystem according to an embodiment of the present disclosure. Method 700 can be at least partially derived from... Figure 1 The memory subsystem 104 Figure 2 The memory subsystem 204 Figure 3A Dual-stacked memory package 310 Figure 3B 311 single-stack memory package Figure 4 The memory subsystem 404 or any combination thereof is used.

[0086] Method 700 may include receiving first configuration data from the memory controller via a first bus at 710 at a control plane hub of the memory subsystem. The control plane hub may include... Figure 1 Control plane hub 116 Figure 2 Control plane hub 216 Figure 3A and 3B Control plane hub 316 Figure 4 Control plane hub 416 Figure 6 The control plane hub 620 or any combination thereof. The memory controller may include... Figure 1 memory controller, Figure 2 Memory controller 202, Figure 4 Memory controller 402, Figure 6 The memory controller 610 or any combination thereof. Configuration data can be used to configure one or more parameters of the memory subsystem, such as timing parameters, addressing parameters, receiver and transmitter component coefficients, operating modes, etc., or any combination thereof. The first bus may contain... Figure 1-4 Any of the SCL / SDA.

[0087] Method 700 may include providing first configuration data to a first register clock driver and a second register clock driver of the memory subsystem in step 720. The first register clock driver and the second register clock driver may each set a corresponding configuration parameter to a first value based on the first configuration data. The first and / or second register clock driver may include... Figure 1 Register clock driver circuit 112(1) and / or register clock driver circuit 112(2), Figure 2 Register clock driver circuit 212(1) and / or register clock driver circuit 212(2), Figure 3A and 3B Register clock driver circuit 312 Figure 4 Register clock driver circuit 412(1) and / or register clock driver circuit 412(2), Figure 6 The method comprises a first register clock driver circuit 630 and / or a second register clock driver circuit 640, or any combination thereof. Each of the first and second register clock drivers has a corresponding configuration parameter that includes at least one of timing parameters, addressing parameters, receiver or transmitter component coefficients, or operating modes. In some instances, method 700 may include setting a corresponding configuration parameter to a first value by the first register clock driver in response to first configuration data. In some instances, method 700 may further include setting a corresponding configuration parameter to a first value by the second register clock driver in response to first configuration data.

[0088] Method 700 may include receiving second configuration data from the memory controller via a second bus at 730 at a first register clock driver. The first register clock driver sets a corresponding configuration parameter to a second value based on the second configuration data. In some instances, method 700 may include setting a corresponding configuration parameter to a second value by the first register clock driver in response to the second configuration data.

[0089] In some instances, method 700 may include decoding, via a first register clock driver, first sub-channel command and address information received from the memory controller via a first command and address bus based on corresponding configuration parameters having a second value, and providing the decoded first sub-channel command and address information to a first set of memories. In some instances, method 700 may further include decoding, via a second register clock driver, second sub-channel command and address information received from the memory controller via a second command and address bus based on corresponding configuration parameters having a first value, and providing the decoded second sub-channel command and address information to a second set of memories.

[0090] The second and third buses can include Figure 1C / AA and / or C / AB buses, Figure 2 C / AA and / or C / AB buses, Figure 3A and 3B C / A bus Figure 4 The C / AA and / or C / AB bus signals or any combination thereof. The first set of memory and / or the second set of memory may contain... Figure 1 The memory 114(1) and / or the memory 114(2), Figure 1 The memory 114(1) and / or the memory 114(2), Figure 3A Memory 314, Figure 3B Memory 315, Figure 4 The memory 414(1)-(16) or any combination thereof. In some instances, first subchannel command and address information may be provided to the first set of memories via a first plurality of internal command and address buses, and second subchannel command and address information may be provided to the second set of memories via a second plurality of internal command and address buses. The first plurality of internal command and address buses may include Figure 1 C / A A1-A4 bus, Figure 2 C / A A1-A4 bus, Figure 3A and 3B C / A bus Figure 4 The C / A ports A1-A2 (and A3-A4, not shown) or any combination thereof. A second plurality of internal command and address buses may include... Figure 1 C / AB1-B4 bus, Figure 2 C / AB1-B4 bus, Figure 3A and 3B C / A bus Figure 4 C / AB1-B2 (and B3-B4, not shown) or any combination thereof. The first and second sets of memory contain DRAM (e.g., DDR4, DDR5, DDR6, etc.). In some instances, the provision of first subchannel command and address information to a first plurality of internal command and address buses is simultaneous with the provision of subchannel command and address information to a second plurality of internal command and address buses.

[0091] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be carried out separately and / or in separate devices or device portions according to the system, apparatus, and method.

[0092] The foregoing description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the present system and method, reference is made to the accompanying drawings, which form part of the description, and the drawings illustrate specific embodiments in which the described system and method can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments can be utilized, and structural and logical changes can be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, certain features that are obvious to those skilled in the art will not be discussed in detail so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of this disclosure is defined only by the appended claims.

[0093] Finally, the above discussion is intended to illustrate the system only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system has been described in particular detail with reference to exemplary embodiments, it should be understood that those skilled in the art can devise many modifications and alternative embodiments without departing from the broader and contemporaneous spirit and scope of the system set forth in the following claims. Thus, the specification and drawings are to be considered illustrative and not intended to limit the scope of the appended claims.

Claims

1. A memory device comprising: A first register clock driver is configured to receive first configuration data from a memory controller via a first command and address bus, in first sub-channel command and address information corresponding to a channel, wherein the first register clock driver is further configured to receive second configuration data, wherein the first register clock driver is configured to update parameters set by the second configuration data using updates provided via the first configuration data; A second register clock driver is configured to receive second sub-channel command and address information corresponding to the channel from the memory controller via a second command and address bus, wherein the second register clock driver is further configured to receive the second configuration data; and A control plane hub is configured to receive the second configuration data from the memory controller via a serial data bus and provide the second configuration data to the first register clock driver and the second register clock driver.

2. The memory device of claim 1, wherein the control plane hub is configured to simultaneously provide the second configuration data to the first register clock driver and the second register clock driver.

3. The memory device of claim 1, wherein the first configuration data and the second configuration data each comprise at least one of timing parameters, addressing parameters, receiver or transmitter component coefficients or operating modes, or any combination thereof.

4. The memory device of claim 1, wherein the first configuration parameter of the first register clock driver and the first configuration parameter of the second register clock driver each include at least one of timing parameters, addressing parameters, receiver or transmitter component coefficients, or operating modes.

5. The memory device of claim 4, wherein the first configuration parameter of the first register clock driver and the first configuration parameter of the second register clock driver are parameters of the same type.

6. The memory device of claim 4, wherein the first register clock driver is configured to receive or transmit the first command and address information based on the first configuration parameters of the first register clock driver having a second value, and the second register clock driver is configured to receive or transmit the second command and address information based on the first configuration parameters of the second register clock driver having a first value.

7. The memory device of claim 1, wherein the first register clock driver is a first semiconductor device and the second register clock driver is a second semiconductor device.

8. The memory device of claim 1, wherein the operation of the first register clock driver is synchronized with the operation of the second register clock driver.

9. The memory device of claim 1, wherein the first register clock driver is configured to provide the first subchannel command and address information to the first set of memories via a first internal command and address bus, and the second register clock driver is configured to provide the second subchannel command and address information to the second set of memories via a second internal command and address bus.

10. The memory device of claim 1, wherein the first register clock driver is configured to set a first configuration parameter to a first value based on the second configuration data, wherein the first register clock driver is further configured to receive the first configuration data of the first sub-channel command and address information via the first command and address bus; and set the first configuration parameter to a second value based on the first configuration data, and wherein the second register clock driver is configured to set the first configuration parameter to the first value based on the second configuration data.

11. A memory subsystem comprising: A first memory package includes a first register clock driver, which is configured to receive first subchannel commands and address information corresponding to a channel via the first bus based on a configuration defined by first configuration data or second configuration data received via the first bus. A second memory package includes a second register clock driver configured to receive second sub-channel commands and address information corresponding to the channel via a second bus based on a configuration defined by the second configuration data. and A control plane hub is configured to receive the second configuration data from the memory controller via a third bus and provide the second configuration data to the first register clock driver and the second register clock driver.

12. The memory subsystem of claim 11, wherein the first memory package includes a first set of memory configured to perform memory access operations via one of a first plurality of internal commands and address buses in response to a first subchannel command and address information from the first register clock driver, wherein the second memory package includes a second set of memory configured to perform memory access operations via one of a second plurality of internal commands and address buses in response to a second subchannel command and address information from the second register clock driver.

13. The memory subsystem of claim 11, wherein the first register clock driver is contained in a first semiconductor device, and the second register clock driver is contained in a second semiconductor device.

14. The memory subsystem of claim 11, wherein the first bus is a first command and address bus, the second bus is a second command and address bus, and the third bus is a serial data bus.

15. The memory subsystem of claim 11, wherein the first register clock driver is configured to decode the first subchannel command and address information based on configuration parameters of the first register clock driver having a second value, and the second register clock driver is configured to decode the second subchannel command and address information based on configuration parameters of the second register clock driver having a first value.

16. The memory subsystem of claim 11, wherein the first register clock driver is configured to set a configuration parameter to a first value based on the second configuration data and to set the configuration parameter to a second value based on the first configuration data received via the first bus in the first subchannel command and address information, and wherein the second register clock driver is configured to set the configuration parameter to the first value based on the second configuration data.

17. A method for a memory subsystem, the method comprising: At the control plane hub of the memory subsystem, first configuration data is received from the memory controller via a serial data bus; The first configuration data is provided to the first register clock driver and the second register clock driver of the memory subsystem, wherein the first register clock driver and the second register clock driver each set the corresponding configuration parameter to a first value based on the first configuration data; and At the first register clock driver, second configuration data is received from the memory controller via the command and address bus, wherein the first register clock driver sets the corresponding configuration parameter to a second value based on the second configuration data.

18. The method of claim 17, further comprising: The first register clock driver sets the corresponding configuration parameter to the first value in response to the first configuration data; and The first register clock driver sets the corresponding configuration parameter to the second value in response to the second configuration data.

19. The method of claim 18, further comprising the second register clock driver setting the corresponding configuration parameter to the first value in response to the first configuration data.

20. The method of claim 17, wherein the respective configuration parameters of each of the first register clock driver and the second register clock driver include at least one of timing parameters, addressing parameters, receiver or transmitter component coefficients, or operating modes.

21. The method of claim 17, further comprising: The first sub-channel command and address information received from the memory controller via the command and address bus is decoded by the first register clock driver based on the corresponding configuration parameters having the second value. The decoded first sub-channel command and address information are provided to the first set of memory; and The second sub-channel command and address information of the channel received from the memory controller via the second command and address bus is decoded by the second register clock driver based on the corresponding configuration parameters having the first value. and The decoded second sub-channel command and address information are provided to the second set of memory.

22. The method of claim 21, wherein the first and second sets of memories comprise dynamic random access memory.

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