Controller, storage device including the controller, and reading method of the storage device

Abstract

A controller includes a control pin for providing a control signal to a nonvolatile memory, a buffer memory configured to store first to third tables, and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is not correctable, an on-chip valley search operation is performed from the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and second offset information corresponding to the detection information is generated.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0081240, filed on July 2, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a controller, a storage device including the controller, and a method for reading from the storage device. Background Technology

[0004] Error-correcting code (ECC) memory is a type of computer data storage that can detect and correct n-bit data corruption in memory. Typically, storage devices use ECC circuitry to generate ECC codes during write operations and correct errors in the ECC data during read operations. However, there may be situations where the storage cells of the device have deteriorated so severely that correction by the ECC circuitry is impossible. In such cases, a read retry operation can be performed using a different read method than the normal read operation. Summary of the Invention

[0005] According to an exemplary embodiment of the inventive concept, a controller is provided, comprising: a control pin for providing control signals to a non-volatile memory device; a buffer memory configured to store a first table, a second table, and a third table; and an error correction code (ECC) circuit configured to correct errors in first data read from the non-volatile memory device according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a historical read level and is determined by the first offset information and the second offset information, and when an error in the first data cannot be corrected by the error correction circuit, the non-volatile memory device performs an on-chip valley search operation according to the second read command, receives detection information of the on-chip valley search operation according to a specific command, and generates second offset information corresponding to the detection information.

[0006] According to an exemplary embodiment of the present invention, a storage device is provided, comprising: a non-volatile memory device; and a controller connected to a control pin, which exchanges a command latch enable (CLE) signal, an address latch enable (ALE) signal, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and a DQS control signal with the non-volatile memory device via the control pin, wherein the controller is configured to read data from the non-volatile memory device, wherein the non-volatile memory device performs a read operation by latching a command or address on the edge of the WE signal according to the CLE signal and the ALE signal, and the non-volatile memory device performs a normal read operation in response to a first read command received from the controller, performs an on-chip valley search operation in response to a second read command received from the controller, and outputs detection information of the on-chip valley search operation to the controller in response to a specific command received from the controller.

[0007] According to an exemplary embodiment of the present invention, a storage device is provided, comprising: a non-volatile memory device; and a controller configured to control the non-volatile memory device, wherein the controller receives detection status information based on on-chip valley search (OVS) operation from the non-volatile memory device, offset information corresponding to the detection status information using an OVS table, and uses the offset information to determine a default read level.

[0008] According to an exemplary embodiment of the present invention, a method for reading a non-volatile memory device is provided, the method comprising: performing a normal read operation according to a default read level in response to a first read command; performing an on-chip valley search operation in response to a second read command; and outputting detection information of the on-chip valley search operation in response to a specific command.

[0009] According to an exemplary embodiment of the present invention, a method for reading a storage device is provided, the method comprising: issuing a read command to a non-volatile memory device by a controller; issuing a read retry command to the non-volatile memory device by the controller when an error in the data based on the read command is uncorrectable; issuing a specific command to the non-volatile memory device by the controller after receiving data from the non-volatile memory device based on the read retry command; receiving information associated with the read retry command corresponding to the specific command by the controller; and changing a default read level by the controller using the received information.

[0010] According to an exemplary embodiment of the present invention, a non-volatile memory device is provided, comprising: a memory cell region including a first metal pad; a peripheral circuit region including a second metal pad and vertically connected to the memory cell region via the first and second metal pads; a memory cell array disposed in the memory cell region, wherein the memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of memory cells that are programmable, erasable, or readable by voltages supplied via bit lines and word lines; an address decoder disposed in the peripheral circuit region and configured to select a word line in response to an address; and a page buffer disposed in the peripheral circuit region. It is configured to read data from a memory cell connected to a selected word line during a read operation; an input / output buffer, located in the peripheral circuit area and configured to pass the read data to an external device during a read operation; and control logic, located in the peripheral circuit area and configured to control the page buffer, address buffer, and input / output buffer during a read operation, wherein the control logic performs a normal read operation in response to a first read command received from the controller, performs an on-chip valley search operation in response to a second read command received from the controller, and outputs detection information of the on-chip valley search operation to the controller in response to a specific command received from the controller.

[0011] According to an exemplary embodiment of the present invention, a storage device is provided, comprising: a non-volatile memory device; and a controller configured to: issue a read command to the non-volatile memory device; issue a read retry command to the non-volatile memory device when an error in the data based on the read command is uncorrectable; issue a specific command to the non-volatile memory device after receiving data from the non-volatile memory device based on the read retry command; receive information associated with the read retry command corresponding to the specific command; and use the received information to change a default read level.

[0012] Brief description of the attached figures

[0013] The above and other features of the inventive concept will become clearer through the following detailed description of the accompanying drawings. Figure 1 The illustration shows a storage device according to an exemplary embodiment of the inventive concept.

[0014] Figure 2 The diagram shows Figure 1 The illustration shows an example of a non-volatile memory device.

[0015] Figure 3 yes Figure 1 The diagram shows the circuit diagram of one of the memory blocks in the memory block diagram.

[0016] Figure 4This is a flowchart illustrating a read operation performed using On-Chip Valley Search (OVS) on a general-purpose storage device.

[0017] Figure 5 This is a diagram illustrating the extraction of the optimal read level of a storage device according to an exemplary embodiment of the inventive concept.

[0018] Figure 6A and Figure 6B This is a graph showing the different reading voltages of the distribution valleys and their corresponding development times.

[0019] Figure 7 This is a diagram illustrating read level offset compensation using an OVS table (OVST) according to an exemplary embodiment of the inventive concept.

[0020] Figure 8A and Figure 8B An exemplary embodiment of the OVST according to the inventive concept is illustrated.

[0021] Figure 9A , Figure 9B ,and Figure 9C The illustration shows an example of using OVST, an exemplary embodiment of the inventive concept, to search for the optimal valley when the predefined table (PDT) offset is insufficient.

[0022] Figure 10A , Figure 10B ,and Figure 10C The illustration shows an example of using OVST, an exemplary embodiment of the inventive concept, to search for the optimal valley when the PDT offset is too large.

[0023] Figure 11A An example of the distribution of OVS modes for applying a read operation according to an exemplary embodiment of the inventive concept is illustrated.

[0024] Figure 11B An example of the distribution of OVS modes for applying a read operation according to another exemplary embodiment of the inventive concept is illustrated.

[0025] Figure 11C An example of the distribution of OVS modes for applying a read operation according to another exemplary embodiment of the inventive concept is illustrated.

[0026] Figure 12 This is a flowchart illustrating a reading method of a storage device according to an exemplary embodiment of the inventive concept.

[0027] Figure 13 This is a flowchart illustrating a reading method of a storage device according to another exemplary embodiment of the inventive concept.

[0028] Figure 14This is a step diagram illustrating the process of retrieving read level offset from a storage device according to an exemplary embodiment of the inventive concept.

[0029] Figure 15 This is a ladder diagram illustrating a read operation using a read level offset extracted from a storage device, according to an exemplary embodiment of the inventive concept.

[0030] Figure 16 This is a step diagram illustrating the read operation of a storage device according to another exemplary embodiment of the inventive concept.

[0031] Figure 17 This is a step diagram illustrating the read operation of another storage device according to another exemplary embodiment of the inventive concept.

[0032] Figure 18A and Figure 18B An example of OVS detection of a non-volatile memory device according to an exemplary embodiment of the inventive concept is illustrated.

[0033] Figure 19 The illustration shows an example of OVS detection information and a method for outputting OVS detection information according to an exemplary embodiment of the inventive concept.

[0034] Figure 20 The illustration shows an example of outputting OVS detection information as a specific command.

[0035] Figure 21 The illustration shows a storage device according to another exemplary embodiment of the inventive concept.

[0036] Figure 22 The illustration shows a storage device according to another exemplary embodiment of the inventive concept.

[0037] Figure 23 The illustration shows a storage device according to another exemplary embodiment of the inventive concept.

[0038] Figure 24 The illustration shows table management of a storage device according to an exemplary embodiment of the inventive concept.

[0039] Figure 25 The illustration shows a non-volatile memory device implemented in a chip-to-chip (C2C) structure according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0040] In the following description, exemplary embodiments of the inventive concept will be illustrated with reference to the accompanying drawings. In the drawings, similar reference numerals may refer to similar elements.

[0041] The controller, the storage device including the controller, and the reading method of the storage device according to exemplary embodiments of the inventive concept can reflect on-chip valley search (OVS) detection information as the optimal read level to perform a read operation, thereby preventing performance degradation while ensuring reliability. Figure 1 The illustration shows a storage device 10 according to an exemplary embodiment of the inventive concept. (Reference) Figure 1 The storage device 10 may include at least one non-volatile memory device (NVM (or more)) 100 and a controller (CNTL) 200.

[0042] At least one non-volatile memory device 100 can store data. The non-volatile memory device 100 can be a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change RAM (PRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FRAM), a spin-torque-shifting RAM (STT-RAM), etc. The non-volatile memory device 100 can be implemented in a three-dimensional array structure. This inventive concept can be applied not only to flash memory devices in which the charge storage layer includes a conductive floating gate, but also to charge-trapped flash memory (CTF) in which the charge storage layer includes an insulating layer. Hereinafter, for ease of description, the non-volatile memory device 100 will be referred to as a vertical NAND flash memory device (“VNAND”).

[0043] The non-volatile memory device 100 may include a plurality of memory blocks BLK1 to BLKz (where z is an integer greater than or equal to 2) and control logic 150.

[0044] Each of the multiple storage blocks BLK1 to BLKz may include multiple pages: page 1 to page m (where m is an integer greater than or equal to 2). Each of the multiple pages page 1 to page m may include multiple storage units. Each of the multiple storage units may store at least one bit.

[0045] Control logic 150 can receive commands CMD and addresses ADD from controller (CNTL) 200, and can perform operations corresponding to the received commands CMD (such as programming operations, read operations, erase operations, etc.) on the memory cell corresponding to the received address ADD.

[0046] Control logic 150 may include OVS circuitry 155. OVS circuitry 155 may perform on-chip valley search (OVS) operations. The on-chip valley search operation may include a first readout operation for determining an OVS detection status based on cell counts, and a second readout operation for modifying and reading out the actual evolution time based on the determined OVS detection status. Details of on-chip valley search operations are disclosed in U.S. Patent Application Publications Nos. 2020-0286545 and 2020-0098436 and U.S. Patents Nos. 10,090,046, 10,559,362, 10,607,708, and 10,629,259, the disclosures of which are incorporated herein by reference in their entirety.

[0047] OVS circuit 155 can store OVS detection information OVSDI corresponding to the results of the on-chip valley search operation. Such OVS detection information OVSDI may include information indicating the optimal distribution valley corresponding to the state (e.g., development time information).

[0048] The controller (CNTL) 200 can be connected to at least one non-volatile memory device 100 via multiple control pins that send control signals (e.g., command latch enable (CLE), address latch enable (ALE), chip enable (CE(multiple)), write enable (WE), read enable (RE), etc.). Furthermore, the controller (CNTL) 200 can control the non-volatile memory device 100 using control signals (e.g., CLE, ALE, CE(or multiple), WE, RE, etc.). For example, the non-volatile memory device 100 can perform programming / reading / erasing operations by latching the command CMD or address ADD on the edge of the write enable signal WE according to the command latch enable signal CLE and the address latch enable signal ALE.

[0049] The controller (CNTL) 200 may include a buffer memory 220 and an error correction code (ECC) circuit 230.

[0050] The buffer memory 220 can be implemented as volatile memory (e.g., static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc.) or non-volatile memory (e.g., flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc.). The buffer memory 220 may include multiple tables, such as at least one predefined table (PDT), an OVS table (OVST), and a history read level table (HRT).

[0051] The first table PDT may include first read level offset information. In an exemplary embodiment of the inventive concept, the first table PDT may include first read level offset information corresponding to the programming elapsed time. In an exemplary embodiment of the inventive concept, the first table PDT may include first read level offset information corresponding to various degradation information other than the programming elapsed time (e.g., temperature, programming / erase cycle, read cycle, open word line status, etc.).

[0052] The second table OVST may include second read level offset information corresponding to the OVS detection information OVSDI. In this case, the OVS detection information OVSDI may be development time information corresponding to the optimal distribution valley. For example, the second read level offset information may include read level offset information corresponding to the development time information in which the OVS operation is performed. Therefore, the second table OVST can be a table used to convert the OVS detection information OVSDI into read level offset information.

[0053] The third table HRT may include third read level offset information associated with a historical read operation. In an exemplary embodiment of the inventive concept, the third read level offset information may be determined using first read level offset information and second read level offset information. The third read level offset information may include information about the optimal read level at which the historical read operation was performed. Details of historical read operations are disclosed in U.S. Patent Nos. 10,120,589 and 10,373,693, the disclosures of which are incorporated herein by reference in their entirety.

[0054] ECC circuit 230 can generate error correction codes during programming operations and can use these codes to recover DATA during read operations. For example, ECC circuit 230 can generate error correction codes (ECC) to correct failure bits or error bits in DATA received from non-volatile memory device 100. ECC circuit 230 can perform error correction encoding on data provided to non-volatile memory device 100 to generate DATA with parity bits added. These parity bits can be stored in non-volatile memory device 100. Furthermore, ECC circuit 230 can perform error correction decoding on DATA output from non-volatile memory device 100. ECC circuit 230 can use parity to correct errors. The ECC circuit 230 can use low-density parity-check (LDPC) codes, Bosch-Joher-Hokvenheim (BCH) codes, turbo codes, Little-Solomon codes, convolutional codes, recursive systematic codes (RSC), or coding modulation such as lattice-coded modulation (TCM) and block-coded modulation (BCM) to correct errors.

[0055] When the error correction circuit 230 fails to perform error correction, a read retry operation can be performed. In an exemplary embodiment of the inventive concept, the read retry operation may include an OVS operation. In another exemplary embodiment of the inventive concept, the read retry operation may include an OVS operation reflecting the first table PDT.

[0056] According to an exemplary embodiment of the inventive concept, the storage device 10 may not perform OVS operation before an uncorrectable error correction code (UECC) occurs, and may activate OVS operation after the occurrence of UECC. The non-volatile memory device 100 may output OVS detection information OVSDI to the controller 200, and the controller (CNTL) 200 may search for read level offset information corresponding to the OVS detection information OVSDI, and may shift the default read level (e.g., the read level of historical / normal read operations) by referring to the searched read level offset information during subsequent read operations.

[0057] Figure 2 The diagram shows Figure 1 An example of a non-volatile memory device 100 is illustrated in the diagram. (Reference) Figure 2 The non-volatile memory device 100 may include a memory cell array 110, a row decoder 120, a page buffer circuit 130, an input / output (I / O) buffer circuit 140, control logic 150, a voltage generator 160, and a cell counter 170.

[0058] The memory cell array 110 can be connected to the row decoder 120 via the word line WL or the string select line SSL and the ground select line GSL. The memory cell array 110 can be connected to the page buffer circuit 130 via the bit line BL. The memory cell array 110 can include multiple cell strings. The channels of each cell string can be formed in a vertical or horizontal direction. Each cell string can include multiple memory cells. Multiple memory cells can be programmed, erased, or read by voltage supplied to the bit line BL or the word line WL. Typically, programming operations are performed in the cells of a page, and erasing operations are performed in the cells of a block.

[0059] The row decoder 120 can select one of the memory blocks BLK1 to BLKz of the memory cell array 110 in response to address ADD. The row decoder 120 can select one word line from the word lines of the selected memory block in response to address ADD. The row decoder 120 can convert the word line voltage VWL corresponding to the operating mode to the word line of the selected memory block. During programming operations, the row decoder 120 can apply a programming voltage and a check voltage to the selected word line, and can apply a pass voltage to the unselected word lines. During read operations, the row decoder 120 can apply a read voltage to the selected word line and a read pass voltage to the unselected word lines.

[0060] Page buffer circuit 130 can operate as a write driver or a sense amplifier. During programming operations, page buffer circuit 130 can apply a bit line voltage corresponding to the data to be programmed to the bit lines of memory cell array 110. During read or check operations, page buffer circuit 130 can detect the data stored in the selected memory cell via bit line BL. Each of the plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 2) included in page buffer circuit 130 can be connected to at least one bit line.

[0061] Each of the multiple page buffers PB1 to PBn can perform read and latch operations for performing OVS operations. For example, each of the multiple page buffers PB1 to PBn can perform multiple read operations under the control of control logic 150 to identify a state stored in a selected memory cell. After storing the data read through the multiple read operations, each of the multiple page buffers PB1 to PBn can select a piece of data under the control of control logic 150. For example, each of the multiple page buffers PB1 to PBn can perform read operations two or more times to identify a state. Furthermore, each of the multiple page buffers PB1 to PBn can select or output the optimal data among multiple read data under the control of control logic 150.

[0062] I / O buffer circuit 140 can provide externally supplied data to page buffer circuit 130. I / O buffer circuit 140 can provide externally supplied command CMD to control logic 150. I / O buffer circuit 140 can provide externally supplied address ADD to control logic 150 or line decoder 120. In addition, I / O buffer circuit 140 can output data read and latched by page buffer circuit 130 to external entities.

[0063] Control logic 150 can respond to externally sent command CMD to control line decoder 120 and page buffer circuit 130.

[0064] Control logic 150 may include OVS circuitry 155 to perform OVS operation.

[0065] OVS circuit 155 can control page buffer circuit 130 and voltage generator 160 for OVS operation. OVS circuit 155 can control page buffer circuit 130 such that page buffer circuit 130 performs read operations two or more times to identify the specific state of the selected memory cell. OVS circuit 155 can control multiple page buffers PB1 to PBn such that multiple page buffers PB1 to PBn store read data corresponding to each of multiple read results in multiple latch sets included in each of the multiple page buffers PB1 to PBn. Additionally, OVS circuit 155 can perform a process for selecting the optimal data among multiple read data. OVS circuit 155 can refer to the counting result nC provided from cell counter 170 to select the optimal data. For example, OVS circuit 155 can control page buffer circuit 130 such that page buffer circuit 130 selects and outputs the read result closest to the distribution valley among multiple read results.

[0066] Additionally, the OVS circuit 155 can store development time information corresponding to the OVS operation. The OVS circuit 155 can output the stored development time information as OVS detection information OVSDI to the controller 200. In an exemplary embodiment of the inventive concept, the OVS detection information OVSDI can be output using a Universal Internal Bus (UIB), or in response to a feature acquisition command, or in response to a status read command. For ease of description, the following description will be given regarding the case where the OVS detection information OVSDI is output in response to a feature acquisition command.

[0067] Voltage generator 160 can generate various types of word line voltages that will be applied to each word line under the control of control logic 150, as well as well voltages that will be supplied to blocks (e.g., well regions) in which memory cells are formed. The word line voltages applied to the word lines may include programming voltages, pass voltages, read voltages, and read pass voltages, etc.

[0068] Cell counter 170 can count memory cells corresponding to a specific threshold voltage range from data read from page buffer circuit 130. For example, cell counter 170 can process data read from each of a plurality of page buffers PB1 to PBn to count the number of memory cells having a threshold voltage within a specific threshold voltage range.

[0069] The non-volatile memory device 100 according to an exemplary embodiment of the inventive concept can perform OVS operation to ensure the reliability of read operations. Furthermore, the non-volatile memory device 100 according to an exemplary embodiment of the inventive concept can output OVS detection information OVSDI to the controller 200 to perform read operations at the optimal read level in subsequent read operations. Therefore, the occurrence of UECC in read operations can be reduced. As a result, read retry operations for data recovery can be reduced.

[0070] Figure 3 yes Figure 1 The diagram shows the circuit diagram of one of the memory blocks, BLK1. Figure 3 The storage block BLK1 illustrated in the figure has a three-dimensional structure. Storage block BLK1 may include multiple cell strings CS11, CS12, CS21, and CS22. The multiple cell strings CS11, CS12, CS21, and CS22 may be arranged in the row and column directions to form rows and columns.

[0071] In an exemplary embodiment of the inventive concept, unit strings CS11 and CS12 can be connected to string select lines SSL1a and SSL1b to form a first row. Unit strings CS21 and CS22 can be connected to string select lines SSL2a and SSL2b to form a second row. For example, unit strings CS11 and CS21 can be connected to the first bit line BL1 to form a first column. Unit strings CS12 and CS22 can be connected to the second bit line BL2 to form a second column.

[0072] Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include multiple cell transistors. For example, each of the multiple cell strings CS11, CS12, CS21, and CS22 may include string select transistors SSTTa and SSTb, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, ground select transistors GSTTa and GSTb, and pseudo memory cells DMC1 and DMC2. For example, each of the multiple cell transistors included in the multiple cell strings CS11, CS12, CS21, and CS22 may be a charge-trap flash memory (CTF) cell.

[0073] Multiple memory cells MC1 to MC8 can be connected in series and stacked in a height direction perpendicular to the plane defined by the row and column directions. Multiple memory cells MC1 to MC8 can be connected to multiple word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8. Serial select transistors SSTa and SSTb can be connected in series. The series-connected serial select transistors SSTa and SSTb can be provided between the multiple memory cells MC1 to MC8 and the first or second bit lines BL1 and BL2. Ground select transistors GSTA and GSTb can be connected in series. The series-connected ground select transistors GSTA and GSTb can be provided between the multiple memory cells MC1 to MC8 and the common source line CSL.

[0074] In an exemplary embodiment of the inventive concept, a first pseudo memory cell DMC1 may be provided between a plurality of memory cells MC1 to MC8 and ground selection transistors GSTA and GSTb. For example, the first pseudo memory cell DMC1 may be positioned between a first memory cell MC1 and a ground selection transistor GSTb. For example, a second pseudo memory cell DMC2 may be provided between a plurality of memory cells MC1 to MC8 and string selection transistors SSTa and SSTb.

[0075] The ground select transistors GSTA and GSTb of cell strings CS11, CS12, CS21, and CS22 can be connected together to the ground select line GSL. For example, ground select transistors in the same row can be connected to the same ground select line, and ground select transistors in different rows can be connected to different ground select lines. For example, the first ground select transistor GSTA of cell strings CS11 and CS12 in the first row can be connected to the first ground select line. Similarly, among the second string select transistors SSTb of the same height, string select transistors in the same row can be connected to the same string select line, and string select transistors in different rows can be connected to different string select lines. For example, the second string select transistors SSTb of cell strings CS11 and CS12 in the first row can be connected together to the string select line SSL1b, and the second string select transistors SSTb of cell strings CS21 and CS22 in the second row can be connected together to the string select line SSL2b.

[0076] Furthermore, the string select transistors of cell strings in the same row can be connected together to the same string select line. For example, the first string select transistor SSTa and the second string select transistor SSTb of cell strings CS11 and CS12 in the first row can be connected together to the same string select line. Similarly, the first string select transistor SSTa and the second string select transistor SSTb of cell strings CS21 and CS22 in the second row can be connected together to the same string select line.

[0077] In an exemplary embodiment of the inventive concept, pseudo memory cells with the same height can be connected to the same pseudo word line, and pseudo memory cells with different heights can be connected to different pseudo word lines. For example, a first pseudo memory cell DMC1 can be connected to a first pseudo word line DWL1, and a second pseudo memory cell DMC2 can be connected to a second pseudo word line DWL2.

[0078] In the first memory block BLK1, erase operations can be performed in cells of the memory block or sub-block. When an erase operation is performed in a cell of the memory block, all memory cells MC of the first memory block BLK1 can be erased simultaneously in response to a single erase request. When an erase operation is performed in a cell of a sub-block, some memory cells MC of the first memory block BLK1 can be erased simultaneously in response to a single erase request, and other memory cells MC can be prevented from being erased. A low voltage (e.g., ground voltage) can be supplied to the word lines connected to the erased memory cells, and the word lines connected to the prevented-from-erasing memory cells can be floating.

[0079] Figure 3 The first storage block BLK1 illustrated herein is an exemplary storage block. In exemplary embodiments of the inventive concept, it will be understood that the number of lines GSL, WL, DWL, SSL, etc. connected to the cell transistors GST, MC, DMC, SST is not limited based on the number of cell strings, the number of rows, the number of columns, the number of cell transistors GST, MC, DMC, SST, etc.

[0080] Typically, OVS operations are only used to input recovery codes to satisfy read timing (e.g., tR) conditions for non-volatile memory devices. However, in existing defense codes, OVS operations encounter problems such as the use of optimal read levels.

[0081] Figure 4 This is a flowchart illustrating a read operation performed using OVS in a general-purpose storage device. It is assumed that a read operation is performed on a memory cell connected to the first word line WL1 using the default read level (401). When such a read operation fails (402), an OVS operation is activated on the memory cell connected to the first word line WL1 (403). For example, a non-volatile memory device inputs a defense code. The OVS operation is performed by reflecting a predefined table PDT (404). When a read operation performed on a memory cell connected to the first word line WL1 passes due to an OVS operation (405), the historical read level table HRT is updated (406). In this case, the offset information of the PDT used for the OVS operation is updated in the HRT.

[0082] Then, when a read operation (407) is performed on a memory cell connected to the next word line, such as the second word line WL2, the OVS operation is essentially deactivated. For example, a read operation is performed on a memory cell connected to the second word line WL2 while the defense code is released (408). In this case, the historical read operation is performed using the updated HRT (409). The general-purpose storage device does not reflect the optimal read level offset searched in the OVS operation in the HRT. Therefore, the probability that a read operation on a memory cell connected to the next word line will fail (410) is high.

[0083] The storage device 10 according to an exemplary embodiment of the inventive concept can reflect detection information OVSDI based on OVS operation in the historical read level table HRT (see also...). Figure 1 This allows for the use of the optimal read level in subsequent read operations.

[0084] Figure 5 This is a diagram illustrating the extraction of the optimal read level of the storage device 10 according to an exemplary embodiment of the inventive concept. (Reference) Figure 5 Storage device 10 can use predefined tables PDT (first table) and OVST (second table) to update the historical read level table HRT (third table) to extract the optimal read level. In other words, storage device 10 can use the first table and the second table to update the historical read level table HRT to extract the optimal read level.

[0085] OVS detection information OVSDI (see also) Figure 1 This can include result information based on OVS operation. The second read level offset OST_ovst, corresponding to the OVS detection information OVSDI, can be reflected in OVST. In other words, the second read level offset OST_ovst can be output from the second table. The second read level offset OST_ovst can be added to the first read level offset OST_pdt based on the elapsed programming time to determine the third read level offset OST_hrt. The first read level offset OST_pdt can be output from the first table. The third read level offset OST_hrt can be determined not only by simply adding the first read level offset OST_pdt and the second read level offset OST_ovst. For example, the third read level offset OST_hrt can be added by applying weights to each of the first and second read level offsets OST_pdt and OST_ovst. The third read level offset OST_hrt can be stored in the third table.

[0086] According to an exemplary embodiment of the inventive concept, the storage device 10 can reflect a second read level offset OST_ovst based on OVS operation in the HRT to perform a read operation at the optimal read level, while deactivating the OVS operation (e.g., not applying a defense code). Therefore, the data reliability of the read operation can be increased, and the input of the defense code can be reduced to improve the performance of the read operation.

[0087] Typically, memory cells distributed around a distribution valley are those located on the boundary between enabled and disabled cells. Therefore, the identification of such cells as enabled or disabled cells can vary depending on the development time. For example, when the development time is slightly reduced, memory cells distributed around the distribution valley can be identified as disabled cells. Furthermore, when the development time is slightly increased, memory cells distributed around the distribution valley can be identified as enabled cells. For example, in a read operation, reducing the development time for memory cells with a threshold voltage similar to the level of the read voltage applied to the word line can have the effect of increasing the read voltage to perform a read operation. Furthermore, in a read operation, increasing the development time for memory cells with a threshold voltage around the read voltage has the effect of decreasing the read voltage to perform a read operation. Therefore, reading the read node of the page buffer several times at different development times can have the effect of changing the word line voltage to precharge and read the bit line. For example, read operations at different development times have the same effect as having different levels of read voltage supplied to the word line.

[0088] Figure 6A and Figure 6B This is a graph illustrating different reading voltages and corresponding development times for the distribution valleys. For example... Figure 6A As illustrated, the OVS operation used to search for the distribution valleys of states S1 and S2 can be performed through multiple read operations. These multiple read operations can be performed simultaneously in each of multiple page buffer groups.

[0089] refer to Figure 6B OVS operations can be performed by sequentially latching the read nodes at the same time points during different development periods using the first page buffer PGB1 and the second page buffer PGB2 to store the read results.

[0090] The precharge operation can be performed from time point T0 to time point T1. The first bit line and read node connected to each of the first page buffers PBG1 can be charged to perform the precharge operation. When the bit line setting signal is activated, the read node and the first bit line can be precharged to a specific level. When the first bit line setting signal is deactivated to a high level at time point T1, the precharge circuit of each of the first page buffers PBG1 can be turned off. Additionally, when the second bit line setting signal is deactivated to a high level at time point T2, which follows time point T1, the precharge circuit of each of the second page buffers PBG2 can be turned off. In this case, the level of the read node of each of the first page buffers PBG1 and the level of the read node of each of the second page buffers PBG2 can vary with the current intensity flowing to the corresponding bit line depending on whether the memory cell is turned on or off.

[0091] like Figure 6B As illustrated, each of the first page buffers PBG1 can precharge the read node from time point T0 to time point T1, and can develop the first bit line from time point T1 to time point T4. Each of the second page buffers PBG2 can precharge the read node from time point T0 to time point T1, and can develop the second bit line from time point T2 to time point T4, where time point T2 is later than time point T1.

[0092] The first read operation may include a latch reset (nS) read operation performed at time point T3 and a latch set (S) read operation performed at time point T5. The first cell count information can be calculated using the enabled cell count values ​​of the latch reset (nS) read operation and the latch set (S) read operation in the first page buffer PGB1. Furthermore, the second cell count information can be calculated using the enabled cell count values ​​of the latch reset (nS) read operation and the latch set (S) read operation in the second page buffer PGB2. The detection condition (one of C1, C2, C3, C4, and C5) corresponding to the optimal read level corresponding to the distribution valley can be determined based on the first cell count information and the second cell count information of the first read operation. The development times tSODev1, tSODev2, tSODev3, tSODev4, and tSODev5 of the second read operation corresponding to the determined detection condition can be determined. Time points T6 to T7 can correspond to the recharge operation, and development and readout operations can be performed from time point T7 onwards.

[0093] Figure 7 This is a diagram illustrating read level offset compensation using OVST according to an exemplary embodiment of the inventive concept.

[0094] The shift in development time corresponding to the optimal distribution valley based on OVS operation can be determined. In the case of the top page, the shift in development time is +80ns. In this case, the detection situation of OVS operation is compared with the third detection situation C3 ( Figure 7 Corresponding to case 3) in the above. Non-volatile memory device 100 (see also...) Figure 1 The OVS circuit 155 (see also) Figure 1 The first transition operation can be performed on the detection case corresponding to the optimal development time of the OVS operation. The OVS circuit 155 can store or latch the data bits for each detection case.

[0095] Then, the OVS detection information OVSDI from the non-volatile memory device 100 (see [link]). Figure 1 It can be output to controller 200 (see [link]). Figure 1 The controller 200 can search the OVST for OVS detection information, such as a read level offset (+20mV) corresponding to OVS detection condition C3. In this case, the controller 200 can perform a second conversion operation on the read level corresponding to the OVS detection condition. Ultimately, the controller 200 can use the OVST to compensate for the default / historical read level. It should be understood that if the OVS detection condition is C1 or condition 1, the read level offset will be, for example, -20mV.

[0096] Figure 8A and Figure 8B An exemplary embodiment of the OVST according to the inventive concept is illustrated.

[0097] refer to Figure 8A The diagram illustrates eight states S1, S2, S3, S4, S5, S6, S7, and S8 corresponding to a 3-bit memory cell, and seven read levels R1, R2, R3, R4, R5, R6, and R7 used to distinguish states S1 through S8. (Reference) Figure 8B OVST includes offsets for detection conditions C1 to C5 corresponding to the seven read levels R1 to R7.

[0098] Despite Figure 8B The diagram illustrates five OVS detection scenarios, but it will be understood that the number of detection scenarios according to this embodiment is not limited to this.

[0099] Figure 9A , Figure 9B ,and Figure 9C The illustration shows an example of using OVST, an exemplary embodiment of the inventive concept, to search for the optimal valley when the predefined table PDT offset is insufficient.

[0100] refer to Figure 9AIt is assumed that the memory cell degradation exceeds the PDT offset (e.g., -50mV). Under this assumption, as... Figure 9B As illustrated in the diagram, read operations using only the existing PDT offset (-50mV) have a high probability of read failure. Furthermore, as... Figure 9C As illustrated, the optimal read offset (-110mV) obtained by adding an OVST offset (-60mV) to the existing PDT offset (-50mV) can be reflected to perform the read operation according to the exemplary embodiment of the inventive concept at the optimal distribution valley. Therefore, the read operation can have a high read pass probability.

[0101] Figure 10A , Figure 10B ,and Figure 10C The illustration shows an example of using OVST, an exemplary embodiment according to the inventive concept, to search for the optimal valley when the PDT offset is too large. Reference Figure 10A It is assumed that the memory cell degradation is less than the PDT offset (e.g., -90mV). Under this assumption, as... Figure 10B As illustrated in the diagram, read operations using only the existing PDT offset (-90mV) have a high probability of read failure. Furthermore, as... Figure 10C As illustrated, the optimal read offset (-30mV) obtained by adding an OVST offset (+60mV) to the existing PDT offset (-90mV) can be reacted to perform a read operation according to an exemplary embodiment of the inventive concept at the optimal distribution valley. Therefore, the read operation has a high read pass probability.

[0102] Figure 9C and Figure 10C The offset compensation method illustrated herein is not intended to limit the scope of the invention.

[0103] Read operations of the non-volatile memory device 100 according to an exemplary embodiment of the present invention can be performed in either normal mode or OVS mode. OVS mode can be applied to at least one state.

[0104] Figure 11A An example of the distribution of OVS modes for applying a read operation according to an exemplary embodiment of the inventive concept is illustrated.

[0105] refer to Figure 11A The OVS operation can be applied only to the highest state (e.g., S8). It should be understood that the OVS operation is not limited to the highest state S8.

[0106] Figure 11B An example of the distribution of OVS modes for applying a read operation according to another exemplary embodiment of the inventive concept is illustrated.

[0107] refer to Figure 11B The OVS operation can be applied to several states (e.g., S6, S7, and S8). Figure 11B The diagram illustrates three states in which OVS operations are applied, but the concept of this invention is not limited thereto.

[0108] Figure 11C The illustration shows an example of the distribution of OVS modes for a read operation applied according to another exemplary embodiment of the inventive concept. (Reference) Figure 11C The OVS operation can be applied to all states (e.g., S1 to S8).

[0109] exist Figure 11A , Figure 11B and Figure 11C The application of OVS mode to a 3-bit memory cell (three-level cell (TLC)) has already been described. However, the memory cell in the exemplary embodiments of the present invention is not limited to TLC. The memory cell in the exemplary embodiments of the present invention can be a 4-bit memory cell (four-level cell (QLC)). In this case, OVS mode can be applied to at least one of 16 states.

[0110] Figure 12 This is a flowchart illustrating a reading method of a storage device according to an exemplary embodiment of the inventive concept. (Reference) Figures 1 to 12 The following will execute a read operation on storage device 10.

[0111] Storage device 10 can receive read requests from the host (e.g., the read request can be provided from outside the host). Storage device 10 can identify the history of such read requests. It can check whether a currently received read request exists in the history buffer (S110). When a currently received read request exists among the previous read requests stored in the history buffer, a historical read operation can be performed (S111). In this case, the historical read operation can be performed at the optimal read level included in the historical read level table HRT. When a current read request does not exist among the previous read requests stored in the history buffer, a normal read operation can be performed (S112). In this case, the normal read operation can be performed at the default read level.

[0112] As a result of a historical or normal read operation, it can be determined whether UECC has occurred (S113). UECC means that the read data cannot be processed by the ECC circuit 230 (see [link to ECC circuit 230]). Figure 1 Recovery. When UECC does not occur, the read operation can be completed immediately. When UECC occurs, OVS mode is activated (S114) and the non-volatile memory device 100 (see [link to documentation]) resumes operation. Figure 1Read retry operations can be performed according to OVS mode. Read retry operations can include read operations using PDT and OVS. For example, read level offset of PDT and OVS operation can be performed to perform read retry operations (S115).

[0113] Whether the read retry operation passes can be determined (S116). As a result of this determination, if the read retry operation passes, the offset information corresponding to the OVS detection status can be determined using OVST (S117). The historical read level table HRT (S118), which reflects the offset information of OVST and PDT, can be updated. The update of the historical read level table HRT can be performed periodically or non-periodically.

[0114] When a read retry operation fails, the controller 200 can perform a chip valley search operation to recover the data (S119). Chip valley search means searching for distribution valleys by sequentially scanning a predetermined voltage period while simultaneously increasing or decreasing the predetermined voltage during the predetermined voltage period.

[0115] The read operation can be performed based on a chip-external valley search operation, according to the distribution valley, and whether the read operation fails can be determined (S120). If the read operation does not fail, the read operation can be completed. If the read operation fails, a UECC (User-Defined Content Request) from the host for the read request can appear. The UECC can be output to the host.

[0116] A read operation of a non-volatile memory device 100 according to an exemplary embodiment of the inventive concept may include a first read operation performed according to a first read command and a second read operation performed according to a second read command. The non-volatile memory device 100 may perform a read operation using a default read level in response to the first read command, and may perform an OVS operation in response to the second read command.

[0117] In an exemplary embodiment of the inventive concept, the time taken for the second read operation may be longer than the time taken for the first read operation. In another exemplary embodiment of the inventive concept, the time taken for the second read operation may be the same as the time taken for the first read operation.

[0118] Figure 13 This is a flowchart illustrating a reading method of a storage device according to another exemplary embodiment of the inventive concept. (Reference) Figures 1 to 1 1 and Figure 13 The read operation of storage device 10 can be performed as follows.

[0119] Non-volatile memory device 100 (see also) Figure 1 It can respond to the controller 200 (see [link]). Figure 1The first command sent performs the first read operation using the default read level (S210). The first command and the information corresponding to the default read level can be sent together from the controller 200. The default read level information may include the optimal read level offset information from the historical read level table HRT.

[0120] As a result of the first read operation, the controller 200 can determine whether UECC has occurred (S220). If UECC has not occurred, the read operation can be completed.

[0121] When UECC occurs, the non-volatile memory device 100 can perform a second read operation by reading from OVS in response to a second command sent from the controller 200. Thus, the read operation can be completed.

[0122] Figure 14 This is a step diagram illustrating the process of extracting the read level offset from the storage device 10 according to an exemplary embodiment of the inventive concept. (See reference) Figures 1 to 14 The read operation of storage device 10 can be performed as follows.

[0123] A default read level corresponding to a host or internal read request can be determined. In an exemplary embodiment of the inventive concept, in the case of a historical read operation, the default read level can be determined using read level offset information of the HRT. The controller 200 can send the default read level along with a first read command for page 1 to the non-volatile memory device 100. The non-volatile memory device 100 can perform a primary read operation based on the first read command and using the default read level. Data read in the primary read operation will be output to the controller 200.

[0124] The controller 200 can determine whether the data received from the non-volatile memory device 100 has passed through the ECC circuit 230. When the data has passed through the ECC circuit 230, the read operation can be completed. When the data has not passed through the ECC circuit 230, the controller 200 can activate the OVS mode of the non-volatile memory device 100 and can send a second read command for page 1 to the non-volatile memory device 100. The second read command may include information for activating the OVS mode.

[0125] The non-volatile memory device 100 can perform an OVS read operation and a primary read operation on page 1 in response to a second read command. The OVS read operation can be applied only to a predetermined state. Simultaneously, the non-volatile memory device 100 can perform a primary read operation in a state where an OVS read operation is not performed. Data read through the OVS read operation and the primary read operation can be output to the controller 200.

[0126] Then, controller 200 can send a specific command (e.g., a feature acquisition command) to non-volatile memory device 100 to obtain OVS detection information. Non-volatile memory device 100 can then output the OVS detection information to controller 200 in response to the specific command. Controller 200 can then use the OVS detection information to extract the read level offset and apply the extracted read level offset to a historical read level table (HRT).

[0127] Additionally, it can be determined once again whether the read data has passed through ECC circuit 230. If the read data has passed through ECC circuit 230, the read operation can be completed. If the read data has not passed through ECC circuit 230, controller 200 can activate OVS mode of non-volatile memory device 100 and can resend a second read command for page 1 to non-volatile memory device 100. In this case, the default read level sent may include the lowest read level applied to the historical read level table HRT.

[0128] Then, the non-volatile memory device 100 can perform an OVS read operation and a primary-side operation on page 1 in response to the second read command. The data read through the OVS read operation and the primary read operation can be output to the controller 200.

[0129] Then, controller 200 can send a specific command to non-volatile memory device 100 to obtain OVS detection information. Non-volatile memory device 100 can respond to the specific command by outputting OVS detection information to controller 200. Then, controller 200 can use the OVS detection information to extract the read level offset and can apply the extracted read level offset to the historical read level table HRT.

[0130] In an exemplary embodiment of the inventive concept, a normal read operation can be performed using a default read level, and the default read level can be changed using OVS detection information. In an exemplary embodiment of the inventive concept, a specific command may include a feature acquisition command. In an exemplary embodiment of the inventive concept, performing an on-chip valley search operation may include performing multiple readout operations at development times corresponding to different detection conditions, and performing readout operations at a selected development time based on the results of the multiple readout operations. In an exemplary embodiment of the inventive concept, the readout method may further include storing detection condition information corresponding to the selected development time, and outputting the detection condition information via multiple data lines.

[0131] Figure 15 This is a ladder diagram of a read operation using a read level offset extracted from a storage device, according to an exemplary embodiment of the inventive concept. (See reference) Figure 15A read operation using a read level offset can be performed as follows.

[0132] like Figure 15 As illustrated, the read level offset corresponding to the OVS read operation can be applied to the default read level. Then, the controller 200 can send a first read command for the second page 2 along with the default read level to the non-volatile memory device 100. The non-volatile memory device 100 can perform a main read operation using the optimal default read level in response to the first read command. The data read in the main read operation can be output to the controller 200. Because the data is read using the optimal read level, the probability that the read data will pass through the ECC circuit 230 is high. When the read data passes through the ECC circuit 230, the read operation can be completed. If the read data does not pass through the ECC circuit 230, data recovery can be performed using another defense code.

[0133] Similar to the read operation described above, a read operation using the optimal read level based on the first read command can be performed on pages 1 to the other m-th pages (pages 3 to m) in the same frame.

[0134] The read retry operation of an exemplary embodiment of the present invention may include an OVS operation. However, the read retry operation of an exemplary embodiment of the present invention is not limited to an OVS operation.

[0135] Figure 16 This is a step diagram illustrating the read operation of a storage device according to another exemplary embodiment of the inventive concept. (Reference) Figure 1 and Figure 16 The following read operations can be performed on the storage device.

[0136] The host can send a read request along with the address ADD to storage device 10 (see [link]). Figure 1 (S30). The controller 200 of the storage device 10 can receive read requests and can search the history buffer to determine whether to perform a history read operation or a normal read operation, and can send a request to the non-volatile memory device (NVM) 100 (see [link to NVM]). Figure 1 The non-volatile memory device 100 can perform a read operation in response to the normal / history read command (S31) and can send the read data to the controller 200 (S32).

[0137] Then, the controller 200 can perform error correction operations on the data read by the ECC circuit 230 (S33). When no error exists or when the error can be corrected, the read data or corrected data can be sent to the host (S34-1).

[0138] When an error is uncorrectable, controller 200 can send a read retry command to non-volatile memory device 100 (S34-2). Non-volatile memory device 100 can perform a read operation in response to the read retry command and can send the read data to controller 200 (S35). Then, controller 200 can perform error correction again on the data read from ECC circuit 230 (S36). When no error exists or when the error is correctable, the read data or corrected data can be sent to the host (S37). Then, controller 200 can send a specific command to non-volatile memory device 100 to obtain read retry information with optimal read level information (S38). Non-volatile memory device 100 can output the read retry information in response to the specific command (S39). Then, controller 200 can use the read retry information to update the historical read level table HRT (S40).

[0139] Then, when a read request for the same address ADD is received from the host (S41), the storage device 100 sends a historical read command to the non-volatile memory device 100 using the optimal read level reflected in the historical read level table HRT (S42).

[0140] exist Figure 16 In the read operation of the storage device 10 illustrated in the figure, a historical read operation is performed. However, the storage device 10 according to the exemplary embodiment of the present invention is not limited thereto. For example, the storage device 10 may not perform a historical read operation.

[0141] Figure 17 This is a step diagram illustrating a read operation of another storage device according to another exemplary embodiment of the inventive concept. Reference Figure 17 ,and Figure 16 The read operations illustrated in the diagram differ; historical read operations are not performed (S31a), and normal read operations are performed (S42a). Normal read operations can be performed using the optimal read level included in the default read level table. The default read level may include the optimal read level based on read retry information.

[0142] According to an exemplary embodiment of the inventive concept, the non-volatile memory device 100 can define OVS detection conditions for all states.

[0143] Figure 18A and Figure 18B The illustration shows an example of OVS detection in a non-volatile memory device according to an exemplary embodiment of the inventive concept. (Reference) Figure 18A The diagram illustrates five detection scenarios for the corresponding OVS detection levels R1 to R5. (Reference) Figure 18BThe illustration shows seven detection scenarios for the corresponding OVS detection levels R1 to R7. In an exemplary embodiment of the inventive concept, at least one of the seven detection scenarios can be set to each of the most significant / center / least significant bit (MSB / CSB / LSB) pages.

[0144] It will be understood that the number of detection cases corresponding to the detection level according to the exemplary embodiments of the inventive concept is not limited thereto.

[0145] Decoding operations can be performed to output OVS detection information corresponding to the OVS detection status. However, the inventive concept is not limited thereto. OVS detection information output according to an exemplary embodiment of the inventive concept can be implemented such that OVS detection statuses and the programming states of units are mapped one-to-one, without performing decoding operations on the OVS detection statuses.

[0146] Figure 19 The illustration shows an example of OVS detection information and a method for outputting OVS detection information according to an exemplary embodiment of the inventive concept.

[0147] like Figure 19 As illustrated, OVS detection cases can be matched one-to-one with states. For example, case 1 can match state [0] and case 6 can match state [5]. In an exemplary embodiment of the inventive concept, the detection cases may not match the most effective state.

[0148] Figure 20 The diagram illustrates the output of OVS detection information as an example of a specific command.

[0149] exist Figure 20 The diagram illustrates an example of timing for outputting OVS detection information based on a specific command. Multiple OVS detection messages for the first pad address MAT2 are output. The output OVS detection information may include a first readout result for detecting level R6, a second readout result for detecting level R4, and a third readout result for detecting level R2.

[0150] Figures 1 to 20 The storage device 10 illustrated in the figure uses a first table (PDT) and a second table (OVST) to change the default read level for normal / historical read operations. However, the storage device of the present invention is not limited thereto. A storage device according to an exemplary embodiment of the present invention may use only OVST to change the default read level for normal / historical read operations.

[0151] Figure 21 The illustration shows a storage device 20 according to another exemplary embodiment of the inventive concept.

[0152] refer to Figure 21Storage device 20 compared to Figure 1 The storage device 10 shown in the figure does not have a first table PDT and may include a controller 200a that uses OVST to update the historical read level table HRT. Figure 21 The storage device 20 is further illustrated with CLE, ALE, CE (or more), WE, RE, DQS (or more) and DQ pins.

[0153] According to an exemplary embodiment of the inventive concept, the storage device may have a coarse offset table for coarsely managing offsets and a fine offset table for finely managing offsets in terms of table management.

[0154] Figure 22 The illustration shows a storage device 30 according to another exemplary embodiment of the inventive concept. (Reference) Figure 22 The storage device 30 may include a non-volatile memory device 100 and a controller 200b for controlling the non-volatile memory device 100.

[0155] The controller 200b can manage the historical read level table using a coarse offset table and a fine offset table, and can send an optimal read level to the non-volatile memory device 100 based on the historical read level table. The non-volatile memory device 100 can use the optimal read level to perform a read operation. In an exemplary embodiment of the inventive concept, the fine offset table may include offset information corresponding to OVS detection information OVSDI based on OVS operation.

[0156] The storage device according to an exemplary embodiment of the present invention can be further reflected in a historical read level table based on environmental information.

[0157] Figure 23 The illustration shows a storage device 40 according to another exemplary embodiment of the inventive concept. (Reference) Figure 23 The storage device 40 may include a non-volatile memory device 100 and a controller 200c for controlling the non-volatile memory device 100.

[0158] Compared to Figure 1 The controller 200c shown in the diagram can additionally reflect environmental information in a historical read level table. Environmental information can be at least one of the following associated with the memory cell to be read: elapsed programming time, programming temperature, read temperature, word line address, block address, die address, erase cycle, programming cycle, read cycle, etc.

[0159] Figure 24 The illustration shows the table management of a storage device 10 according to an exemplary embodiment of the inventive concept.

[0160] refer to Figure 24 The non-volatile memory device 100 may include a user area and a metadata area. The user area can store user data and can be implemented as... Figures 1 to 3 The multiple storage blocks described herein, such as storage blocks BLK1 to BLKz. The meta-region can store management information used to manage the non-volatile memory device 100 and can be implemented as... Figures 1 to 3 At least one storage block as described herein, such as one of storage blocks BLK1 to BLKz. The meta-region may not be implemented as the same storage block as the user region.

[0161] The meta-region may include a predefined table and an OVS table. The predefined table may store values ​​indicating the degree to which the read level changes over time as programmed. When the storage device 10 is initialized, the predefined table and OVS table of the meta-region may be loaded into the buffer memory 220 of the controller 200 (e.g., SRAM, DRAM, etc.). In an exemplary embodiment of the inventive concept, the historical read level table 223 of the buffer memory 220 may be updated to the meta-region periodically or non-periodically from the buffer memory 220.

[0162] The controller 200 can be connected to the non-volatile memory device 100 via a channel CH. The controller 200 may include a timer 202, at least one processor 210, and a buffer memory 220. The timer 202 may be implemented in hardware / software / firmware. The timer 202 can externally receive time-related information and can generate / output the current time. For example, the timer 202 can receive and count the system clock to generate the current time. In another exemplary embodiment of the inventive concept, the timer 202 can externally receive time information and can count an internal clock to generate the current time. In this case, the internal clock can be generated from an oscillator within the storage device 10.

[0163] At least one processor 210 can control the overall operation of the storage device 10. At least one processor 210 can perform various management operations, such as cache / buffer management, firmware management, useless cell collection management, wear leveling management, data deduplication management, read refresh / reclaim management, bad block management, multi-stream management, host data and non-volatile memory mapping management, quality of service (QoS) management, system resource allocation management, non-volatile memory queue management, read level management, erase / programming management, hot / cold data management, power loss protection management, dynamic thermal management, initialization management, and redundant array of low-cost disks (RAID) management, etc.

[0164] For example, at least one processor 210 can drive the read level management module 212. The read level management module 212 can manage tables to send optimal read levels to the non-volatile memory device 100, as referenced. Figures 1 to 23 As described.

[0165] In an exemplary embodiment of the inventive concept, the read level management module 212 can issue a specific command (e.g., a get feature command) to the non-volatile memory device 100 to receive OVS detection information OVSDI (see [link to documentation]). Figure 1 And generate an OVS table 222 corresponding to the OVS detection information. In an exemplary embodiment of the inventive concept, the read level management module 212 can use the predefined table 221 and the OVS table 222 to update the historical read level table 223. In an exemplary embodiment of the inventive concept, the read level management module 212 can send an optimal read level to the non-volatile memory device 100 during normal read operations or historical read operations.

[0166] The buffer memory 220 can temporarily store the data required by the drive. For example, the buffer memory 220 can store at least one predefined table 221, an OVS table 222, and a historical read level table 223.

[0167] exist Figure 24 The buffer memory 220 shown in the figure is housed within the controller 200. However, the inventive concept is not limited thereto. The buffer memory 220 may be arranged as an external configuration of the controller 200. The controller 200 may further include a code memory storing at least one instruction. Various management operations can be performed as at least one instruction stored in the code memory is executed by at least one processor 210. The controller 200 may further include a host interface device for interfacing with a host and a non-volatile interface device for interfacing with the non-volatile memory device 100.

[0168] The non-volatile memory device according to an exemplary embodiment of the present invention can be implemented in a chip-to-chip (C2C) structure.

[0169] Figure 25 The illustration shows a non-volatile memory device 1000 implemented in a C2C structure according to an exemplary embodiment of the inventive concept.

[0170] A C2C structure can mean fabricating an upper chip including cell regions (CELL) on a first wafer, and fabricating a lower chip including peripheral circuit regions (PERI) on a second wafer separate from the first wafer, and then bonding the upper and lower chips together. Here, the bonding process can be a method of electrically connecting adhesive metal formed on the uppermost metal layer of the upper chip and adhesive metal formed on the uppermost metal layer of the lower chip to each other. In an exemplary embodiment of the inventive concept, when the adhesive metal is copper (Cu), Cu-to-Cu bonding can be performed. However, the inventive concept is not limited to this. For example, the adhesive metal can be formed of aluminum (Al) or tungsten (W).

[0171] Each of the peripheral circuit region PERI and cell region CELL of the non-volatile memory device 1000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0172] The Peripheral Circuit Region (PERI) may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c disposed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c respectively connected to the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal layers 1240a, 1240b, and 1240c disposed on the first metal layers 1230a, 1230b, and 1230c. In an exemplary embodiment of the inventive concept, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten (W) having relatively high resistance. In an exemplary embodiment of the inventive concept, the second metal layers 1240a, 1240b, and 1240c may be formed of copper (Cu) having relatively low resistance.

[0173] exist Figure 25 The diagram illustrates first metal layers 1230a, 1230b, and 1230c and second metal layers 1240a, 1240b, and 1240c, but the inventive concept is not limited thereto. One or more additional metal layers may be provided on the second metal layers 1240a, 1240b, and 1240c. At least some of the one or more additional metal layers provided on the second metal layers 1240a, 1240b, and 1240c may be formed of aluminum (Al), etc., which has a lower resistivity compared to copper (Cu) used to form the second metal layers 1240a, 1240b, and 1240c.

[0174] In an exemplary embodiment of the inventive concept, an interlayer insulating layer 1215 may be disposed on a first substrate 1210 to cover a plurality of circuit elements 1220a, 1220b and 1220c, first metal layers 1230a, 1230b and 1230c, and second metal layers 1240a, 1240b and 1240c. In an exemplary embodiment of the inventive concept, the interlayer insulating layer 1215 may include an insulating material such as silicon oxide or silicon nitride.

[0175] Lower bonding metals 1271b and 1272b can be provided on the second metal layer 1240b in the word line bonding area (WLBA). In the word line bonding area (WLBA), the lower bonding metals 1271b and 1272b of the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 1371b and 1372b of the cell area (CELL) using an bonding method. In an exemplary embodiment of the inventive concept, the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b can be formed of aluminum (Al), copper (Cu), tungsten (W), etc. Furthermore, the upper bonding metals 1371b and 1372b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 1271b and 1272b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0176] A cell region (CELL) may include at least one memory block. In an exemplary embodiment of the inventive concept, the cell region (CELL) may include a second substrate 1310 and a common source line 1320. A plurality of word lines 1331, 1332, 1333, 1334, 1335, 1336, 1337, and 1338 (collectively referred to as 1330) may be stacked on the second substrate 1310 in a direction perpendicular to the upper surface of the second substrate 1310 (e.g., the Z-axis direction). In an exemplary embodiment of the inventive concept, a string select line and a ground select line may be positioned above and below the word lines 1330, respectively. In an exemplary embodiment of the inventive concept, the plurality of word lines 1330 may be positioned between the string select line and the ground select line.

[0177] In the bit line bonding area BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 1310 (e.g., the Z-axis direction) to penetrate the word line 1330, the serial select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc. The channel layer can be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c can be a bit line contact, and the second metal layer 1360c can be a bit line. In an exemplary embodiment of the inventive concept, the bit line 1360c can extend in a first direction parallel to the upper surface of the second substrate 1310 (e.g., the Y-axis direction).

[0178] like Figure 25 As illustrated, the area where the channel structure CH and bit line 1360c are located can be a bit line bonding area BLBA. In an exemplary embodiment of the inventive concept, within the bit line bonding area BLBA, bit line 1360c can be electrically connected to circuit element 1220c that provides page buffer 1393 in peripheral circuit area PERI. Bit line 1360c can be connected to upper bonding metals 1371c and 1372c in peripheral circuit area PERI. Upper bonding metals 1371c and 1372c can be connected to lower bonding metals 1271c and 1272c, which are connected to circuit element 1220c of page buffer 1393.

[0179] In the word line bonding area WLBA, the word line 1330 may extend in a second direction (e.g., the X-axis direction) parallel to the upper surface of the second substrate 1310 and perpendicular to the first direction. In an exemplary embodiment of the inventive concept, the word line bonding area WLBA may be connected to a plurality of unit contact plugs 1341, 1342, 1343, 1344, 1345, 1346, and 1347 (collectively referred to as 1340). For example, the word line 1330 and the unit contact plug 1340 may be connected to each other on pads, wherein at least some of the word lines 1330 are provided to extend at different lengths in the second direction. In an exemplary embodiment of the inventive concept, a first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper portion of the unit contact plug 1340, which is connected to the word line 1330. In an exemplary embodiment of the inventive concept, in the word line bonding area WLBA, the unit contact plug 1340 can be connected to the peripheral circuit area PERI via the upper bonding metals 1371b and 1372b in the unit area CELL and the lower bonding metals 1271b and 1272b in the peripheral circuit area PERI.

[0180] In an exemplary embodiment of the inventive concept, the unit contact plug 1340 may be electrically connected to circuit element 1220b of the line decoder 1394 forming the peripheral circuit region PERI. In an exemplary embodiment of the inventive concept, the operating voltage of the circuit element 1220b forming the line decoder 1394 may differ from the operating voltage of the circuit element 1220c forming the page buffer 1393. For example, the operating voltage of the circuit element 1220c forming the page buffer 1393 may be higher than the operating voltage of the circuit element 1220b forming the line decoder 1394.

[0181] The common power line contact plug 1380 can be placed in the external pad bonding area PA. In an exemplary embodiment of the inventive concept, the common power line contact plug 1380 can be formed of a conductive material such as metal, metal compound, polysilicon, etc. The common power line contact plug 1380 can be electrically connected to the common power line 1320. The first metal layer 1350a and the second metal layer 1360a can be sequentially stacked on the common power line contact plug 1380. For example, the area where the common power line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed can be the external pad bonding area PA.

[0182] Input / output pads 1205 and 1305 can be placed within the external pad bonding area PA. (See reference) Figure 25 A lower insulating layer 1201 may be provided beneath the first substrate 1210 to cover the lower surface of the first substrate 1210. A first input / output pad 1205 may be provided on the lower insulating layer 1201. In an exemplary embodiment of the inventive concept, the first input / output pad 1205 may be connected to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c located in the peripheral circuit region PERI via a first input / output contact plug 1203. In an exemplary embodiment of the inventive concept, the first input / output pad 1205 may be separated from the first substrate 1210 by the lower insulating layer 1201. Additionally, a side insulating layer may be placed between the first input / output contact plug 1203 and the first substrate 1210 to electrically isolate the first input / output contact plug 1203 and the first substrate 1210 from each other. In this embodiment, a second input / output pad 1305 is electrically connected to circuit element 1220a.

[0183] refer to Figure 25 An upper insulating layer 1301 may be provided on the second substrate 1310 to cover the upper surface of the second substrate 1310. A second input / output pad 1305 may be placed on the upper insulating layer 1301. In an exemplary embodiment of the inventive concept, the second input / output pad 1305 may be connected via a second input / output contact plug 1303 to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c located in the peripheral circuit region PERI.

[0184] In an exemplary embodiment of the inventive concept, the second substrate 1310, common source line 1320, etc., may not be placed in the area where the second input / output contact plug 1303 is disposed. The second input / output pad 1305 may not overlap with the word line 1380 in a third direction (e.g., the Z-axis direction). Reference Figure 25The second input / output contact plug 1303 can be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310. Furthermore, the second input / output contact plug 1303 can be connected to the second input / output pad 1305 via the interlayer insulating layer 1315 in the cell region.

[0185] In an exemplary embodiment of the inventive concept, the first input / output pad 1205 and the second input / output pad 1305 may be provided selectively. For example, the non-volatile memory device 1000 may include only the first input / output pad 1205 provided on the first substrate 1201, or only the second input / output pad 1305 provided on the second substrate 1301. In another exemplary embodiment of the inventive concept, the non-volatile memory device 1000 may include both the first input / output pad 1205 and the second input / output pad 1305.

[0186] The metal pattern provided on the top metal layer can be presented as a pseudo-pattern or can be presented in each of the external pad bonding areas PA and bit line bonding areas BLBA not included in each of the cell area CELL and peripheral circuit area PERI.

[0187] In the external pad bonding area PA, the non-volatile memory device 1000 according to an exemplary embodiment of the inventive concept may include a lower metal pattern 1273a provided on the uppermost metal layer in the peripheral circuitry area PERI to correspond to an upper metal pattern 1372a provided on the uppermost metal layer in the cell region CELL, the lower metal pattern 1273a having the same cross-sectional shape as the upper metal pattern 1372a in the cell region CELL for connection to each other. The lower metal pattern 1273a provided on the uppermost metal layer in the peripheral circuitry area PERI may not be connected to additional contacts in the peripheral circuitry area PERI. Similarly, in the external pad bonding area PA, the non-volatile memory device 1000 may include an upper metal pattern 1372a provided on the uppermost metal layer in the peripheral circuitry area PERI to correspond to the lower metal pattern 1273a provided on the uppermost metal layer in the peripheral circuitry area PERI, the upper metal pattern 1372a having the same shape as the lower metal pattern 1273a in the peripheral circuitry area PERI.

[0188] Lower bonding metals 1271b and 1272b can be provided on the second metal layer 1240b in the word line bonding area WLBA. In an exemplary embodiment of the inventive concept, in the word line bonding area WLBA, the lower bonding metals 1271b and 1272b in the peripheral circuit area PERI can be electrically connected to the upper bonding metals 1371b and 1372b in the cell area CELL via Cu-to-Cu bonding.

[0189] Furthermore, in the bit line bonding area (BLBA), the non-volatile memory device 1000 may include an upper metal pattern 1392 provided on the uppermost metal layer in the cell region (CELL) to correspond to a lower metal pattern 1252 provided on the uppermost metal layer in the peripheral circuit region (PERI), the lower metal pattern 1252 having the same cross-sectional shape as the lower metal pattern 1252 in the PERI. Contacts may not be formed on the upper metal pattern 1392 provided on the uppermost metal layer in the cell region (CELL).

[0190] In an exemplary embodiment of the inventive concept, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern formed in the uppermost metal layer of one of the cell region (CELL) and the peripheral circuit region (PERI) can be formed in the uppermost metal layer of the other. Contacts may not be formed on the reinforcing metal pattern.

[0191] A non-volatile memory device according to an exemplary embodiment of the inventive concept can perform a primary read operation using a default read level and an OVS read operation using on-chip valley search. A controller controlling the non-volatile memory device may include a predefined table PDT and an OVST to correct read failures. The predefined table PDT is a pre-defined read level offset table with reservations, and can be referenced when a read failure occurs and can be used to change the read level. The OVST is a table in which the OVS read operation is converted into a read level offset depending on the development time of each valley location, and may include the product of the number of valleys (N) searched by the OVS read operation and the number of programming states (M). For example, when the number of TLC valley search detections is 5, N is 5 and M is 7. The OVST is a table pre-formed in the evaluation step of the non-volatile memory device (e.g., NAND flash memory). In a first step, a table of detection offsets relative to development time is formed. In a second step, a table of development time offsets relative to read level offsets is formed. In the third or final step, a table of the detection status offset relative to the read level is formed as OVST.

[0192] The OVST is stored in the controller's memory and can be used during solution operation to determine the read level of the next word line based on detection information output as a status output / obtained feature / UIB output. Predefined tables PDT and OVST included in the controller can be used after adding two level offsets to them. Alternatively, only the level offsets of the OVST can be used.

[0193] The primary read operation can be performed using the default read level until a read failure occurs. Conversely, when a read failure occurs, an OVS read operation can be performed, along with corresponding read retry and recovery operations. The OVS read operation can include a first read step that searches for OVS detection based on cell counts, and a second read step that modifies the actual evolution time based on the searched detection and reads the modified actual evolution time.

[0194] In a reading method for a non-volatile memory device according to an exemplary embodiment of the inventive concept, an OVS read operation using only on-chip valley search can be activated during a read retry operation following a read failure. When the read operation passes through the optimal development time searched by the OVS read operation during the read retry operation, after the read operation is completed, OVS detection information corresponding to the development time passed by the read operation can be output as a status output / obtained feature / UIB. In an exemplary embodiment of the inventive concept, the development time can be converted into a read level offset corresponding to the OVS detection information by a pre-formed OVST, and the read level offset information can be stored by adding PDT information and OVST output information to a historical read level table. In an exemplary embodiment of the inventive concept, in a subsequent word line read operation, the read operation can be performed at a historical read level updated to the first PDT information and OVST information. In this case, the OVS read operation is not activated. Then, when a read failure occurs at a historical read level in a subsequent word line read operation, the read operation can be performed using the second PDT information. In this case, the OVS read operation can be reactivated.

[0195] In the storage device and its reading method according to exemplary embodiments of the inventive concept, in the current read operation, an optimal valley position can be searched in a first read step, and data can be read in a second read step. Information about the searched OVS valley position is then output as a status output or a feature is obtained. In subsequent read operations, the storage device can use the OVS position information output in the previous read operation, along with a pre-formed table, to determine the next read level.

[0196] In the storage device and storage device reading method according to exemplary embodiments of the inventive concept, location information can be obtained through development time after a search valley in the data recovery process. After the search valley, the location information can be output as a status output or a feature can be obtained, and a conversion table of development time relative to reading level can be pre-formed to correct the reading level.

[0197] In the storage device and the method for reading the storage device according to the exemplary embodiments of the inventive concept, since a UECC is issued and the UECC is then used only as a defense code, the reading time can only be increased when the first defense code is entered, and the user's reading time can be increased without increasing the reading time.

[0198] In the storage device and the method for reading the storage device according to the exemplary embodiments of the inventive concept, the on-chip valley search can be used for the recovery process only after UECC is issued. Furthermore, the table for converting the on time to the read level can be used as a correction means, and the read operation for data recovery can be performed only once.

[0199] As described above, according to an exemplary embodiment of the inventive concept, OVS detection information can be reflected at an optimal read level to perform a read operation to prevent performance degradation while ensuring reliability.

[0200] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that modifications and variations may be made thereto without departing from the scope of the inventive concept as set forth in the appended claims.

Claims

1. A controller, comprising: Control pins are used to provide control signals to non-volatile memory devices; The buffer memory is configured to store the first table, the second table, and the third table; as well as An error correction code (ECC) circuit is configured to correct errors in the first data read from the non-volatile memory device according to a first read command. The first table stores the first offset information. The second table stores the second offset information, and The third table stores the third offset information, which corresponds to the historical read level and is determined by the first and second offset information. When the error in the first data cannot be corrected by the error correction code (ECC) circuit, the non-volatile memory device performs an on-chip valley search operation according to a second read command. The detection information of the on-chip valley search operation is received according to a specific command, and second offset information corresponding to the detection information is generated.

2. The controller according to claim 1, wherein, The first offset information includes read level offset information based on the programmed elapsed time.

3. The controller according to claim 1, wherein, The detection information includes information corresponding to the development time of the on-chip valley search operation, and The second offset information includes read level offset information corresponding to the development time.

4. The controller according to claim 1, wherein, The historical read level includes the default read level for normal read operations or historical read operations.

5. The controller according to claim 1, wherein, When an external read request is received, determine whether to perform a normal read operation or a historical read operation.

6. The controller according to claim 1, wherein, The specific commands include commands to obtain characteristics.

7. The controller according to claim 1, wherein, The control signals include the Command Latch Enable (CLE) signal, the Address Latch Enable (ALE) signal, the Chip Enable (CE) signal, the Write Enable (WE) signal, the Read Enable (RE) signal, and the DQS signal. The non-volatile memory device performs read operations by latching commands or addresses based on the CLE and ALE signals at the edge of the WE signal, and If the read operation based on the on-chip valley search operation fails, an off-chip valley search operation is performed.

8. A storage device, comprising: Non-volatile memory devices; and A controller, connected to a control pin, exchanges command latch enable (CLE), address latch enable (ALE), chip enable (CE), write enable (WE), read enable (RE), and DQS control signals with the non-volatile memory device via the control pin. The controller is configured to read data from the non-volatile memory device. The non-volatile memory device performs read operations by latching commands or addresses on the edge of the WE signal based on the CLE and ALE signals. The non-volatile memory device performs a normal read operation in response to a first read command received from the controller, performs an on-chip valley search operation in response to a second read command received from the controller, and outputs detection information of the on-chip valley search operation to the controller in response to a specific command received from the controller. When data read from the non-volatile memory device fails to pass through the error correction code (ECC) circuit, the controller sends the second read command to the non-volatile memory device. The on-chip valley search operation includes a first readout operation corresponding to different development times, and a second readout operation using the development time selected based on the result of the first readout operation.

9. The storage device according to claim 8, wherein, The detection information includes detection status information corresponding to the selected development time.

10. The storage device according to claim 9, wherein, In response to the specific command, the detection status information is sent to the controller via at least one data line.

11. The storage device according to claim 8, wherein, The on-chip valley search operation is performed on at least one of the multiple states of the storage cell.

12. The storage device according to claim 8, wherein, Perform the on-chip valley search operation on all states of the storage unit.

13. The storage device according to claim 12, wherein, Select the detection case corresponding to all states from multiple bit pages corresponding to a single word line.

14. The storage device according to claim 12, wherein, The detection status corresponding to the development time of the on-chip valley search operation corresponds one-to-one with the state of the storage unit.

15. A method for reading a non-volatile memory device, the method comprising: In response to the first read command, a normal read operation is performed based on the default read level; In response to the second read command, perform an on-chip valley search operation; as well as The detection information of the on-chip valley search operation is output in response to a specific command. Specifically, when data read from the non-volatile memory device fails to pass through the error correction code (ECC) circuit, the non-volatile memory device receives the second read command. The execution of the on-chip valley search operation includes: Perform multiple readout operations during the development time corresponding to different detection scenarios; and A single read operation is performed using the development time selected based on the results of the multiple read operations.

16. The reading method according to claim 15, wherein, The default read level varies depending on the detection information.

17. The reading method according to claim 15, wherein, The specific commands include commands to obtain characteristics.

18. The reading method according to claim 15, further comprising: Store detection information corresponding to the selected development time; as well as The detection information is output through multiple data lines.

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