Screening method and apparatus for detecting deep trench isolation and SOI defects

Abstract

A test method and apparatus for testing an integrated circuit device (100) having a dedicated ground bias pad (121) connected to a well drive ground pad (122) by a high voltage electrostatic discharge clamp circuit (123) applies a first voltage to the dedicated ground bias pad to bias a wafer substrate (101) while simultaneously applying a second voltage to the well drive ground pad to bias the well region (103), wherein the first voltage and the second voltage generate a stress voltage across a buried insulator layer (102, 105) in the integrated circuit device such that screening tests can be performed to screen for defects (106) in the buried insulator layer by measuring leakage current.

Description

Technical Field

[0001] This invention generally relates to the field of semiconductor devices. In one aspect, the invention relates to defect testing of high-performance integrated circuit devices. Background Technology

[0002] Deep trench isolation (DTI) structures are well-known isolation structures used in semiconductor devices to isolate laterally adjacent regions of a substrate, epitaxial layer, or well from each other. DTI structures are typically formed by first etching deep trenches into the substrate or etching through the epitaxial layer into the substrate. Once formed, the trenches are typically lined with one or more insulating layers (e.g., oxide) and then filled with a conductive material (e.g., polysilicon) to provide a conductive path from the surface to the underlying substrate. Other types of isolation structures include buried oxide (BOX) layers formed between the underlying wafer substrate and the overlying substrate, epitaxial layer, or well. In such isolation structures, the insulating layer may be formed from stress-free oxide with foreign particles or cracks that create defects in the insulating layer. For example, cracks in a DTI structure create empty regions that are subsequently filled with conductive polysilicon, thereby creating an unwanted conductive path between the electrically isolated device and substrate ground. Defect problems may also exist in the absence of issues other than short circuits. For example, another type of defect may arise when a localized reduction in the thickness of the DTI oxide layer effectively lowers the breakage voltage of the isolation barrier. Similar defects can occur when buried oxide layers are formed in semiconductor-on-insulator (SOI) substrates. While surface-level defects in DTI structures can be observed through visual inspection, this method is unsuitable for production purposes and cannot identify underlying insulator defects in the substrate. Such undetected defects pose quality risks because existing device testing methods cannot detect buried defects in the underlying DT and SOI structures. In addition to quality risks, undetected defects also pose reliability risks, as thinner oxide failures may eventually occur in the field, leading to customer dissatisfaction. As can be seen from the preceding text, existing solutions for detecting defects in DTI and / or SOI structures are extremely difficult in practice because effectively screening for buried defects in DTI and / or SOI structures while meeting the performance requirements and cost constraints of high-volume production testing of semiconductor devices and avoiding the performance and reliability issues associated with traditional testing solutions is a challenge. Summary of the Invention

[0003] According to one embodiment, a method for testing buried insulator defects in an integrated circuit device includes:

[0004] A test circuit is formed in an integrated circuit device, the integrated circuit device including a dedicated ground bias pad connected to a well drive ground pad via a high-voltage electrostatic discharge clamping circuit, wherein the dedicated ground bias pad is electrically connected to the wafer substrate in the integrated circuit device only through a conductive structure in a deep trench isolation structure and is not connected to any other circuit system on the integrated circuit device, and wherein the well drive ground pad is electrically connected to a well region in the integrated circuit device.

[0005] A first voltage is applied to the dedicated ground bias pad to bias the wafer substrate, while a second voltage is simultaneously applied to the well drive ground pad to bias the well region, wherein the first voltage and the second voltage generate stress voltages on the buried insulator layer in the integrated circuit device; and

[0006] Screening tests are performed to screen for defects in the buried insulation layer by measuring the leakage current at the trap drive ground pad or the dedicated ground bias pad.

[0007] According to one or more embodiments, the method further includes shorting the dedicated ground bias pad to the sink drive ground pad after performing the test.

[0008] According to one or more embodiments, forming the test circuit includes forming a single well drive ground pad, the single well drive ground pad being electrically connected to the well region directly or through one or more semiconductor devices formed on the surface of the well region.

[0009] According to one or more embodiments, the stress voltage is greater than the absolute maximum rating of the application specification of the integrated circuit device and less than the breakdown voltage of the buried insulating layer.

[0010] According to one or more embodiments, applying the first voltage includes applying a negative voltage of at least -40V to the dedicated ground bias pad to bias the wafer substrate.

[0011] According to one or more embodiments, applying the second voltage includes applying a voltage approximately between +5V and -5V to the well drive ground pad to bias the well region.

[0012] According to one or more embodiments, the screening test includes measuring the leakage current at the well drive ground pad to screen for defects in the buried insulator layer formed between the wafer substrate and the well region.

[0013] According to one or more embodiments, the screening test includes measuring the leakage current at the well drive ground pad to screen for defects in the insulating liner layer formed between the conductive structure and the well region in the deep trench isolation structure.

[0014] According to another embodiment, an apparatus includes:

[0015] A semiconductor-on-insulator (SOI) substrate, the SOI including device regions disposed on the surface of the SOI substrate and isolated from each other by a deep trench isolation structure extending from the surface of the SOI substrate to an underlying semiconductor substrate, the underlying semiconductor substrate being separated from the SOI substrate by a first buried insulating layer;

[0016] A first group of semiconductor devices, wherein the first group of semiconductor devices is formed in each device region on the surface of the SOI substrate; and

[0017] The test circuit entry point, supported by the SOI substrate, includes a dedicated semiconductor substrate bias terminal connected to one or more ground terminals via a high-voltage electrostatic discharge clamping circuit.

[0018] The dedicated semiconductor substrate bias terminal is electrically connected to the semiconductor substrate through at least one conductive structure in the deep trench isolation structure, and

[0019] One or more of the ground terminals are directly or electrically connected to the device region in the SOI substrate, either directly or through the first set of semiconductor devices.

[0020] According to one or more embodiments, the test circuit input includes:

[0021] A first conductive interconnect path electrically connects the semiconductor substrate to the dedicated semiconductor substrate bias terminal; and

[0022] A second conductive interconnect path electrically connects the device area to the one or more ground terminals.

[0023] According to one or more embodiments, the first buried insulating layer includes a buried insulating layer formed between the semiconductor substrate and the SOI substrate in which the device region is disposed.

[0024] According to one or more embodiments, the first buried insulating layer includes an insulating pad layer formed between a first conductive structure in a first deep trench isolation structure and the SOI substrate forming the device region.

[0025] According to one or more embodiments, the high-voltage electrostatic discharge clamping circuit includes a combination of transistors and diodes that provide electrostatic discharge protection for the first set of semiconductor devices formed on the surface of the SOI substrate.

[0026] According to one or more embodiments, the device further includes a conductive path that forms an electrical short circuit between the bias terminal of the dedicated semiconductor substrate and the one or more ground terminals.

[0027] According to one or more embodiments, a first voltage supplied to a bias terminal of the dedicated semiconductor substrate by a first external probe biases the semiconductor substrate, and a second voltage supplied to the one or more ground terminals by a second external probe biases the SOI substrate, thereby generating a high-stress voltage on the first buried insulator layer in the device, the high-stress voltage being greater than the absolute maximum rating for the application specifications of the device and generating a leakage current measurable at the one or more ground terminals to detect defects in the first buried insulator layer.

[0028] According to one or more embodiments, the high-voltage electrostatic discharge clamping circuit includes a 65V+ electrostatic discharge clamp.

[0029] According to one or more embodiments, the high-voltage electrostatic discharge clamping circuit protects the buried insulating layer in the device from electrical stress by discharging electrostatic discharge between the bias terminal of the dedicated semiconductor substrate and the one or more ground terminals.

[0030] According to another embodiment, a method for manufacturing and testing a semiconductor device includes:

[0031] A semiconductor-on-insulator (SOI) layer is formed on a wafer substrate;

[0032] A device region is formed in the SOI layer;

[0033] A deep trench isolation structure is formed around the device region, extending from the surface of the SOI layer to the wafer substrate;

[0034] A test circuit is formed on the semiconductor substrate, the test circuit comprising:

[0035] A first set of interconnects and a second set of interconnects, the first set of interconnects and the second set of interconnects being electrically connected to the device region and the wafer substrate, respectively.

[0036] A high-voltage electrostatic discharge clamping circuit, wherein the high-voltage electrostatic discharge clamping circuit connects the first set of interconnects and the second set of interconnects to protect the device area from electrostatic discharge; and

[0037] The test circuit is used to test and detect defects in the buried insulating layer of the semiconductor device.

[0038] According to one or more embodiments, the method further includes shorting the first set of interconnects and the second set of interconnects after the test is performed.

[0039] According to one or more embodiments, forming the test circuit includes forming the first set of interconnects as having a dedicated ground bias pad electrically connected to the wafer substrate through a conductive structure in the deep trench isolation structure.

[0040] According to one or more embodiments, forming the test circuit includes forming the second set of interconnects as including one or more ground bias pads electrically connected to the SOI layer through the device area.

[0041] According to one or more implementation methods, the test includes:

[0042] A first voltage is applied to the dedicated ground bias pads to bias the wafer substrate, while a second voltage is applied to the one or more ground bias pads to bias the SOI layer, wherein the first voltage and the second voltage generate a strong negative stress voltage on the buried insulator layer; and

[0043] Screening tests are performed to screen for defects in the buried insulation layer by measuring the leakage current at one or more ground bias pads.

[0044] According to one or more embodiments, applying the first voltage includes applying a negative voltage of at least -60V to the dedicated ground bias pad to bias the wafer substrate.

[0045] According to one or more embodiments, applying the second voltage includes applying a voltage of approximately 0V to the one or more ground bias pads to bias the SOI layer.

[0046] According to one or more embodiments, the method further includes dicing the wafer substrate into individual semiconductor devices that are encapsulated and packaged. Attached Figure Description

[0047] The invention and its numerous objectives, features and advantages will be understood when the following detailed description of preferred embodiments is considered in conjunction with the following figures.

[0048] Figure 1 A first cross-sectional view of an integrated circuit on a semiconductor-on-insulator (SOI) wafer according to a selected embodiment of the present disclosure is depicted, the SOI wafer having component devices formed by a buried insulating layer, which can be screened for defects by applying a stress voltage.

[0049] Figure 2A wafer-level test system for multiple integrated circuit dies is described, the wafer-level test system having die test circuitry connected to screen for defects in a buried insulator layer formed in an underlying substrate.

[0050] Figure 3 A simplified flowchart is depicted to illustrate the process flow of detecting defects in a deep trench isolation layer by applying a stress voltage to the deep trench isolation layer using a dedicated ground bias pad and a trap drive ground pad connected by a high-voltage ESD clamp, according to a selected embodiment of the present disclosure.

[0051] Figure 4 A simplified plan view of the wiring connections of a first packaged integrated circuit device according to a selected embodiment of the present disclosure is depicted, wherein a dedicated ground bias pad and a well drive ground pad are connected to the same package pin.

[0052] Figure 5 A simplified plan view of wiring connections for a second packaged integrated circuit device according to a selected embodiment of the present disclosure is depicted, wherein a dedicated ground bias pad and a well drive ground pad are connected to a package mark. Detailed Implementation

[0053] Methods and apparatus for manufacturing and testing defects in buried insulator layers located in DTI and / or SOI structures of semiconductor devices are described. As disclosed, the apparatus for screening device-induced defects in semiconductor devices includes one or more dedicated ground bias pads connected to one or more well drive ground pads via a high-voltage ESD clamp, allowing stress voltage to be applied to the buried insulator layer using die test circuitry. Specifically, the one or more dedicated ground bias pads are manufactured and configured to provide a conductive path to the underlying semiconductor wafer substrate, either directly or through a conductive layer in one or more DTI structures. Furthermore, the one or more well drive pads are manufactured and configured to provide a conductive path to the SOI substrate (e.g., a global well formed on buried oxide), an epitaxial layer, or a well, either directly or through one or more surface circuits on the SOI substrate. With a protective high-voltage electrostatic discharge (ESD) clamp connected between a dedicated ground bias pad and a well drive pad, a stress voltage can be applied to the buried insulator layer in a DTI structure and / or BOX structure by applying a first voltage (e.g., 0V) to the well drive ground pad to bias the SOI substrate / well, while simultaneously applying a second stress voltage (e.g., -60V) to the dedicated bias pad to bias the wafer substrate via a deep trench conductive structure. When the stress voltage is applied, defect testing may include or involve measuring the leakage current at the well drive bias pad using a targeted probe without any additional interconnects, inserts, or dedicated probe test cards. However, measurement via the bias pad may be a contingency measure, for example, using a dedicated probe test card. In the selected embodiment, a negative DTI oxide stress voltage of at least -40V (and preferably at least approximately -60V) is applied for a predetermined duration (e.g., 10ms) such that any leakage current measured at the well drive ground bias pad can identify the location of any defects. However, the stress voltage will depend on the voltage capacity of the buried insulator layer. While the target is to apply a stress of at least -60V, the selected embodiment can apply a smaller stress voltage (e.g., -40V) due to limitations of the test equipment. Therefore, other techniques may require different stress voltages. Parasitic currents in the wafer substrate do not cause contamination by measuring the leakage current at the well-driven ground bias pad. Furthermore, current measurement using the well-driven ground bias pad can identify the individual wafer die where the detected defect is located. Therefore, the disclosed embodiments can be used to provide complete test coverage for all buried insulating layers, BOX layers, or other substrate dielectric layers in a DTI structure. In the selected embodiment, after defect testing and after die dicing during encapsulation, the dedicated substrate bias pad is disabled or shorted to the well-driven ground bias pad (e.g., by connecting it to the same package pin or package mark using a bonding wire).

[0054] Various illustrative embodiments will now be described in detail with reference to the accompanying drawings. As described below, the disclosed embodiments can be arranged and designed in a wide variety of different configurations. Therefore, the detailed description of the various embodiments illustrated below is not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. While various details are set forth in the following description, it should be understood that the invention can be practiced without these specific details, and many specific implementation decisions can be made with respect to the invention described herein to achieve specific objectives of the device designer, such as compliance with processing techniques or associated design constraints that vary depending on the implementation. While such research and development work may be complex and time-consuming, it is merely a routine task and daily work for those of ordinary skill in the art who will benefit from this disclosure. Furthermore, various aspects of the embodiments are presented in the illustrations, and unless specifically stated otherwise, the illustrations are not necessarily drawn to scale. Moreover, the features, advantages, and characteristics described in the invention can be combined in any suitable manner in one or more embodiments. In view of the description herein, those skilled in the art will recognize that embodiments can be practiced without one or more of a particular feature or advantage of a specific embodiment. In other instances, additional features and advantages that are not present in all embodiments may be identified in some embodiments. For example, selected aspects are depicted with reference to simplified cross-sectional views of a semiconductor device, but not including every device feature or geometry so as not to limit or obscure the invention. It should also be noted that throughout this detailed description, certain materials will be formed and removed to fabricate the semiconductor structure. Unless the specific procedures for forming or removing such materials are described in detail below, those skilled in the art will expect to use conventional techniques to grow, deposit, remove, or otherwise form such layers to an appropriate thickness. Such details are well-known and are not to be considered necessary to teach those skilled in the art how to make or use the invention.

[0055] To provide additional details for improving the contextual understanding of this disclosure, reference is now made to... Figure 1 , Figure 1A first cross-sectional view of an integrated circuit 100 on a semiconductor-on-insulator (SOI) wafer 101-113 is depicted. The SOI wafer 101-113 has component devices formed by buried insulating layers 102, 104A-B. These component devices are not easily accessible using conventional screening tests, but defects can be tested by applying a stress voltage to the buried insulating layers using the disclosed embodiments. As shown, the integrated circuit 100 includes an n-type metal-oxide-semiconductor (nMOS) field-effect transistor device formed on the surface of the SOI substrate 103-113, having interconnecting metallized conductors (MC) and / or silicide layers to connect the source, drain, and substrate contact regions and the conductive gate, as shown. For example, each nMOSFET device may have a gate electrode (G1, G2, G3, G4) formed above SOI substrate 103-113 and separated from SOI substrate 103-113 by a gate dielectric (not shown). Each gate electrode may include one or more sidewall spacers disposed at one end of the gate electrode and may be located close to at least a first source / drain region (e.g., n+ region) formed in the SOI substrate 103-113 to define a channel region below the gate electrode.

[0056] The depicted integrated circuit 100 is shown formed on or as part of SOI wafer substrates 101-113, which can be formed as bulk semiconductor substrates or other substrates, wherein one or more additional semiconductor layers and / or well regions are formed using epitaxial semiconductor growth and / or selective doping techniques, which will be described in more detail below. For example, SOI wafer substrates 101-113 can be semiconductor-on-insulator (SOI) type substrates, comprising wafer substrate 101, buried oxide or insulating layer 102, and p-type semiconductor epitaxial substrate layer 103. Wafer substrate 101 can be provided as a processed wafer layer formed from a material having a first conductivity type impurity (e.g., n-type wafer substrate 101) at a predetermined doping level and depth by using any suitable dopant type and / or concentration. On the processing wafer substrate 101, an insulating layer 102 and a thin substrate semiconductor seed layer (e.g., a 1.5 μm thick p-type substrate layer on top of the insulating layer 102) can be formed to provide a seed layer for the thick epitaxial growth of the p-type semiconductor substrate layer 103, thereby forming the initial SOI substrate structure 103. Alternatively, the SOI wafer substrate structures 101-103 can be formed by bonding a donor wafer to the processing wafer. Using this technique, at least a portion of the n-type wafer substrate 101 and the dielectric layer 102 is provided as a processing wafer, which is bonded or otherwise attached to a donor wafer including portions of the dielectric layer 102 and the p-type semiconductor layer 103, which may be wholly or partially formed as a p-type epitaxial layer. Alternatively, and depending on the type of transistor being manufactured, the semiconductor substrate can be implemented as a bulk silicon substrate, single-crystal silicon (doped or undoped), an SOI substrate, or any semiconductor material, including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors or any combination thereof. For the selected bulk silicon substrate embodiment, a buried insulating layer 102 can be formed by implanting a dielectric material (e.g., silicon oxide) into the substrate 101 at a predetermined energy and depth.

[0057] In SOI wafer substrates 101-103, isolation structures surrounding active device regions, either alone or in combination with patterned shallow trench isolation (STI) structures 110-113, include deep trench isolation (DTI) structures 104A, 104B and / or buried insulating layers 102. As will be understood, trench openings can be etched using any desired technique and at least partially filled with one or more dielectric (and semiconductor) materials. For example, deep trench isolation structures 104 can be formed in SOI wafer substrates 101-103 to surround and isolate various well regions and active regions in integrated circuit device 100. In selected embodiments, deep trench isolation structures 104 are formed by etching through the underlying p-epi layer 103 and buried insulating layers 102 to reach deep trench openings in the underlying n-wafer substrate 101 using one or more etch masks (e.g., by applying anisotropic etching to a patterned trench etch mask layer). Once the deep trench openings are formed, they are typically lined with one or more insulating layers (e.g., oxides), and then the center is filled with heavily doped n-type polysilicon 105 to provide a conductive contact path from the surface to the underlying substrate 101. Similarly, shallow trench openings can be formed by patterning and etching shallow trench openings in the upper surface of the p-epi layer 103, filling the openings with one or more insulating dielectric layers, and then polishing or planarizing the filling layers to the substrate surface to form shallow trench isolation (STI) structures 110-113.

[0058] Before or after the formation of the DTI and STI structures 104, 110-113, additional wells, source / drains, and contact regions are formed in the p-epi layer 103 using any suitable patterning, masking, etching, and / or implantation steps. For example, an HV n-well region 107 can be formed in the p-epi layer 103 by implanting n-type impurities at a predetermined density and energy to define a high-voltage n-well 107 prior to the formation of the STI region, for example, by implanting p-type impurities at a predetermined density and energy to define a high voltage (PHV) 108 prior to the formation of the STI region, a second masking and selective implantation process can be applied to form p-type PHV regions 108A, 108B in the p-epi layer 103. After the formation of STI regions 110-113, additional processing steps are performed to define gate electrodes (G1-G4), which may be used in combination with one or more additional masks to selectively implant indicated p+, n+ source / drain, n+ body contact and lightly doped drain (LDD) regions in p-epi layer 103.

[0059] After forming doped regions and isolation structures in SOI wafers 101-113, electrical interconnects are formed above the wafer surface to connect to the first dedicated substrate bias pad 121 (GND_SUB pad) and the well drive pad 122 (GND pad). As will be understood, the electrical interconnects may be defined as silicide layers and interconnect metallized conductors (MCs) formed of one or more metal materials or layers, such as ohmic metal layers, transition layers, and conductive layers. Formed in a manner of stacking dielectric layers (not shown), the metal layers electrically connect the conductive DTI polycrystalline contacts 105A, 105B (and wafer substrate 101) to the first dedicated ground substrate bias pad 121, and also electrically connect the SOI substrates 103-113 to the well drive ground pad 122. Additionally, a high-voltage ESD clamping circuit 123 is connected between the first dedicated ground substrate bias pad 121 (GND_SUB pad) and the well drive ground pad 122 (GND pad) to prevent die damage during a final ESD event between the aforementioned pads without interrupting the significant stress voltage Vstress applied between pads 121 and 122, which is necessary for effective screening. Finally, one or more circuits and connection elements 124 are formed between the well drive ground pad 122 and the semiconductor surface devices formed on the SOI substrates 103-113, thereby enabling the well drive ground pad 122 to be selectively connected to the SOI substrates 103-113, either directly or via one or more surface circuits on the SOI substrate. As disclosed herein, the circuits and connection elements 124 may be included in a packaged integrated circuit device to provide customers with functional and electrical characteristics, including providing electrical connections from the well drive ground pad 122 to bias into the well region within the device.

[0060] The connection of the depicted dedicated ground substrate bias pad 121 and well drive ground pad 122 provides a test circuit topology for custom testing to detect defects in buried insulating layers located within integrated circuits, such as DTI insulating layer 104 and / or SOI insulating layers (e.g., buried oxide layers). To perform defect testing, a stress voltage Vstress is applied or forced onto the pads 121, 122, thereby pressurizing each oxide 104A, 104B of the DTI structure oxide, allowing measurement of any leakage current to detect potential defects in the DTI structure. In the selected embodiment, the stress voltage is not merely a voltage sufficient to generate leakage current, but rather a voltage sufficiently high to be applied to the buried insulating layer to translate potential defects into faults recorded in the leakage current measurement.

[0061] While any suitable stress voltage with voltage capacity appropriate to the application use case and technology can be applied, in the selected embodiment, the stress voltage is applied via a deep trench conductive structure by applying a first voltage (e.g., 0V) to the well drive ground pad 122 to bias the SOI substrate / wells 103-108, while simultaneously applying a second voltage (e.g., at least -40V, or preferably at least -60V) to a dedicated ground bias pad 121 to bias the wafer substrate. Polycrystalline contacts 105A, 105B and the n-wafer substrate 101 are driven to the second strong negative voltage by providing the dedicated ground pad 121. And wells 103, 107-108 are driven to a first relatively small voltage (e.g., 0V) by supplying the first voltage to the ground pad 122, which is connected by circuitry and connection elements 124, to bias the wells (devices) on the SOI substrates 103-109. Therefore, the circuit and connection element 124 may include one or more FET switches that are controlled to appropriately select the drive pad 122 for biasing the SOI substrate 103 to a second voltage (e.g., approximately 0V).

[0062] In the selected embodiment, when the ground pad 122 is used as a selective drive pad to maintain all wells at a first voltage of 0V, the dedicated ground pad 121 can be used to drive the wafer substrate 101 to a stress voltage in the range of -40V to -60V or possibly +40V to +60V, if the circuitry or basic technical conditions permit. In other embodiments, the wafer substrate 101 can be driven to a stress voltage between -45V and -65V via the dedicated ground pad 121, wherein the ESD clamp 123 is connected to protect the integrated circuit 100 from eventual ESD events during wafer testing and / or wafer transport. However, it should be understood that both positive and negative biases can be applied between the bias pad and the drive pad. For example, some techniques can manage bidirectional stresses with the same voltage magnitude.

[0063] When referring to the “dedicated” ground pad 121, it should be understood that the substrate 101 and polycrystalline contacts 105A, 105B are biased by a pad not shared with the rest of the circuitry of the integrated circuit 100, except for the ESD clamping protection circuitry 123. Therefore, for electromagnetic compatibility and / or ESD protection reasons, the network is typically shorted to ground at the package level after die manufacturing, and according to this disclosure, the network should be isolated from the dedicated ground pad 121. This prevents the injection of leakage current through the dedicated ground pad 121 into the connected circuitry or devices, which would distort leakage current measurements used for defect detection. Additionally, it prevents the potential biasing of “on-die” devices with stress voltage, which could damage the devices.

[0064] By applying a stress voltage Vstress to pads 121 and 122, the leakage current I is measured when a stress voltage (-40 to -60V) is forcibly applied to the dedicated ground pad GND_SUB pad 121. LEAKAGE Any defects in the DTI insulator 104A can be detected. For example, if a defect 106 is present in the DTI insulator layer 104A, it can be detected by measuring the leakage current using a measurement probe applied to the ground pad 122 or the dedicated ground pad 121. Although not shown, another defect location that can be detected by measuring the leakage current is a defect in the buried oxide layer 102 that shorts or connects the n-wafer substrate 101 and the p-epi layer 103. Due to parasitic current noise that may occur at the dedicated ground pad 121 (GND_SUB pad), DTI defects can be tested and measured by applying or contacting the ground pad 122 (GND pad) with a measurement probe.

[0065] By providing direct connections to dedicated ground pads 121 and 122 for biasing the n-wafer substrate 101 and substrate well 108, stress voltages can be applied to pads 121 and 122. This allows measurement of the leakage current I flowing from ground pad 122 to dedicated ground pad 121 under the protection of the high-voltage ESD clamping circuit 123 directly connecting pads 121 and 122. LEAKAGE This supports unrestricted defect testing of buried insulating layers. Therefore, defect testing is not limited to detecting surface defects as in past visual screening tests. The test circuits and methods of the disclosed embodiments provide techniques for applying stress voltages to all buried insulators in integrated circuit (IC) products. Therefore, the disclosed embodiments can support more comprehensive leakage current testing and measurement methods than other available tests and measurements. Thus, zero-defect screening of buried oxide layer defects can be achieved. The disclosed embodiments can alternatively or additionally reduce the amount of circuitry and wafer area dedicated to built-in self-test (BIST).

[0066] Tests can be performed by using dedicated ground pad 121 and ground pad 122 as a set of probe pads to simultaneously test all devices on the wafer for buried insulator defects. Simultaneous testing can be performed in parallel. Test circuitry may include rows and columns or other interconnect schemes that cross die boundaries or otherwise minimize probe indexing time. While useful for wafer-level testing, the disclosed embodiments are scalable to perform testing at different levels of specificity. Test circuitry can be configured to perform testing on a die-by-die basis or at the mask or wafer quadrant level. After testing, the network of dedicated ground pad 121 is typically shorted to the ground network of die-level ground pad 122 for EMC and ESD reasons, as shown by dashed line 125. As will be appreciated, any suitable shorting configuration can be used, for example, by forming a conductive path that electrically shorts dedicated ground pad 121 and ground pad 122.

[0067] To better understand the selected embodiments of this disclosure, reference is now made to... Figure 2 , Figure 2 A wafer-level test system 200 for multiple integrated circuit dies is depicted, wherein a die test circuit 230 is connected to test integrated circuit 224 to screen for defects 207 in a buried insulating layer 204 formed in integrated circuit substrates 201-206. In this example, integrated circuit 208 includes a semiconductor device, such as a MOSFET (not shown) formed on the surface of SOI substrates 201-205, comprising a first wafer substrate layer 201, a buried insulating layer 202, and an epitaxial layer 203 sequentially formed to define SOI substrates 201-203. Additionally, integrated circuit 208 includes isolation structures 202, 204-205 to separate and electrically isolate active device well regions 206 from each other. Specifically, the isolation structure surrounding each active device region 206 may include a deep trench isolation (DTI) structure 204-205 formed in deep trench openings that penetrate layers 202-203 to expose a first wafer substrate layer 201 and are lined with one or more insulating layers 204 (e.g., oxide) and then filled with a conductive material 205 (e.g., doped polysilicon) to provide a conductive contact path from the surface to the underlying substrate 201. Alternatively, the isolation structure may include a buried insulating layer 202 formed between the first wafer substrate layer 201 and the epitaxial layer 203 using any suitable technique (e.g., deposition, oxidation, or implantation).

[0068] To screen for defects in buried insulators that are difficult to reach using conventional screening tests, such as DTI liner defect 207, the die test circuit 230 can be implemented to connect to a probe card of integrated circuit 208 via a dedicated substrate ground pad 221, one or more device pads 222A, 222B, and an interconnect path / circuit system on die 224 to apply a stress voltage to the buried insulator layer (e.g., buried insulator layer 202 and / or DTI oxide liner layer 204). Specifically, a stress voltage is generated with sufficient force between the conductive material layer 205 and the active device well region 206, such that the short-circuit resistance R caused by defect 207 is reduced. SHORT The conductive path on the die generates a leakage current I that can be measured by the die test circuit 230. LEAKAGE For example, all active device well regions 206 are biased by applying a first bias voltage to one or more device pads 222A, 222B, and the substrate wafer 201 and DTI structure 205 are biased to -V by simultaneously applying a second bias voltage to the dedicated substrate ground pad 221. STRESS Any leakage current measured as the sum of currents I1 and I2 measured through device pads 222A and 222B can be used to detect which die (e.g., 224) has a buried insulator defect 207 by using a pass / fail current threshold standard. As will be understood, other bias voltages can be applied. For example, depending on the application, the first bias voltage can be 0V or + / - 5V. Furthermore, the second bias voltage can be -60V, but a larger or smaller negative stress voltage can be applied. Because stress voltages are applied to pads 221 and 222, screening tests can detect defects 207 not only in the DTI pad layer 205 but also in the buried insulator layer 202.

[0069] To this end, die 224 may include a first interconnect path formed on the surface of the integrated circuit wafer to connect a dedicated substrate ground pad 221 (GND_SUB pad) to one or more of the conductive DTI polycrystalline contacts 205 and to the first wafer substrate layer 201. Additionally, die 224 may include a second interconnect path formed on the surface of the integrated circuit wafer to connect one or more device pads 222A-E (e.g., GND pad 222B) to one or more active device well regions 206. Using any suitable manufacturing process, the interconnect path may include a defined silicide layer and a connection metallization conductor (MC), said MC being formed of one or more metal materials or layers (e.g., ohmic metal layers, transition layers, and conductive layers) formed in a dielectric layer stack. In the depicted example, the active device region 206 is biased using the ground pad 222B. Furthermore, if it is necessary to bias a well that the ground pad 222B cannot effectively drive or connect to, the pad 222A can be used to measure current I1 and drive an additional well 206, thereby increasing screening coverage. In the depicted example, since pads 222A-B provide sufficient bias coverage for the well, circuit pads 222C-E are not used for well driving or measurement. Therefore, pads 222C-E can have any function in the system (e.g., input, output, supply) and remain disconnected to avoid distorting leakage current measurements through all connected pads 222A-B by summing the currents I1 and I2 measured at pads 222A and 222B. However, any pad 222C-E can be used as an additional well ground pad, for example, by applying a bias voltage to the probe pins used during cell probe testing.

[0070] To protect the device on integrated circuit 208 under stress voltage, interconnect path / circuit system 224 also includes high-voltage ESD clamping circuitry 223 connected between dedicated substrate ground pad 221 and device ground pad 222B. Additional ESD protection is provided by applying stress voltage to bias the first wafer substrate layer 201 by connecting chuck 220. Preferably, chuck 220 remains unconnected during normal operation, but can be connected via an optional high-value resistor R. HI (For example, >1MΩ) Connect to ground. However, this connection of chuck 220 generates parasitic currents that, if made at the dedicated substrate ground pad 221, will interfere with the accurate measurement of leakage current. Therefore, leakage current should instead be measured at the device ground pad 222, which also allows identification of which die is leaking due to a defect in the buried insulation.

[0071] As disclosed herein, the die test circuit 230 can be implemented with any suitable probe test equipment for generating a stress voltage applied to the buried insulator layer and for measuring any resulting current indicating the presence of a defect 206 in the buried insulator (e.g., DTI pad layer 204 or buried insulator layer). For example, the die test circuit can be implemented with an automated test equipment (ATE) 210 that generates test signals supplied to the device under test (DUT) (i.e., integrated circuit 208) and also receives or measures response signals from the DUT. For this purpose, the depicted ATE 210 includes one or more first voltage generators 211, 212 for generating a first bias voltage signal (e.g., 0V) supplied to corresponding device pads 222A, 222B (GND pads). Additionally, the ATE 210 includes a second voltage generator 216 for generating a second strong negative bias voltage signal (e.g., -40V to -60V) supplied to a dedicated substrate ground pad 221 (GND_SUB pad). Alternatively, a strong positive voltage can be applied. In the selected embodiment, where this stress may exist in the automotive product and the test equipment can only generate this voltage, the negative bias voltage signal should be -40V. However, the targeted negative bias voltage can be any different stress voltage (e.g., -60V or -65V) to improve defect screening performance. As will be understood, there may be cases where ATE 210 cannot generate a second strong negative bias voltage signal. In such cases, die test circuit 230 may include an additional or separate bias voltage generator 231 connected to provide the required bias voltage signal to dedicated substrate ground pad 221. Where ATE 210 is connected to other pads 222C-222E on die 224, one or more switching circuits 213-215 in ATE 210 may be provided to disconnect pads 222C-E during probe testing for buried insulator defects. To prevent parasitic currents from distorting leakage current measurements, all DTI structures 204-205 are connected to a dedicated substrate bias pad 221 (GND_SUB pad), which is not connected to any other circuitry except the ESD clamping circuit 223. In the selected embodiment, the ESD clamping circuit 223 provides sufficient ESD protection (e.g., 65V) to prevent leakage during testing with stress voltages (e.g., |Vclamp|>|Vstress|) and to prevent voltages from exceeding the damage level of the connected device (e.g., |Vclamp|<|Vbreakdown|). However, it should be understood that for extended stress, the ESD clamp 223 can provide stronger protection (e.g., 90V). Conversely, conventional low-voltage ESD clamps do not allow for sufficient screening voltages.In the selected embodiment, it is possible to include multiple separate dedicated ground bias pads for biasing the substrate 201 at the unit probe, but the separate dedicated ground biases should be reconnected at the package level. For example, four dedicated ground bias pads may be shorted together at the die level, one on each side of the die, to provide a connection to the solid ground substrate of the pin of the individual probe.

[0072] To provide further details to improve understanding of selected embodiments of this disclosure, reference is now made to... Figure 3 , Figure 3 A simplified flowchart illustrating the process flow for manufacturing and testing a semiconductor device to detect defects in a buried isolation layer formed within the semiconductor device is depicted. After the process begins at step 301, a series of manufacturing steps are performed at step 302 to manufacture a wafer comprising a plurality of dies, wherein each die includes one or more dedicated ground bias pads connected to one or more well drive ground pads via a high-voltage ESD clamping circuitry system.

[0073] Regarding manufacturing step 302, there can be many preliminary steps for preparing the wafer substrate for subsequent processing. Any bulk or composite substrate can be used, but in selected embodiments, the SOI wafer substrate is fabricated to include an underlayer wafer substrate, a buried insulating layer, and an epitaxial semiconductor layer. In the SOI wafer substrate, active device regions are defined and delineated in the epitaxial semiconductor layer, which has a deep trench isolation structure extending downward from the surface of the SOI wafer substrate to the underlayer wafer substrate. As formed, each deep trench isolation structure is formed in a deep trench opening to include one or more outer insulating pad layers and a conductive (e.g., doped polycrystalline) inner layer in direct electrical contact with the underlayer wafer substrate. On the active device regions, additional steps are performed in step 302 to fabricate semiconductor devices, such as additional well regions, gate electrodes, and associated source / drain regions, on the surface of the SOI wafer substrate. For example, the well regions can be formed by doping the epitaxial semiconductor substrate layer using any suitable dopant implantation procedure to define n-type or p-type well regions. Furthermore, gate electrodes can be selectively formed by depositing, patterning, and etching conductive polysilicon layers formed on one or more gate dielectric layers, and then used with one or more selective masks to implant source and / or drain regions. As will be understood, other device regions, such as shallow trench insulators or resistors, can also be formed at this time. The process at step 302 also forms interconnect paths with defined silicide layers and interconnect metallized conductors (MCs), which are formed in a dielectric layer stack to directly electrically connect to contact pads formed in the uppermost metal layer. These pads include one or more well-driven ground pads connected to one or more dedicated ground bias pads via ESD clamping circuitry. During manufacturing, these pads are not connected to any other circuitry on the die except for the ESD clamping protection circuitry. As a result of step 302, an integrated circuit device with multiple I / O and reference voltage pads, including dedicated ground bias pads and well-driven ground pads, is formed.

[0074] In step 303, a switching circuit system in the integrated circuit device can be used to selectively switch or connect the well drive ground pad to the surface semiconductor device on the SOI wafer substrate, and further switch or connect it to the bottom well region. This step disconnects other I / O and reference voltage pads from the surface semiconductor device access, for example, by disconnecting any connection switches to other I / O and reference voltage pads. Alternatively, connection switches can be closed to connect each well drive ground pad to its corresponding well region. By correctly selecting and closing the connection switches, a set of well drive ground pads can be connected to most or all of the bottom wells. The selective connection process at step 303 can take into account any circuit elements (e.g., forward bias diodes, Zener diodes, or resistors) in the path between the well and the well drive ground pad, depending on their impact on the well biasing result. In addition to using switching circuitry in the integrated circuit device, or as an alternative, the selective switching / connection at step 303 can be achieved by using control switches in the ATE or die test circuitry to disconnect any pads other than the well drive ground pad and the dedicated ground bias pad from receiving bias voltage. For example, if the die does not have a supply voltage during testing, any potential application of bias voltage must be driven from outside the die, for example, by using a control switch in the ATE.

[0075] In step 304, the test circuit is connected to the integrated circuit device to apply a stress voltage to the buried insulator (e.g., a deep trench isolation (DTI) structure and / or a buried oxide layer). To apply the stress voltage, a first voltage (e.g., 0V) is applied to the well drive ground pad to bias the bottom well region in the SOI wafer substrate / well via the semiconductor surface mount device. Simultaneously, a second stress voltage (e.g., -60V) is applied to a dedicated ground bias pad to bias the bottom wafer substrate via the conductive polycrystalline inner wall / layer in the DTI structure. With a high-voltage ESD clamp connected between the well drive ground pad and the dedicated ground bias pad, the surface semiconductor is protected from electrostatic discharge events. In selected embodiments, the test circuit can be implemented as an automated test equipment probe card capable of applying a negative stress voltage of at least -60V to -65V, such that the bottom well region is biased to 0V and the conductive layer in the DTI structure is biased to at least -60V. Additionally, as described above, the test circuit may include a reference voltage generator, which is applied via one or more switching circuits to bias the well and DTI structure via dedicated ground bias pads and well drive pads, respectively. During step 304, a first voltage (e.g., 0V or + / -5V) may be applied using one or more first probe pads and corresponding interconnects from the test circuit to bias the well drive pads. Additionally, a second strong negative voltage (e.g., -65V) may be applied using second probe pads and corresponding interconnects from the test circuit to bias the wafer substrate region.

[0076] In step 305, leakage current is measured after stress voltage is simultaneously applied to the dedicated ground bias pad and the well drive pad, or simultaneously, to screen for one or more buried insulator defects in the deep trench isolation structure and / or buried oxide region. In a selected embodiment, the leakage current may be measured as the sum of the currents flowing through the well drive pads. As described above, the test circuit may include one or more current measurement circuits for measuring the current flowing through each well drive pad. As disclosed herein, the current measurement at step 305 may include several operations. For example, a baseline or reference leakage current value may be retrieved or established to define a baseline or reference level for integrated circuits in which no buried insulator defects are present. During step 305, one or more first probe pads and corresponding interconnects from the test circuit may be used to measure the leakage current generated by the stress voltage. The leakage current measurement data may be compared with the baseline or reference leakage current value to determine whether a buried insulator defect is present in the integrated circuit device. By tracking the leakage current value at each well drive pad, the individual die region where the defect is located can be determined.

[0077] In step 306, the dedicated ground bias pad is functionally removed from the integrated circuit device. As will be understood, this occurs only after the substrate has been biased using the ground bias pad during functional and parameter probe testing. In the selected embodiment, this can be achieved by shorting the dedicated ground bias pad to ground (e.g., a well drive pad) at the package level. As will be understood, this prevents the ability to screen for buried insulator defects in the final packaged chip because the well and wafer substrate regions cannot be separately biased.

[0078] In step 307, the testing process ends. At this point, the fabrication of the semiconductor device can continue with the dicing into individual integrated circuit dies and additional packaging steps. Of course, the sequence of actions described above can be altered to form the specific device regions and features required for any particular integrated circuit application. It should be understood that additional processing steps will be used to fabricate the semiconductor device described herein, such as nitride banding, the preparation and formation of one or more sacrificial oxide layers, shallow trench isolation regions, and the formation of various buried wells or regions. Additionally, other circuit features, such as capacitors, diodes, etc., can be formed on the wafer structure. For example, one or more sacrificial oxide formations, stripping, isolation region formation, well region formation, gate dielectric and electrode formation, extended implantation, halogen implantation, spacer formation, source / drain implantation, thermally driven or annealed steps, and polishing steps can be performed, as well as conventional back-end processing (not depicted), typically including the formation of multi-level interconnects for connecting transistors in the desired manner to achieve the desired function. Therefore, the specific sequence of steps used to complete the fabrication of the semiconductor structure can vary depending on process and / or design requirements.

[0079] To better understand the selected embodiments of this disclosure, reference is now made to... Figure 4 , Figure 4 A simplified plan view 400 of a first packaged integrated circuit device 403 is depicted, wherein a dedicated ground substrate bias pad is disabled or shorted with a well drive bias pad after defect testing during packaging. The disclosed integrated circuit device 403 includes test circuitry having a dedicated ground substrate bias pad 421 and a well drive bias pad 422 connected via an ESD clamp 423 and further connected to bias the substrate and well region of the integrated circuit device 403, respectively, during screening tests. As shown, the integrated circuit device 403 is mounted on a package mark 402 electrically isolated from package pins 401A-L, and bonding lines (e.g., 410-413) are attached to connect pads (e.g., 421, 422) to package pins 401A-L. In the illustrated embodiment, the dedicated ground bias pad 421 and the well drive bias pad 422 are shorted together by bonding lines 411, 412 connecting pads 421, 422 to the same package pin 401H. As described above, the function of ESD clamp 423 is to protect the buried insulating oxide from electrical stresses that may occur during assembly, when placing probes during probe testing, or when handling the wafer. However, once pads 421 and 422 are shorted at the package level to the same package pin 401H, ESD clamp 423 becomes ineffective.

[0080] To better understand the selected embodiments of this disclosure, reference is now made to... Figure 5 , Figure 5 A simplified plan view 500 of a second packaged integrated circuit device 503 is depicted, wherein a dedicated ground substrate bias pad is disabled or shorted to a well drive bias pad after defect testing during packaging. The disclosed integrated circuit device 503 includes test circuitry having a dedicated ground substrate bias pad 521 and a well drive bias pad 522 connected via an ESD clamp 523 and further connected to bias the substrate and well region of the integrated circuit device 503, respectively, during screening tests. As shown, the integrated circuit device 503 is mounted on a package mark 502 electrically isolated from package pins 501A-L, and bonding lines (e.g., 510-513) are attached to connect pads to package pins 501A-L. In the illustrated embodiment, the dedicated ground bias pad 521 and the well drive bias pad 522 are shorted together by bonding lines 511 and 512 connecting the pads 521 and 522 to the package mark 502, which in turn is connected to the package pin 501J via bonding line 513. Similarly, once the pads 521 and 522 are shorted to the same package pin 501J on the package mark, the protection function of the ESD clamp 523 is eliminated.

[0081] The above embodiments enable wafer-level, zero-defect screening. The test circuitry can also be configured to provide any desired test level. The test circuitry can be designed to test a limited number of buried insulators in active device areas or other components, such as components of one or more circuits, or one or more dies, for example, a set of dies corresponding to a single mask, or any other subset of wafers. These and other test levels can be implemented to meet manufacturing cost or time constraints.

[0082] It is now understood that a method and apparatus for testing buried insulator defects in an integrated circuit device have been provided. As disclosed, a test circuit is formed in the integrated circuit device, the integrated circuit device including a dedicated ground bias pad connected to a well drive ground pad via a high-voltage electrostatic discharge clamping circuit, wherein the dedicated ground bias pad is electrically connected to the wafer substrate in the integrated circuit device only through conductive structures in a deep trench isolation structure and is not connected to any other circuitry on the integrated circuit device, and wherein the well drive ground pad is electrically connected to a well region in the integrated circuit device. In a selected embodiment, the test circuit is formed with a single well drive ground pad, the single well drive ground pad being electrically connected to the well region directly or through one or more semiconductor devices formed on the surface of the well region. In the disclosed test method and apparatus, a first voltage is applied to the dedicated ground bias pad to bias the wafer substrate, while a second voltage is simultaneously applied to the well drive ground pad to bias the well region, wherein the first voltage and the second voltage generate a strong negative stress voltage on the buried insulator layer in the integrated circuit device. In a selected embodiment, the first voltage is applied as a negative voltage to the dedicated ground bias pad to bias the wafer substrate. Generally, the resulting stress voltage is greater than the absolute maximum rating of the application specifications of the integrated circuit device (e.g., absolute maximum rating) and less than the breakdown voltage of the buried insulator layer (e.g., DTI and buried oxide layer). Therefore, the absolute maximum rating of the IC is |<|Vstress|<|BV of DTI / Box|. In other embodiments, the second voltage is applied as approximately 0V to the well drive ground pad to bias the well region. In other embodiments, the second voltage of approximately + / - 5V is applied to the well drive ground pad to bias the well region. Furthermore, the disclosed test methods and apparatus screen for defects in the buried insulator layer by measuring the leakage current at the well drive ground pad or the dedicated ground bias pad. In a selected embodiment, screening tests are performed by measuring the leakage current at the well drive ground pad to screen for defects in the buried insulator layer formed between the wafer substrate and the well region. In other embodiments, the screening test is performed by measuring the leakage current at the well drive ground pad to screen for defects in the insulating liner layer formed between the conductive structure and the well region in the deep trench isolation structure. In a selected embodiment, the dedicated ground bias pad is shorted to the well drive ground pad after the screening test and during the packaging of the integrated circuit device.

[0083] In another form, an apparatus and an associated method of manufacturing are provided. As disclosed, the apparatus includes a semiconductor-on-insulator (SOI) substrate, the SOI including device regions disposed on a surface of the SOI substrate and isolated from each other by a deep trench isolation structure extending from the surface of the SOI substrate to an underlying semiconductor substrate, the underlying semiconductor substrate being separated from the SOI substrate by a first buried insulating layer substrate. The disclosed apparatus further includes a first set of semiconductor devices formed in each device region on the surface of the SOI substrate. Additionally, the disclosed apparatus includes a test circuit inlet supported by the SOI substrate, including a dedicated semiconductor substrate bias terminal connected to one or more ground terminals via a high-voltage electrostatic discharge clamping circuit. In a selected embodiment, the high-voltage electrostatic discharge clamping circuit includes a combination of transistors and diodes that provide electrostatic discharge protection for the first set of semiconductor devices formed on the surface of the SOI substrate. In a selected embodiment, the high-voltage electrostatic discharge clamping circuit may be a 65V+ electrostatic discharge clamp. In other embodiments, the high-voltage electrostatic discharge clamping circuit protects the buried insulating layer in the device from electrical stress by discharging electrostatic discharge between the dedicated semiconductor substrate bias terminal and the one or more ground terminals. As disclosed, the dedicated semiconductor substrate bias terminal is electrically connected to the semiconductor substrate through one or more conductive structures in the deep trench isolation structure, while being otherwise electrically isolated from the first group of semiconductor devices. Additionally, the one or more ground terminals are electrically connected directly or through the first group of semiconductor devices to the device region in the SOI substrate. In a selected embodiment, the test circuit entry includes a first conductive interconnect path electrically connecting the semiconductor substrate to the dedicated semiconductor substrate bias terminal, and also includes a second conductive interconnect path electrically connecting the device region to the one or more ground terminals. In a selected embodiment, a first voltage supplied to a bias terminal of the dedicated semiconductor substrate by a first external probe biases the semiconductor substrate, and a second voltage supplied to the one or more ground terminals by a second external probe biases the SOI substrate, thereby generating a high-stress voltage on the first buried insulator layer in the device. This high-stress voltage is greater than the absolute maximum rating for the application specifications of the device and generates a leakage current measurable at the one or more ground terminals to detect defects in the first buried insulator layer. In a selected embodiment, the first buried insulator layer is formed between the semiconductor substrate and the SOI substrate where the device region is disposed. In other embodiments, the first buried insulator layer is an insulating pad layer formed between a first conductive structure in a first deep trench isolation structure and the SOI substrate.If finally formed, the device may include a conductive path that forms an electrical short circuit between the bias terminal of the dedicated semiconductor substrate and the one or more ground terminals.

[0084] In another embodiment, a method for manufacturing and testing a semiconductor device is provided. In the disclosed method, a semiconductor-on-insulator (SOI) layer is formed over a wafer substrate. Additionally, one or more device regions are formed in the SOI layer, and a deep trench isolation structure extending from the surface of the SOI layer to the wafer substrate is formed around the device regions. Furthermore, the disclosed method forms a test circuit over the semiconductor substrate. As formed, the test circuit includes a first set of interconnects and a second set of interconnects electrically connected to the device regions and the wafer substrate, respectively. In a selected embodiment, the first set of interconnects is formed to include dedicated ground bias pads electrically connected to the wafer substrate through conductive structures in the deep trench isolation structure. Additionally, the second set of interconnects may be formed to include one or more ground bias pads electrically connected to the SOI layer through the device regions. Furthermore, the test circuit includes a high-voltage electrostatic discharge clamping circuit connecting the first set of interconnects and the second set of interconnects to protect the device regions from electrostatic discharge. The disclosed method also uses the test circuit to test for defects in the buried insulator layer (SOI) of the semiconductor device. In a selected embodiment, the test can be performed by applying a first voltage to the dedicated ground bias pads to bias the wafer substrate, while simultaneously applying a second voltage to the one or more ground bias pads to bias the SOI layer, wherein the first and second voltages generate strong negative stress voltages on the buried insulator layer. With the first and second voltages applied, a screening test can be performed to screen for defects in the buried insulator layer by measuring the leakage current at the one or more ground bias pads. In a selected embodiment, the first voltage is applied as a negative voltage of at least -60V to the dedicated ground bias pads to bias the wafer substrate. Alternatively, the second voltage can be applied as approximately 0V to the one or more ground bias pads to bias the SOI layer. The disclosed method can also short-circuit the first and second sets of interconnects after the test. Furthermore, the disclosed method can diced the wafer substrate into individual encapsulated and packaged semiconductor devices.

[0085] While the exemplary embodiments described herein are directed to various semiconductor devices and methods for manufacturing and testing their buried insulator defects, the invention is not necessarily limited to these exemplary embodiments, which illustrate inventive aspects of the invention applicable to various semiconductor processes and / or devices. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limiting the invention, as the invention can be modified and practiced in different but equivalent ways, which will be apparent to those skilled in the art who benefit from the teachings herein. Accordingly, the foregoing description is not intended to limit the invention to the specific forms set forth, but rather is intended to cover such alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, such that those skilled in the art should understand that they may be made in their broadest form without departing from the spirit and scope of the invention.

[0086] The foregoing description of specific embodiments has described benefits, other advantages, and solutions to the problem. However, those benefits, advantages, solutions to the problem, and any elements that may cause any benefit, advantage, or solution to occur, or become more significant, shall not be construed as key, claimed, or essential features or elements of any or all claims. As used herein, the term "comprising" or any other variation thereof is intended to cover a non-exclusive inclusion, such that a process, method, article of manufacture, or apparatus that comprises a list of elements includes not only those elements but may include other elements not expressly listed or not inherent to such process, method, article of manufacture, or apparatus.

Claims

1. A method for testing defects in the buried insulator of an integrated circuit device, characterized in that, include: A test circuit is formed in an integrated circuit device, the integrated circuit device including a dedicated ground bias pad connected to a well drive ground pad via a high-voltage electrostatic discharge clamping circuit, wherein the dedicated ground bias pad is electrically connected to the wafer substrate in the integrated circuit device only through a conductive structure in a deep trench isolation structure and is not connected to any other circuit system on the integrated circuit device, and wherein the well drive ground pad is electrically connected to a well region in the integrated circuit device. A first voltage is applied to the dedicated ground bias pad to bias the wafer substrate, while a second voltage is applied to the well drive ground pad to bias the well region, wherein the first voltage and the second voltage generate stress voltages on the buried insulator layer in the integrated circuit device; as well as Screening tests are performed to screen for defects in the buried insulation layer by measuring the leakage current at the trap drive ground pad or the dedicated ground bias pad.

2. The method according to claim 1, characterized in that, Forming the test circuit includes forming a single well drive ground pad, which is electrically connected to the well region directly or via one or more semiconductor devices formed on the surface of the well region.

3. The method according to claim 1, characterized in that, The screening test includes measuring the leakage current at the well drive ground pad to screen for defects in the buried insulator layer formed between the wafer substrate and the well region.

4. The method according to claim 1, characterized in that, The screening test includes measuring the leakage current at the well drive ground pad to screen for defects in the insulating liner layer formed between the conductive structure and the well region in the deep trench isolation structure.

5. An integrated circuit device, characterized in that, include: A semiconductor-on-insulator (SOI) substrate, wherein the SOI includes device regions disposed on the surface of the SOI substrate and isolated from each other by a deep trench isolation structure, the deep trench isolation structure extending from the surface of the SOI substrate to an underlying semiconductor substrate, the underlying semiconductor substrate being separated from the SOI substrate by a first buried insulating layer; A first group of semiconductor devices is formed in each device region on the surface of the SOI substrate; as well as The test circuit entry point, supported by the SOI substrate, includes a dedicated semiconductor substrate bias terminal connected to one or more ground terminals via a high-voltage electrostatic discharge clamping circuit. The dedicated semiconductor substrate bias terminal is electrically connected to the semiconductor substrate through at least one conductive structure in the deep trench isolation structure. One or more of the ground terminals are directly or electrically connected to the device region in the SOI substrate, either directly or through the first group of semiconductor devices. as well as A first voltage supplied to the bias terminal of the dedicated semiconductor substrate by a first external probe biases the semiconductor substrate, and a second voltage supplied to the one or more ground terminals by a second external probe biases the SOI substrate, thereby generating a high-stress voltage on the first buried insulator layer in the device, the high-stress voltage being greater than the absolute maximum rating for the application specifications of the device and generating a leakage current measurable at the one or more ground terminals to detect defects in the first buried insulator layer.

6. The integrated circuit device according to claim 5, characterized in that, The test circuit input includes: A first conductive interconnect path electrically connects the semiconductor substrate to the dedicated semiconductor substrate bias terminal; and A second conductive interconnect path electrically connects the device area to the one or more ground terminals.

7. A method for manufacturing and testing a semiconductor device, characterized in that, include: A semiconductor-on-insulator (SOI) layer is formed on a wafer substrate; A device region is formed in the SOI layer; A deep trench isolation structure is formed around the device region, extending from the surface of the SOI layer to the wafer substrate; A test circuit is formed on the semiconductor substrate, the test circuit comprising: A first set of interconnects and a second set of interconnects, the first set of interconnects and the second set of interconnects being electrically connected to the device region and the wafer substrate, respectively. A high-voltage electrostatic discharge clamping circuit, wherein the high-voltage electrostatic discharge clamping circuit connects the first set of interconnects and the second set of interconnects to protect the device area from electrostatic discharge; and The test circuit is used to test and detect defects in the buried insulator layer in the semiconductor device. The test circuit comprises: The first set of interconnects is formed to include a dedicated ground bias pad electrically connected to the wafer substrate via a conductive structure in the deep trench isolation structure; and The second set of interconnects is formed to include one or more ground bias pads electrically connected to the SOI layer via the device region; and The test includes: A first voltage is applied to the dedicated ground bias pads to bias the wafer substrate, while a second voltage is applied to the one or more ground bias pads to bias the SOI layer, wherein the first voltage and the second voltage generate a strong negative stress voltage on the buried insulator layer; and Screening tests are performed to screen for defects in the buried insulation layer by measuring the leakage current at one or more ground bias pads.

8. The method according to claim 7, characterized in that, Additionally, after performing the test, the first set of interconnects and the second set of interconnects are shorted.

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